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cfb739b4 GKH |
1 | /* |
2 | * Agere Systems Inc. | |
3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs | |
4 | * | |
64f93036 | 5 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
6 | * All rights reserved. |
7 | * http://www.agere.com | |
8 | * | |
9 | *------------------------------------------------------------------------------ | |
10 | * | |
11 | * et1310_address_map.h - Contains the register mapping for the ET1310 | |
12 | * | |
13 | *------------------------------------------------------------------------------ | |
14 | * | |
15 | * SOFTWARE LICENSE | |
16 | * | |
17 | * This software is provided subject to the following terms and conditions, | |
18 | * which you should read carefully before using the software. Using this | |
19 | * software indicates your acceptance of these terms and conditions. If you do | |
20 | * not agree with these terms and conditions, do not use the software. | |
21 | * | |
64f93036 | 22 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
23 | * All rights reserved. |
24 | * | |
25 | * Redistribution and use in source or binary forms, with or without | |
26 | * modifications, are permitted provided that the following conditions are met: | |
27 | * | |
28 | * . Redistributions of source code must retain the above copyright notice, this | |
29 | * list of conditions and the following Disclaimer as comments in the code as | |
30 | * well as in the documentation and/or other materials provided with the | |
31 | * distribution. | |
32 | * | |
33 | * . Redistributions in binary form must reproduce the above copyright notice, | |
34 | * this list of conditions and the following Disclaimer in the documentation | |
35 | * and/or other materials provided with the distribution. | |
36 | * | |
37 | * . Neither the name of Agere Systems Inc. nor the names of the contributors | |
38 | * may be used to endorse or promote products derived from this software | |
39 | * without specific prior written permission. | |
40 | * | |
41 | * Disclaimer | |
42 | * | |
64f93036 | 43 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
cfb739b4 GKH |
44 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
45 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY | |
46 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN | |
47 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY | |
48 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
49 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
50 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
51 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT | |
52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
53 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH | |
54 | * DAMAGE. | |
55 | * | |
56 | */ | |
57 | ||
58 | #ifndef _ET1310_ADDRESS_MAP_H_ | |
59 | #define _ET1310_ADDRESS_MAP_H_ | |
60 | ||
61 | ||
62 | /* START OF GLOBAL REGISTER ADDRESS MAP */ | |
63 | ||
cfb739b4 | 64 | /* |
b8ab7352 AC |
65 | * 10bit registers |
66 | * | |
67 | * Tx queue start address reg in global address map at address 0x0000 | |
68 | * tx queue end address reg in global address map at address 0x0004 | |
69 | * rx queue start address reg in global address map at address 0x0008 | |
70 | * rx queue end address reg in global address map at address 0x000C | |
cfb739b4 GKH |
71 | */ |
72 | ||
73 | /* | |
74 | * structure for power management control status reg in global address map | |
75 | * located at address 0x0010 | |
f2c98d27 AC |
76 | * jagcore_rx_rdy bit 9 |
77 | * jagcore_tx_rdy bit 8 | |
78 | * phy_lped_en bit 7 | |
79 | * phy_sw_coma bit 6 | |
80 | * rxclk_gate bit 5 | |
81 | * txclk_gate bit 4 | |
82 | * sysclk_gate bit 3 | |
83 | * jagcore_rx_en bit 2 | |
84 | * jagcore_tx_en bit 1 | |
85 | * gigephy_en bit 0 | |
cfb739b4 | 86 | */ |
f2c98d27 AC |
87 | |
88 | #define ET_PM_PHY_SW_COMA 0x40 | |
89 | #define ET_PMCSR_INIT 0x38 | |
cfb739b4 GKH |
90 | |
91 | /* | |
2211b732 | 92 | * Interrupt status reg at address 0x0018 |
cfb739b4 | 93 | */ |
cfb739b4 | 94 | |
2211b732 AC |
95 | #define ET_INTR_TXDMA_ISR 0x00000008 |
96 | #define ET_INTR_TXDMA_ERR 0x00000010 | |
97 | #define ET_INTR_RXDMA_XFR_DONE 0x00000020 | |
98 | #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040 | |
99 | #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080 | |
100 | #define ET_INTR_RXDMA_STAT_LOW 0x00000100 | |
101 | #define ET_INTR_RXDMA_ERR 0x00000200 | |
102 | #define ET_INTR_WATCHDOG 0x00004000 | |
103 | #define ET_INTR_WOL 0x00008000 | |
104 | #define ET_INTR_PHY 0x00010000 | |
105 | #define ET_INTR_TXMAC 0x00020000 | |
106 | #define ET_INTR_RXMAC 0x00040000 | |
107 | #define ET_INTR_MAC_STAT 0x00080000 | |
108 | #define ET_INTR_SLV_TIMEOUT 0x00100000 | |
cfb739b4 GKH |
109 | |
110 | /* | |
2211b732 AC |
111 | * Interrupt mask register at address 0x001C |
112 | * Interrupt alias clear mask reg at address 0x0020 | |
113 | * Interrupt status alias reg at address 0x0024 | |
114 | * | |
115 | * Same masks as above | |
cfb739b4 GKH |
116 | */ |
117 | ||
118 | /* | |
b8c4cc46 | 119 | * Software reset reg at address 0x0028 |
f3fd4cd5 | 120 | * 0: txdma_sw_reset |
b8c4cc46 AC |
121 | * 1: rxdma_sw_reset |
122 | * 2: txmac_sw_reset | |
123 | * 3: rxmac_sw_reset | |
124 | * 4: mac_sw_reset | |
125 | * 5: mac_stat_sw_reset | |
126 | * 6: mmc_sw_reset | |
127 | *31: selfclr_disable | |
cfb739b4 | 128 | */ |
cfb739b4 GKH |
129 | |
130 | /* | |
b8c4cc46 | 131 | * SLV Timer reg at address 0x002C (low 24 bits) |
cfb739b4 | 132 | */ |
cfb739b4 GKH |
133 | |
134 | /* | |
e266b202 | 135 | * MSI Configuration reg at address 0x0030 |
cfb739b4 | 136 | */ |
e266b202 AC |
137 | |
138 | #define ET_MSI_VECTOR 0x0000001F | |
139 | #define ET_MSI_TC 0x00070000 | |
cfb739b4 GKH |
140 | |
141 | /* | |
bc7f9c59 | 142 | * Loopback reg located at address 0x0034 |
cfb739b4 | 143 | */ |
bc7f9c59 AC |
144 | |
145 | #define ET_LOOP_MAC 0x00000001 | |
146 | #define ET_LOOP_DMA 0x00000002 | |
cfb739b4 GKH |
147 | |
148 | /* | |
149 | * GLOBAL Module of JAGCore Address Mapping | |
150 | * Located at address 0x0000 | |
151 | */ | |
2b903327 | 152 | struct global_regs { /* Location: */ |
b8ab7352 AC |
153 | u32 txq_start_addr; /* 0x0000 */ |
154 | u32 txq_end_addr; /* 0x0004 */ | |
155 | u32 rxq_start_addr; /* 0x0008 */ | |
156 | u32 rxq_end_addr; /* 0x000C */ | |
f2c98d27 | 157 | u32 pm_csr; /* 0x0010 */ |
64f93036 | 158 | u32 unused; /* 0x0014 */ |
2211b732 AC |
159 | u32 int_status; /* 0x0018 */ |
160 | u32 int_mask; /* 0x001C */ | |
161 | u32 int_alias_clr_en; /* 0x0020 */ | |
162 | u32 int_status_alias; /* 0x0024 */ | |
b8c4cc46 AC |
163 | u32 sw_reset; /* 0x0028 */ |
164 | u32 slv_timer; /* 0x002C */ | |
e266b202 | 165 | u32 msi_config; /* 0x0030 */ |
bc7f9c59 | 166 | u32 loopback; /* 0x0034 */ |
64f93036 | 167 | u32 watchdog_timer; /* 0x0038 */ |
2b903327 | 168 | }; |
cfb739b4 GKH |
169 | |
170 | ||
171 | /* START OF TXDMA REGISTER ADDRESS MAP */ | |
172 | ||
173 | /* | |
bcb903fa | 174 | * txdma control status reg at address 0x1000 |
cfb739b4 | 175 | */ |
bcb903fa AC |
176 | |
177 | #define ET_TXDMA_CSR_HALT 0x00000001 | |
178 | #define ET_TXDMA_DROP_TLP 0x00000002 | |
179 | #define ET_TXDMA_CACHE_THRS 0x000000F0 | |
180 | #define ET_TXDMA_CACHE_SHIFT 4 | |
181 | #define ET_TXDMA_SNGL_EPKT 0x00000100 | |
182 | #define ET_TXDMA_CLASS 0x00001E00 | |
cfb739b4 GKH |
183 | |
184 | /* | |
185 | * structure for txdma packet ring base address hi reg in txdma address map | |
186 | * located at address 0x1004 | |
187 | * Defined earlier (u32) | |
188 | */ | |
189 | ||
190 | /* | |
191 | * structure for txdma packet ring base address low reg in txdma address map | |
192 | * located at address 0x1008 | |
193 | * Defined earlier (u32) | |
194 | */ | |
195 | ||
196 | /* | |
197 | * structure for txdma packet ring number of descriptor reg in txdma address | |
198 | * map. Located at address 0x100C | |
42a03e98 AC |
199 | * |
200 | * 31-10: unused | |
201 | * 9-0: pr ndes | |
cfb739b4 | 202 | */ |
cfb739b4 | 203 | |
d31a2ff0 AC |
204 | #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */ |
205 | #define ET_DMA12_WRAP 0x1000 | |
206 | #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */ | |
207 | #define ET_DMA10_WRAP 0x0400 | |
208 | #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */ | |
209 | #define ET_DMA4_WRAP 0x0010 | |
210 | ||
211 | #define INDEX12(x) ((x) & ET_DMA12_MASK) | |
356c74b4 AC |
212 | #define INDEX10(x) ((x) & ET_DMA10_MASK) |
213 | #define INDEX4(x) ((x) & ET_DMA4_MASK) | |
cfb739b4 | 214 | |
356c74b4 AC |
215 | extern inline void add_10bit(u32 *v, int n) |
216 | { | |
317c68c0 | 217 | *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP); |
356c74b4 | 218 | } |
cfb739b4 | 219 | |
d31a2ff0 AC |
220 | extern inline void add_12bit(u32 *v, int n) |
221 | { | |
222 | *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP); | |
223 | } | |
224 | ||
cfb739b4 | 225 | /* |
356c74b4 AC |
226 | * 10bit DMA with wrap |
227 | * txdma tx queue write address reg in txdma address map at 0x1010 | |
228 | * txdma tx queue write address external reg in txdma address map at 0x1014 | |
229 | * txdma tx queue read address reg in txdma address map at 0x1018 | |
230 | * | |
231 | * u32 | |
232 | * txdma status writeback address hi reg in txdma address map at0x101C | |
233 | * txdma status writeback address lo reg in txdma address map at 0x1020 | |
234 | * | |
235 | * 10bit DMA with wrap | |
236 | * txdma service request reg in txdma address map at 0x1024 | |
237 | * structure for txdma service complete reg in txdma address map at 0x1028 | |
238 | * | |
239 | * 4bit DMA with wrap | |
240 | * txdma tx descriptor cache read index reg in txdma address map at 0x102C | |
241 | * txdma tx descriptor cache write index reg in txdma address map at 0x1030 | |
242 | * | |
243 | * txdma error reg in txdma address map at address 0x1034 | |
fba84166 AC |
244 | * 0: PyldResend |
245 | * 1: PyldRewind | |
246 | * 4: DescrResend | |
247 | * 5: DescrRewind | |
248 | * 8: WrbkResend | |
249 | * 9: WrbkRewind | |
cfb739b4 GKH |
250 | */ |
251 | ||
cfb739b4 GKH |
252 | /* |
253 | * Tx DMA Module of JAGCore Address Mapping | |
254 | * Located at address 0x1000 | |
255 | */ | |
060a78a0 | 256 | struct txdma_regs { /* Location: */ |
bcb903fa | 257 | u32 csr; /* 0x1000 */ |
64f93036 AC |
258 | u32 pr_base_hi; /* 0x1004 */ |
259 | u32 pr_base_lo; /* 0x1008 */ | |
42a03e98 | 260 | u32 pr_num_des; /* 0x100C */ |
356c74b4 AC |
261 | u32 txq_wr_addr; /* 0x1010 */ |
262 | u32 txq_wr_addr_ext; /* 0x1014 */ | |
263 | u32 txq_rd_addr; /* 0x1018 */ | |
64f93036 AC |
264 | u32 dma_wb_base_hi; /* 0x101C */ |
265 | u32 dma_wb_base_lo; /* 0x1020 */ | |
356c74b4 AC |
266 | u32 service_request; /* 0x1024 */ |
267 | u32 service_complete; /* 0x1028 */ | |
268 | u32 cache_rd_index; /* 0x102C */ | |
269 | u32 cache_wr_index; /* 0x1030 */ | |
fba84166 | 270 | u32 TxDmaError; /* 0x1034 */ |
64f93036 AC |
271 | u32 DescAbortCount; /* 0x1038 */ |
272 | u32 PayloadAbortCnt; /* 0x103c */ | |
273 | u32 WriteBackAbortCnt; /* 0x1040 */ | |
274 | u32 DescTimeoutCnt; /* 0x1044 */ | |
275 | u32 PayloadTimeoutCnt; /* 0x1048 */ | |
276 | u32 WriteBackTimeoutCnt; /* 0x104c */ | |
277 | u32 DescErrorCount; /* 0x1050 */ | |
278 | u32 PayloadErrorCnt; /* 0x1054 */ | |
279 | u32 WriteBackErrorCnt; /* 0x1058 */ | |
280 | u32 DroppedTLPCount; /* 0x105c */ | |
356c74b4 | 281 | u32 NewServiceComplete; /* 0x1060 */ |
64f93036 | 282 | u32 EthernetPacketCount; /* 0x1064 */ |
060a78a0 | 283 | }; |
cfb739b4 GKH |
284 | |
285 | /* END OF TXDMA REGISTER ADDRESS MAP */ | |
286 | ||
287 | ||
288 | /* START OF RXDMA REGISTER ADDRESS MAP */ | |
289 | ||
290 | /* | |
291 | * structure for control status reg in rxdma address map | |
292 | * Located at address 0x2000 | |
1bd751c1 AC |
293 | * |
294 | * CSR | |
295 | * 0: halt | |
296 | * 1-3: tc | |
297 | * 4: fbr_big_endian | |
298 | * 5: psr_big_endian | |
299 | * 6: pkt_big_endian | |
300 | * 7: dma_big_endian | |
301 | * 8-9: fbr0_size | |
302 | * 10: fbr0_enable | |
303 | * 11-12: fbr1_size | |
304 | * 13: fbr1_enable | |
305 | * 14: unused | |
306 | * 15: pkt_drop_disable | |
307 | * 16: pkt_done_flush | |
308 | * 17: halt_status | |
309 | * 18-31: unused | |
cfb739b4 | 310 | */ |
1bd751c1 | 311 | |
cfb739b4 GKH |
312 | |
313 | /* | |
314 | * structure for dma writeback lo reg in rxdma address map | |
315 | * located at address 0x2004 | |
316 | * Defined earlier (u32) | |
317 | */ | |
318 | ||
319 | /* | |
320 | * structure for dma writeback hi reg in rxdma address map | |
321 | * located at address 0x2008 | |
322 | * Defined earlier (u32) | |
323 | */ | |
324 | ||
325 | /* | |
326 | * structure for number of packets done reg in rxdma address map | |
327 | * located at address 0x200C | |
2e5e0b89 AC |
328 | * |
329 | * 31-8: unused | |
330 | * 7-0: num done | |
cfb739b4 | 331 | */ |
cfb739b4 GKH |
332 | |
333 | /* | |
334 | * structure for max packet time reg in rxdma address map | |
335 | * located at address 0x2010 | |
67947125 AC |
336 | * |
337 | * 31-18: unused | |
338 | * 17-0: time done | |
cfb739b4 | 339 | */ |
cfb739b4 GKH |
340 | |
341 | /* | |
342 | * structure for rx queue read address reg in rxdma address map | |
343 | * located at address 0x2014 | |
356c74b4 | 344 | * Defined earlier (u32) |
cfb739b4 GKH |
345 | */ |
346 | ||
347 | /* | |
348 | * structure for rx queue read address external reg in rxdma address map | |
349 | * located at address 0x2018 | |
356c74b4 | 350 | * Defined earlier (u32) |
cfb739b4 GKH |
351 | */ |
352 | ||
353 | /* | |
354 | * structure for rx queue write address reg in rxdma address map | |
355 | * located at address 0x201C | |
356c74b4 | 356 | * Defined earlier (u32) |
cfb739b4 GKH |
357 | */ |
358 | ||
359 | /* | |
360 | * structure for packet status ring base address lo reg in rxdma address map | |
361 | * located at address 0x2020 | |
362 | * Defined earlier (u32) | |
363 | */ | |
364 | ||
365 | /* | |
366 | * structure for packet status ring base address hi reg in rxdma address map | |
367 | * located at address 0x2024 | |
368 | * Defined earlier (u32) | |
369 | */ | |
370 | ||
371 | /* | |
372 | * structure for packet status ring number of descriptors reg in rxdma address | |
373 | * map. Located at address 0x2028 | |
2e5e0b89 AC |
374 | * |
375 | * 31-12: unused | |
376 | * 11-0: psr ndes | |
cfb739b4 | 377 | */ |
cfb739b4 GKH |
378 | |
379 | /* | |
380 | * structure for packet status ring available offset reg in rxdma address map | |
381 | * located at address 0x202C | |
99fd99f6 AC |
382 | * |
383 | * 31-13: unused | |
384 | * 12: psr avail wrap | |
385 | * 11-0: psr avail | |
cfb739b4 | 386 | */ |
cfb739b4 GKH |
387 | |
388 | /* | |
389 | * structure for packet status ring full offset reg in rxdma address map | |
390 | * located at address 0x2030 | |
99fd99f6 AC |
391 | * |
392 | * 31-13: unused | |
393 | * 12: psr full wrap | |
394 | * 11-0: psr full | |
cfb739b4 | 395 | */ |
cfb739b4 GKH |
396 | |
397 | /* | |
398 | * structure for packet status ring access index reg in rxdma address map | |
399 | * located at address 0x2034 | |
2e5e0b89 AC |
400 | * |
401 | * 31-5: unused | |
402 | * 4-0: psr_ai | |
cfb739b4 | 403 | */ |
cfb739b4 GKH |
404 | |
405 | /* | |
406 | * structure for packet status ring minimum descriptors reg in rxdma address | |
407 | * map. Located at address 0x2038 | |
2e5e0b89 AC |
408 | * |
409 | * 31-12: unused | |
410 | * 11-0: psr_min | |
cfb739b4 | 411 | */ |
cfb739b4 GKH |
412 | |
413 | /* | |
414 | * structure for free buffer ring base lo address reg in rxdma address map | |
415 | * located at address 0x203C | |
416 | * Defined earlier (u32) | |
417 | */ | |
418 | ||
419 | /* | |
420 | * structure for free buffer ring base hi address reg in rxdma address map | |
421 | * located at address 0x2040 | |
422 | * Defined earlier (u32) | |
423 | */ | |
424 | ||
425 | /* | |
426 | * structure for free buffer ring number of descriptors reg in rxdma address | |
427 | * map. Located at address 0x2044 | |
2e5e0b89 AC |
428 | * |
429 | * 31-10: unused | |
430 | * 9-0: fbr ndesc | |
cfb739b4 | 431 | */ |
cfb739b4 GKH |
432 | |
433 | /* | |
434 | * structure for free buffer ring 0 available offset reg in rxdma address map | |
435 | * located at address 0x2048 | |
356c74b4 | 436 | * Defined earlier (u32) |
cfb739b4 GKH |
437 | */ |
438 | ||
439 | /* | |
440 | * structure for free buffer ring 0 full offset reg in rxdma address map | |
441 | * located at address 0x204C | |
356c74b4 | 442 | * Defined earlier (u32) |
cfb739b4 GKH |
443 | */ |
444 | ||
445 | /* | |
446 | * structure for free buffer cache 0 full offset reg in rxdma address map | |
447 | * located at address 0x2050 | |
2e5e0b89 AC |
448 | * |
449 | * 31-5: unused | |
450 | * 4-0: fbc rdi | |
cfb739b4 | 451 | */ |
cfb739b4 GKH |
452 | |
453 | /* | |
454 | * structure for free buffer ring 0 minimum descriptor reg in rxdma address map | |
455 | * located at address 0x2054 | |
2e5e0b89 AC |
456 | * |
457 | * 31-10: unused | |
458 | * 9-0: fbr min | |
cfb739b4 | 459 | */ |
cfb739b4 GKH |
460 | |
461 | /* | |
462 | * structure for free buffer ring 1 base address lo reg in rxdma address map | |
463 | * located at address 0x2058 - 0x205C | |
464 | * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t) | |
465 | */ | |
466 | ||
467 | /* | |
468 | * structure for free buffer ring 1 number of descriptors reg in rxdma address | |
469 | * map. Located at address 0x2060 | |
470 | * Defined earlier (RXDMA_FBR_NUM_DES_t) | |
471 | */ | |
472 | ||
473 | /* | |
474 | * structure for free buffer ring 1 available offset reg in rxdma address map | |
475 | * located at address 0x2064 | |
476 | * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t) | |
477 | */ | |
478 | ||
479 | /* | |
480 | * structure for free buffer ring 1 full offset reg in rxdma address map | |
481 | * located at address 0x2068 | |
482 | * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t) | |
483 | */ | |
484 | ||
485 | /* | |
486 | * structure for free buffer cache 1 read index reg in rxdma address map | |
487 | * located at address 0x206C | |
488 | * Defined Earlier (RXDMA_FBC_RD_INDEX_t) | |
489 | */ | |
490 | ||
491 | /* | |
492 | * structure for free buffer ring 1 minimum descriptor reg in rxdma address map | |
493 | * located at address 0x2070 | |
494 | * Defined Earlier (RXDMA_FBR_MIN_DES_t) | |
495 | */ | |
496 | ||
497 | /* | |
498 | * Rx DMA Module of JAGCore Address Mapping | |
499 | * Located at address 0x2000 | |
500 | */ | |
61d5ed8c | 501 | struct rxdma_regs { /* Location: */ |
1bd751c1 | 502 | u32 csr; /* 0x2000 */ |
64f93036 AC |
503 | u32 dma_wb_base_lo; /* 0x2004 */ |
504 | u32 dma_wb_base_hi; /* 0x2008 */ | |
2e5e0b89 | 505 | u32 num_pkt_done; /* 0x200C */ |
67947125 | 506 | u32 max_pkt_time; /* 0x2010 */ |
356c74b4 | 507 | u32 rxq_rd_addr; /* 0x2014 */ |
2e5e0b89 | 508 | u32 rxq_rd_addr_ext; /* 0x2018 */ |
356c74b4 | 509 | u32 rxq_wr_addr; /* 0x201C */ |
64f93036 AC |
510 | u32 psr_base_lo; /* 0x2020 */ |
511 | u32 psr_base_hi; /* 0x2024 */ | |
2e5e0b89 | 512 | u32 psr_num_des; /* 0x2028 */ |
99fd99f6 AC |
513 | u32 psr_avail_offset; /* 0x202C */ |
514 | u32 psr_full_offset; /* 0x2030 */ | |
2e5e0b89 AC |
515 | u32 psr_access_index; /* 0x2034 */ |
516 | u32 psr_min_des; /* 0x2038 */ | |
64f93036 AC |
517 | u32 fbr0_base_lo; /* 0x203C */ |
518 | u32 fbr0_base_hi; /* 0x2040 */ | |
2e5e0b89 AC |
519 | u32 fbr0_num_des; /* 0x2044 */ |
520 | u32 fbr0_avail_offset; /* 0x2048 */ | |
521 | u32 fbr0_full_offset; /* 0x204C */ | |
522 | u32 fbr0_rd_index; /* 0x2050 */ | |
523 | u32 fbr0_min_des; /* 0x2054 */ | |
64f93036 AC |
524 | u32 fbr1_base_lo; /* 0x2058 */ |
525 | u32 fbr1_base_hi; /* 0x205C */ | |
2e5e0b89 AC |
526 | u32 fbr1_num_des; /* 0x2060 */ |
527 | u32 fbr1_avail_offset; /* 0x2064 */ | |
528 | u32 fbr1_full_offset; /* 0x2068 */ | |
529 | u32 fbr1_rd_index; /* 0x206C */ | |
530 | u32 fbr1_min_des; /* 0x2070 */ | |
61d5ed8c | 531 | }; |
cfb739b4 GKH |
532 | |
533 | /* END OF RXDMA REGISTER ADDRESS MAP */ | |
534 | ||
535 | ||
536 | /* START OF TXMAC REGISTER ADDRESS MAP */ | |
537 | ||
538 | /* | |
539 | * structure for control reg in txmac address map | |
540 | * located at address 0x3000 | |
6720949d AC |
541 | * |
542 | * bits | |
543 | * 31-8: unused | |
544 | * 7: cklseg_disable | |
545 | * 6: ckbcnt_disable | |
546 | * 5: cksegnum | |
547 | * 4: async_disable | |
548 | * 3: fc_disable | |
549 | * 2: mcif_disable | |
550 | * 1: mif_disable | |
551 | * 0: txmac_en | |
cfb739b4 | 552 | */ |
cfb739b4 GKH |
553 | |
554 | /* | |
555 | * structure for shadow pointer reg in txmac address map | |
556 | * located at address 0x3004 | |
02cdb0b4 AC |
557 | * 31-27: reserved |
558 | * 26-16: txq rd ptr | |
559 | * 15-11: reserved | |
560 | * 10-0: txq wr ptr | |
cfb739b4 | 561 | */ |
cfb739b4 GKH |
562 | |
563 | /* | |
564 | * structure for error count reg in txmac address map | |
565 | * located at address 0x3008 | |
1cb180dc AC |
566 | * |
567 | * 31-12: unused | |
568 | * 11-8: reserved | |
569 | * 7-4: txq_underrun | |
570 | * 3-0: fifo_underrun | |
cfb739b4 | 571 | */ |
cfb739b4 GKH |
572 | |
573 | /* | |
574 | * structure for max fill reg in txmac address map | |
575 | * located at address 0x300C | |
f838cabd AC |
576 | * 31-12: unused |
577 | * 11-0: max fill | |
cfb739b4 | 578 | */ |
cfb739b4 GKH |
579 | |
580 | /* | |
581 | * structure for cf parameter reg in txmac address map | |
582 | * located at address 0x3010 | |
f838cabd AC |
583 | * 31-16: cfep |
584 | * 15-0: cfpt | |
cfb739b4 | 585 | */ |
cfb739b4 GKH |
586 | |
587 | /* | |
588 | * structure for tx test reg in txmac address map | |
589 | * located at address 0x3014 | |
f838cabd AC |
590 | * 31-17: unused |
591 | * 16: reserved1 | |
592 | * 15: txtest_en | |
593 | * 14-11: unused | |
594 | * 10-0: txq test pointer | |
cfb739b4 | 595 | */ |
cfb739b4 GKH |
596 | |
597 | /* | |
598 | * structure for error reg in txmac address map | |
599 | * located at address 0x3018 | |
003e52e8 AC |
600 | * |
601 | * 31-9: unused | |
602 | * 8: fifo_underrun | |
603 | * 7-6: unused | |
604 | * 5: ctrl2_err | |
605 | * 4: txq_underrun | |
606 | * 3: bcnt_err | |
607 | * 2: lseg_err | |
608 | * 1: segnum_err | |
609 | * 0: seg0_err | |
cfb739b4 | 610 | */ |
cfb739b4 GKH |
611 | |
612 | /* | |
613 | * structure for error interrupt reg in txmac address map | |
614 | * located at address 0x301C | |
afa7e5ec AC |
615 | * |
616 | * 31-9: unused | |
617 | * 8: fifo_underrun | |
618 | * 7-6: unused | |
619 | * 5: ctrl2_err | |
620 | * 4: txq_underrun | |
621 | * 3: bcnt_err | |
622 | * 2: lseg_err | |
623 | * 1: segnum_err | |
624 | * 0: seg0_err | |
cfb739b4 | 625 | */ |
cfb739b4 GKH |
626 | |
627 | /* | |
628 | * structure for error interrupt reg in txmac address map | |
629 | * located at address 0x3020 | |
cfc52eb6 AC |
630 | * |
631 | * 31-2: unused | |
632 | * 1: bp_req | |
633 | * 0: bp_xonxoff | |
cfb739b4 | 634 | */ |
cfb739b4 GKH |
635 | |
636 | /* | |
637 | * Tx MAC Module of JAGCore Address Mapping | |
638 | */ | |
afa7e5ec | 639 | struct txmac_regs { /* Location: */ |
6720949d | 640 | u32 ctl; /* 0x3000 */ |
02cdb0b4 | 641 | u32 shadow_ptr; /* 0x3004 */ |
1cb180dc | 642 | u32 err_cnt; /* 0x3008 */ |
f838cabd AC |
643 | u32 max_fill; /* 0x300C */ |
644 | u32 cf_param; /* 0x3010 */ | |
645 | u32 tx_test; /* 0x3014 */ | |
003e52e8 | 646 | u32 err; /* 0x3018 */ |
afa7e5ec | 647 | u32 err_int; /* 0x301C */ |
cfc52eb6 | 648 | u32 bp_ctrl; /* 0x3020 */ |
afa7e5ec | 649 | }; |
cfb739b4 GKH |
650 | |
651 | /* END OF TXMAC REGISTER ADDRESS MAP */ | |
652 | ||
653 | /* START OF RXMAC REGISTER ADDRESS MAP */ | |
654 | ||
655 | /* | |
656 | * structure for rxmac control reg in rxmac address map | |
657 | * located at address 0x4000 | |
bd03d0d5 AC |
658 | * |
659 | * 31-7: reserved | |
660 | * 6: rxmac_int_disable | |
661 | * 5: async_disable | |
662 | * 4: mif_disable | |
663 | * 3: wol_disable | |
664 | * 2: pkt_filter_disable | |
665 | * 1: mcif_disable | |
666 | * 0: rxmac_en | |
cfb739b4 | 667 | */ |
cfb739b4 GKH |
668 | |
669 | /* | |
670 | * structure for Wake On Lan Control and CRC 0 reg in rxmac address map | |
671 | * located at address 0x4004 | |
70a29a24 AC |
672 | * 31-16: crc |
673 | * 15-12: reserved | |
674 | * 11: ignore_pp | |
675 | * 10: ignore_mp | |
676 | * 9: clr_intr | |
677 | * 8: ignore_link_chg | |
678 | * 7: ignore_uni | |
679 | * 6: ignore_multi | |
680 | * 5: ignore_broad | |
681 | * 4-0: valid_crc 4-0 | |
cfb739b4 | 682 | */ |
cfb739b4 GKH |
683 | |
684 | /* | |
685 | * structure for CRC 1 and CRC 2 reg in rxmac address map | |
686 | * located at address 0x4008 | |
70a29a24 AC |
687 | * |
688 | * 31-16: crc2 | |
689 | * 15-0: crc1 | |
cfb739b4 | 690 | */ |
cfb739b4 GKH |
691 | |
692 | /* | |
693 | * structure for CRC 3 and CRC 4 reg in rxmac address map | |
694 | * located at address 0x400C | |
70a29a24 AC |
695 | * |
696 | * 31-16: crc4 | |
697 | * 15-0: crc3 | |
cfb739b4 | 698 | */ |
cfb739b4 GKH |
699 | |
700 | /* | |
701 | * structure for Wake On Lan Source Address Lo reg in rxmac address map | |
702 | * located at address 0x4010 | |
703 | */ | |
704 | typedef union _RXMAC_WOL_SA_LO_t { | |
705 | u32 value; | |
706 | struct { | |
707 | #ifdef _BIT_FIELDS_HTOL | |
64f93036 AC |
708 | u32 sa3:8; /* bits 24-31 */ |
709 | u32 sa4:8; /* bits 16-23 */ | |
710 | u32 sa5:8; /* bits 8-15 */ | |
711 | u32 sa6:8; /* bits 0-7 */ | |
cfb739b4 | 712 | #else |
64f93036 AC |
713 | u32 sa6:8; /* bits 0-7 */ |
714 | u32 sa5:8; /* bits 8-15 */ | |
715 | u32 sa4:8; /* bits 16-23 */ | |
716 | u32 sa3:8; /* bits 24-31 */ | |
cfb739b4 GKH |
717 | #endif |
718 | } bits; | |
719 | } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t; | |
720 | ||
721 | /* | |
722 | * structure for Wake On Lan Source Address Hi reg in rxmac address map | |
723 | * located at address 0x4014 | |
724 | */ | |
725 | typedef union _RXMAC_WOL_SA_HI_t { | |
726 | u32 value; | |
727 | struct { | |
728 | #ifdef _BIT_FIELDS_HTOL | |
64f93036 AC |
729 | u32 reserved:16; /* bits 16-31 */ |
730 | u32 sa1:8; /* bits 8-15 */ | |
731 | u32 sa2:8; /* bits 0-7 */ | |
cfb739b4 | 732 | #else |
64f93036 AC |
733 | u32 sa2:8; /* bits 0-7 */ |
734 | u32 sa1:8; /* bits 8-15 */ | |
735 | u32 reserved:16; /* bits 16-31 */ | |
cfb739b4 GKH |
736 | #endif |
737 | } bits; | |
738 | } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t; | |
739 | ||
740 | /* | |
741 | * structure for Wake On Lan mask reg in rxmac address map | |
742 | * located at address 0x4018 - 0x4064 | |
743 | * Defined earlier (u32) | |
744 | */ | |
745 | ||
746 | /* | |
747 | * structure for Unicast Paket Filter Address 1 reg in rxmac address map | |
748 | * located at address 0x4068 | |
749 | */ | |
750 | typedef union _RXMAC_UNI_PF_ADDR1_t { | |
751 | u32 value; | |
752 | struct { | |
753 | #ifdef _BIT_FIELDS_HTOL | |
64f93036 AC |
754 | u32 addr1_3:8; /* bits 24-31 */ |
755 | u32 addr1_4:8; /* bits 16-23 */ | |
756 | u32 addr1_5:8; /* bits 8-15 */ | |
757 | u32 addr1_6:8; /* bits 0-7 */ | |
cfb739b4 | 758 | #else |
64f93036 AC |
759 | u32 addr1_6:8; /* bits 0-7 */ |
760 | u32 addr1_5:8; /* bits 8-15 */ | |
761 | u32 addr1_4:8; /* bits 16-23 */ | |
762 | u32 addr1_3:8; /* bits 24-31 */ | |
cfb739b4 GKH |
763 | #endif |
764 | } bits; | |
765 | } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t; | |
766 | ||
767 | /* | |
768 | * structure for Unicast Paket Filter Address 2 reg in rxmac address map | |
769 | * located at address 0x406C | |
770 | */ | |
771 | typedef union _RXMAC_UNI_PF_ADDR2_t { | |
772 | u32 value; | |
773 | struct { | |
774 | #ifdef _BIT_FIELDS_HTOL | |
64f93036 AC |
775 | u32 addr2_3:8; /* bits 24-31 */ |
776 | u32 addr2_4:8; /* bits 16-23 */ | |
777 | u32 addr2_5:8; /* bits 8-15 */ | |
778 | u32 addr2_6:8; /* bits 0-7 */ | |
cfb739b4 | 779 | #else |
64f93036 AC |
780 | u32 addr2_6:8; /* bits 0-7 */ |
781 | u32 addr2_5:8; /* bits 8-15 */ | |
782 | u32 addr2_4:8; /* bits 16-23 */ | |
783 | u32 addr2_3:8; /* bits 24-31 */ | |
cfb739b4 GKH |
784 | #endif |
785 | } bits; | |
786 | } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t; | |
787 | ||
788 | /* | |
789 | * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map | |
790 | * located at address 0x4070 | |
791 | */ | |
792 | typedef union _RXMAC_UNI_PF_ADDR3_t { | |
793 | u32 value; | |
794 | struct { | |
795 | #ifdef _BIT_FIELDS_HTOL | |
64f93036 AC |
796 | u32 addr2_1:8; /* bits 24-31 */ |
797 | u32 addr2_2:8; /* bits 16-23 */ | |
798 | u32 addr1_1:8; /* bits 8-15 */ | |
799 | u32 addr1_2:8; /* bits 0-7 */ | |
cfb739b4 | 800 | #else |
64f93036 AC |
801 | u32 addr1_2:8; /* bits 0-7 */ |
802 | u32 addr1_1:8; /* bits 8-15 */ | |
803 | u32 addr2_2:8; /* bits 16-23 */ | |
804 | u32 addr2_1:8; /* bits 24-31 */ | |
cfb739b4 GKH |
805 | #endif |
806 | } bits; | |
807 | } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t; | |
808 | ||
809 | /* | |
810 | * structure for Multicast Hash reg in rxmac address map | |
811 | * located at address 0x4074 - 0x4080 | |
812 | * Defined earlier (u32) | |
813 | */ | |
814 | ||
815 | /* | |
816 | * structure for Packet Filter Control reg in rxmac address map | |
817 | * located at address 0x4084 | |
b186f331 AC |
818 | * |
819 | * 31-23: unused | |
820 | * 22-16: min_pkt_size | |
821 | * 15-4: unused | |
822 | * 3: filter_frag_en | |
823 | * 2: filter_uni_en | |
824 | * 1: filter_multi_en | |
825 | * 0: filter_broad_en | |
cfb739b4 | 826 | */ |
cfb739b4 GKH |
827 | |
828 | /* | |
829 | * structure for Memory Controller Interface Control Max Segment reg in rxmac | |
830 | * address map. Located at address 0x4088 | |
287acb63 AC |
831 | * |
832 | * 31-10: reserved | |
833 | * 9-2: max_size | |
834 | * 1: fc_en | |
835 | * 0: seg_en | |
cfb739b4 | 836 | */ |
cfb739b4 GKH |
837 | |
838 | /* | |
839 | * structure for Memory Controller Interface Water Mark reg in rxmac address | |
840 | * map. Located at address 0x408C | |
287acb63 AC |
841 | * |
842 | * 31-26: unused | |
843 | * 25-16: mark_hi | |
844 | * 15-10: unused | |
845 | * 9-0: mark_lo | |
cfb739b4 | 846 | */ |
cfb739b4 GKH |
847 | |
848 | /* | |
849 | * structure for Rx Queue Dialog reg in rxmac address map. | |
850 | * located at address 0x4090 | |
f7ae1957 AC |
851 | * |
852 | * 31-26: reserved | |
853 | * 25-16: rd_ptr | |
854 | * 15-10: reserved | |
855 | * 9-0: wr_ptr | |
cfb739b4 | 856 | */ |
cfb739b4 GKH |
857 | |
858 | /* | |
25985edc | 859 | * structure for space available reg in rxmac address map. |
cfb739b4 | 860 | * located at address 0x4094 |
370d52ac AC |
861 | * |
862 | * 31-17: reserved | |
863 | * 16: space_avail_en | |
864 | * 15-10: reserved | |
865 | * 9-0: space_avail | |
cfb739b4 | 866 | */ |
cfb739b4 GKH |
867 | |
868 | /* | |
869 | * structure for management interface reg in rxmac address map. | |
870 | * located at address 0x4098 | |
dcb0789b AC |
871 | * |
872 | * 31-18: reserved | |
873 | * 17: drop_pkt_en | |
874 | * 16-0: drop_pkt_mask | |
cfb739b4 | 875 | */ |
cfb739b4 GKH |
876 | |
877 | /* | |
878 | * structure for Error reg in rxmac address map. | |
879 | * located at address 0x409C | |
fef5ba3a AC |
880 | * |
881 | * 31-4: unused | |
882 | * 3: mif | |
883 | * 2: async | |
884 | * 1: pkt_filter | |
885 | * 0: mcif | |
cfb739b4 | 886 | */ |
cfb739b4 GKH |
887 | |
888 | /* | |
889 | * Rx MAC Module of JAGCore Address Mapping | |
890 | */ | |
64f93036 | 891 | typedef struct _RXMAC_t { /* Location: */ |
bd03d0d5 | 892 | u32 ctrl; /* 0x4000 */ |
70a29a24 AC |
893 | u32 crc0; /* 0x4004 */ |
894 | u32 crc12; /* 0x4008 */ | |
895 | u32 crc34; /* 0x400C */ | |
64f93036 AC |
896 | RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */ |
897 | RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */ | |
898 | u32 mask0_word0; /* 0x4018 */ | |
899 | u32 mask0_word1; /* 0x401C */ | |
900 | u32 mask0_word2; /* 0x4020 */ | |
901 | u32 mask0_word3; /* 0x4024 */ | |
902 | u32 mask1_word0; /* 0x4028 */ | |
903 | u32 mask1_word1; /* 0x402C */ | |
904 | u32 mask1_word2; /* 0x4030 */ | |
905 | u32 mask1_word3; /* 0x4034 */ | |
906 | u32 mask2_word0; /* 0x4038 */ | |
907 | u32 mask2_word1; /* 0x403C */ | |
908 | u32 mask2_word2; /* 0x4040 */ | |
909 | u32 mask2_word3; /* 0x4044 */ | |
910 | u32 mask3_word0; /* 0x4048 */ | |
911 | u32 mask3_word1; /* 0x404C */ | |
912 | u32 mask3_word2; /* 0x4050 */ | |
913 | u32 mask3_word3; /* 0x4054 */ | |
914 | u32 mask4_word0; /* 0x4058 */ | |
915 | u32 mask4_word1; /* 0x405C */ | |
916 | u32 mask4_word2; /* 0x4060 */ | |
917 | u32 mask4_word3; /* 0x4064 */ | |
918 | RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; /* 0x4068 */ | |
919 | RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; /* 0x406C */ | |
920 | RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; /* 0x4070 */ | |
921 | u32 multi_hash1; /* 0x4074 */ | |
922 | u32 multi_hash2; /* 0x4078 */ | |
923 | u32 multi_hash3; /* 0x407C */ | |
924 | u32 multi_hash4; /* 0x4080 */ | |
b186f331 | 925 | u32 pf_ctrl; /* 0x4084 */ |
287acb63 AC |
926 | u32 mcif_ctrl_max_seg; /* 0x4088 */ |
927 | u32 mcif_water_mark; /* 0x408C */ | |
f7ae1957 | 928 | u32 rxq_diag; /* 0x4090 */ |
370d52ac | 929 | u32 space_avail; /* 0x4094 */ |
64f93036 | 930 | |
dcb0789b | 931 | u32 mif_ctrl; /* 0x4098 */ |
fef5ba3a | 932 | u32 err_reg; /* 0x409C */ |
cfb739b4 GKH |
933 | } RXMAC_t, *PRXMAC_t; |
934 | ||
afa7e5ec | 935 | /* END OF RXMAC REGISTER ADDRESS MAP */ |
cfb739b4 GKH |
936 | |
937 | ||
938 | /* START OF MAC REGISTER ADDRESS MAP */ | |
939 | ||
940 | /* | |
941 | * structure for configuration #1 reg in mac address map. | |
942 | * located at address 0x5000 | |
c9835d97 AC |
943 | * |
944 | * 31: soft reset | |
945 | * 30: sim reset | |
946 | * 29-20: reserved | |
947 | * 19: reset rx mc | |
948 | * 18: reset tx mc | |
949 | * 17: reset rx func | |
950 | * 16: reset tx fnc | |
951 | * 15-9: reserved | |
952 | * 8: loopback | |
953 | * 7-6: reserved | |
954 | * 5: rx flow | |
955 | * 4: tx flow | |
956 | * 3: syncd rx en | |
957 | * 2: rx enable | |
958 | * 1: syncd tx en | |
959 | * 0: tx enable | |
960 | */ | |
961 | ||
962 | #define CFG1_LOOPBACK 0x00000100 | |
963 | #define CFG1_RX_FLOW 0x00000020 | |
964 | #define CFG1_TX_FLOW 0x00000010 | |
965 | #define CFG1_RX_ENABLE 0x00000004 | |
966 | #define CFG1_TX_ENABLE 0x00000001 | |
967 | #define CFG1_WAIT 0x0000000A /* RX & TX syncd */ | |
cfb739b4 GKH |
968 | |
969 | /* | |
970 | * structure for configuration #2 reg in mac address map. | |
971 | * located at address 0x5004 | |
c9835d97 AC |
972 | * 31-16: reserved |
973 | * 15-12: preamble | |
974 | * 11-10: reserved | |
975 | * 9-8: if mode | |
976 | * 7-6: reserved | |
977 | * 5: huge frame | |
978 | * 4: length check | |
979 | * 3: undefined | |
980 | * 2: pad crc | |
981 | * 1: crc enable | |
982 | * 0: full duplex | |
cfb739b4 | 983 | */ |
c9835d97 | 984 | |
cfb739b4 GKH |
985 | |
986 | /* | |
987 | * structure for Interpacket gap reg in mac address map. | |
988 | * located at address 0x5008 | |
308e93e0 AC |
989 | * |
990 | * 31: reserved | |
991 | * 30-24: non B2B ipg 1 | |
992 | * 23: undefined | |
993 | * 22-16: non B2B ipg 2 | |
994 | * 15-8: Min ifg enforce | |
995 | * 7-0: B2B ipg | |
c2f6118a | 996 | * |
cfb739b4 GKH |
997 | * structure for half duplex reg in mac address map. |
998 | * located at address 0x500C | |
c2f6118a AC |
999 | * 31-24: reserved |
1000 | * 23-20: Alt BEB trunc | |
1001 | * 19: Alt BEB enable | |
1002 | * 18: BP no backoff | |
1003 | * 17: no backoff | |
1004 | * 16: excess defer | |
1005 | * 15-12: re-xmit max | |
1006 | * 11-10: reserved | |
1007 | * 9-0: collision window | |
cfb739b4 | 1008 | */ |
cfb739b4 GKH |
1009 | |
1010 | /* | |
1011 | * structure for Maximum Frame Length reg in mac address map. | |
cc5dc29c | 1012 | * located at address 0x5010: bits 0-15 hold the length. |
cfb739b4 | 1013 | */ |
cfb739b4 GKH |
1014 | |
1015 | /* | |
1016 | * structure for Reserve 1 reg in mac address map. | |
1017 | * located at address 0x5014 - 0x5018 | |
1018 | * Defined earlier (u32) | |
1019 | */ | |
1020 | ||
1021 | /* | |
1022 | * structure for Test reg in mac address map. | |
1023 | * located at address 0x501C | |
4ea30f84 | 1024 | * test: bits 0-2, rest unused |
cfb739b4 | 1025 | */ |
cfb739b4 GKH |
1026 | |
1027 | /* | |
1028 | * structure for MII Management Configuration reg in mac address map. | |
1029 | * located at address 0x5020 | |
eccdd88f AC |
1030 | * |
1031 | * 31: reset MII mgmt | |
1032 | * 30-6: unused | |
1033 | * 5: scan auto increment | |
25985edc | 1034 | * 4: preamble suppress |
eccdd88f AC |
1035 | * 3: undefined |
1036 | * 2-0: mgmt clock reset | |
cfb739b4 | 1037 | */ |
cfb739b4 GKH |
1038 | |
1039 | /* | |
1040 | * structure for MII Management Command reg in mac address map. | |
1041 | * located at address 0x5024 | |
57aed3b4 AC |
1042 | * bit 1: scan cycle |
1043 | * bit 0: read cycle | |
cfb739b4 | 1044 | */ |
cfb739b4 GKH |
1045 | |
1046 | /* | |
1047 | * structure for MII Management Address reg in mac address map. | |
1048 | * located at address 0x5028 | |
57aed3b4 AC |
1049 | * 31-13: reserved |
1050 | * 12-8: phy addr | |
1051 | * 7-5: reserved | |
1052 | * 4-0: register | |
cfb739b4 | 1053 | */ |
57aed3b4 | 1054 | |
f3fd4cd5 | 1055 | #define MII_ADDR(phy, reg) ((phy) << 8 | (reg)) |
cfb739b4 GKH |
1056 | |
1057 | /* | |
1058 | * structure for MII Management Control reg in mac address map. | |
1059 | * located at address 0x502C | |
57aed3b4 AC |
1060 | * 31-16: reserved |
1061 | * 15-0: phy control | |
cfb739b4 | 1062 | */ |
cfb739b4 GKH |
1063 | |
1064 | /* | |
1065 | * structure for MII Management Status reg in mac address map. | |
1066 | * located at address 0x5030 | |
57aed3b4 AC |
1067 | * 31-16: reserved |
1068 | * 15-0: phy control | |
cfb739b4 | 1069 | */ |
cfb739b4 GKH |
1070 | |
1071 | /* | |
1072 | * structure for MII Management Indicators reg in mac address map. | |
1073 | * located at address 0x5034 | |
57aed3b4 AC |
1074 | * 31-3: reserved |
1075 | * 2: not valid | |
1076 | * 1: scanning | |
1077 | * 0: busy | |
cfb739b4 | 1078 | */ |
57aed3b4 AC |
1079 | |
1080 | #define MGMT_BUSY 0x00000001 /* busy */ | |
1081 | #define MGMT_WAIT 0x00000005 /* busy | not valid */ | |
cfb739b4 GKH |
1082 | |
1083 | /* | |
1084 | * structure for Interface Control reg in mac address map. | |
1085 | * located at address 0x5038 | |
b491f147 AC |
1086 | * |
1087 | * 31: reset if module | |
1088 | * 30-28: reserved | |
1089 | * 27: tbi mode | |
1090 | * 26: ghd mode | |
1091 | * 25: lhd mode | |
1092 | * 24: phy mode | |
1093 | * 23: reset per mii | |
1094 | * 22-17: reserved | |
1095 | * 16: speed | |
1096 | * 15: reset pe100x | |
1097 | * 14-11: reserved | |
1098 | * 10: force quiet | |
1099 | * 9: no cipher | |
1100 | * 8: disable link fail | |
1101 | * 7: reset gpsi | |
1102 | * 6-1: reserved | |
1103 | * 0: enable jabber protection | |
cfb739b4 | 1104 | */ |
cfb739b4 GKH |
1105 | |
1106 | /* | |
1107 | * structure for Interface Status reg in mac address map. | |
1108 | * located at address 0x503C | |
22e0967f AC |
1109 | * |
1110 | * 31-10: reserved | |
1111 | * 9: excess_defer | |
1112 | * 8: clash | |
1113 | * 7: phy_jabber | |
1114 | * 6: phy_link_ok | |
1115 | * 5: phy_full_duplex | |
1116 | * 4: phy_speed | |
1117 | * 3: pe100x_link_fail | |
1118 | * 2: pe10t_loss_carrier | |
1119 | * 1: pe10t_sqe_error | |
1120 | * 0: pe10t_jabber | |
cfb739b4 | 1121 | */ |
cfb739b4 GKH |
1122 | |
1123 | /* | |
1124 | * structure for Mac Station Address, Part 1 reg in mac address map. | |
1125 | * located at address 0x5040 | |
1126 | */ | |
1127 | typedef union _MAC_STATION_ADDR1_t { | |
1128 | u32 value; | |
1129 | struct { | |
1130 | #ifdef _BIT_FIELDS_HTOL | |
64f93036 AC |
1131 | u32 Octet6:8; /* bits 24-31 */ |
1132 | u32 Octet5:8; /* bits 16-23 */ | |
1133 | u32 Octet4:8; /* bits 8-15 */ | |
1134 | u32 Octet3:8; /* bits 0-7 */ | |
cfb739b4 | 1135 | #else |
64f93036 AC |
1136 | u32 Octet3:8; /* bits 0-7 */ |
1137 | u32 Octet4:8; /* bits 8-15 */ | |
1138 | u32 Octet5:8; /* bits 16-23 */ | |
1139 | u32 Octet6:8; /* bits 24-31 */ | |
cfb739b4 GKH |
1140 | #endif |
1141 | } bits; | |
1142 | } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t; | |
1143 | ||
1144 | /* | |
1145 | * structure for Mac Station Address, Part 2 reg in mac address map. | |
1146 | * located at address 0x5044 | |
1147 | */ | |
1148 | typedef union _MAC_STATION_ADDR2_t { | |
1149 | u32 value; | |
1150 | struct { | |
1151 | #ifdef _BIT_FIELDS_HTOL | |
64f93036 AC |
1152 | u32 Octet2:8; /* bits 24-31 */ |
1153 | u32 Octet1:8; /* bits 16-23 */ | |
1154 | u32 reserved:16; /* bits 0-15 */ | |
cfb739b4 | 1155 | #else |
64f93036 AC |
1156 | u32 reserved:16; /* bit 0-15 */ |
1157 | u32 Octet1:8; /* bits 16-23 */ | |
1158 | u32 Octet2:8; /* bits 24-31 */ | |
cfb739b4 GKH |
1159 | #endif |
1160 | } bits; | |
1161 | } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t; | |
1162 | ||
1163 | /* | |
1164 | * MAC Module of JAGCore Address Mapping | |
1165 | */ | |
64f93036 | 1166 | typedef struct _MAC_t { /* Location: */ |
c9835d97 AC |
1167 | u32 cfg1; /* 0x5000 */ |
1168 | u32 cfg2; /* 0x5004 */ | |
308e93e0 | 1169 | u32 ipg; /* 0x5008 */ |
c2f6118a | 1170 | u32 hfdp; /* 0x500C */ |
cc5dc29c | 1171 | u32 max_fm_len; /* 0x5010 */ |
64f93036 AC |
1172 | u32 rsv1; /* 0x5014 */ |
1173 | u32 rsv2; /* 0x5018 */ | |
4ea30f84 | 1174 | u32 mac_test; /* 0x501C */ |
eccdd88f | 1175 | u32 mii_mgmt_cfg; /* 0x5020 */ |
57aed3b4 AC |
1176 | u32 mii_mgmt_cmd; /* 0x5024 */ |
1177 | u32 mii_mgmt_addr; /* 0x5028 */ | |
1178 | u32 mii_mgmt_ctrl; /* 0x502C */ | |
1179 | u32 mii_mgmt_stat; /* 0x5030 */ | |
1180 | u32 mii_mgmt_indicator; /* 0x5034 */ | |
b491f147 | 1181 | u32 if_ctrl; /* 0x5038 */ |
22e0967f | 1182 | u32 if_stat; /* 0x503C */ |
64f93036 AC |
1183 | MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */ |
1184 | MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */ | |
cfb739b4 GKH |
1185 | } MAC_t, *PMAC_t; |
1186 | ||
1187 | /* END OF MAC REGISTER ADDRESS MAP */ | |
1188 | ||
1189 | /* START OF MAC STAT REGISTER ADDRESS MAP */ | |
1190 | ||
1191 | /* | |
1192 | * structure for Carry Register One and it's Mask Register reg located in mac | |
1193 | * stat address map address 0x6130 and 0x6138. | |
ae8d9d84 AC |
1194 | * |
1195 | * 31: tr64 | |
1196 | * 30: tr127 | |
1197 | * 29: tr255 | |
1198 | * 28: tr511 | |
1199 | * 27: tr1k | |
1200 | * 26: trmax | |
1201 | * 25: trmgv | |
1202 | * 24-17: unused | |
1203 | * 16: rbyt | |
1204 | * 15: rpkt | |
1205 | * 14: rfcs | |
1206 | * 13: rmca | |
1207 | * 12: rbca | |
1208 | * 11: rxcf | |
1209 | * 10: rxpf | |
1210 | * 9: rxuo | |
1211 | * 8: raln | |
1212 | * 7: rflr | |
1213 | * 6: rcde | |
1214 | * 5: rcse | |
1215 | * 4: rund | |
1216 | * 3: rovr | |
1217 | * 2: rfrg | |
1218 | * 1: rjbr | |
1219 | * 0: rdrp | |
cfb739b4 | 1220 | */ |
cfb739b4 GKH |
1221 | |
1222 | /* | |
1223 | * structure for Carry Register Two Mask Register reg in mac stat address map. | |
1224 | * located at address 0x613C | |
ae8d9d84 AC |
1225 | * |
1226 | * 31-20: unused | |
1227 | * 19: tjbr | |
1228 | * 18: tfcs | |
1229 | * 17: txcf | |
1230 | * 16: tovr | |
1231 | * 15: tund | |
1232 | * 14: trfg | |
1233 | * 13: tbyt | |
1234 | * 12: tpkt | |
1235 | * 11: tmca | |
1236 | * 10: tbca | |
1237 | * 9: txpf | |
1238 | * 8: tdfr | |
1239 | * 7: tedf | |
1240 | * 6: tscl | |
1241 | * 5: tmcl | |
1242 | * 4: tlcl | |
1243 | * 3: txcl | |
1244 | * 2: tncl | |
1245 | * 1: tpfh | |
1246 | * 0: tdrp | |
cfb739b4 | 1247 | */ |
cfb739b4 GKH |
1248 | |
1249 | /* | |
1250 | * MAC STATS Module of JAGCore Address Mapping | |
1251 | */ | |
f3fd4cd5 | 1252 | struct macstat_regs { /* Location: */ |
dc26ffc7 | 1253 | u32 pad[32]; /* 0x6000 - 607C */ |
cfb739b4 | 1254 | |
64f93036 AC |
1255 | /* Tx/Rx 0-64 Byte Frame Counter */ |
1256 | u32 TR64; /* 0x6080 */ | |
cfb739b4 | 1257 | |
64f93036 AC |
1258 | /* Tx/Rx 65-127 Byte Frame Counter */ |
1259 | u32 TR127; /* 0x6084 */ | |
cfb739b4 | 1260 | |
64f93036 AC |
1261 | /* Tx/Rx 128-255 Byte Frame Counter */ |
1262 | u32 TR255; /* 0x6088 */ | |
cfb739b4 | 1263 | |
64f93036 AC |
1264 | /* Tx/Rx 256-511 Byte Frame Counter */ |
1265 | u32 TR511; /* 0x608C */ | |
cfb739b4 | 1266 | |
64f93036 AC |
1267 | /* Tx/Rx 512-1023 Byte Frame Counter */ |
1268 | u32 TR1K; /* 0x6090 */ | |
cfb739b4 | 1269 | |
64f93036 AC |
1270 | /* Tx/Rx 1024-1518 Byte Frame Counter */ |
1271 | u32 TRMax; /* 0x6094 */ | |
cfb739b4 | 1272 | |
64f93036 AC |
1273 | /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */ |
1274 | u32 TRMgv; /* 0x6098 */ | |
cfb739b4 | 1275 | |
64f93036 AC |
1276 | /* Rx Byte Counter */ |
1277 | u32 RByt; /* 0x609C */ | |
cfb739b4 | 1278 | |
64f93036 AC |
1279 | /* Rx Packet Counter */ |
1280 | u32 RPkt; /* 0x60A0 */ | |
cfb739b4 | 1281 | |
64f93036 AC |
1282 | /* Rx FCS Error Counter */ |
1283 | u32 RFcs; /* 0x60A4 */ | |
cfb739b4 | 1284 | |
64f93036 AC |
1285 | /* Rx Multicast Packet Counter */ |
1286 | u32 RMca; /* 0x60A8 */ | |
cfb739b4 | 1287 | |
64f93036 AC |
1288 | /* Rx Broadcast Packet Counter */ |
1289 | u32 RBca; /* 0x60AC */ | |
cfb739b4 | 1290 | |
64f93036 AC |
1291 | /* Rx Control Frame Packet Counter */ |
1292 | u32 RxCf; /* 0x60B0 */ | |
cfb739b4 | 1293 | |
64f93036 AC |
1294 | /* Rx Pause Frame Packet Counter */ |
1295 | u32 RxPf; /* 0x60B4 */ | |
cfb739b4 | 1296 | |
64f93036 AC |
1297 | /* Rx Unknown OP Code Counter */ |
1298 | u32 RxUo; /* 0x60B8 */ | |
cfb739b4 | 1299 | |
64f93036 AC |
1300 | /* Rx Alignment Error Counter */ |
1301 | u32 RAln; /* 0x60BC */ | |
cfb739b4 | 1302 | |
64f93036 AC |
1303 | /* Rx Frame Length Error Counter */ |
1304 | u32 RFlr; /* 0x60C0 */ | |
cfb739b4 | 1305 | |
64f93036 AC |
1306 | /* Rx Code Error Counter */ |
1307 | u32 RCde; /* 0x60C4 */ | |
cfb739b4 | 1308 | |
64f93036 AC |
1309 | /* Rx Carrier Sense Error Counter */ |
1310 | u32 RCse; /* 0x60C8 */ | |
cfb739b4 | 1311 | |
64f93036 AC |
1312 | /* Rx Undersize Packet Counter */ |
1313 | u32 RUnd; /* 0x60CC */ | |
cfb739b4 | 1314 | |
64f93036 AC |
1315 | /* Rx Oversize Packet Counter */ |
1316 | u32 ROvr; /* 0x60D0 */ | |
cfb739b4 | 1317 | |
64f93036 AC |
1318 | /* Rx Fragment Counter */ |
1319 | u32 RFrg; /* 0x60D4 */ | |
cfb739b4 | 1320 | |
64f93036 AC |
1321 | /* Rx Jabber Counter */ |
1322 | u32 RJbr; /* 0x60D8 */ | |
cfb739b4 | 1323 | |
64f93036 AC |
1324 | /* Rx Drop */ |
1325 | u32 RDrp; /* 0x60DC */ | |
cfb739b4 | 1326 | |
64f93036 AC |
1327 | /* Tx Byte Counter */ |
1328 | u32 TByt; /* 0x60E0 */ | |
cfb739b4 | 1329 | |
64f93036 AC |
1330 | /* Tx Packet Counter */ |
1331 | u32 TPkt; /* 0x60E4 */ | |
cfb739b4 | 1332 | |
64f93036 AC |
1333 | /* Tx Multicast Packet Counter */ |
1334 | u32 TMca; /* 0x60E8 */ | |
cfb739b4 | 1335 | |
64f93036 AC |
1336 | /* Tx Broadcast Packet Counter */ |
1337 | u32 TBca; /* 0x60EC */ | |
cfb739b4 | 1338 | |
64f93036 AC |
1339 | /* Tx Pause Control Frame Counter */ |
1340 | u32 TxPf; /* 0x60F0 */ | |
cfb739b4 | 1341 | |
64f93036 AC |
1342 | /* Tx Deferral Packet Counter */ |
1343 | u32 TDfr; /* 0x60F4 */ | |
cfb739b4 | 1344 | |
64f93036 AC |
1345 | /* Tx Excessive Deferral Packet Counter */ |
1346 | u32 TEdf; /* 0x60F8 */ | |
cfb739b4 | 1347 | |
64f93036 AC |
1348 | /* Tx Single Collision Packet Counter */ |
1349 | u32 TScl; /* 0x60FC */ | |
cfb739b4 | 1350 | |
64f93036 AC |
1351 | /* Tx Multiple Collision Packet Counter */ |
1352 | u32 TMcl; /* 0x6100 */ | |
cfb739b4 | 1353 | |
64f93036 AC |
1354 | /* Tx Late Collision Packet Counter */ |
1355 | u32 TLcl; /* 0x6104 */ | |
cfb739b4 | 1356 | |
64f93036 AC |
1357 | /* Tx Excessive Collision Packet Counter */ |
1358 | u32 TXcl; /* 0x6108 */ | |
cfb739b4 | 1359 | |
64f93036 AC |
1360 | /* Tx Total Collision Packet Counter */ |
1361 | u32 TNcl; /* 0x610C */ | |
cfb739b4 | 1362 | |
64f93036 AC |
1363 | /* Tx Pause Frame Honored Counter */ |
1364 | u32 TPfh; /* 0x6110 */ | |
cfb739b4 | 1365 | |
64f93036 AC |
1366 | /* Tx Drop Frame Counter */ |
1367 | u32 TDrp; /* 0x6114 */ | |
cfb739b4 | 1368 | |
64f93036 AC |
1369 | /* Tx Jabber Frame Counter */ |
1370 | u32 TJbr; /* 0x6118 */ | |
cfb739b4 | 1371 | |
64f93036 AC |
1372 | /* Tx FCS Error Counter */ |
1373 | u32 TFcs; /* 0x611C */ | |
cfb739b4 | 1374 | |
64f93036 AC |
1375 | /* Tx Control Frame Counter */ |
1376 | u32 TxCf; /* 0x6120 */ | |
cfb739b4 | 1377 | |
64f93036 AC |
1378 | /* Tx Oversize Frame Counter */ |
1379 | u32 TOvr; /* 0x6124 */ | |
cfb739b4 | 1380 | |
64f93036 AC |
1381 | /* Tx Undersize Frame Counter */ |
1382 | u32 TUnd; /* 0x6128 */ | |
cfb739b4 | 1383 | |
64f93036 AC |
1384 | /* Tx Fragments Frame Counter */ |
1385 | u32 TFrg; /* 0x612C */ | |
cfb739b4 | 1386 | |
64f93036 | 1387 | /* Carry Register One Register */ |
ae8d9d84 | 1388 | u32 Carry1; /* 0x6130 */ |
cfb739b4 | 1389 | |
64f93036 | 1390 | /* Carry Register Two Register */ |
ae8d9d84 | 1391 | u32 Carry2; /* 0x6134 */ |
cfb739b4 | 1392 | |
64f93036 | 1393 | /* Carry Register One Mask Register */ |
ae8d9d84 | 1394 | u32 Carry1M; /* 0x6138 */ |
cfb739b4 | 1395 | |
64f93036 | 1396 | /* Carry Register Two Mask Register */ |
ae8d9d84 | 1397 | u32 Carry2M; /* 0x613C */ |
dc26ffc7 | 1398 | }; |
cfb739b4 GKH |
1399 | |
1400 | /* END OF MAC STAT REGISTER ADDRESS MAP */ | |
1401 | ||
1402 | ||
1403 | /* START OF MMC REGISTER ADDRESS MAP */ | |
1404 | ||
1405 | /* | |
e5cf1b75 | 1406 | * Main Memory Controller Control reg in mmc address map. |
cfb739b4 GKH |
1407 | * located at address 0x7000 |
1408 | */ | |
df482a09 AC |
1409 | |
1410 | #define ET_MMC_ENABLE 1 | |
1411 | #define ET_MMC_ARB_DISABLE 2 | |
1412 | #define ET_MMC_RXMAC_DISABLE 4 | |
1413 | #define ET_MMC_TXMAC_DISABLE 8 | |
1414 | #define ET_MMC_TXDMA_DISABLE 16 | |
1415 | #define ET_MMC_RXDMA_DISABLE 32 | |
1416 | #define ET_MMC_FORCE_CE 64 | |
cfb739b4 GKH |
1417 | |
1418 | /* | |
e5cf1b75 AC |
1419 | * Main Memory Controller Host Memory Access Address reg in mmc |
1420 | * address map. Located at address 0x7004. Top 16 bits hold the address bits | |
cfb739b4 | 1421 | */ |
e5cf1b75 AC |
1422 | |
1423 | #define ET_SRAM_REQ_ACCESS 1 | |
1424 | #define ET_SRAM_WR_ACCESS 2 | |
1425 | #define ET_SRAM_IS_CTRL 4 | |
cfb739b4 GKH |
1426 | |
1427 | /* | |
1428 | * structure for Main Memory Controller Host Memory Access Data reg in mmc | |
1429 | * address map. Located at address 0x7008 - 0x7014 | |
1430 | * Defined earlier (u32) | |
1431 | */ | |
1432 | ||
1433 | /* | |
1434 | * Memory Control Module of JAGCore Address Mapping | |
1435 | */ | |
461e0e8b | 1436 | struct mmc_regs { /* Location: */ |
df482a09 | 1437 | u32 mmc_ctrl; /* 0x7000 */ |
e5cf1b75 | 1438 | u32 sram_access; /* 0x7004 */ |
64f93036 AC |
1439 | u32 sram_word1; /* 0x7008 */ |
1440 | u32 sram_word2; /* 0x700C */ | |
1441 | u32 sram_word3; /* 0x7010 */ | |
1442 | u32 sram_word4; /* 0x7014 */ | |
461e0e8b | 1443 | }; |
cfb739b4 GKH |
1444 | |
1445 | /* END OF MMC REGISTER ADDRESS MAP */ | |
1446 | ||
1447 | ||
cfb739b4 GKH |
1448 | /* |
1449 | * JAGCore Address Mapping | |
1450 | */ | |
1451 | typedef struct _ADDRESS_MAP_t { | |
2b903327 | 1452 | struct global_regs global; |
64f93036 | 1453 | /* unused section of global address map */ |
2b903327 | 1454 | u8 unused_global[4096 - sizeof(struct global_regs)]; |
060a78a0 | 1455 | struct txdma_regs txdma; |
64f93036 | 1456 | /* unused section of txdma address map */ |
060a78a0 | 1457 | u8 unused_txdma[4096 - sizeof(struct txdma_regs)]; |
61d5ed8c | 1458 | struct rxdma_regs rxdma; |
64f93036 | 1459 | /* unused section of rxdma address map */ |
61d5ed8c | 1460 | u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)]; |
afa7e5ec | 1461 | struct txmac_regs txmac; |
64f93036 | 1462 | /* unused section of txmac address map */ |
afa7e5ec | 1463 | u8 unused_txmac[4096 - sizeof(struct txmac_regs)]; |
cfb739b4 | 1464 | RXMAC_t rxmac; |
64f93036 | 1465 | /* unused section of rxmac address map */ |
cfb739b4 GKH |
1466 | u8 unused_rxmac[4096 - sizeof(RXMAC_t)]; |
1467 | MAC_t mac; | |
64f93036 | 1468 | /* unused section of mac address map */ |
cfb739b4 | 1469 | u8 unused_mac[4096 - sizeof(MAC_t)]; |
dc26ffc7 | 1470 | struct macstat_regs macstat; |
64f93036 | 1471 | /* unused section of mac stat address map */ |
dc26ffc7 | 1472 | u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)]; |
461e0e8b | 1473 | struct mmc_regs mmc; |
64f93036 | 1474 | /* unused section of mmc address map */ |
461e0e8b | 1475 | u8 unused_mmc[4096 - sizeof(struct mmc_regs)]; |
64f93036 | 1476 | /* unused section of address map */ |
cfb739b4 GKH |
1477 | u8 unused_[1015808]; |
1478 | ||
64f93036 AC |
1479 | u8 unused_exp_rom[4096]; /* MGS-size TBD */ |
1480 | u8 unused__[524288]; /* unused section of address map */ | |
cfb739b4 GKH |
1481 | } ADDRESS_MAP_t, *PADDRESS_MAP_t; |
1482 | ||
1483 | #endif /* _ET1310_ADDRESS_MAP_H_ */ |