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cfb739b4 GKH |
1 | /* |
2 | * Agere Systems Inc. | |
3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs | |
4 | * | |
64f93036 | 5 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
6 | * All rights reserved. |
7 | * http://www.agere.com | |
8 | * | |
9 | *------------------------------------------------------------------------------ | |
10 | * | |
11 | * et1310_eeprom.c - Code used to access the device's EEPROM | |
12 | * | |
13 | *------------------------------------------------------------------------------ | |
14 | * | |
15 | * SOFTWARE LICENSE | |
16 | * | |
17 | * This software is provided subject to the following terms and conditions, | |
18 | * which you should read carefully before using the software. Using this | |
19 | * software indicates your acceptance of these terms and conditions. If you do | |
20 | * not agree with these terms and conditions, do not use the software. | |
21 | * | |
64f93036 | 22 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
23 | * All rights reserved. |
24 | * | |
25 | * Redistribution and use in source or binary forms, with or without | |
26 | * modifications, are permitted provided that the following conditions are met: | |
27 | * | |
28 | * . Redistributions of source code must retain the above copyright notice, this | |
29 | * list of conditions and the following Disclaimer as comments in the code as | |
30 | * well as in the documentation and/or other materials provided with the | |
31 | * distribution. | |
32 | * | |
33 | * . Redistributions in binary form must reproduce the above copyright notice, | |
34 | * this list of conditions and the following Disclaimer in the documentation | |
35 | * and/or other materials provided with the distribution. | |
36 | * | |
37 | * . Neither the name of Agere Systems Inc. nor the names of the contributors | |
38 | * may be used to endorse or promote products derived from this software | |
39 | * without specific prior written permission. | |
40 | * | |
41 | * Disclaimer | |
42 | * | |
64f93036 | 43 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
cfb739b4 GKH |
44 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
45 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY | |
46 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN | |
47 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY | |
48 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
49 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
50 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
51 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT | |
52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
53 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH | |
54 | * DAMAGE. | |
55 | * | |
56 | */ | |
57 | ||
58 | #include "et131x_version.h" | |
cfb739b4 GKH |
59 | #include "et131x_defs.h" |
60 | ||
61 | #include <linux/pci.h> | |
62 | #include <linux/init.h> | |
63 | #include <linux/module.h> | |
64 | #include <linux/types.h> | |
65 | #include <linux/kernel.h> | |
66 | ||
67 | #include <linux/sched.h> | |
68 | #include <linux/ptrace.h> | |
cfb739b4 GKH |
69 | #include <linux/ctype.h> |
70 | #include <linux/string.h> | |
71 | #include <linux/timer.h> | |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/in.h> | |
74 | #include <linux/delay.h> | |
64f93036 AC |
75 | #include <linux/bitops.h> |
76 | #include <linux/io.h> | |
cfb739b4 | 77 | #include <asm/system.h> |
cfb739b4 GKH |
78 | |
79 | #include <linux/netdevice.h> | |
80 | #include <linux/etherdevice.h> | |
81 | #include <linux/skbuff.h> | |
82 | #include <linux/if_arp.h> | |
83 | #include <linux/ioport.h> | |
84 | ||
85 | #include "et1310_phy.h" | |
cfb739b4 | 86 | #include "et131x_adapter.h" |
69ea5fcb AC |
87 | #include "et131x.h" |
88 | ||
89 | /* | |
90 | * EEPROM Defines | |
91 | */ | |
92 | ||
93 | /* LBCIF Register Groups (addressed via 32-bit offsets) */ | |
94 | #define LBCIF_DWORD0_GROUP 0xAC | |
95 | #define LBCIF_DWORD1_GROUP 0xB0 | |
96 | ||
97 | /* LBCIF Registers (addressed via 8-bit offsets) */ | |
98 | #define LBCIF_ADDRESS_REGISTER 0xAC | |
99 | #define LBCIF_DATA_REGISTER 0xB0 | |
100 | #define LBCIF_CONTROL_REGISTER 0xB1 | |
101 | #define LBCIF_STATUS_REGISTER 0xB2 | |
cfb739b4 | 102 | |
69ea5fcb AC |
103 | /* LBCIF Control Register Bits */ |
104 | #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 | |
105 | #define LBCIF_CONTROL_PAGE_WRITE 0x02 | |
106 | #define LBCIF_CONTROL_EEPROM_RELOAD 0x08 | |
107 | #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 | |
108 | #define LBCIF_CONTROL_I2C_WRITE 0x40 | |
109 | #define LBCIF_CONTROL_LBCIF_ENABLE 0x80 | |
cfb739b4 | 110 | |
69ea5fcb AC |
111 | /* LBCIF Status Register Bits */ |
112 | #define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01 | |
113 | #define LBCIF_STATUS_I2C_IDLE 0x02 | |
114 | #define LBCIF_STATUS_ACK_ERROR 0x04 | |
115 | #define LBCIF_STATUS_GENERAL_ERROR 0x08 | |
116 | #define LBCIF_STATUS_CHECKSUM_ERROR 0x40 | |
117 | #define LBCIF_STATUS_EEPROM_PRESENT 0x80 | |
cfb739b4 | 118 | |
69ea5fcb AC |
119 | /* Miscellaneous Constraints */ |
120 | #define MAX_NUM_REGISTER_POLLS 1000 | |
121 | #define MAX_NUM_WRITE_RETRIES 2 | |
cfb739b4 | 122 | |
b802ce0c AC |
123 | static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status) |
124 | { | |
125 | u32 reg; | |
126 | int i; | |
cfb739b4 | 127 | |
b802ce0c AC |
128 | /* |
129 | * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and | |
130 | * bits 7,1:0 both equal to 1, at least once after reset. | |
131 | * Subsequent operations need only to check that bits 1:0 are equal | |
132 | * to 1 prior to starting a single byte read/write | |
133 | */ | |
cfb739b4 | 134 | |
b802ce0c AC |
135 | for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) { |
136 | /* Read registers grouped in DWORD1 */ | |
137 | if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®)) | |
138 | return -EIO; | |
139 | ||
140 | /* I2C idle and Phy Queue Avail both true */ | |
141 | if ((reg & 0x3000) == 0x3000) { | |
142 | if (status) | |
143 | *status = reg; | |
144 | return reg & 0xFF; | |
145 | } | |
146 | } | |
147 | return -ETIMEDOUT; | |
148 | } | |
cfb739b4 | 149 | |
cfb739b4 GKH |
150 | |
151 | /** | |
b802ce0c | 152 | * eeprom_write - Write a byte to the ET1310's EEPROM |
25ad00bb | 153 | * @etdev: pointer to our private adapter structure |
9fa81099 AC |
154 | * @addr: the address to write |
155 | * @data: the value to write | |
cfb739b4 | 156 | * |
53f8aeef | 157 | * Returns 1 for a successful write. |
cfb739b4 | 158 | */ |
4e02b4b5 | 159 | static int eeprom_write(struct et131x_adapter *etdev, u32 addr, u8 data) |
cfb739b4 | 160 | { |
25ad00bb | 161 | struct pci_dev *pdev = etdev->pdev; |
b802ce0c | 162 | int index = 0; |
9fa81099 AC |
163 | int retries; |
164 | int err = 0; | |
165 | int i2c_wack = 0; | |
166 | int writeok = 0; | |
b802ce0c | 167 | u32 status; |
9fa81099 | 168 | u32 val = 0; |
cfb739b4 GKH |
169 | |
170 | /* | |
cfb739b4 GKH |
171 | * For an EEPROM, an I2C single byte write is defined as a START |
172 | * condition followed by the device address, EEPROM address, one byte | |
173 | * of data and a STOP condition. The STOP condition will trigger the | |
174 | * EEPROM's internally timed write cycle to the nonvolatile memory. | |
175 | * All inputs are disabled during this write cycle and the EEPROM will | |
176 | * not respond to any access until the internal write is complete. | |
b802ce0c AC |
177 | */ |
178 | ||
179 | err = eeprom_wait_ready(pdev, NULL); | |
180 | if (err) | |
181 | return err; | |
182 | ||
183 | /* | |
cfb739b4 GKH |
184 | * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0, |
185 | * and bits 1:0 both =0. Bit 5 should be set according to the | |
186 | * type of EEPROM being accessed (1=two byte addressing, 0=one | |
187 | * byte addressing). | |
cfb739b4 | 188 | */ |
b802ce0c AC |
189 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, |
190 | LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE)) | |
191 | return -EIO; | |
cfb739b4 | 192 | |
9fa81099 | 193 | i2c_wack = 1; |
cfb739b4 GKH |
194 | |
195 | /* Prepare EEPROM address for Step 3 */ | |
cfb739b4 | 196 | |
9fa81099 | 197 | for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) { |
b802ce0c AC |
198 | /* Write the address to the LBCIF Address Register */ |
199 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr)) | |
cfb739b4 | 200 | break; |
b802ce0c AC |
201 | /* |
202 | * Write the data to the LBCIF Data Register (the I2C write | |
203 | * will begin). | |
204 | */ | |
205 | if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data)) | |
cfb739b4 | 206 | break; |
b802ce0c AC |
207 | /* |
208 | * Monitor bit 1:0 of the LBCIF Status Register. When bits | |
209 | * 1:0 are both equal to 1, the I2C write has completed and the | |
210 | * internal write cycle of the EEPROM is about to start. | |
211 | * (bits 1:0 = 01 is a legal state while waiting from both | |
212 | * equal to 1, but bits 1:0 = 10 is invalid and implies that | |
213 | * something is broken). | |
214 | */ | |
215 | err = eeprom_wait_ready(pdev, &status); | |
216 | if (err < 0) | |
217 | return 0; | |
cfb739b4 GKH |
218 | |
219 | /* | |
b802ce0c AC |
220 | * Check bit 3 of the LBCIF Status Register. If equal to 1, |
221 | * an error has occurred.Don't break here if we are revision | |
222 | * 1, this is so we do a blind write for load bug. | |
64f93036 | 223 | */ |
b802ce0c AC |
224 | if ((status & LBCIF_STATUS_GENERAL_ERROR) |
225 | && etdev->pdev->revision == 0) | |
cfb739b4 | 226 | break; |
cfb739b4 | 227 | |
b802ce0c AC |
228 | /* |
229 | * Check bit 2 of the LBCIF Status Register. If equal to 1 an | |
230 | * ACK error has occurred on the address phase of the write. | |
231 | * This could be due to an actual hardware failure or the | |
232 | * EEPROM may still be in its internal write cycle from a | |
233 | * previous write. This write operation was ignored and must be | |
234 | *repeated later. | |
235 | */ | |
9fa81099 | 236 | if (status & LBCIF_STATUS_ACK_ERROR) { |
cfb739b4 GKH |
237 | /* |
238 | * This could be due to an actual hardware failure | |
239 | * or the EEPROM may still be in its internal write | |
240 | * cycle from a previous write. This write operation | |
241 | * was ignored and must be repeated later. | |
242 | */ | |
243 | udelay(10); | |
244 | continue; | |
245 | } | |
246 | ||
9fa81099 | 247 | writeok = 1; |
cfb739b4 GKH |
248 | break; |
249 | } | |
250 | ||
b802ce0c AC |
251 | /* |
252 | * Set bit 6 of the LBCIF Control Register = 0. | |
253 | */ | |
cfb739b4 | 254 | udelay(10); |
cfb739b4 | 255 | |
b802ce0c AC |
256 | while (i2c_wack) { |
257 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, | |
258 | LBCIF_CONTROL_LBCIF_ENABLE)) | |
9fa81099 | 259 | writeok = 0; |
cfb739b4 GKH |
260 | |
261 | /* Do read until internal ACK_ERROR goes away meaning write | |
262 | * completed | |
263 | */ | |
264 | do { | |
265 | pci_write_config_dword(pdev, | |
b802ce0c | 266 | LBCIF_ADDRESS_REGISTER, |
9fa81099 | 267 | addr); |
cfb739b4 GKH |
268 | do { |
269 | pci_read_config_dword(pdev, | |
b802ce0c | 270 | LBCIF_DATA_REGISTER, &val); |
9fa81099 AC |
271 | } while ((val & 0x00010000) == 0); |
272 | } while (val & 0x00040000); | |
cfb739b4 | 273 | |
b802ce0c | 274 | if ((val & 0xFF00) != 0xC000 || index == 10000) |
cfb739b4 | 275 | break; |
9fa81099 | 276 | index++; |
cfb739b4 | 277 | } |
b802ce0c | 278 | return writeok ? 0 : -EIO; |
cfb739b4 GKH |
279 | } |
280 | ||
281 | /** | |
b802ce0c | 282 | * eeprom_read - Read a byte from the ET1310's EEPROM |
25ad00bb | 283 | * @etdev: pointer to our private adapter structure |
9fa81099 AC |
284 | * @addr: the address from which to read |
285 | * @pdata: a pointer to a byte in which to store the value of the read | |
286 | * @eeprom_id: the ID of the EEPROM | |
287 | * @addrmode: how the EEPROM is to be accessed | |
cfb739b4 | 288 | * |
53f8aeef | 289 | * Returns 1 for a successful read |
cfb739b4 | 290 | */ |
4e02b4b5 | 291 | static int eeprom_read(struct et131x_adapter *etdev, u32 addr, u8 *pdata) |
cfb739b4 | 292 | { |
25ad00bb | 293 | struct pci_dev *pdev = etdev->pdev; |
b802ce0c AC |
294 | int err; |
295 | u32 status; | |
cfb739b4 GKH |
296 | |
297 | /* | |
cfb739b4 GKH |
298 | * A single byte read is similar to the single byte write, with the |
299 | * exception of the data flow: | |
cfb739b4 GKH |
300 | */ |
301 | ||
b802ce0c AC |
302 | err = eeprom_wait_ready(pdev, NULL); |
303 | if (err) | |
304 | return err; | |
305 | /* | |
306 | * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0, | |
307 | * and bits 1:0 both =0. Bit 5 should be set according to the type | |
308 | * of EEPROM being accessed (1=two byte addressing, 0=one byte | |
309 | * addressing). | |
310 | */ | |
311 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, | |
312 | LBCIF_CONTROL_LBCIF_ENABLE)) | |
313 | return -EIO; | |
314 | /* | |
315 | * Write the address to the LBCIF Address Register (I2C read will | |
316 | * begin). | |
317 | */ | |
318 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr)) | |
319 | return -EIO; | |
320 | /* | |
321 | * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read | |
322 | * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure | |
323 | * has occurred). | |
324 | */ | |
325 | err = eeprom_wait_ready(pdev, &status); | |
326 | if (err < 0) | |
327 | return err; | |
328 | /* | |
329 | * Regardless of error status, read data byte from LBCIF Data | |
330 | * Register. | |
331 | */ | |
332 | *pdata = err; | |
333 | /* | |
334 | * Check bit 2 of the LBCIF Status Register. If = 1, | |
335 | * then an error has occurred. | |
336 | */ | |
337 | return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0; | |
cfb739b4 | 338 | } |
4e02b4b5 AC |
339 | |
340 | int et131x_init_eeprom(struct et131x_adapter *etdev) | |
341 | { | |
342 | struct pci_dev *pdev = etdev->pdev; | |
343 | u8 eestatus; | |
344 | ||
345 | /* We first need to check the EEPROM Status code located at offset | |
346 | * 0xB2 of config space | |
347 | */ | |
348 | pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, | |
349 | &eestatus); | |
350 | ||
351 | /* THIS IS A WORKAROUND: | |
352 | * I need to call this function twice to get my card in a | |
353 | * LG M1 Express Dual running. I tried also a msleep before this | |
354 | * function, because I thougth there could be some time condidions | |
355 | * but it didn't work. Call the whole function twice also work. | |
356 | */ | |
357 | if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) { | |
358 | dev_err(&pdev->dev, | |
359 | "Could not read PCI config space for EEPROM Status\n"); | |
360 | return -EIO; | |
361 | } | |
362 | ||
363 | /* Determine if the error(s) we care about are present. If they are | |
364 | * present we need to fail. | |
365 | */ | |
366 | if (eestatus & 0x4C) { | |
367 | int write_failed = 0; | |
368 | if (pdev->revision == 0x01) { | |
369 | int i; | |
370 | static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF }; | |
371 | ||
372 | /* Re-write the first 4 bytes if we have an eeprom | |
373 | * present and the revision id is 1, this fixes the | |
374 | * corruption seen with 1310 B Silicon | |
375 | */ | |
376 | for (i = 0; i < 3; i++) | |
377 | if (eeprom_write(etdev, i, eedata[i]) < 0) | |
378 | write_failed = 1; | |
379 | } | |
380 | if (pdev->revision != 0x01 || write_failed) { | |
381 | dev_err(&pdev->dev, | |
382 | "Fatal EEPROM Status Error - 0x%04x\n", eestatus); | |
383 | ||
384 | /* This error could mean that there was an error | |
385 | * reading the eeprom or that the eeprom doesn't exist. | |
386 | * We will treat each case the same and not try to gather | |
387 | * additional information that normally would come from the | |
388 | * eeprom, like MAC Address | |
389 | */ | |
390 | etdev->has_eeprom = 0; | |
391 | return -EIO; | |
392 | } | |
393 | } | |
394 | etdev->has_eeprom = 1; | |
395 | ||
396 | /* Read the EEPROM for information regarding LED behavior. Refer to | |
397 | * ET1310_phy.c, et131x_xcvr_init(), for its use. | |
398 | */ | |
399 | eeprom_read(etdev, 0x70, &etdev->eepromData[0]); | |
400 | eeprom_read(etdev, 0x71, &etdev->eepromData[1]); | |
401 | ||
402 | if (etdev->eepromData[0] != 0xcd) | |
403 | /* Disable all optional features */ | |
404 | etdev->eepromData[1] = 0x00; | |
405 | ||
406 | return 0; | |
407 | } |