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cfb739b4 GKH |
1 | /* |
2 | * Agere Systems Inc. | |
3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs | |
4 | * | |
64f93036 | 5 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
6 | * All rights reserved. |
7 | * http://www.agere.com | |
8 | * | |
9 | *------------------------------------------------------------------------------ | |
10 | * | |
11 | * et1310_mac.c - All code and routines pertaining to the MAC | |
12 | * | |
13 | *------------------------------------------------------------------------------ | |
14 | * | |
15 | * SOFTWARE LICENSE | |
16 | * | |
17 | * This software is provided subject to the following terms and conditions, | |
18 | * which you should read carefully before using the software. Using this | |
19 | * software indicates your acceptance of these terms and conditions. If you do | |
20 | * not agree with these terms and conditions, do not use the software. | |
21 | * | |
64f93036 | 22 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
23 | * All rights reserved. |
24 | * | |
25 | * Redistribution and use in source or binary forms, with or without | |
26 | * modifications, are permitted provided that the following conditions are met: | |
27 | * | |
28 | * . Redistributions of source code must retain the above copyright notice, this | |
29 | * list of conditions and the following Disclaimer as comments in the code as | |
30 | * well as in the documentation and/or other materials provided with the | |
31 | * distribution. | |
32 | * | |
33 | * . Redistributions in binary form must reproduce the above copyright notice, | |
34 | * this list of conditions and the following Disclaimer in the documentation | |
35 | * and/or other materials provided with the distribution. | |
36 | * | |
37 | * . Neither the name of Agere Systems Inc. nor the names of the contributors | |
38 | * may be used to endorse or promote products derived from this software | |
39 | * without specific prior written permission. | |
40 | * | |
41 | * Disclaimer | |
42 | * | |
64f93036 | 43 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
cfb739b4 GKH |
44 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
45 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY | |
46 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN | |
47 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY | |
48 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
49 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
50 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
51 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT | |
52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
53 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH | |
54 | * DAMAGE. | |
55 | * | |
56 | */ | |
57 | ||
58 | #include "et131x_version.h" | |
cfb739b4 GKH |
59 | #include "et131x_defs.h" |
60 | ||
61 | #include <linux/init.h> | |
62 | #include <linux/module.h> | |
63 | #include <linux/types.h> | |
64 | #include <linux/kernel.h> | |
65 | ||
66 | #include <linux/sched.h> | |
67 | #include <linux/ptrace.h> | |
68 | #include <linux/slab.h> | |
69 | #include <linux/ctype.h> | |
70 | #include <linux/string.h> | |
71 | #include <linux/timer.h> | |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/in.h> | |
74 | #include <linux/delay.h> | |
64f93036 AC |
75 | #include <linux/io.h> |
76 | #include <linux/bitops.h> | |
15700039 | 77 | #include <linux/pci.h> |
cfb739b4 | 78 | #include <asm/system.h> |
cfb739b4 GKH |
79 | |
80 | #include <linux/netdevice.h> | |
81 | #include <linux/etherdevice.h> | |
82 | #include <linux/skbuff.h> | |
83 | #include <linux/if_arp.h> | |
84 | #include <linux/ioport.h> | |
85 | #include <linux/crc32.h> | |
86 | ||
87 | #include "et1310_phy.h" | |
88 | #include "et1310_pm.h" | |
89 | #include "et1310_jagcore.h" | |
90 | #include "et1310_mac.h" | |
91 | ||
92 | #include "et131x_adapter.h" | |
93 | #include "et131x_initpci.h" | |
94 | ||
cfb739b4 GKH |
95 | /** |
96 | * ConfigMacRegs1 - Initialize the first part of MAC regs | |
97 | * @pAdpater: pointer to our adapter structure | |
98 | */ | |
25ad00bb | 99 | void ConfigMACRegs1(struct et131x_adapter *etdev) |
cfb739b4 | 100 | { |
f3f415a3 | 101 | struct _MAC_t __iomem *pMac = &etdev->regs->mac; |
cfb739b4 GKH |
102 | MAC_STATION_ADDR1_t station1; |
103 | MAC_STATION_ADDR2_t station2; | |
308e93e0 | 104 | u32 ipg; |
cfb739b4 GKH |
105 | MAC_HFDP_t hfdp; |
106 | MII_MGMT_CFG_t mii_mgmt_cfg; | |
107 | ||
cfb739b4 GKH |
108 | /* First we need to reset everything. Write to MAC configuration |
109 | * register 1 to perform reset. | |
110 | */ | |
111 | writel(0xC00F0000, &pMac->cfg1.value); | |
112 | ||
113 | /* Next lets configure the MAC Inter-packet gap register */ | |
308e93e0 AC |
114 | ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */ |
115 | ipg |= 0x50 << 8; /* ifg enforce 0x50 */ | |
116 | writel(ipg, &pMac->ipg); | |
cfb739b4 GKH |
117 | |
118 | /* Next lets configure the MAC Half Duplex register */ | |
119 | hfdp.bits.alt_beb_trunc = 0xA; | |
120 | hfdp.bits.alt_beb_enable = 0x0; | |
121 | hfdp.bits.bp_no_backoff = 0x0; | |
122 | hfdp.bits.no_backoff = 0x0; | |
123 | hfdp.bits.excess_defer = 0x1; | |
124 | hfdp.bits.rexmit_max = 0xF; | |
64f93036 | 125 | hfdp.bits.coll_window = 0x37; /* 55d */ |
cfb739b4 GKH |
126 | writel(hfdp.value, &pMac->hfdp.value); |
127 | ||
128 | /* Next lets configure the MAC Interface Control register */ | |
129 | writel(0, &pMac->if_ctrl.value); | |
130 | ||
658ce9d6 | 131 | /* Let's move on to setting up the mii management configuration */ |
cfb739b4 GKH |
132 | mii_mgmt_cfg.bits.reset_mii_mgmt = 0; |
133 | mii_mgmt_cfg.bits.scan_auto_incremt = 0; | |
134 | mii_mgmt_cfg.bits.preamble_suppress = 0; | |
135 | mii_mgmt_cfg.bits.mgmt_clk_reset = 0x7; | |
136 | writel(mii_mgmt_cfg.value, &pMac->mii_mgmt_cfg.value); | |
137 | ||
138 | /* Next lets configure the MAC Station Address register. These | |
139 | * values are read from the EEPROM during initialization and stored | |
140 | * in the adapter structure. We write what is stored in the adapter | |
141 | * structure to the MAC Station Address registers high and low. This | |
142 | * station address is used for generating and checking pause control | |
143 | * packets. | |
144 | */ | |
25ad00bb AC |
145 | station2.bits.Octet1 = etdev->CurrentAddress[0]; |
146 | station2.bits.Octet2 = etdev->CurrentAddress[1]; | |
147 | station1.bits.Octet3 = etdev->CurrentAddress[2]; | |
148 | station1.bits.Octet4 = etdev->CurrentAddress[3]; | |
149 | station1.bits.Octet5 = etdev->CurrentAddress[4]; | |
150 | station1.bits.Octet6 = etdev->CurrentAddress[5]; | |
cfb739b4 GKH |
151 | writel(station1.value, &pMac->station_addr_1.value); |
152 | writel(station2.value, &pMac->station_addr_2.value); | |
153 | ||
154 | /* Max ethernet packet in bytes that will passed by the mac without | |
155 | * being truncated. Allow the MAC to pass 4 more than our max packet | |
156 | * size. This is 4 for the Ethernet CRC. | |
157 | * | |
158 | * Packets larger than (RegistryJumboPacket) that do not contain a | |
159 | * VLAN ID will be dropped by the Rx function. | |
160 | */ | |
25ad00bb | 161 | writel(etdev->RegistryJumboPacket + 4, &pMac->max_fm_len.value); |
cfb739b4 GKH |
162 | |
163 | /* clear out MAC config reset */ | |
164 | writel(0, &pMac->cfg1.value); | |
cfb739b4 GKH |
165 | } |
166 | ||
167 | /** | |
168 | * ConfigMacRegs2 - Initialize the second part of MAC regs | |
169 | * @pAdpater: pointer to our adapter structure | |
170 | */ | |
25ad00bb | 171 | void ConfigMACRegs2(struct et131x_adapter *etdev) |
cfb739b4 GKH |
172 | { |
173 | int32_t delay = 0; | |
f3f415a3 | 174 | struct _MAC_t __iomem *pMac = &etdev->regs->mac; |
cfb739b4 GKH |
175 | MAC_CFG1_t cfg1; |
176 | MAC_CFG2_t cfg2; | |
177 | MAC_IF_CTRL_t ifctrl; | |
178 | TXMAC_CTL_t ctl; | |
179 | ||
f3f415a3 | 180 | ctl.value = readl(&etdev->regs->txmac.ctl.value); |
cfb739b4 GKH |
181 | cfg1.value = readl(&pMac->cfg1.value); |
182 | cfg2.value = readl(&pMac->cfg2.value); | |
183 | ifctrl.value = readl(&pMac->if_ctrl.value); | |
184 | ||
9fa81099 | 185 | if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) { |
cfb739b4 GKH |
186 | cfg2.bits.if_mode = 0x2; |
187 | ifctrl.bits.phy_mode = 0x0; | |
188 | } else { | |
189 | cfg2.bits.if_mode = 0x1; | |
190 | ifctrl.bits.phy_mode = 0x1; | |
191 | } | |
192 | ||
193 | /* We need to enable Rx/Tx */ | |
194 | cfg1.bits.rx_enable = 0x1; | |
195 | cfg1.bits.tx_enable = 0x1; | |
196 | ||
197 | /* Set up flow control */ | |
198 | cfg1.bits.tx_flow = 0x1; | |
199 | ||
25ad00bb AC |
200 | if ((etdev->FlowControl == RxOnly) || |
201 | (etdev->FlowControl == Both)) { | |
cfb739b4 GKH |
202 | cfg1.bits.rx_flow = 0x1; |
203 | } else { | |
204 | cfg1.bits.rx_flow = 0x0; | |
205 | } | |
206 | ||
207 | /* Initialize loop back to off */ | |
208 | cfg1.bits.loop_back = 0; | |
209 | ||
210 | writel(cfg1.value, &pMac->cfg1.value); | |
211 | ||
212 | /* Now we need to initialize the MAC Configuration 2 register */ | |
213 | cfg2.bits.preamble_len = 0x7; | |
214 | cfg2.bits.huge_frame = 0x0; | |
215 | /* LENGTH FIELD CHECKING bit4: Set this bit to cause the MAC to check | |
216 | * the frame's length field to ensure it matches the actual data | |
217 | * field length. Clear this bit if no length field checking is | |
218 | * desired. Its default is 0. | |
219 | */ | |
220 | cfg2.bits.len_check = 0x1; | |
221 | ||
5f1377d4 AC |
222 | cfg2.bits.pad_crc = 0x1; |
223 | cfg2.bits.crc_enable = 0x1; | |
cfb739b4 GKH |
224 | |
225 | /* 1 - full duplex, 0 - half-duplex */ | |
9fa81099 AC |
226 | cfg2.bits.full_duplex = etdev->duplex_mode; |
227 | ifctrl.bits.ghd_mode = !etdev->duplex_mode; | |
cfb739b4 GKH |
228 | |
229 | writel(ifctrl.value, &pMac->if_ctrl.value); | |
230 | writel(cfg2.value, &pMac->cfg2.value); | |
231 | ||
232 | do { | |
233 | udelay(10); | |
234 | delay++; | |
235 | cfg1.value = readl(&pMac->cfg1.value); | |
64f93036 AC |
236 | } while ((!cfg1.bits.syncd_rx_en || !cfg1.bits.syncd_tx_en) && |
237 | delay < 100); | |
cfb739b4 GKH |
238 | |
239 | if (delay == 100) { | |
15700039 | 240 | dev_warn(&etdev->pdev->dev, |
64f93036 AC |
241 | "Syncd bits did not respond correctly cfg1 word 0x%08x\n", |
242 | cfg1.value); | |
cfb739b4 GKH |
243 | } |
244 | ||
cfb739b4 GKH |
245 | /* Enable TXMAC */ |
246 | ctl.bits.txmac_en = 0x1; | |
247 | ctl.bits.fc_disable = 0x1; | |
f3f415a3 | 248 | writel(ctl.value, &etdev->regs->txmac.ctl.value); |
cfb739b4 GKH |
249 | |
250 | /* Ready to start the RXDMA/TXDMA engine */ | |
f6b35d66 | 251 | if (etdev->Flags & fMP_ADAPTER_LOWER_POWER) { |
25ad00bb AC |
252 | et131x_rx_dma_enable(etdev); |
253 | et131x_tx_dma_enable(etdev); | |
cfb739b4 | 254 | } |
cfb739b4 GKH |
255 | } |
256 | ||
25ad00bb | 257 | void ConfigRxMacRegs(struct et131x_adapter *etdev) |
cfb739b4 | 258 | { |
f3f415a3 | 259 | struct _RXMAC_t __iomem *pRxMac = &etdev->regs->rxmac; |
cfb739b4 GKH |
260 | RXMAC_WOL_SA_LO_t sa_lo; |
261 | RXMAC_WOL_SA_HI_t sa_hi; | |
262 | RXMAC_PF_CTRL_t pf_ctrl = { 0 }; | |
263 | ||
cfb739b4 GKH |
264 | /* Disable the MAC while it is being configured (also disable WOL) */ |
265 | writel(0x8, &pRxMac->ctrl.value); | |
266 | ||
267 | /* Initialize WOL to disabled. */ | |
268 | writel(0, &pRxMac->crc0.value); | |
269 | writel(0, &pRxMac->crc12.value); | |
270 | writel(0, &pRxMac->crc34.value); | |
271 | ||
272 | /* We need to set the WOL mask0 - mask4 next. We initialize it to | |
273 | * its default Values of 0x00000000 because there are not WOL masks | |
274 | * as of this time. | |
275 | */ | |
276 | writel(0, &pRxMac->mask0_word0); | |
277 | writel(0, &pRxMac->mask0_word1); | |
278 | writel(0, &pRxMac->mask0_word2); | |
279 | writel(0, &pRxMac->mask0_word3); | |
280 | ||
281 | writel(0, &pRxMac->mask1_word0); | |
282 | writel(0, &pRxMac->mask1_word1); | |
283 | writel(0, &pRxMac->mask1_word2); | |
284 | writel(0, &pRxMac->mask1_word3); | |
285 | ||
286 | writel(0, &pRxMac->mask2_word0); | |
287 | writel(0, &pRxMac->mask2_word1); | |
288 | writel(0, &pRxMac->mask2_word2); | |
289 | writel(0, &pRxMac->mask2_word3); | |
290 | ||
291 | writel(0, &pRxMac->mask3_word0); | |
292 | writel(0, &pRxMac->mask3_word1); | |
293 | writel(0, &pRxMac->mask3_word2); | |
294 | writel(0, &pRxMac->mask3_word3); | |
295 | ||
296 | writel(0, &pRxMac->mask4_word0); | |
297 | writel(0, &pRxMac->mask4_word1); | |
298 | writel(0, &pRxMac->mask4_word2); | |
299 | writel(0, &pRxMac->mask4_word3); | |
300 | ||
301 | /* Lets setup the WOL Source Address */ | |
25ad00bb AC |
302 | sa_lo.bits.sa3 = etdev->CurrentAddress[2]; |
303 | sa_lo.bits.sa4 = etdev->CurrentAddress[3]; | |
304 | sa_lo.bits.sa5 = etdev->CurrentAddress[4]; | |
305 | sa_lo.bits.sa6 = etdev->CurrentAddress[5]; | |
cfb739b4 GKH |
306 | writel(sa_lo.value, &pRxMac->sa_lo.value); |
307 | ||
25ad00bb AC |
308 | sa_hi.bits.sa1 = etdev->CurrentAddress[0]; |
309 | sa_hi.bits.sa2 = etdev->CurrentAddress[1]; | |
cfb739b4 GKH |
310 | writel(sa_hi.value, &pRxMac->sa_hi.value); |
311 | ||
312 | /* Disable all Packet Filtering */ | |
313 | writel(0, &pRxMac->pf_ctrl.value); | |
314 | ||
315 | /* Let's initialize the Unicast Packet filtering address */ | |
25ad00bb AC |
316 | if (etdev->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) { |
317 | SetupDeviceForUnicast(etdev); | |
cfb739b4 GKH |
318 | pf_ctrl.bits.filter_uni_en = 1; |
319 | } else { | |
320 | writel(0, &pRxMac->uni_pf_addr1.value); | |
321 | writel(0, &pRxMac->uni_pf_addr2.value); | |
322 | writel(0, &pRxMac->uni_pf_addr3.value); | |
323 | } | |
324 | ||
325 | /* Let's initialize the Multicast hash */ | |
25ad00bb | 326 | if (etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) { |
cfb739b4 GKH |
327 | pf_ctrl.bits.filter_multi_en = 0; |
328 | } else { | |
329 | pf_ctrl.bits.filter_multi_en = 1; | |
25ad00bb | 330 | SetupDeviceForMulticast(etdev); |
cfb739b4 GKH |
331 | } |
332 | ||
333 | /* Runt packet filtering. Didn't work in version A silicon. */ | |
334 | pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4; | |
335 | pf_ctrl.bits.filter_frag_en = 1; | |
336 | ||
25ad00bb | 337 | if (etdev->RegistryJumboPacket > 8192) { |
cfb739b4 GKH |
338 | RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; |
339 | ||
340 | /* In order to transmit jumbo packets greater than 8k, the | |
341 | * FIFO between RxMAC and RxDMA needs to be reduced in size | |
342 | * to (16k - Jumbo packet size). In order to implement this, | |
343 | * we must use "cut through" mode in the RxMAC, which chops | |
344 | * packets down into segments which are (max_size * 16). In | |
345 | * this case we selected 256 bytes, since this is the size of | |
346 | * the PCI-Express TLP's that the 1310 uses. | |
347 | */ | |
348 | mcif_ctrl_max_seg.bits.seg_en = 0x1; | |
349 | mcif_ctrl_max_seg.bits.fc_en = 0x0; | |
350 | mcif_ctrl_max_seg.bits.max_size = 0x10; | |
351 | ||
352 | writel(mcif_ctrl_max_seg.value, | |
353 | &pRxMac->mcif_ctrl_max_seg.value); | |
354 | } else { | |
355 | writel(0, &pRxMac->mcif_ctrl_max_seg.value); | |
356 | } | |
357 | ||
358 | /* Initialize the MCIF water marks */ | |
359 | writel(0, &pRxMac->mcif_water_mark.value); | |
360 | ||
361 | /* Initialize the MIF control */ | |
362 | writel(0, &pRxMac->mif_ctrl.value); | |
363 | ||
364 | /* Initialize the Space Available Register */ | |
365 | writel(0, &pRxMac->space_avail.value); | |
366 | ||
367 | /* Initialize the the mif_ctrl register | |
368 | * bit 3: Receive code error. One or more nibbles were signaled as | |
369 | * errors during the reception of the packet. Clear this | |
370 | * bit in Gigabit, set it in 100Mbit. This was derived | |
371 | * experimentally at UNH. | |
372 | * bit 4: Receive CRC error. The packet's CRC did not match the | |
373 | * internally generated CRC. | |
374 | * bit 5: Receive length check error. Indicates that frame length | |
375 | * field value in the packet does not match the actual data | |
376 | * byte length and is not a type field. | |
377 | * bit 16: Receive frame truncated. | |
378 | * bit 17: Drop packet enable | |
379 | */ | |
9fa81099 | 380 | if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS) |
cfb739b4 | 381 | writel(0x30038, &pRxMac->mif_ctrl.value); |
64f93036 | 382 | else |
cfb739b4 | 383 | writel(0x30030, &pRxMac->mif_ctrl.value); |
cfb739b4 GKH |
384 | |
385 | /* Finally we initialize RxMac to be enabled & WOL disabled. Packet | |
386 | * filter is always enabled since it is where the runt packets are | |
387 | * supposed to be dropped. For version A silicon, runt packet | |
388 | * dropping doesn't work, so it is disabled in the pf_ctrl register, | |
389 | * but we still leave the packet filter on. | |
390 | */ | |
391 | writel(pf_ctrl.value, &pRxMac->pf_ctrl.value); | |
392 | writel(0x9, &pRxMac->ctrl.value); | |
cfb739b4 GKH |
393 | } |
394 | ||
25ad00bb | 395 | void ConfigTxMacRegs(struct et131x_adapter *etdev) |
cfb739b4 | 396 | { |
f3f415a3 | 397 | struct _TXMAC_t __iomem *pTxMac = &etdev->regs->txmac; |
cfb739b4 GKH |
398 | TXMAC_CF_PARAM_t Local; |
399 | ||
cfb739b4 GKH |
400 | /* We need to update the Control Frame Parameters |
401 | * cfpt - control frame pause timer set to 64 (0x40) | |
402 | * cfep - control frame extended pause timer set to 0x0 | |
403 | */ | |
25ad00bb | 404 | if (etdev->FlowControl == None) { |
cfb739b4 GKH |
405 | writel(0, &pTxMac->cf_param.value); |
406 | } else { | |
407 | Local.bits.cfpt = 0x40; | |
408 | Local.bits.cfep = 0x0; | |
409 | writel(Local.value, &pTxMac->cf_param.value); | |
410 | } | |
cfb739b4 GKH |
411 | } |
412 | ||
25ad00bb | 413 | void ConfigMacStatRegs(struct et131x_adapter *etdev) |
cfb739b4 GKH |
414 | { |
415 | struct _MAC_STAT_t __iomem *pDevMacStat = | |
f3f415a3 | 416 | &etdev->regs->macStat; |
cfb739b4 | 417 | |
cfb739b4 GKH |
418 | /* Next we need to initialize all the MAC_STAT registers to zero on |
419 | * the device. | |
420 | */ | |
421 | writel(0, &pDevMacStat->RFcs); | |
422 | writel(0, &pDevMacStat->RAln); | |
423 | writel(0, &pDevMacStat->RFlr); | |
424 | writel(0, &pDevMacStat->RDrp); | |
425 | writel(0, &pDevMacStat->RCde); | |
426 | writel(0, &pDevMacStat->ROvr); | |
427 | writel(0, &pDevMacStat->RFrg); | |
428 | ||
429 | writel(0, &pDevMacStat->TScl); | |
430 | writel(0, &pDevMacStat->TDfr); | |
431 | writel(0, &pDevMacStat->TMcl); | |
432 | writel(0, &pDevMacStat->TLcl); | |
433 | writel(0, &pDevMacStat->TNcl); | |
434 | writel(0, &pDevMacStat->TOvr); | |
435 | writel(0, &pDevMacStat->TUnd); | |
436 | ||
437 | /* Unmask any counters that we want to track the overflow of. | |
438 | * Initially this will be all counters. It may become clear later | |
439 | * that we do not need to track all counters. | |
440 | */ | |
441 | { | |
442 | MAC_STAT_REG_1_t Carry1M = { 0xffffffff }; | |
443 | ||
444 | Carry1M.bits.rdrp = 0; | |
445 | Carry1M.bits.rjbr = 1; | |
446 | Carry1M.bits.rfrg = 0; | |
447 | Carry1M.bits.rovr = 0; | |
448 | Carry1M.bits.rund = 1; | |
449 | Carry1M.bits.rcse = 1; | |
450 | Carry1M.bits.rcde = 0; | |
451 | Carry1M.bits.rflr = 0; | |
452 | Carry1M.bits.raln = 0; | |
453 | Carry1M.bits.rxuo = 1; | |
454 | Carry1M.bits.rxpf = 1; | |
455 | Carry1M.bits.rxcf = 1; | |
456 | Carry1M.bits.rbca = 1; | |
457 | Carry1M.bits.rmca = 1; | |
458 | Carry1M.bits.rfcs = 0; | |
459 | Carry1M.bits.rpkt = 1; | |
460 | Carry1M.bits.rbyt = 1; | |
461 | Carry1M.bits.trmgv = 1; | |
462 | Carry1M.bits.trmax = 1; | |
463 | Carry1M.bits.tr1k = 1; | |
464 | Carry1M.bits.tr511 = 1; | |
465 | Carry1M.bits.tr255 = 1; | |
466 | Carry1M.bits.tr127 = 1; | |
467 | Carry1M.bits.tr64 = 1; | |
468 | ||
469 | writel(Carry1M.value, &pDevMacStat->Carry1M.value); | |
470 | } | |
471 | ||
472 | { | |
473 | MAC_STAT_REG_2_t Carry2M = { 0xffffffff }; | |
474 | ||
475 | Carry2M.bits.tdrp = 1; | |
476 | Carry2M.bits.tpfh = 1; | |
477 | Carry2M.bits.tncl = 0; | |
478 | Carry2M.bits.txcl = 1; | |
479 | Carry2M.bits.tlcl = 0; | |
480 | Carry2M.bits.tmcl = 0; | |
481 | Carry2M.bits.tscl = 0; | |
482 | Carry2M.bits.tedf = 1; | |
483 | Carry2M.bits.tdfr = 0; | |
484 | Carry2M.bits.txpf = 1; | |
485 | Carry2M.bits.tbca = 1; | |
486 | Carry2M.bits.tmca = 1; | |
487 | Carry2M.bits.tpkt = 1; | |
488 | Carry2M.bits.tbyt = 1; | |
489 | Carry2M.bits.tfrg = 1; | |
490 | Carry2M.bits.tund = 0; | |
491 | Carry2M.bits.tovr = 0; | |
492 | Carry2M.bits.txcf = 1; | |
493 | Carry2M.bits.tfcs = 1; | |
494 | Carry2M.bits.tjbr = 1; | |
495 | ||
496 | writel(Carry2M.value, &pDevMacStat->Carry2M.value); | |
497 | } | |
cfb739b4 GKH |
498 | } |
499 | ||
25ad00bb | 500 | void ConfigFlowControl(struct et131x_adapter *etdev) |
cfb739b4 | 501 | { |
9fa81099 | 502 | if (etdev->duplex_mode == 0) { |
25ad00bb | 503 | etdev->FlowControl = None; |
cfb739b4 GKH |
504 | } else { |
505 | char RemotePause, RemoteAsyncPause; | |
506 | ||
25ad00bb | 507 | ET1310_PhyAccessMiBit(etdev, |
cfb739b4 | 508 | TRUEPHY_BIT_READ, 5, 10, &RemotePause); |
25ad00bb | 509 | ET1310_PhyAccessMiBit(etdev, |
cfb739b4 GKH |
510 | TRUEPHY_BIT_READ, 5, 11, |
511 | &RemoteAsyncPause); | |
512 | ||
513 | if ((RemotePause == TRUEPHY_BIT_SET) && | |
514 | (RemoteAsyncPause == TRUEPHY_BIT_SET)) { | |
25ad00bb | 515 | etdev->FlowControl = etdev->RegistryFlowControl; |
cfb739b4 GKH |
516 | } else if ((RemotePause == TRUEPHY_BIT_SET) && |
517 | (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) { | |
25ad00bb AC |
518 | if (etdev->RegistryFlowControl == Both) |
519 | etdev->FlowControl = Both; | |
64f93036 | 520 | else |
25ad00bb | 521 | etdev->FlowControl = None; |
cfb739b4 GKH |
522 | } else if ((RemotePause == TRUEPHY_BIT_CLEAR) && |
523 | (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) { | |
25ad00bb | 524 | etdev->FlowControl = None; |
cfb739b4 GKH |
525 | } else {/* if (RemotePause == TRUEPHY_CLEAR_BIT && |
526 | RemoteAsyncPause == TRUEPHY_SET_BIT) */ | |
25ad00bb AC |
527 | if (etdev->RegistryFlowControl == Both) |
528 | etdev->FlowControl = RxOnly; | |
64f93036 | 529 | else |
25ad00bb | 530 | etdev->FlowControl = None; |
cfb739b4 GKH |
531 | } |
532 | } | |
533 | } | |
534 | ||
535 | /** | |
536 | * UpdateMacStatHostCounters - Update the local copy of the statistics | |
25ad00bb | 537 | * @etdev: pointer to the adapter structure |
cfb739b4 | 538 | */ |
25ad00bb | 539 | void UpdateMacStatHostCounters(struct et131x_adapter *etdev) |
cfb739b4 | 540 | { |
25ad00bb | 541 | struct _ce_stats_t *stats = &etdev->Stats; |
cfb739b4 | 542 | struct _MAC_STAT_t __iomem *pDevMacStat = |
f3f415a3 | 543 | &etdev->regs->macStat; |
cfb739b4 GKH |
544 | |
545 | stats->collisions += readl(&pDevMacStat->TNcl); | |
546 | stats->first_collision += readl(&pDevMacStat->TScl); | |
547 | stats->tx_deferred += readl(&pDevMacStat->TDfr); | |
548 | stats->excessive_collisions += readl(&pDevMacStat->TMcl); | |
549 | stats->late_collisions += readl(&pDevMacStat->TLcl); | |
550 | stats->tx_uflo += readl(&pDevMacStat->TUnd); | |
551 | stats->max_pkt_error += readl(&pDevMacStat->TOvr); | |
552 | ||
553 | stats->alignment_err += readl(&pDevMacStat->RAln); | |
554 | stats->crc_err += readl(&pDevMacStat->RCde); | |
555 | stats->norcvbuf += readl(&pDevMacStat->RDrp); | |
556 | stats->rx_ov_flow += readl(&pDevMacStat->ROvr); | |
557 | stats->code_violations += readl(&pDevMacStat->RFcs); | |
558 | stats->length_err += readl(&pDevMacStat->RFlr); | |
559 | ||
560 | stats->other_errors += readl(&pDevMacStat->RFrg); | |
561 | } | |
562 | ||
563 | /** | |
564 | * HandleMacStatInterrupt | |
25ad00bb | 565 | * @etdev: pointer to the adapter structure |
cfb739b4 GKH |
566 | * |
567 | * One of the MACSTAT counters has wrapped. Update the local copy of | |
568 | * the statistics held in the adapter structure, checking the "wrap" | |
569 | * bit for each counter. | |
570 | */ | |
25ad00bb | 571 | void HandleMacStatInterrupt(struct et131x_adapter *etdev) |
cfb739b4 GKH |
572 | { |
573 | MAC_STAT_REG_1_t Carry1; | |
574 | MAC_STAT_REG_2_t Carry2; | |
575 | ||
cfb739b4 GKH |
576 | /* Read the interrupt bits from the register(s). These are Clear On |
577 | * Write. | |
578 | */ | |
f3f415a3 AC |
579 | Carry1.value = readl(&etdev->regs->macStat.Carry1.value); |
580 | Carry2.value = readl(&etdev->regs->macStat.Carry2.value); | |
cfb739b4 | 581 | |
f3f415a3 AC |
582 | writel(Carry1.value, &etdev->regs->macStat.Carry1.value); |
583 | writel(Carry2.value, &etdev->regs->macStat.Carry2.value); | |
cfb739b4 GKH |
584 | |
585 | /* We need to do update the host copy of all the MAC_STAT counters. | |
586 | * For each counter, check it's overflow bit. If the overflow bit is | |
587 | * set, then increment the host version of the count by one complete | |
588 | * revolution of the counter. This routine is called when the counter | |
589 | * block indicates that one of the counters has wrapped. | |
590 | */ | |
64f93036 | 591 | if (Carry1.bits.rfcs) |
25ad00bb | 592 | etdev->Stats.code_violations += COUNTER_WRAP_16_BIT; |
64f93036 | 593 | if (Carry1.bits.raln) |
25ad00bb | 594 | etdev->Stats.alignment_err += COUNTER_WRAP_12_BIT; |
64f93036 | 595 | if (Carry1.bits.rflr) |
25ad00bb | 596 | etdev->Stats.length_err += COUNTER_WRAP_16_BIT; |
64f93036 | 597 | if (Carry1.bits.rfrg) |
25ad00bb | 598 | etdev->Stats.other_errors += COUNTER_WRAP_16_BIT; |
64f93036 | 599 | if (Carry1.bits.rcde) |
25ad00bb | 600 | etdev->Stats.crc_err += COUNTER_WRAP_16_BIT; |
64f93036 | 601 | if (Carry1.bits.rovr) |
25ad00bb | 602 | etdev->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT; |
64f93036 | 603 | if (Carry1.bits.rdrp) |
25ad00bb | 604 | etdev->Stats.norcvbuf += COUNTER_WRAP_16_BIT; |
64f93036 | 605 | if (Carry2.bits.tovr) |
25ad00bb | 606 | etdev->Stats.max_pkt_error += COUNTER_WRAP_12_BIT; |
64f93036 | 607 | if (Carry2.bits.tund) |
25ad00bb | 608 | etdev->Stats.tx_uflo += COUNTER_WRAP_12_BIT; |
64f93036 | 609 | if (Carry2.bits.tscl) |
25ad00bb | 610 | etdev->Stats.first_collision += COUNTER_WRAP_12_BIT; |
64f93036 | 611 | if (Carry2.bits.tdfr) |
25ad00bb | 612 | etdev->Stats.tx_deferred += COUNTER_WRAP_12_BIT; |
64f93036 | 613 | if (Carry2.bits.tmcl) |
25ad00bb | 614 | etdev->Stats.excessive_collisions += COUNTER_WRAP_12_BIT; |
64f93036 | 615 | if (Carry2.bits.tlcl) |
25ad00bb | 616 | etdev->Stats.late_collisions += COUNTER_WRAP_12_BIT; |
64f93036 | 617 | if (Carry2.bits.tncl) |
25ad00bb | 618 | etdev->Stats.collisions += COUNTER_WRAP_12_BIT; |
cfb739b4 GKH |
619 | } |
620 | ||
25ad00bb | 621 | void SetupDeviceForMulticast(struct et131x_adapter *etdev) |
cfb739b4 | 622 | { |
f3f415a3 | 623 | struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac; |
cfb739b4 GKH |
624 | uint32_t nIndex; |
625 | uint32_t result; | |
626 | uint32_t hash1 = 0; | |
627 | uint32_t hash2 = 0; | |
628 | uint32_t hash3 = 0; | |
629 | uint32_t hash4 = 0; | |
f2c98d27 | 630 | u32 pm_csr; |
cfb739b4 | 631 | |
cfb739b4 GKH |
632 | /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision |
633 | * the multi-cast LIST. If it is NOT specified, (and "ALL" is not | |
634 | * specified) then we should pass NO multi-cast addresses to the | |
635 | * driver. | |
636 | */ | |
25ad00bb | 637 | if (etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) { |
cfb739b4 | 638 | /* Loop through our multicast array and set up the device */ |
25ad00bb | 639 | for (nIndex = 0; nIndex < etdev->MCAddressCount; nIndex++) { |
25ad00bb | 640 | result = ether_crc(6, etdev->MCList[nIndex]); |
cfb739b4 GKH |
641 | |
642 | result = (result & 0x3F800000) >> 23; | |
643 | ||
644 | if (result < 32) { | |
645 | hash1 |= (1 << result); | |
646 | } else if ((31 < result) && (result < 64)) { | |
647 | result -= 32; | |
648 | hash2 |= (1 << result); | |
649 | } else if ((63 < result) && (result < 96)) { | |
650 | result -= 64; | |
651 | hash3 |= (1 << result); | |
652 | } else { | |
653 | result -= 96; | |
654 | hash4 |= (1 << result); | |
655 | } | |
656 | } | |
657 | } | |
658 | ||
659 | /* Write out the new hash to the device */ | |
f2c98d27 AC |
660 | pm_csr = readl(&etdev->regs->global.pm_csr); |
661 | if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) { | |
cfb739b4 GKH |
662 | writel(hash1, &rxmac->multi_hash1); |
663 | writel(hash2, &rxmac->multi_hash2); | |
664 | writel(hash3, &rxmac->multi_hash3); | |
665 | writel(hash4, &rxmac->multi_hash4); | |
666 | } | |
cfb739b4 GKH |
667 | } |
668 | ||
25ad00bb | 669 | void SetupDeviceForUnicast(struct et131x_adapter *etdev) |
cfb739b4 | 670 | { |
f3f415a3 | 671 | struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac; |
cfb739b4 GKH |
672 | RXMAC_UNI_PF_ADDR1_t uni_pf1; |
673 | RXMAC_UNI_PF_ADDR2_t uni_pf2; | |
674 | RXMAC_UNI_PF_ADDR3_t uni_pf3; | |
f2c98d27 | 675 | u32 pm_csr; |
cfb739b4 | 676 | |
cfb739b4 GKH |
677 | /* Set up unicast packet filter reg 3 to be the first two octets of |
678 | * the MAC address for both address | |
679 | * | |
680 | * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the | |
681 | * MAC address for second address | |
682 | * | |
683 | * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the | |
684 | * MAC address for first address | |
685 | */ | |
25ad00bb AC |
686 | uni_pf3.bits.addr1_1 = etdev->CurrentAddress[0]; |
687 | uni_pf3.bits.addr1_2 = etdev->CurrentAddress[1]; | |
688 | uni_pf3.bits.addr2_1 = etdev->CurrentAddress[0]; | |
689 | uni_pf3.bits.addr2_2 = etdev->CurrentAddress[1]; | |
690 | ||
691 | uni_pf2.bits.addr2_3 = etdev->CurrentAddress[2]; | |
692 | uni_pf2.bits.addr2_4 = etdev->CurrentAddress[3]; | |
693 | uni_pf2.bits.addr2_5 = etdev->CurrentAddress[4]; | |
694 | uni_pf2.bits.addr2_6 = etdev->CurrentAddress[5]; | |
695 | ||
696 | uni_pf1.bits.addr1_3 = etdev->CurrentAddress[2]; | |
697 | uni_pf1.bits.addr1_4 = etdev->CurrentAddress[3]; | |
698 | uni_pf1.bits.addr1_5 = etdev->CurrentAddress[4]; | |
699 | uni_pf1.bits.addr1_6 = etdev->CurrentAddress[5]; | |
700 | ||
f2c98d27 AC |
701 | pm_csr = readl(&etdev->regs->global.pm_csr); |
702 | if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) { | |
cfb739b4 GKH |
703 | writel(uni_pf1.value, &rxmac->uni_pf_addr1.value); |
704 | writel(uni_pf2.value, &rxmac->uni_pf_addr2.value); | |
705 | writel(uni_pf3.value, &rxmac->uni_pf_addr3.value); | |
706 | } | |
cfb739b4 | 707 | } |