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cfb739b4 GKH |
1 | /* |
2 | * Agere Systems Inc. | |
3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs | |
4 | * | |
64f93036 | 5 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
6 | * All rights reserved. |
7 | * http://www.agere.com | |
8 | * | |
9 | *------------------------------------------------------------------------------ | |
10 | * | |
11 | * et1310_mac.c - All code and routines pertaining to the MAC | |
12 | * | |
13 | *------------------------------------------------------------------------------ | |
14 | * | |
15 | * SOFTWARE LICENSE | |
16 | * | |
17 | * This software is provided subject to the following terms and conditions, | |
18 | * which you should read carefully before using the software. Using this | |
19 | * software indicates your acceptance of these terms and conditions. If you do | |
20 | * not agree with these terms and conditions, do not use the software. | |
21 | * | |
64f93036 | 22 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
23 | * All rights reserved. |
24 | * | |
25 | * Redistribution and use in source or binary forms, with or without | |
26 | * modifications, are permitted provided that the following conditions are met: | |
27 | * | |
28 | * . Redistributions of source code must retain the above copyright notice, this | |
29 | * list of conditions and the following Disclaimer as comments in the code as | |
30 | * well as in the documentation and/or other materials provided with the | |
31 | * distribution. | |
32 | * | |
33 | * . Redistributions in binary form must reproduce the above copyright notice, | |
34 | * this list of conditions and the following Disclaimer in the documentation | |
35 | * and/or other materials provided with the distribution. | |
36 | * | |
37 | * . Neither the name of Agere Systems Inc. nor the names of the contributors | |
38 | * may be used to endorse or promote products derived from this software | |
39 | * without specific prior written permission. | |
40 | * | |
41 | * Disclaimer | |
42 | * | |
64f93036 | 43 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
cfb739b4 GKH |
44 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
45 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY | |
46 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN | |
47 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY | |
48 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
49 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
50 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
51 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT | |
52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
53 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH | |
54 | * DAMAGE. | |
55 | * | |
56 | */ | |
57 | ||
58 | #include "et131x_version.h" | |
59 | #include "et131x_debug.h" | |
60 | #include "et131x_defs.h" | |
61 | ||
62 | #include <linux/init.h> | |
63 | #include <linux/module.h> | |
64 | #include <linux/types.h> | |
65 | #include <linux/kernel.h> | |
66 | ||
67 | #include <linux/sched.h> | |
68 | #include <linux/ptrace.h> | |
69 | #include <linux/slab.h> | |
70 | #include <linux/ctype.h> | |
71 | #include <linux/string.h> | |
72 | #include <linux/timer.h> | |
73 | #include <linux/interrupt.h> | |
74 | #include <linux/in.h> | |
75 | #include <linux/delay.h> | |
64f93036 AC |
76 | #include <linux/io.h> |
77 | #include <linux/bitops.h> | |
cfb739b4 | 78 | #include <asm/system.h> |
cfb739b4 GKH |
79 | |
80 | #include <linux/netdevice.h> | |
81 | #include <linux/etherdevice.h> | |
82 | #include <linux/skbuff.h> | |
83 | #include <linux/if_arp.h> | |
84 | #include <linux/ioport.h> | |
85 | #include <linux/crc32.h> | |
86 | ||
87 | #include "et1310_phy.h" | |
88 | #include "et1310_pm.h" | |
89 | #include "et1310_jagcore.h" | |
90 | #include "et1310_mac.h" | |
91 | ||
92 | #include "et131x_adapter.h" | |
93 | #include "et131x_initpci.h" | |
94 | ||
95 | /* Data for debugging facilities */ | |
96 | #ifdef CONFIG_ET131X_DEBUG | |
97 | extern dbg_info_t *et131x_dbginfo; | |
98 | #endif /* CONFIG_ET131X_DEBUG */ | |
99 | ||
100 | /** | |
101 | * ConfigMacRegs1 - Initialize the first part of MAC regs | |
102 | * @pAdpater: pointer to our adapter structure | |
103 | */ | |
104 | void ConfigMACRegs1(struct et131x_adapter *pAdapter) | |
105 | { | |
106 | struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac; | |
107 | MAC_STATION_ADDR1_t station1; | |
108 | MAC_STATION_ADDR2_t station2; | |
109 | MAC_IPG_t ipg; | |
110 | MAC_HFDP_t hfdp; | |
111 | MII_MGMT_CFG_t mii_mgmt_cfg; | |
112 | ||
113 | DBG_ENTER(et131x_dbginfo); | |
114 | ||
115 | /* First we need to reset everything. Write to MAC configuration | |
116 | * register 1 to perform reset. | |
117 | */ | |
118 | writel(0xC00F0000, &pMac->cfg1.value); | |
119 | ||
120 | /* Next lets configure the MAC Inter-packet gap register */ | |
64f93036 AC |
121 | ipg.bits.non_B2B_ipg_1 = 0x38; /* 58d */ |
122 | ipg.bits.non_B2B_ipg_2 = 0x58; /* 88d */ | |
123 | ipg.bits.min_ifg_enforce = 0x50; /* 80d */ | |
124 | ipg.bits.B2B_ipg = 0x60; /* 96d */ | |
cfb739b4 GKH |
125 | writel(ipg.value, &pMac->ipg.value); |
126 | ||
127 | /* Next lets configure the MAC Half Duplex register */ | |
128 | hfdp.bits.alt_beb_trunc = 0xA; | |
129 | hfdp.bits.alt_beb_enable = 0x0; | |
130 | hfdp.bits.bp_no_backoff = 0x0; | |
131 | hfdp.bits.no_backoff = 0x0; | |
132 | hfdp.bits.excess_defer = 0x1; | |
133 | hfdp.bits.rexmit_max = 0xF; | |
64f93036 | 134 | hfdp.bits.coll_window = 0x37; /* 55d */ |
cfb739b4 GKH |
135 | writel(hfdp.value, &pMac->hfdp.value); |
136 | ||
137 | /* Next lets configure the MAC Interface Control register */ | |
138 | writel(0, &pMac->if_ctrl.value); | |
139 | ||
140 | /* Let's move on to setting up the mii managment configuration */ | |
141 | mii_mgmt_cfg.bits.reset_mii_mgmt = 0; | |
142 | mii_mgmt_cfg.bits.scan_auto_incremt = 0; | |
143 | mii_mgmt_cfg.bits.preamble_suppress = 0; | |
144 | mii_mgmt_cfg.bits.mgmt_clk_reset = 0x7; | |
145 | writel(mii_mgmt_cfg.value, &pMac->mii_mgmt_cfg.value); | |
146 | ||
147 | /* Next lets configure the MAC Station Address register. These | |
148 | * values are read from the EEPROM during initialization and stored | |
149 | * in the adapter structure. We write what is stored in the adapter | |
150 | * structure to the MAC Station Address registers high and low. This | |
151 | * station address is used for generating and checking pause control | |
152 | * packets. | |
153 | */ | |
154 | station2.bits.Octet1 = pAdapter->CurrentAddress[0]; | |
155 | station2.bits.Octet2 = pAdapter->CurrentAddress[1]; | |
156 | station1.bits.Octet3 = pAdapter->CurrentAddress[2]; | |
157 | station1.bits.Octet4 = pAdapter->CurrentAddress[3]; | |
158 | station1.bits.Octet5 = pAdapter->CurrentAddress[4]; | |
159 | station1.bits.Octet6 = pAdapter->CurrentAddress[5]; | |
160 | writel(station1.value, &pMac->station_addr_1.value); | |
161 | writel(station2.value, &pMac->station_addr_2.value); | |
162 | ||
163 | /* Max ethernet packet in bytes that will passed by the mac without | |
164 | * being truncated. Allow the MAC to pass 4 more than our max packet | |
165 | * size. This is 4 for the Ethernet CRC. | |
166 | * | |
167 | * Packets larger than (RegistryJumboPacket) that do not contain a | |
168 | * VLAN ID will be dropped by the Rx function. | |
169 | */ | |
170 | writel(pAdapter->RegistryJumboPacket + 4, &pMac->max_fm_len.value); | |
171 | ||
172 | /* clear out MAC config reset */ | |
173 | writel(0, &pMac->cfg1.value); | |
174 | ||
175 | DBG_LEAVE(et131x_dbginfo); | |
176 | } | |
177 | ||
178 | /** | |
179 | * ConfigMacRegs2 - Initialize the second part of MAC regs | |
180 | * @pAdpater: pointer to our adapter structure | |
181 | */ | |
182 | void ConfigMACRegs2(struct et131x_adapter *pAdapter) | |
183 | { | |
184 | int32_t delay = 0; | |
185 | struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac; | |
186 | MAC_CFG1_t cfg1; | |
187 | MAC_CFG2_t cfg2; | |
188 | MAC_IF_CTRL_t ifctrl; | |
189 | TXMAC_CTL_t ctl; | |
190 | ||
191 | DBG_ENTER(et131x_dbginfo); | |
192 | ||
193 | ctl.value = readl(&pAdapter->CSRAddress->txmac.ctl.value); | |
194 | cfg1.value = readl(&pMac->cfg1.value); | |
195 | cfg2.value = readl(&pMac->cfg2.value); | |
196 | ifctrl.value = readl(&pMac->if_ctrl.value); | |
197 | ||
198 | if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) { | |
199 | cfg2.bits.if_mode = 0x2; | |
200 | ifctrl.bits.phy_mode = 0x0; | |
201 | } else { | |
202 | cfg2.bits.if_mode = 0x1; | |
203 | ifctrl.bits.phy_mode = 0x1; | |
204 | } | |
205 | ||
206 | /* We need to enable Rx/Tx */ | |
207 | cfg1.bits.rx_enable = 0x1; | |
208 | cfg1.bits.tx_enable = 0x1; | |
209 | ||
210 | /* Set up flow control */ | |
211 | cfg1.bits.tx_flow = 0x1; | |
212 | ||
213 | if ((pAdapter->FlowControl == RxOnly) || | |
214 | (pAdapter->FlowControl == Both)) { | |
215 | cfg1.bits.rx_flow = 0x1; | |
216 | } else { | |
217 | cfg1.bits.rx_flow = 0x0; | |
218 | } | |
219 | ||
220 | /* Initialize loop back to off */ | |
221 | cfg1.bits.loop_back = 0; | |
222 | ||
223 | writel(cfg1.value, &pMac->cfg1.value); | |
224 | ||
225 | /* Now we need to initialize the MAC Configuration 2 register */ | |
226 | cfg2.bits.preamble_len = 0x7; | |
227 | cfg2.bits.huge_frame = 0x0; | |
228 | /* LENGTH FIELD CHECKING bit4: Set this bit to cause the MAC to check | |
229 | * the frame's length field to ensure it matches the actual data | |
230 | * field length. Clear this bit if no length field checking is | |
231 | * desired. Its default is 0. | |
232 | */ | |
233 | cfg2.bits.len_check = 0x1; | |
234 | ||
235 | if (pAdapter->RegistryPhyLoopbk == false) { | |
236 | cfg2.bits.pad_crc = 0x1; | |
237 | cfg2.bits.crc_enable = 0x1; | |
238 | } else { | |
239 | cfg2.bits.pad_crc = 0; | |
240 | cfg2.bits.crc_enable = 0; | |
241 | } | |
242 | ||
243 | /* 1 - full duplex, 0 - half-duplex */ | |
244 | cfg2.bits.full_duplex = pAdapter->uiDuplexMode; | |
245 | ifctrl.bits.ghd_mode = !pAdapter->uiDuplexMode; | |
246 | ||
247 | writel(ifctrl.value, &pMac->if_ctrl.value); | |
248 | writel(cfg2.value, &pMac->cfg2.value); | |
249 | ||
250 | do { | |
251 | udelay(10); | |
252 | delay++; | |
253 | cfg1.value = readl(&pMac->cfg1.value); | |
64f93036 AC |
254 | } while ((!cfg1.bits.syncd_rx_en || !cfg1.bits.syncd_tx_en) && |
255 | delay < 100); | |
cfb739b4 GKH |
256 | |
257 | if (delay == 100) { | |
258 | DBG_ERROR(et131x_dbginfo, | |
64f93036 AC |
259 | "Syncd bits did not respond correctly cfg1 word 0x%08x\n", |
260 | cfg1.value); | |
cfb739b4 GKH |
261 | } |
262 | ||
263 | DBG_TRACE(et131x_dbginfo, | |
64f93036 AC |
264 | "Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n", |
265 | pAdapter->uiLinkSpeed, pAdapter->uiDuplexMode, | |
266 | readl(&pMac->cfg1.value), readl(&pMac->cfg2.value), | |
267 | readl(&pMac->if_ctrl.value)); | |
cfb739b4 GKH |
268 | |
269 | /* Enable TXMAC */ | |
270 | ctl.bits.txmac_en = 0x1; | |
271 | ctl.bits.fc_disable = 0x1; | |
272 | writel(ctl.value, &pAdapter->CSRAddress->txmac.ctl.value); | |
273 | ||
274 | /* Ready to start the RXDMA/TXDMA engine */ | |
275 | if (!MP_TEST_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER)) { | |
276 | et131x_rx_dma_enable(pAdapter); | |
277 | et131x_tx_dma_enable(pAdapter); | |
278 | } else { | |
279 | DBG_WARNING(et131x_dbginfo, | |
280 | "Didn't enable Rx/Tx due to low-power mode\n"); | |
281 | } | |
282 | ||
283 | DBG_LEAVE(et131x_dbginfo); | |
284 | } | |
285 | ||
286 | void ConfigRxMacRegs(struct et131x_adapter *pAdapter) | |
287 | { | |
288 | struct _RXMAC_t __iomem *pRxMac = &pAdapter->CSRAddress->rxmac; | |
289 | RXMAC_WOL_SA_LO_t sa_lo; | |
290 | RXMAC_WOL_SA_HI_t sa_hi; | |
291 | RXMAC_PF_CTRL_t pf_ctrl = { 0 }; | |
292 | ||
293 | DBG_ENTER(et131x_dbginfo); | |
294 | ||
295 | /* Disable the MAC while it is being configured (also disable WOL) */ | |
296 | writel(0x8, &pRxMac->ctrl.value); | |
297 | ||
298 | /* Initialize WOL to disabled. */ | |
299 | writel(0, &pRxMac->crc0.value); | |
300 | writel(0, &pRxMac->crc12.value); | |
301 | writel(0, &pRxMac->crc34.value); | |
302 | ||
303 | /* We need to set the WOL mask0 - mask4 next. We initialize it to | |
304 | * its default Values of 0x00000000 because there are not WOL masks | |
305 | * as of this time. | |
306 | */ | |
307 | writel(0, &pRxMac->mask0_word0); | |
308 | writel(0, &pRxMac->mask0_word1); | |
309 | writel(0, &pRxMac->mask0_word2); | |
310 | writel(0, &pRxMac->mask0_word3); | |
311 | ||
312 | writel(0, &pRxMac->mask1_word0); | |
313 | writel(0, &pRxMac->mask1_word1); | |
314 | writel(0, &pRxMac->mask1_word2); | |
315 | writel(0, &pRxMac->mask1_word3); | |
316 | ||
317 | writel(0, &pRxMac->mask2_word0); | |
318 | writel(0, &pRxMac->mask2_word1); | |
319 | writel(0, &pRxMac->mask2_word2); | |
320 | writel(0, &pRxMac->mask2_word3); | |
321 | ||
322 | writel(0, &pRxMac->mask3_word0); | |
323 | writel(0, &pRxMac->mask3_word1); | |
324 | writel(0, &pRxMac->mask3_word2); | |
325 | writel(0, &pRxMac->mask3_word3); | |
326 | ||
327 | writel(0, &pRxMac->mask4_word0); | |
328 | writel(0, &pRxMac->mask4_word1); | |
329 | writel(0, &pRxMac->mask4_word2); | |
330 | writel(0, &pRxMac->mask4_word3); | |
331 | ||
332 | /* Lets setup the WOL Source Address */ | |
333 | sa_lo.bits.sa3 = pAdapter->CurrentAddress[2]; | |
334 | sa_lo.bits.sa4 = pAdapter->CurrentAddress[3]; | |
335 | sa_lo.bits.sa5 = pAdapter->CurrentAddress[4]; | |
336 | sa_lo.bits.sa6 = pAdapter->CurrentAddress[5]; | |
337 | writel(sa_lo.value, &pRxMac->sa_lo.value); | |
338 | ||
339 | sa_hi.bits.sa1 = pAdapter->CurrentAddress[0]; | |
340 | sa_hi.bits.sa2 = pAdapter->CurrentAddress[1]; | |
341 | writel(sa_hi.value, &pRxMac->sa_hi.value); | |
342 | ||
343 | /* Disable all Packet Filtering */ | |
344 | writel(0, &pRxMac->pf_ctrl.value); | |
345 | ||
346 | /* Let's initialize the Unicast Packet filtering address */ | |
347 | if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) { | |
348 | SetupDeviceForUnicast(pAdapter); | |
349 | pf_ctrl.bits.filter_uni_en = 1; | |
350 | } else { | |
351 | writel(0, &pRxMac->uni_pf_addr1.value); | |
352 | writel(0, &pRxMac->uni_pf_addr2.value); | |
353 | writel(0, &pRxMac->uni_pf_addr3.value); | |
354 | } | |
355 | ||
356 | /* Let's initialize the Multicast hash */ | |
357 | if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) { | |
358 | pf_ctrl.bits.filter_multi_en = 0; | |
359 | } else { | |
360 | pf_ctrl.bits.filter_multi_en = 1; | |
361 | SetupDeviceForMulticast(pAdapter); | |
362 | } | |
363 | ||
364 | /* Runt packet filtering. Didn't work in version A silicon. */ | |
365 | pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4; | |
366 | pf_ctrl.bits.filter_frag_en = 1; | |
367 | ||
368 | if (pAdapter->RegistryJumboPacket > 8192) { | |
369 | RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; | |
370 | ||
371 | /* In order to transmit jumbo packets greater than 8k, the | |
372 | * FIFO between RxMAC and RxDMA needs to be reduced in size | |
373 | * to (16k - Jumbo packet size). In order to implement this, | |
374 | * we must use "cut through" mode in the RxMAC, which chops | |
375 | * packets down into segments which are (max_size * 16). In | |
376 | * this case we selected 256 bytes, since this is the size of | |
377 | * the PCI-Express TLP's that the 1310 uses. | |
378 | */ | |
379 | mcif_ctrl_max_seg.bits.seg_en = 0x1; | |
380 | mcif_ctrl_max_seg.bits.fc_en = 0x0; | |
381 | mcif_ctrl_max_seg.bits.max_size = 0x10; | |
382 | ||
383 | writel(mcif_ctrl_max_seg.value, | |
384 | &pRxMac->mcif_ctrl_max_seg.value); | |
385 | } else { | |
386 | writel(0, &pRxMac->mcif_ctrl_max_seg.value); | |
387 | } | |
388 | ||
389 | /* Initialize the MCIF water marks */ | |
390 | writel(0, &pRxMac->mcif_water_mark.value); | |
391 | ||
392 | /* Initialize the MIF control */ | |
393 | writel(0, &pRxMac->mif_ctrl.value); | |
394 | ||
395 | /* Initialize the Space Available Register */ | |
396 | writel(0, &pRxMac->space_avail.value); | |
397 | ||
398 | /* Initialize the the mif_ctrl register | |
399 | * bit 3: Receive code error. One or more nibbles were signaled as | |
400 | * errors during the reception of the packet. Clear this | |
401 | * bit in Gigabit, set it in 100Mbit. This was derived | |
402 | * experimentally at UNH. | |
403 | * bit 4: Receive CRC error. The packet's CRC did not match the | |
404 | * internally generated CRC. | |
405 | * bit 5: Receive length check error. Indicates that frame length | |
406 | * field value in the packet does not match the actual data | |
407 | * byte length and is not a type field. | |
408 | * bit 16: Receive frame truncated. | |
409 | * bit 17: Drop packet enable | |
410 | */ | |
64f93036 | 411 | if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) |
cfb739b4 | 412 | writel(0x30038, &pRxMac->mif_ctrl.value); |
64f93036 | 413 | else |
cfb739b4 | 414 | writel(0x30030, &pRxMac->mif_ctrl.value); |
cfb739b4 GKH |
415 | |
416 | /* Finally we initialize RxMac to be enabled & WOL disabled. Packet | |
417 | * filter is always enabled since it is where the runt packets are | |
418 | * supposed to be dropped. For version A silicon, runt packet | |
419 | * dropping doesn't work, so it is disabled in the pf_ctrl register, | |
420 | * but we still leave the packet filter on. | |
421 | */ | |
422 | writel(pf_ctrl.value, &pRxMac->pf_ctrl.value); | |
423 | writel(0x9, &pRxMac->ctrl.value); | |
424 | ||
425 | DBG_LEAVE(et131x_dbginfo); | |
426 | } | |
427 | ||
428 | void ConfigTxMacRegs(struct et131x_adapter *pAdapter) | |
429 | { | |
430 | struct _TXMAC_t __iomem *pTxMac = &pAdapter->CSRAddress->txmac; | |
431 | TXMAC_CF_PARAM_t Local; | |
432 | ||
433 | DBG_ENTER(et131x_dbginfo); | |
434 | ||
435 | /* We need to update the Control Frame Parameters | |
436 | * cfpt - control frame pause timer set to 64 (0x40) | |
437 | * cfep - control frame extended pause timer set to 0x0 | |
438 | */ | |
439 | if (pAdapter->FlowControl == None) { | |
440 | writel(0, &pTxMac->cf_param.value); | |
441 | } else { | |
442 | Local.bits.cfpt = 0x40; | |
443 | Local.bits.cfep = 0x0; | |
444 | writel(Local.value, &pTxMac->cf_param.value); | |
445 | } | |
446 | ||
447 | DBG_LEAVE(et131x_dbginfo); | |
448 | } | |
449 | ||
450 | void ConfigMacStatRegs(struct et131x_adapter *pAdapter) | |
451 | { | |
452 | struct _MAC_STAT_t __iomem *pDevMacStat = | |
453 | &pAdapter->CSRAddress->macStat; | |
454 | ||
455 | DBG_ENTER(et131x_dbginfo); | |
456 | ||
457 | /* Next we need to initialize all the MAC_STAT registers to zero on | |
458 | * the device. | |
459 | */ | |
460 | writel(0, &pDevMacStat->RFcs); | |
461 | writel(0, &pDevMacStat->RAln); | |
462 | writel(0, &pDevMacStat->RFlr); | |
463 | writel(0, &pDevMacStat->RDrp); | |
464 | writel(0, &pDevMacStat->RCde); | |
465 | writel(0, &pDevMacStat->ROvr); | |
466 | writel(0, &pDevMacStat->RFrg); | |
467 | ||
468 | writel(0, &pDevMacStat->TScl); | |
469 | writel(0, &pDevMacStat->TDfr); | |
470 | writel(0, &pDevMacStat->TMcl); | |
471 | writel(0, &pDevMacStat->TLcl); | |
472 | writel(0, &pDevMacStat->TNcl); | |
473 | writel(0, &pDevMacStat->TOvr); | |
474 | writel(0, &pDevMacStat->TUnd); | |
475 | ||
476 | /* Unmask any counters that we want to track the overflow of. | |
477 | * Initially this will be all counters. It may become clear later | |
478 | * that we do not need to track all counters. | |
479 | */ | |
480 | { | |
481 | MAC_STAT_REG_1_t Carry1M = { 0xffffffff }; | |
482 | ||
483 | Carry1M.bits.rdrp = 0; | |
484 | Carry1M.bits.rjbr = 1; | |
485 | Carry1M.bits.rfrg = 0; | |
486 | Carry1M.bits.rovr = 0; | |
487 | Carry1M.bits.rund = 1; | |
488 | Carry1M.bits.rcse = 1; | |
489 | Carry1M.bits.rcde = 0; | |
490 | Carry1M.bits.rflr = 0; | |
491 | Carry1M.bits.raln = 0; | |
492 | Carry1M.bits.rxuo = 1; | |
493 | Carry1M.bits.rxpf = 1; | |
494 | Carry1M.bits.rxcf = 1; | |
495 | Carry1M.bits.rbca = 1; | |
496 | Carry1M.bits.rmca = 1; | |
497 | Carry1M.bits.rfcs = 0; | |
498 | Carry1M.bits.rpkt = 1; | |
499 | Carry1M.bits.rbyt = 1; | |
500 | Carry1M.bits.trmgv = 1; | |
501 | Carry1M.bits.trmax = 1; | |
502 | Carry1M.bits.tr1k = 1; | |
503 | Carry1M.bits.tr511 = 1; | |
504 | Carry1M.bits.tr255 = 1; | |
505 | Carry1M.bits.tr127 = 1; | |
506 | Carry1M.bits.tr64 = 1; | |
507 | ||
508 | writel(Carry1M.value, &pDevMacStat->Carry1M.value); | |
509 | } | |
510 | ||
511 | { | |
512 | MAC_STAT_REG_2_t Carry2M = { 0xffffffff }; | |
513 | ||
514 | Carry2M.bits.tdrp = 1; | |
515 | Carry2M.bits.tpfh = 1; | |
516 | Carry2M.bits.tncl = 0; | |
517 | Carry2M.bits.txcl = 1; | |
518 | Carry2M.bits.tlcl = 0; | |
519 | Carry2M.bits.tmcl = 0; | |
520 | Carry2M.bits.tscl = 0; | |
521 | Carry2M.bits.tedf = 1; | |
522 | Carry2M.bits.tdfr = 0; | |
523 | Carry2M.bits.txpf = 1; | |
524 | Carry2M.bits.tbca = 1; | |
525 | Carry2M.bits.tmca = 1; | |
526 | Carry2M.bits.tpkt = 1; | |
527 | Carry2M.bits.tbyt = 1; | |
528 | Carry2M.bits.tfrg = 1; | |
529 | Carry2M.bits.tund = 0; | |
530 | Carry2M.bits.tovr = 0; | |
531 | Carry2M.bits.txcf = 1; | |
532 | Carry2M.bits.tfcs = 1; | |
533 | Carry2M.bits.tjbr = 1; | |
534 | ||
535 | writel(Carry2M.value, &pDevMacStat->Carry2M.value); | |
536 | } | |
537 | ||
538 | DBG_LEAVE(et131x_dbginfo); | |
539 | } | |
540 | ||
64f93036 | 541 | void ConfigFlowControl(struct et131x_adapter *pAdapter) |
cfb739b4 GKH |
542 | { |
543 | if (pAdapter->uiDuplexMode == 0) { | |
544 | pAdapter->FlowControl = None; | |
545 | } else { | |
546 | char RemotePause, RemoteAsyncPause; | |
547 | ||
548 | ET1310_PhyAccessMiBit(pAdapter, | |
549 | TRUEPHY_BIT_READ, 5, 10, &RemotePause); | |
550 | ET1310_PhyAccessMiBit(pAdapter, | |
551 | TRUEPHY_BIT_READ, 5, 11, | |
552 | &RemoteAsyncPause); | |
553 | ||
554 | if ((RemotePause == TRUEPHY_BIT_SET) && | |
555 | (RemoteAsyncPause == TRUEPHY_BIT_SET)) { | |
556 | pAdapter->FlowControl = pAdapter->RegistryFlowControl; | |
557 | } else if ((RemotePause == TRUEPHY_BIT_SET) && | |
558 | (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) { | |
64f93036 | 559 | if (pAdapter->RegistryFlowControl == Both) |
cfb739b4 | 560 | pAdapter->FlowControl = Both; |
64f93036 | 561 | else |
cfb739b4 | 562 | pAdapter->FlowControl = None; |
cfb739b4 GKH |
563 | } else if ((RemotePause == TRUEPHY_BIT_CLEAR) && |
564 | (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) { | |
565 | pAdapter->FlowControl = None; | |
566 | } else {/* if (RemotePause == TRUEPHY_CLEAR_BIT && | |
567 | RemoteAsyncPause == TRUEPHY_SET_BIT) */ | |
64f93036 | 568 | if (pAdapter->RegistryFlowControl == Both) |
cfb739b4 | 569 | pAdapter->FlowControl = RxOnly; |
64f93036 | 570 | else |
cfb739b4 | 571 | pAdapter->FlowControl = None; |
cfb739b4 GKH |
572 | } |
573 | } | |
574 | } | |
575 | ||
576 | /** | |
577 | * UpdateMacStatHostCounters - Update the local copy of the statistics | |
578 | * @pAdapter: pointer to the adapter structure | |
579 | */ | |
580 | void UpdateMacStatHostCounters(struct et131x_adapter *pAdapter) | |
581 | { | |
582 | struct _ce_stats_t *stats = &pAdapter->Stats; | |
583 | struct _MAC_STAT_t __iomem *pDevMacStat = | |
584 | &pAdapter->CSRAddress->macStat; | |
585 | ||
586 | stats->collisions += readl(&pDevMacStat->TNcl); | |
587 | stats->first_collision += readl(&pDevMacStat->TScl); | |
588 | stats->tx_deferred += readl(&pDevMacStat->TDfr); | |
589 | stats->excessive_collisions += readl(&pDevMacStat->TMcl); | |
590 | stats->late_collisions += readl(&pDevMacStat->TLcl); | |
591 | stats->tx_uflo += readl(&pDevMacStat->TUnd); | |
592 | stats->max_pkt_error += readl(&pDevMacStat->TOvr); | |
593 | ||
594 | stats->alignment_err += readl(&pDevMacStat->RAln); | |
595 | stats->crc_err += readl(&pDevMacStat->RCde); | |
596 | stats->norcvbuf += readl(&pDevMacStat->RDrp); | |
597 | stats->rx_ov_flow += readl(&pDevMacStat->ROvr); | |
598 | stats->code_violations += readl(&pDevMacStat->RFcs); | |
599 | stats->length_err += readl(&pDevMacStat->RFlr); | |
600 | ||
601 | stats->other_errors += readl(&pDevMacStat->RFrg); | |
602 | } | |
603 | ||
604 | /** | |
605 | * HandleMacStatInterrupt | |
606 | * @pAdapter: pointer to the adapter structure | |
607 | * | |
608 | * One of the MACSTAT counters has wrapped. Update the local copy of | |
609 | * the statistics held in the adapter structure, checking the "wrap" | |
610 | * bit for each counter. | |
611 | */ | |
612 | void HandleMacStatInterrupt(struct et131x_adapter *pAdapter) | |
613 | { | |
614 | MAC_STAT_REG_1_t Carry1; | |
615 | MAC_STAT_REG_2_t Carry2; | |
616 | ||
617 | DBG_ENTER(et131x_dbginfo); | |
618 | ||
619 | /* Read the interrupt bits from the register(s). These are Clear On | |
620 | * Write. | |
621 | */ | |
622 | Carry1.value = readl(&pAdapter->CSRAddress->macStat.Carry1.value); | |
623 | Carry2.value = readl(&pAdapter->CSRAddress->macStat.Carry2.value); | |
624 | ||
625 | writel(Carry1.value, &pAdapter->CSRAddress->macStat.Carry1.value); | |
626 | writel(Carry2.value, &pAdapter->CSRAddress->macStat.Carry2.value); | |
627 | ||
628 | /* We need to do update the host copy of all the MAC_STAT counters. | |
629 | * For each counter, check it's overflow bit. If the overflow bit is | |
630 | * set, then increment the host version of the count by one complete | |
631 | * revolution of the counter. This routine is called when the counter | |
632 | * block indicates that one of the counters has wrapped. | |
633 | */ | |
64f93036 | 634 | if (Carry1.bits.rfcs) |
cfb739b4 | 635 | pAdapter->Stats.code_violations += COUNTER_WRAP_16_BIT; |
64f93036 | 636 | if (Carry1.bits.raln) |
cfb739b4 | 637 | pAdapter->Stats.alignment_err += COUNTER_WRAP_12_BIT; |
64f93036 | 638 | if (Carry1.bits.rflr) |
cfb739b4 | 639 | pAdapter->Stats.length_err += COUNTER_WRAP_16_BIT; |
64f93036 | 640 | if (Carry1.bits.rfrg) |
cfb739b4 | 641 | pAdapter->Stats.other_errors += COUNTER_WRAP_16_BIT; |
64f93036 | 642 | if (Carry1.bits.rcde) |
cfb739b4 | 643 | pAdapter->Stats.crc_err += COUNTER_WRAP_16_BIT; |
64f93036 | 644 | if (Carry1.bits.rovr) |
cfb739b4 | 645 | pAdapter->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT; |
64f93036 | 646 | if (Carry1.bits.rdrp) |
cfb739b4 | 647 | pAdapter->Stats.norcvbuf += COUNTER_WRAP_16_BIT; |
64f93036 | 648 | if (Carry2.bits.tovr) |
cfb739b4 | 649 | pAdapter->Stats.max_pkt_error += COUNTER_WRAP_12_BIT; |
64f93036 | 650 | if (Carry2.bits.tund) |
cfb739b4 | 651 | pAdapter->Stats.tx_uflo += COUNTER_WRAP_12_BIT; |
64f93036 | 652 | if (Carry2.bits.tscl) |
cfb739b4 | 653 | pAdapter->Stats.first_collision += COUNTER_WRAP_12_BIT; |
64f93036 | 654 | if (Carry2.bits.tdfr) |
cfb739b4 | 655 | pAdapter->Stats.tx_deferred += COUNTER_WRAP_12_BIT; |
64f93036 | 656 | if (Carry2.bits.tmcl) |
cfb739b4 | 657 | pAdapter->Stats.excessive_collisions += COUNTER_WRAP_12_BIT; |
64f93036 | 658 | if (Carry2.bits.tlcl) |
cfb739b4 | 659 | pAdapter->Stats.late_collisions += COUNTER_WRAP_12_BIT; |
64f93036 | 660 | if (Carry2.bits.tncl) |
cfb739b4 | 661 | pAdapter->Stats.collisions += COUNTER_WRAP_12_BIT; |
cfb739b4 GKH |
662 | |
663 | DBG_LEAVE(et131x_dbginfo); | |
664 | } | |
665 | ||
666 | void SetupDeviceForMulticast(struct et131x_adapter *pAdapter) | |
667 | { | |
668 | struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac; | |
669 | uint32_t nIndex; | |
670 | uint32_t result; | |
671 | uint32_t hash1 = 0; | |
672 | uint32_t hash2 = 0; | |
673 | uint32_t hash3 = 0; | |
674 | uint32_t hash4 = 0; | |
675 | PM_CSR_t pm_csr; | |
676 | ||
677 | DBG_ENTER(et131x_dbginfo); | |
678 | ||
679 | /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision | |
680 | * the multi-cast LIST. If it is NOT specified, (and "ALL" is not | |
681 | * specified) then we should pass NO multi-cast addresses to the | |
682 | * driver. | |
683 | */ | |
684 | if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) { | |
685 | DBG_VERBOSE(et131x_dbginfo, | |
686 | "MULTICAST flag is set, MCCount: %d\n", | |
687 | pAdapter->MCAddressCount); | |
688 | ||
689 | /* Loop through our multicast array and set up the device */ | |
690 | for (nIndex = 0; nIndex < pAdapter->MCAddressCount; nIndex++) { | |
691 | DBG_VERBOSE(et131x_dbginfo, | |
64f93036 AC |
692 | "MCList[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n", |
693 | nIndex, | |
694 | pAdapter->MCList[nIndex][0], | |
695 | pAdapter->MCList[nIndex][1], | |
696 | pAdapter->MCList[nIndex][2], | |
697 | pAdapter->MCList[nIndex][3], | |
698 | pAdapter->MCList[nIndex][4], | |
699 | pAdapter->MCList[nIndex][5]); | |
cfb739b4 GKH |
700 | |
701 | result = ether_crc(6, pAdapter->MCList[nIndex]); | |
702 | ||
703 | result = (result & 0x3F800000) >> 23; | |
704 | ||
705 | if (result < 32) { | |
706 | hash1 |= (1 << result); | |
707 | } else if ((31 < result) && (result < 64)) { | |
708 | result -= 32; | |
709 | hash2 |= (1 << result); | |
710 | } else if ((63 < result) && (result < 96)) { | |
711 | result -= 64; | |
712 | hash3 |= (1 << result); | |
713 | } else { | |
714 | result -= 96; | |
715 | hash4 |= (1 << result); | |
716 | } | |
717 | } | |
718 | } | |
719 | ||
720 | /* Write out the new hash to the device */ | |
721 | pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value); | |
722 | if (pm_csr.bits.pm_phy_sw_coma == 0) { | |
723 | writel(hash1, &rxmac->multi_hash1); | |
724 | writel(hash2, &rxmac->multi_hash2); | |
725 | writel(hash3, &rxmac->multi_hash3); | |
726 | writel(hash4, &rxmac->multi_hash4); | |
727 | } | |
728 | ||
729 | DBG_LEAVE(et131x_dbginfo); | |
730 | } | |
731 | ||
732 | void SetupDeviceForUnicast(struct et131x_adapter *pAdapter) | |
733 | { | |
734 | struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac; | |
735 | RXMAC_UNI_PF_ADDR1_t uni_pf1; | |
736 | RXMAC_UNI_PF_ADDR2_t uni_pf2; | |
737 | RXMAC_UNI_PF_ADDR3_t uni_pf3; | |
738 | PM_CSR_t pm_csr; | |
739 | ||
740 | DBG_ENTER(et131x_dbginfo); | |
741 | ||
742 | /* Set up unicast packet filter reg 3 to be the first two octets of | |
743 | * the MAC address for both address | |
744 | * | |
745 | * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the | |
746 | * MAC address for second address | |
747 | * | |
748 | * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the | |
749 | * MAC address for first address | |
750 | */ | |
751 | uni_pf3.bits.addr1_1 = pAdapter->CurrentAddress[0]; | |
752 | uni_pf3.bits.addr1_2 = pAdapter->CurrentAddress[1]; | |
753 | uni_pf3.bits.addr2_1 = pAdapter->CurrentAddress[0]; | |
754 | uni_pf3.bits.addr2_2 = pAdapter->CurrentAddress[1]; | |
755 | ||
756 | uni_pf2.bits.addr2_3 = pAdapter->CurrentAddress[2]; | |
757 | uni_pf2.bits.addr2_4 = pAdapter->CurrentAddress[3]; | |
758 | uni_pf2.bits.addr2_5 = pAdapter->CurrentAddress[4]; | |
759 | uni_pf2.bits.addr2_6 = pAdapter->CurrentAddress[5]; | |
760 | ||
761 | uni_pf1.bits.addr1_3 = pAdapter->CurrentAddress[2]; | |
762 | uni_pf1.bits.addr1_4 = pAdapter->CurrentAddress[3]; | |
763 | uni_pf1.bits.addr1_5 = pAdapter->CurrentAddress[4]; | |
764 | uni_pf1.bits.addr1_6 = pAdapter->CurrentAddress[5]; | |
765 | ||
766 | pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value); | |
767 | if (pm_csr.bits.pm_phy_sw_coma == 0) { | |
768 | writel(uni_pf1.value, &rxmac->uni_pf_addr1.value); | |
769 | writel(uni_pf2.value, &rxmac->uni_pf_addr2.value); | |
770 | writel(uni_pf3.value, &rxmac->uni_pf_addr3.value); | |
771 | } | |
772 | ||
773 | DBG_LEAVE(et131x_dbginfo); | |
774 | } |