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cfb739b4 GKH |
1 | /* |
2 | * Agere Systems Inc. | |
3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs | |
4 | * | |
64f93036 | 5 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
6 | * All rights reserved. |
7 | * http://www.agere.com | |
8 | * | |
9 | *------------------------------------------------------------------------------ | |
10 | * | |
11 | * et131x_isr.c - File which contains the ISR, ISR handler, and related routines | |
12 | * for processing interrupts from the device. | |
13 | * | |
14 | *------------------------------------------------------------------------------ | |
15 | * | |
16 | * SOFTWARE LICENSE | |
17 | * | |
18 | * This software is provided subject to the following terms and conditions, | |
19 | * which you should read carefully before using the software. Using this | |
20 | * software indicates your acceptance of these terms and conditions. If you do | |
21 | * not agree with these terms and conditions, do not use the software. | |
22 | * | |
64f93036 | 23 | * Copyright © 2005 Agere Systems Inc. |
cfb739b4 GKH |
24 | * All rights reserved. |
25 | * | |
26 | * Redistribution and use in source or binary forms, with or without | |
27 | * modifications, are permitted provided that the following conditions are met: | |
28 | * | |
29 | * . Redistributions of source code must retain the above copyright notice, this | |
30 | * list of conditions and the following Disclaimer as comments in the code as | |
31 | * well as in the documentation and/or other materials provided with the | |
32 | * distribution. | |
33 | * | |
34 | * . Redistributions in binary form must reproduce the above copyright notice, | |
35 | * this list of conditions and the following Disclaimer in the documentation | |
36 | * and/or other materials provided with the distribution. | |
37 | * | |
38 | * . Neither the name of Agere Systems Inc. nor the names of the contributors | |
39 | * may be used to endorse or promote products derived from this software | |
40 | * without specific prior written permission. | |
41 | * | |
42 | * Disclaimer | |
43 | * | |
64f93036 | 44 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
cfb739b4 GKH |
45 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
46 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY | |
47 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN | |
48 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY | |
49 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
50 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
51 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
52 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT | |
53 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
54 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH | |
55 | * DAMAGE. | |
56 | * | |
57 | */ | |
58 | ||
59 | #include "et131x_version.h" | |
cfb739b4 GKH |
60 | #include "et131x_defs.h" |
61 | ||
62 | #include <linux/init.h> | |
63 | #include <linux/module.h> | |
64 | #include <linux/types.h> | |
65 | #include <linux/kernel.h> | |
66 | ||
67 | #include <linux/sched.h> | |
68 | #include <linux/ptrace.h> | |
cfb739b4 GKH |
69 | #include <linux/ctype.h> |
70 | #include <linux/string.h> | |
71 | #include <linux/timer.h> | |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/in.h> | |
74 | #include <linux/delay.h> | |
64f93036 AC |
75 | #include <linux/io.h> |
76 | #include <linux/bitops.h> | |
15700039 | 77 | #include <linux/pci.h> |
cfb739b4 | 78 | #include <asm/system.h> |
cfb739b4 GKH |
79 | |
80 | #include <linux/netdevice.h> | |
81 | #include <linux/etherdevice.h> | |
82 | #include <linux/skbuff.h> | |
83 | #include <linux/if_arp.h> | |
84 | #include <linux/ioport.h> | |
85 | ||
86 | #include "et1310_phy.h" | |
cfb739b4 | 87 | #include "et131x_adapter.h" |
69ea5fcb AC |
88 | #include "et131x.h" |
89 | ||
90 | /* | |
91 | * For interrupts, normal running is: | |
92 | * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt, | |
93 | * watchdog_interrupt & txdma_xfer_done | |
94 | * | |
95 | * In both cases, when flow control is enabled for either Tx or bi-direction, | |
96 | * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the | |
97 | * buffer rings are running low. | |
98 | */ | |
99 | #define INT_MASK_DISABLE 0xffffffff | |
100 | ||
101 | /* NOTE: Masking out MAC_STAT Interrupt for now... | |
102 | * #define INT_MASK_ENABLE 0xfff6bf17 | |
103 | * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7 | |
104 | */ | |
105 | #define INT_MASK_ENABLE 0xfffebf17 | |
106 | #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7 | |
107 | ||
cfb739b4 | 108 | |
b8c4cc46 AC |
109 | /** |
110 | * et131x_enable_interrupts - enable interrupt | |
111 | * @adapter: et131x device | |
112 | * | |
113 | * Enable the appropriate interrupts on the ET131x according to our | |
114 | * configuration | |
115 | */ | |
116 | ||
117 | void et131x_enable_interrupts(struct et131x_adapter *adapter) | |
118 | { | |
119 | u32 mask; | |
120 | ||
121 | /* Enable all global interrupts */ | |
122 | if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both) | |
123 | mask = INT_MASK_ENABLE; | |
124 | else | |
125 | mask = INT_MASK_ENABLE_NO_FLOW; | |
126 | ||
b8c4cc46 AC |
127 | adapter->CachedMaskValue = mask; |
128 | writel(mask, &adapter->regs->global.int_mask); | |
129 | } | |
130 | ||
131 | /** | |
132 | * et131x_disable_interrupts - interrupt disable | |
133 | * @adapter: et131x device | |
134 | * | |
135 | * Block all interrupts from the et131x device at the device itself | |
136 | */ | |
137 | ||
138 | void et131x_disable_interrupts(struct et131x_adapter *adapter) | |
139 | { | |
140 | /* Disable all global interrupts */ | |
141 | adapter->CachedMaskValue = INT_MASK_DISABLE; | |
142 | writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask); | |
143 | } | |
144 | ||
145 | ||
cfb739b4 GKH |
146 | /** |
147 | * et131x_isr - The Interrupt Service Routine for the driver. | |
148 | * @irq: the IRQ on which the interrupt was received. | |
149 | * @dev_id: device-specific info (here a pointer to a net_device struct) | |
150 | * | |
151 | * Returns a value indicating if the interrupt was handled. | |
152 | */ | |
b8c4cc46 | 153 | |
cfb739b4 GKH |
154 | irqreturn_t et131x_isr(int irq, void *dev_id) |
155 | { | |
156 | bool handled = true; | |
157 | struct net_device *netdev = (struct net_device *)dev_id; | |
158 | struct et131x_adapter *adapter = NULL; | |
2211b732 | 159 | u32 status; |
cfb739b4 | 160 | |
15700039 | 161 | if (!netif_device_present(netdev)) { |
cfb739b4 GKH |
162 | handled = false; |
163 | goto out; | |
164 | } | |
165 | ||
166 | adapter = netdev_priv(netdev); | |
167 | ||
168 | /* If the adapter is in low power state, then it should not | |
169 | * recognize any interrupt | |
170 | */ | |
171 | ||
172 | /* Disable Device Interrupts */ | |
173 | et131x_disable_interrupts(adapter); | |
174 | ||
175 | /* Get a copy of the value in the interrupt status register | |
176 | * so we can process the interrupting section | |
177 | */ | |
2211b732 | 178 | status = readl(&adapter->regs->global.int_status); |
cfb739b4 GKH |
179 | |
180 | if (adapter->FlowControl == TxOnly || | |
181 | adapter->FlowControl == Both) { | |
2211b732 | 182 | status &= ~INT_MASK_ENABLE; |
cfb739b4 | 183 | } else { |
2211b732 | 184 | status &= ~INT_MASK_ENABLE_NO_FLOW; |
cfb739b4 GKH |
185 | } |
186 | ||
187 | /* Make sure this is our interrupt */ | |
2211b732 | 188 | if (!status) { |
cfb739b4 | 189 | handled = false; |
cfb739b4 GKH |
190 | et131x_enable_interrupts(adapter); |
191 | goto out; | |
192 | } | |
193 | ||
194 | /* This is our interrupt, so process accordingly */ | |
cfb739b4 | 195 | |
2211b732 | 196 | if (status & ET_INTR_WATCHDOG) { |
c78732ad | 197 | struct tcb *tcb = adapter->tx_ring.send_head; |
cfb739b4 | 198 | |
b711b2e0 | 199 | if (tcb) |
c78732ad | 200 | if (++tcb->stale > 1) |
2211b732 | 201 | status |= ET_INTR_TXDMA_ISR; |
cfb739b4 | 202 | |
8f12785d | 203 | if (adapter->rx_ring.UnfinishedReceives) |
2211b732 | 204 | status |= ET_INTR_RXDMA_XFR_DONE; |
b711b2e0 | 205 | else if (tcb == NULL) |
f3f415a3 | 206 | writel(0, &adapter->regs->global.watchdog_timer); |
cfb739b4 | 207 | |
2211b732 | 208 | status &= ~ET_INTR_WATCHDOG; |
cfb739b4 GKH |
209 | } |
210 | ||
2211b732 | 211 | if (status == 0) { |
cfb739b4 GKH |
212 | /* This interrupt has in some way been "handled" by |
213 | * the ISR. Either it was a spurious Rx interrupt, or | |
214 | * it was a Tx interrupt that has been filtered by | |
215 | * the ISR. | |
216 | */ | |
217 | et131x_enable_interrupts(adapter); | |
218 | goto out; | |
219 | } | |
220 | ||
221 | /* We need to save the interrupt status value for use in our | |
222 | * DPC. We will clear the software copy of that in that | |
223 | * routine. | |
224 | */ | |
225 | adapter->Stats.InterruptStatus = status; | |
226 | ||
227 | /* Schedule the ISR handler as a bottom-half task in the | |
228 | * kernel's tq_immediate queue, and mark the queue for | |
229 | * execution | |
230 | */ | |
231 | schedule_work(&adapter->task); | |
cfb739b4 GKH |
232 | out: |
233 | return IRQ_RETVAL(handled); | |
234 | } | |
235 | ||
236 | /** | |
237 | * et131x_isr_handler - The ISR handler | |
238 | * @p_adapter, a pointer to the device's private adapter structure | |
239 | * | |
240 | * scheduled to run in a deferred context by the ISR. This is where the ISR's | |
241 | * work actually gets done. | |
242 | */ | |
243 | void et131x_isr_handler(struct work_struct *work) | |
244 | { | |
25ad00bb | 245 | struct et131x_adapter *etdev = |
cfb739b4 | 246 | container_of(work, struct et131x_adapter, task); |
2211b732 | 247 | u32 status = etdev->Stats.InterruptStatus; |
f3f415a3 | 248 | ADDRESS_MAP_t __iomem *iomem = etdev->regs; |
cfb739b4 GKH |
249 | |
250 | /* | |
251 | * These first two are by far the most common. Once handled, we clear | |
252 | * their two bits in the status word. If the word is now zero, we | |
253 | * exit. | |
254 | */ | |
255 | /* Handle all the completed Transmit interrupts */ | |
2211b732 | 256 | if (status & ET_INTR_TXDMA_ISR) { |
25ad00bb | 257 | et131x_handle_send_interrupt(etdev); |
cfb739b4 GKH |
258 | } |
259 | ||
260 | /* Handle all the completed Receives interrupts */ | |
2211b732 | 261 | if (status & ET_INTR_RXDMA_XFR_DONE) { |
25ad00bb | 262 | et131x_handle_recv_interrupt(etdev); |
cfb739b4 GKH |
263 | } |
264 | ||
2211b732 | 265 | status &= 0xffffffd7; |
cfb739b4 | 266 | |
2211b732 | 267 | if (status) { |
cfb739b4 | 268 | /* Handle the TXDMA Error interrupt */ |
2211b732 | 269 | if (status & ET_INTR_TXDMA_ERR) { |
fba84166 | 270 | u32 txdma_err; |
cfb739b4 GKH |
271 | |
272 | /* Following read also clears the register (COR) */ | |
fba84166 | 273 | txdma_err = readl(&iomem->txdma.TxDmaError); |
cfb739b4 | 274 | |
15700039 | 275 | dev_warn(&etdev->pdev->dev, |
cfb739b4 | 276 | "TXDMA_ERR interrupt, error = %d\n", |
fba84166 | 277 | txdma_err); |
cfb739b4 GKH |
278 | } |
279 | ||
280 | /* Handle Free Buffer Ring 0 and 1 Low interrupt */ | |
2211b732 | 281 | if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) { |
cfb739b4 GKH |
282 | /* |
283 | * This indicates the number of unused buffers in | |
284 | * RXDMA free buffer ring 0 is <= the limit you | |
285 | * programmed. Free buffer resources need to be | |
286 | * returned. Free buffers are consumed as packets | |
287 | * are passed from the network to the host. The host | |
288 | * becomes aware of the packets from the contents of | |
289 | * the packet status ring. This ring is queried when | |
290 | * the packet done interrupt occurs. Packets are then | |
291 | * passed to the OS. When the OS is done with the | |
292 | * packets the resources can be returned to the | |
293 | * ET1310 for re-use. This interrupt is one method of | |
294 | * returning resources. | |
295 | */ | |
cfb739b4 GKH |
296 | |
297 | /* If the user has flow control on, then we will | |
298 | * send a pause packet, otherwise just exit | |
299 | */ | |
25ad00bb AC |
300 | if (etdev->FlowControl == TxOnly || |
301 | etdev->FlowControl == Both) { | |
f2c98d27 | 302 | u32 pm_csr; |
cfb739b4 GKH |
303 | |
304 | /* Tell the device to send a pause packet via | |
cfc52eb6 AC |
305 | * the back pressure register (bp req and |
306 | * bp xon/xoff) | |
cfb739b4 | 307 | */ |
f2c98d27 | 308 | pm_csr = readl(&iomem->global.pm_csr); |
cfc52eb6 AC |
309 | if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) |
310 | writel(3, &iomem->txmac.bp_ctrl); | |
cfb739b4 GKH |
311 | } |
312 | } | |
313 | ||
314 | /* Handle Packet Status Ring Low Interrupt */ | |
2211b732 | 315 | if (status & ET_INTR_RXDMA_STAT_LOW) { |
cfb739b4 GKH |
316 | |
317 | /* | |
318 | * Same idea as with the two Free Buffer Rings. | |
319 | * Packets going from the network to the host each | |
320 | * consume a free buffer resource and a packet status | |
321 | * resource. These resoures are passed to the OS. | |
322 | * When the OS is done with the resources, they need | |
323 | * to be returned to the ET1310. This is one method | |
324 | * of returning the resources. | |
325 | */ | |
326 | } | |
327 | ||
328 | /* Handle RXDMA Error Interrupt */ | |
2211b732 | 329 | if (status & ET_INTR_RXDMA_ERR) { |
cfb739b4 GKH |
330 | /* |
331 | * The rxdma_error interrupt is sent when a time-out | |
332 | * on a request issued by the JAGCore has occurred or | |
333 | * a completion is returned with an un-successful | |
334 | * status. In both cases the request is considered | |
335 | * complete. The JAGCore will automatically re-try the | |
336 | * request in question. Normally information on events | |
337 | * like these are sent to the host using the "Advanced | |
338 | * Error Reporting" capability. This interrupt is | |
339 | * another way of getting similar information. The | |
340 | * only thing required is to clear the interrupt by | |
341 | * reading the ISR in the global resources. The | |
342 | * JAGCore will do a re-try on the request. Normally | |
343 | * you should never see this interrupt. If you start | |
344 | * to see this interrupt occurring frequently then | |
345 | * something bad has occurred. A reset might be the | |
346 | * thing to do. | |
347 | */ | |
64f93036 | 348 | /* TRAP();*/ |
cfb739b4 | 349 | |
15700039 | 350 | dev_warn(&etdev->pdev->dev, |
cfb739b4 | 351 | "RxDMA_ERR interrupt, error %x\n", |
d97aabcd | 352 | readl(&iomem->txmac.tx_test)); |
cfb739b4 GKH |
353 | } |
354 | ||
355 | /* Handle the Wake on LAN Event */ | |
2211b732 | 356 | if (status & ET_INTR_WOL) { |
cfb739b4 GKH |
357 | /* |
358 | * This is a secondary interrupt for wake on LAN. | |
359 | * The driver should never see this, if it does, | |
360 | * something serious is wrong. We will TRAP the | |
361 | * message when we are in DBG mode, otherwise we | |
362 | * will ignore it. | |
363 | */ | |
15700039 | 364 | dev_err(&etdev->pdev->dev, "WAKE_ON_LAN interrupt\n"); |
cfb739b4 GKH |
365 | } |
366 | ||
367 | /* Handle the PHY interrupt */ | |
2211b732 | 368 | if (status & ET_INTR_PHY) { |
f2c98d27 | 369 | u32 pm_csr; |
cfb739b4 GKH |
370 | MI_BMSR_t BmsrInts, BmsrData; |
371 | MI_ISR_t myIsr; | |
372 | ||
cfb739b4 GKH |
373 | /* If we are in coma mode when we get this interrupt, |
374 | * we need to disable it. | |
375 | */ | |
f2c98d27 AC |
376 | pm_csr = readl(&iomem->global.pm_csr); |
377 | if (pm_csr & ET_PM_PHY_SW_COMA) { | |
cfb739b4 GKH |
378 | /* |
379 | * Check to see if we are in coma mode and if | |
380 | * so, disable it because we will not be able | |
381 | * to read PHY values until we are out. | |
382 | */ | |
25ad00bb | 383 | DisablePhyComa(etdev); |
cfb739b4 GKH |
384 | } |
385 | ||
386 | /* Read the PHY ISR to clear the reason for the | |
387 | * interrupt. | |
388 | */ | |
25ad00bb | 389 | MiRead(etdev, (uint8_t) offsetof(MI_REGS_t, isr), |
cfb739b4 GKH |
390 | &myIsr.value); |
391 | ||
25ad00bb AC |
392 | if (!etdev->ReplicaPhyLoopbk) { |
393 | MiRead(etdev, | |
cfb739b4 GKH |
394 | (uint8_t) offsetof(MI_REGS_t, bmsr), |
395 | &BmsrData.value); | |
396 | ||
397 | BmsrInts.value = | |
25ad00bb AC |
398 | etdev->Bmsr.value ^ BmsrData.value; |
399 | etdev->Bmsr.value = BmsrData.value; | |
cfb739b4 | 400 | |
cfb739b4 | 401 | /* Do all the cable in / cable out stuff */ |
25ad00bb | 402 | et131x_Mii_check(etdev, BmsrData, BmsrInts); |
cfb739b4 GKH |
403 | } |
404 | } | |
405 | ||
406 | /* Let's move on to the TxMac */ | |
2211b732 | 407 | if (status & ET_INTR_TXMAC) { |
003e52e8 | 408 | u32 err = readl(&iomem->txmac.err); |
cfb739b4 GKH |
409 | |
410 | /* | |
411 | * When any of the errors occur and TXMAC generates | |
412 | * an interrupt to report these errors, it usually | |
413 | * means that TXMAC has detected an error in the data | |
414 | * stream retrieved from the on-chip Tx Q. All of | |
415 | * these errors are catastrophic and TXMAC won't be | |
416 | * able to recover data when these errors occur. In | |
417 | * a nutshell, the whole Tx path will have to be reset | |
418 | * and re-configured afterwards. | |
419 | */ | |
15700039 | 420 | dev_warn(&etdev->pdev->dev, |
cfb739b4 | 421 | "TXMAC interrupt, error 0x%08x\n", |
ceef1a5e | 422 | err); |
cfb739b4 GKH |
423 | |
424 | /* If we are debugging, we want to see this error, | |
425 | * otherwise we just want the device to be reset and | |
426 | * continue | |
427 | */ | |
cfb739b4 GKH |
428 | } |
429 | ||
430 | /* Handle RXMAC Interrupt */ | |
2211b732 | 431 | if (status & ET_INTR_RXMAC) { |
cfb739b4 GKH |
432 | /* |
433 | * These interrupts are catastrophic to the device, | |
434 | * what we need to do is disable the interrupts and | |
435 | * set the flag to cause us to reset so we can solve | |
436 | * this issue. | |
437 | */ | |
25ad00bb | 438 | /* MP_SET_FLAG( etdev, |
64f93036 | 439 | fMP_ADAPTER_HARDWARE_ERROR); */ |
cfb739b4 | 440 | |
15700039 | 441 | dev_warn(&etdev->pdev->dev, |
64f93036 | 442 | "RXMAC interrupt, error 0x%08x. Requesting reset\n", |
fef5ba3a | 443 | readl(&iomem->rxmac.err_reg)); |
cfb739b4 | 444 | |
15700039 | 445 | dev_warn(&etdev->pdev->dev, |
cfb739b4 | 446 | "Enable 0x%08x, Diag 0x%08x\n", |
bd03d0d5 | 447 | readl(&iomem->rxmac.ctrl), |
f7ae1957 | 448 | readl(&iomem->rxmac.rxq_diag)); |
cfb739b4 GKH |
449 | |
450 | /* | |
451 | * If we are debugging, we want to see this error, | |
452 | * otherwise we just want the device to be reset and | |
453 | * continue | |
454 | */ | |
cfb739b4 GKH |
455 | } |
456 | ||
457 | /* Handle MAC_STAT Interrupt */ | |
2211b732 | 458 | if (status & ET_INTR_MAC_STAT) { |
cfb739b4 GKH |
459 | /* |
460 | * This means at least one of the un-masked counters | |
461 | * in the MAC_STAT block has rolled over. Use this | |
462 | * to maintain the top, software managed bits of the | |
463 | * counter(s). | |
464 | */ | |
25ad00bb | 465 | HandleMacStatInterrupt(etdev); |
cfb739b4 GKH |
466 | } |
467 | ||
468 | /* Handle SLV Timeout Interrupt */ | |
2211b732 | 469 | if (status & ET_INTR_SLV_TIMEOUT) { |
cfb739b4 GKH |
470 | /* |
471 | * This means a timeout has occured on a read or | |
472 | * write request to one of the JAGCore registers. The | |
473 | * Global Resources block has terminated the request | |
474 | * and on a read request, returned a "fake" value. | |
475 | * The most likely reasons are: Bad Address or the | |
476 | * addressed module is in a power-down state and | |
477 | * can't respond. | |
478 | */ | |
cfb739b4 GKH |
479 | } |
480 | } | |
20dedd3f | 481 | et131x_enable_interrupts(etdev); |
cfb739b4 | 482 | } |