[mirror_ubuntu-artful-kernel.git] / drivers / staging / fbtft / fb_upd161704.c

/*
 * FB driver for the uPD161704 LCD Controller
 *
 * Copyright (C) 2014 Seong-Woo Kim
 *
 * Based on fb_ili9325.c by Noralf Tronnes
 * Based on ili9325.c by Jeroen Domburg
 * Init code from UTFT library by Henning Karlsen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/delay.h>

#include "fbtft.h"

#define DRVNAME		"fb_upd161704"
#define WIDTH		240
#define HEIGHT		320
#define BPP		16

static int init_display(struct fbtft_par *par)
{
	par->fbtftops.reset(par);

	if (par->gpio.cs != -1)
		gpio_set_value(par->gpio.cs, 0);  /* Activate chip */

	/* Initialization sequence from Lib_UTFT */

	/* register reset */
	write_reg(par, 0x0003, 0x0001);	/* Soft reset */

	/* oscillator start */
	write_reg(par, 0x003A, 0x0001);	/*Oscillator 0: stop, 1: operation */
	udelay(100);

	/* y-setting */
	write_reg(par, 0x0024, 0x007B);	/* amplitude setting */
	udelay(10);
	write_reg(par, 0x0025, 0x003B);	/* amplitude setting */
	write_reg(par, 0x0026, 0x0034);	/* amplitude setting */
	udelay(10);
	write_reg(par, 0x0027, 0x0004);	/* amplitude setting */
	write_reg(par, 0x0052, 0x0025);	/* circuit setting 1 */
	udelay(10);
	write_reg(par, 0x0053, 0x0033);	/* circuit setting 2 */
	write_reg(par, 0x0061, 0x001C);	/* adjustment V10 positive polarity */
	udelay(10);
	write_reg(par, 0x0062, 0x002C);	/* adjustment V9 negative polarity */
	write_reg(par, 0x0063, 0x0022);	/* adjustment V34 positive polarity */
	udelay(10);
	write_reg(par, 0x0064, 0x0027);	/* adjustment V31 negative polarity */
	udelay(10);
	write_reg(par, 0x0065, 0x0014);	/* adjustment V61 negative polarity */
	udelay(10);
	write_reg(par, 0x0066, 0x0010);	/* adjustment V61 negative polarity */

	/* Basical clock for 1 line (BASECOUNT[7:0]) number specified */
	write_reg(par, 0x002E, 0x002D);

	/* Power supply setting */
	write_reg(par, 0x0019, 0x0000);	/* DC/DC output setting */
	udelay(200);
	write_reg(par, 0x001A, 0x1000);	/* DC/DC frequency setting */
	write_reg(par, 0x001B, 0x0023);	/* DC/DC rising setting */
	write_reg(par, 0x001C, 0x0C01);	/* Regulator voltage setting */
	write_reg(par, 0x001D, 0x0000);	/* Regulator current setting */
	write_reg(par, 0x001E, 0x0009);	/* VCOM output setting */
	write_reg(par, 0x001F, 0x0035);	/* VCOM amplitude setting */
	write_reg(par, 0x0020, 0x0015);	/* VCOMM cencter setting */
	write_reg(par, 0x0018, 0x1E7B);	/* DC/DC operation setting */

	/* windows setting */
	write_reg(par, 0x0008, 0x0000);	/* Minimum X address */
	write_reg(par, 0x0009, 0x00EF);	/* Maximum X address */
	write_reg(par, 0x000a, 0x0000);	/* Minimum Y address */
	write_reg(par, 0x000b, 0x013F);	/* Maximum Y address */

	/* LCD display area setting */
	write_reg(par, 0x0029, 0x0000);	/* [LCDSIZE]  X MIN. size set */
	write_reg(par, 0x002A, 0x0000);	/* [LCDSIZE]  Y MIN. size set */
	write_reg(par, 0x002B, 0x00EF);	/* [LCDSIZE]  X MAX. size set */
	write_reg(par, 0x002C, 0x013F);	/* [LCDSIZE]  Y MAX. size set */

	/* Gate scan setting */
	write_reg(par, 0x0032, 0x0002);

	/* n line inversion line number */
	write_reg(par, 0x0033, 0x0000);

	/* Line inversion/frame inversion/interlace setting */
	write_reg(par, 0x0037, 0x0000);

	/* Gate scan operation setting register */
	write_reg(par, 0x003B, 0x0001);

	/* Color mode */
	/*GS = 0: 260-k color (64 gray scale), GS = 1: 8 color (2 gray scale) */
	write_reg(par, 0x0004, 0x0000);

	/* RAM control register */
	write_reg(par, 0x0005, 0x0000);	/*Window access 00:Normal, 10:Window */

	/* Display setting register 2 */
	write_reg(par, 0x0001, 0x0000);

	/* display setting */
	write_reg(par, 0x0000, 0x0000);	/* display on */

	return 0;
}

static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
{
	switch (par->info->var.rotate) {
	/* R20h = Horizontal GRAM Start Address */
	/* R21h = Vertical GRAM Start Address */
	case 0:
		write_reg(par, 0x0006, xs);
		write_reg(par, 0x0007, ys);
		break;
	case 180:
		write_reg(par, 0x0006, WIDTH - 1 - xs);
		write_reg(par, 0x0007, HEIGHT - 1 - ys);
		break;
	case 270:
		write_reg(par, 0x0006, WIDTH - 1 - ys);
		write_reg(par, 0x0007, xs);
		break;
	case 90:
		write_reg(par, 0x0006, ys);
		write_reg(par, 0x0007, HEIGHT - 1 - xs);
		break;
	}

	write_reg(par, 0x0e); /* Write Data to GRAM */
}

static int set_var(struct fbtft_par *par)
{
	switch (par->info->var.rotate) {
	/* AM: GRAM update direction */
	case 0:
		write_reg(par, 0x01, 0x0000);
		write_reg(par, 0x05, 0x0000);
		break;
	case 180:
		write_reg(par, 0x01, 0x00C0);
		write_reg(par, 0x05, 0x0000);
		break;
	case 270:
		write_reg(par, 0x01, 0x0080);
		write_reg(par, 0x05, 0x0001);
		break;
	case 90:
		write_reg(par, 0x01, 0x0040);
		write_reg(par, 0x05, 0x0001);
		break;
	}

	return 0;
}

static struct fbtft_display display = {
	.regwidth = 16,
	.width = WIDTH,
	.height = HEIGHT,
	.fbtftops = {
		.init_display = init_display,
		.set_addr_win = set_addr_win,
		.set_var = set_var,
	},
};

FBTFT_REGISTER_DRIVER(DRVNAME, "nec,upd161704", &display);

MODULE_ALIAS("spi:" DRVNAME);
MODULE_ALIAS("platform:" DRVNAME);
MODULE_ALIAS("spi:upd161704");
MODULE_ALIAS("platform:upd161704");

MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller");
MODULE_AUTHOR("Seong-Woo Kim");
MODULE_LICENSE("GPL");
Commit	Line	Data
ef0459c7 TP	1	/*
	2	* FB driver for the uPD161704 LCD Controller
	3	*
	4	* Copyright (C) 2014 Seong-Woo Kim
	5	*
	6	* Based on fb_ili9325.c by Noralf Tronnes
	7	* Based on ili9325.c by Jeroen Domburg
	8	* Init code from UTFT library by Henning Karlsen
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
ef0459c7 TP	19	*/
	20
	21	#include <linux/module.h>
	22	#include <linux/kernel.h>
	23	#include <linux/init.h>
	24	#include <linux/gpio.h>
	25	#include <linux/delay.h>
	26
	27	#include "fbtft.h"
	28
	29	#define DRVNAME "fb_upd161704"
	30	#define WIDTH 240
	31	#define HEIGHT 320
	32	#define BPP 16
	33
	34	static int init_display(struct fbtft_par *par)
	35	{
ef0459c7 TP	36	par->fbtftops.reset(par);
	37
	38	if (par->gpio.cs != -1)
	39	gpio_set_value(par->gpio.cs, 0); /* Activate chip */
	40
	41	/* Initialization sequence from Lib_UTFT */
	42
	43	/* register reset */
4643b70a	44	write_reg(par, 0x0003, 0x0001); /* Soft reset */
ef0459c7 TP	45
ef0459c7 TP	46	/* oscillator start */
4643b70a	47	write_reg(par, 0x003A, 0x0001); /Oscillator 0: stop, 1: operation /
ef0459c7 TP	48	udelay(100);
	49
	50	/* y-setting */
4643b70a	51	write_reg(par, 0x0024, 0x007B); /* amplitude setting */
ef0459c7	52	udelay(10);
4643b70a MS	53	write_reg(par, 0x0025, 0x003B); /* amplitude setting */
4643b70a MS	54	write_reg(par, 0x0026, 0x0034); /* amplitude setting */
ef0459c7	55	udelay(10);
4643b70a MS	56	write_reg(par, 0x0027, 0x0004); /* amplitude setting */
4643b70a MS	57	write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */
ef0459c7	58	udelay(10);
4643b70a MS	59	write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */
4643b70a MS	60	write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */
ef0459c7	61	udelay(10);
4643b70a MS	62	write_reg(par, 0x0062, 0x002C); /* adjustment V9 negative polarity */
4643b70a MS	63	write_reg(par, 0x0063, 0x0022); /* adjustment V34 positive polarity */
ef0459c7	64	udelay(10);
4643b70a	65	write_reg(par, 0x0064, 0x0027); /* adjustment V31 negative polarity */
ef0459c7	66	udelay(10);
4643b70a	67	write_reg(par, 0x0065, 0x0014); /* adjustment V61 negative polarity */
ef0459c7	68	udelay(10);
4643b70a MS	69	write_reg(par, 0x0066, 0x0010); /* adjustment V61 negative polarity */
4643b70a MS	70
ef0459c7	71	/* Basical clock for 1 line (BASECOUNT[7:0]) number specified */
4643b70a MS	72	write_reg(par, 0x002E, 0x002D);
4643b70a MS	73
ef0459c7	74	/* Power supply setting */
4643b70a	75	write_reg(par, 0x0019, 0x0000); /* DC/DC output setting */
ef0459c7	76	udelay(200);
4643b70a MS	77	write_reg(par, 0x001A, 0x1000); /* DC/DC frequency setting */
	78	write_reg(par, 0x001B, 0x0023); /* DC/DC rising setting */
	79	write_reg(par, 0x001C, 0x0C01); /* Regulator voltage setting */
	80	write_reg(par, 0x001D, 0x0000); /* Regulator current setting */
	81	write_reg(par, 0x001E, 0x0009); /* VCOM output setting */
	82	write_reg(par, 0x001F, 0x0035); /* VCOM amplitude setting */
	83	write_reg(par, 0x0020, 0x0015); /* VCOMM cencter setting */
	84	write_reg(par, 0x0018, 0x1E7B); /* DC/DC operation setting */
ef0459c7 TP	85
ef0459c7 TP	86	/* windows setting */
4643b70a MS	87	write_reg(par, 0x0008, 0x0000); /* Minimum X address */
	88	write_reg(par, 0x0009, 0x00EF); /* Maximum X address */
	89	write_reg(par, 0x000a, 0x0000); /* Minimum Y address */
	90	write_reg(par, 0x000b, 0x013F); /* Maximum Y address */
ef0459c7 TP	91
ef0459c7 TP	92	/* LCD display area setting */
4643b70a MS	93	write_reg(par, 0x0029, 0x0000); /* [LCDSIZE] X MIN. size set */
	94	write_reg(par, 0x002A, 0x0000); /* [LCDSIZE] Y MIN. size set */
	95	write_reg(par, 0x002B, 0x00EF); /* [LCDSIZE] X MAX. size set */
	96	write_reg(par, 0x002C, 0x013F); /* [LCDSIZE] Y MAX. size set */
ef0459c7 TP	97
ef0459c7 TP	98	/* Gate scan setting */
4643b70a MS	99	write_reg(par, 0x0032, 0x0002);
4643b70a MS	100
ef0459c7	101	/* n line inversion line number */
4643b70a	102	write_reg(par, 0x0033, 0x0000);
ef0459c7 TP	103
ef0459c7 TP	104	/* Line inversion/frame inversion/interlace setting */
4643b70a MS	105	write_reg(par, 0x0037, 0x0000);
4643b70a MS	106
ef0459c7	107	/* Gate scan operation setting register */
4643b70a MS	108	write_reg(par, 0x003B, 0x0001);
4643b70a MS	109
ef0459c7 TP	110	/* Color mode */
ef0459c7 TP	111	/GS = 0: 260-k color (64 gray scale), GS = 1: 8 color (2 gray scale) /
4643b70a	112	write_reg(par, 0x0004, 0x0000);
ef0459c7 TP	113
ef0459c7 TP	114	/* RAM control register */
4643b70a	115	write_reg(par, 0x0005, 0x0000); /Window access 00:Normal, 10:Window /
ef0459c7 TP	116
ef0459c7 TP	117	/* Display setting register 2 */
4643b70a	118	write_reg(par, 0x0001, 0x0000);
ef0459c7 TP	119
ef0459c7 TP	120	/* display setting */
4643b70a	121	write_reg(par, 0x0000, 0x0000); /* display on */
ef0459c7 TP	122
	123	return 0;
	124	}
	125
	126	static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
	127	{
ef0459c7 TP	128	switch (par->info->var.rotate) {
	129	/* R20h = Horizontal GRAM Start Address */
	130	/* R21h = Vertical GRAM Start Address */
	131	case 0:
	132	write_reg(par, 0x0006, xs);
	133	write_reg(par, 0x0007, ys);
	134	break;
	135	case 180:
	136	write_reg(par, 0x0006, WIDTH - 1 - xs);
	137	write_reg(par, 0x0007, HEIGHT - 1 - ys);
	138	break;
	139	case 270:
	140	write_reg(par, 0x0006, WIDTH - 1 - ys);
	141	write_reg(par, 0x0007, xs);
	142	break;
	143	case 90:
	144	write_reg(par, 0x0006, ys);
	145	write_reg(par, 0x0007, HEIGHT - 1 - xs);
	146	break;
	147	}
	148
	149	write_reg(par, 0x0e); /* Write Data to GRAM */
	150	}
	151
	152	static int set_var(struct fbtft_par *par)
	153	{
ef0459c7 TP	154	switch (par->info->var.rotate) {
	155	/* AM: GRAM update direction */
	156	case 0:
	157	write_reg(par, 0x01, 0x0000);
	158	write_reg(par, 0x05, 0x0000);
	159	break;
	160	case 180:
	161	write_reg(par, 0x01, 0x00C0);
	162	write_reg(par, 0x05, 0x0000);
	163	break;
	164	case 270:
	165	write_reg(par, 0x01, 0x0080);
	166	write_reg(par, 0x05, 0x0001);
	167	break;
	168	case 90:
	169	write_reg(par, 0x01, 0x0040);
	170	write_reg(par, 0x05, 0x0001);
	171	break;
	172	}
	173
	174	return 0;
	175	}
	176
	177	static struct fbtft_display display = {
	178	.regwidth = 16,
	179	.width = WIDTH,
	180	.height = HEIGHT,
	181	.fbtftops = {
	182	.init_display = init_display,
	183	.set_addr_win = set_addr_win,
	184	.set_var = set_var,
	185	},
	186	};
1014c2ce	187
ef0459c7 TP	188	FBTFT_REGISTER_DRIVER(DRVNAME, "nec,upd161704", &display);
	189
	190	MODULE_ALIAS("spi:" DRVNAME);
	191	MODULE_ALIAS("platform:" DRVNAME);
	192	MODULE_ALIAS("spi:upd161704");
	193	MODULE_ALIAS("platform:upd161704");
	194
	195	MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller");
	196	MODULE_AUTHOR("Seong-Woo Kim");
	197	MODULE_LICENSE("GPL");