[mirror_ubuntu-artful-kernel.git] / drivers / staging / fsl-dpaa2 / ethernet / dpaa2-eth.h

/* Copyright 2014-2016 Freescale Semiconductor Inc.
 * Copyright 2016 NXP
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *	 notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *	 notice, this list of conditions and the following disclaimer in the
 *	 documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *	 names of its contributors may be used to endorse or promote products
 *	 derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef __DPAA2_ETH_H
#define __DPAA2_ETH_H

#include <linux/netdevice.h>
#include <linux/if_vlan.h>

#include "../../fsl-mc/include/dpaa2-io.h"
#include "../../fsl-mc/include/dpaa2-fd.h"
#include "../../fsl-mc/include/dpbp.h"
#include "../../fsl-mc/include/dpcon.h"
#include "dpni.h"
#include "dpni-cmd.h"

#include "dpaa2-eth-trace.h"

#define DPAA2_ETH_STORE_SIZE		16

/* Maximum number of scatter-gather entries in an ingress frame,
 * considering the maximum receive frame size is 64K
 */
#define DPAA2_ETH_MAX_SG_ENTRIES	((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)

/* Maximum acceptable MTU value. It is in direct relation with the hardware
 * enforced Max Frame Length (currently 10k).
 */
#define DPAA2_ETH_MFL			(10 * 1024)
#define DPAA2_ETH_MAX_MTU		(DPAA2_ETH_MFL - VLAN_ETH_HLEN)
/* Convert L3 MTU to L2 MFL */
#define DPAA2_ETH_L2_MAX_FRM(mtu)	((mtu) + VLAN_ETH_HLEN)

/* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo
 * frames in the Rx queues (length of the current frame is not
 * taken into account when making the taildrop decision)
 */
#define DPAA2_ETH_TAILDROP_THRESH	(64 * 1024)

/* Buffer quota per queue. Must be large enough such that for minimum sized
 * frames taildrop kicks in before the bpool gets depleted, so we compute
 * how many 64B frames fit inside the taildrop threshold and add a margin
 * to accommodate the buffer refill delay.
 */
#define DPAA2_ETH_MAX_FRAMES_PER_QUEUE	(DPAA2_ETH_TAILDROP_THRESH / 64)
#define DPAA2_ETH_NUM_BUFS		(DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256)
#define DPAA2_ETH_REFILL_THRESH		DPAA2_ETH_MAX_FRAMES_PER_QUEUE

/* Maximum number of buffers that can be acquired/released through a single
 * QBMan command
 */
#define DPAA2_ETH_BUFS_PER_CMD		7

/* Hardware requires alignment for ingress/egress buffer addresses
 * and ingress buffer lengths.
 */
#define DPAA2_ETH_RX_BUF_SIZE		2048
#define DPAA2_ETH_TX_BUF_ALIGN		64
#define DPAA2_ETH_RX_BUF_ALIGN		256
#define DPAA2_ETH_NEEDED_HEADROOM(p_priv) \
	((p_priv)->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN)

/* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but we need to allocate ingress
 * buffers large enough to allow building an skb around them and also account
 * for alignment restrictions
 */
#define DPAA2_ETH_BUF_RAW_SIZE \
	(DPAA2_ETH_RX_BUF_SIZE + \
	SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \
	DPAA2_ETH_RX_BUF_ALIGN)

/* We are accommodating a skb backpointer and some S/G info
 * in the frame's software annotation. The hardware
 * options are either 0 or 64, so we choose the latter.
 */
#define DPAA2_ETH_SWA_SIZE		64

/* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
struct dpaa2_eth_swa {
	struct sk_buff *skb;
	struct scatterlist *scl;
	int num_sg;
	int num_dma_bufs;
};

/* Annotation valid bits in FD FRC */
#define DPAA2_FD_FRC_FASV		0x8000
#define DPAA2_FD_FRC_FAEADV		0x4000
#define DPAA2_FD_FRC_FAPRV		0x2000
#define DPAA2_FD_FRC_FAIADV		0x1000
#define DPAA2_FD_FRC_FASWOV		0x0800
#define DPAA2_FD_FRC_FAICFDV		0x0400

/* Error bits in FD CTRL */
#define DPAA2_FD_CTRL_UFD		0x00000004
#define DPAA2_FD_CTRL_SBE		0x00000008
#define DPAA2_FD_CTRL_FSE		0x00000010
#define DPAA2_FD_CTRL_FAERR		0x00000020

#define DPAA2_FD_RX_ERR_MASK		(DPAA2_FD_CTRL_SBE	| \
					 DPAA2_FD_CTRL_FAERR)
#define DPAA2_FD_TX_ERR_MASK		(DPAA2_FD_CTRL_UFD	| \
					 DPAA2_FD_CTRL_SBE	| \
					 DPAA2_FD_CTRL_FSE	| \
					 DPAA2_FD_CTRL_FAERR)

/* Annotation bits in FD CTRL */
#define DPAA2_FD_CTRL_ASAL		0x00020000	/* ASAL = 128 */
#define DPAA2_FD_CTRL_PTA		0x00800000
#define DPAA2_FD_CTRL_PTV1		0x00400000

/* Frame annotation status */
struct dpaa2_fas {
	u8 reserved;
	u8 ppid;
	__le16 ifpid;
	__le32 status;
} __packed;

/* Frame annotation status word is located in the first 8 bytes
 * of the buffer's hardware annoatation area
 */
#define DPAA2_FAS_OFFSET		0
#define DPAA2_FAS_SIZE			(sizeof(struct dpaa2_fas))

/* Accessors for the hardware annotation fields that we use */
#define dpaa2_get_hwa(buf_addr) \
	((void *)(buf_addr) + DPAA2_ETH_SWA_SIZE)
#define dpaa2_get_fas(buf_addr) \
	(struct dpaa2_fas *)(dpaa2_get_hwa(buf_addr) + DPAA2_FAS_OFFSET)

/* Error and status bits in the frame annotation status word */
/* Debug frame, otherwise supposed to be discarded */
#define DPAA2_FAS_DISC			0x80000000
/* MACSEC frame */
#define DPAA2_FAS_MS			0x40000000
#define DPAA2_FAS_PTP			0x08000000
/* Ethernet multicast frame */
#define DPAA2_FAS_MC			0x04000000
/* Ethernet broadcast frame */
#define DPAA2_FAS_BC			0x02000000
#define DPAA2_FAS_KSE			0x00040000
#define DPAA2_FAS_EOFHE			0x00020000
#define DPAA2_FAS_MNLE			0x00010000
#define DPAA2_FAS_TIDE			0x00008000
#define DPAA2_FAS_PIEE			0x00004000
/* Frame length error */
#define DPAA2_FAS_FLE			0x00002000
/* Frame physical error */
#define DPAA2_FAS_FPE			0x00001000
#define DPAA2_FAS_PTE			0x00000080
#define DPAA2_FAS_ISP			0x00000040
#define DPAA2_FAS_PHE			0x00000020
#define DPAA2_FAS_BLE			0x00000010
/* L3 csum validation performed */
#define DPAA2_FAS_L3CV			0x00000008
/* L3 csum error */
#define DPAA2_FAS_L3CE			0x00000004
/* L4 csum validation performed */
#define DPAA2_FAS_L4CV			0x00000002
/* L4 csum error */
#define DPAA2_FAS_L4CE			0x00000001
/* Possible errors on the ingress path */
#define DPAA2_FAS_RX_ERR_MASK		(DPAA2_FAS_KSE		| \
					 DPAA2_FAS_EOFHE	| \
					 DPAA2_FAS_MNLE		| \
					 DPAA2_FAS_TIDE		| \
					 DPAA2_FAS_PIEE		| \
					 DPAA2_FAS_FLE		| \
					 DPAA2_FAS_FPE		| \
					 DPAA2_FAS_PTE		| \
					 DPAA2_FAS_ISP		| \
					 DPAA2_FAS_PHE		| \
					 DPAA2_FAS_BLE		| \
					 DPAA2_FAS_L3CE		| \
					 DPAA2_FAS_L4CE)
/* Tx errors */
#define DPAA2_FAS_TX_ERR_MASK		(DPAA2_FAS_KSE		| \
					 DPAA2_FAS_EOFHE	| \
					 DPAA2_FAS_MNLE		| \
					 DPAA2_FAS_TIDE)

/* Time in milliseconds between link state updates */
#define DPAA2_ETH_LINK_STATE_REFRESH	1000

/* Number of times to retry a frame enqueue before giving up.
 * Value determined empirically, in order to minimize the number
 * of frames dropped on Tx
 */
#define DPAA2_ETH_ENQUEUE_RETRIES	10

/* Driver statistics, other than those in struct rtnl_link_stats64.
 * These are usually collected per-CPU and aggregated by ethtool.
 */
struct dpaa2_eth_drv_stats {
	__u64	tx_conf_frames;
	__u64	tx_conf_bytes;
	__u64	tx_sg_frames;
	__u64	tx_sg_bytes;
	__u64	rx_sg_frames;
	__u64	rx_sg_bytes;
	/* Enqueues retried due to portal busy */
	__u64	tx_portal_busy;
};

/* Per-FQ statistics */
struct dpaa2_eth_fq_stats {
	/* Number of frames received on this queue */
	__u64 frames;
};

/* Per-channel statistics */
struct dpaa2_eth_ch_stats {
	/* Volatile dequeues retried due to portal busy */
	__u64 dequeue_portal_busy;
	/* Number of CDANs; useful to estimate avg NAPI len */
	__u64 cdan;
	/* Number of frames received on queues from this channel */
	__u64 frames;
	/* Pull errors */
	__u64 pull_err;
};

/* Maximum number of queues associated with a DPNI */
#define DPAA2_ETH_MAX_RX_QUEUES		16
#define DPAA2_ETH_MAX_TX_QUEUES		NR_CPUS
#define DPAA2_ETH_MAX_QUEUES		(DPAA2_ETH_MAX_RX_QUEUES + \
					DPAA2_ETH_MAX_TX_QUEUES)

#define DPAA2_ETH_MAX_DPCONS		NR_CPUS

enum dpaa2_eth_fq_type {
	DPAA2_RX_FQ = 0,
	DPAA2_TX_CONF_FQ,
};

struct dpaa2_eth_priv;

struct dpaa2_eth_fq {
	u32 fqid;
	u32 tx_qdbin;
	u16 flowid;
	int target_cpu;
	struct dpaa2_eth_channel *channel;
	enum dpaa2_eth_fq_type type;

	void (*consume)(struct dpaa2_eth_priv *,
			struct dpaa2_eth_channel *,
			const struct dpaa2_fd *,
			struct napi_struct *);
	struct dpaa2_eth_fq_stats stats;
};

struct dpaa2_eth_channel {
	struct dpaa2_io_notification_ctx nctx;
	struct fsl_mc_device *dpcon;
	int dpcon_id;
	int ch_id;
	int dpio_id;
	struct napi_struct napi;
	struct dpaa2_io_store *store;
	struct dpaa2_eth_priv *priv;
	int buf_count;
	struct dpaa2_eth_ch_stats stats;
};

struct dpaa2_eth_hash_fields {
	u64 rxnfc_field;
	enum net_prot cls_prot;
	int cls_field;
	int size;
};

/* Driver private data */
struct dpaa2_eth_priv {
	struct net_device *net_dev;

	u8 num_fqs;
	struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];

	u8 num_channels;
	struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];

	struct dpni_attr dpni_attrs;
	u16 tx_data_offset;

	struct fsl_mc_device *dpbp_dev;
	u16 bpid;
	struct iommu_domain *iommu_domain;

	u16 tx_qdid;
	struct fsl_mc_io *mc_io;
	/* Cores which have an affine DPIO/DPCON.
	 * This is the cpu set on which Rx and Tx conf frames are processed
	 */
	struct cpumask dpio_cpumask;

	/* Standard statistics */
	struct rtnl_link_stats64 __percpu *percpu_stats;
	/* Extra stats, in addition to the ones known by the kernel */
	struct dpaa2_eth_drv_stats __percpu *percpu_extras;

	u16 mc_token;

	struct dpni_link_state link_state;
	bool do_link_poll;
	struct task_struct *poll_thread;

	/* enabled ethtool hashing bits */
	u64 rx_hash_fields;
};

/* default Rx hash options, set during probing */
#define DPAA2_RXH_SUPPORTED	(RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
				| RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
				| RXH_L4_B_2_3)

#define dpaa2_eth_hash_enabled(priv)	\
	((priv)->dpni_attrs.num_queues > 1)

/* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
#define DPAA2_CLASSIFIER_DMA_SIZE 256

extern const struct ethtool_ops dpaa2_ethtool_ops;
extern const char dpaa2_eth_drv_version[];

static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv)
{
	return priv->dpni_attrs.num_queues;
}

#endif	/* __DPAA2_H */
Commit	Line	Data
6e2387e8 IR	1	/* Copyright 2014-2016 Freescale Semiconductor Inc.
	2	* Copyright 2016 NXP
	3	*
	4	* Redistribution and use in source and binary forms, with or without
	5	* modification, are permitted provided that the following conditions are met:
	6	* * Redistributions of source code must retain the above copyright
	7	* notice, this list of conditions and the following disclaimer.
	8	* * Redistributions in binary form must reproduce the above copyright
	9	* notice, this list of conditions and the following disclaimer in the
	10	* documentation and/or other materials provided with the distribution.
	11	* * Neither the name of Freescale Semiconductor nor the
	12	* names of its contributors may be used to endorse or promote products
	13	* derived from this software without specific prior written permission.
	14	*
	15	*
	16	* ALTERNATIVELY, this software may be distributed under the terms of the
	17	* GNU General Public License ("GPL") as published by the Free Software
	18	* Foundation, either version 2 of that License or (at your option) any
	19	* later version.
	20	*
	21	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	22	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	23	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	24	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	25	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	26	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	27	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	28	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	30	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#ifndef __DPAA2_ETH_H
	34	#define __DPAA2_ETH_H
	35
	36	#include <linux/netdevice.h>
	37	#include <linux/if_vlan.h>
	38
	39	#include "../../fsl-mc/include/dpaa2-io.h"
	40	#include "../../fsl-mc/include/dpaa2-fd.h"
	41	#include "../../fsl-mc/include/dpbp.h"
	42	#include "../../fsl-mc/include/dpcon.h"
	43	#include "dpni.h"
	44	#include "dpni-cmd.h"
	45
5636187b IR	46	#include "dpaa2-eth-trace.h"
5636187b IR	47
6e2387e8 IR	48	#define DPAA2_ETH_STORE_SIZE 16
	49
	50	/* Maximum number of scatter-gather entries in an ingress frame,
	51	* considering the maximum receive frame size is 64K
	52	*/
	53	#define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
	54
	55	/* Maximum acceptable MTU value. It is in direct relation with the hardware
	56	* enforced Max Frame Length (currently 10k).
	57	*/
	58	#define DPAA2_ETH_MFL (10 * 1024)
	59	#define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
	60	/* Convert L3 MTU to L2 MFL */
	61	#define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
	62
	63	/* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo
	64	* frames in the Rx queues (length of the current frame is not
	65	* taken into account when making the taildrop decision)
	66	*/
	67	#define DPAA2_ETH_TAILDROP_THRESH (64 * 1024)
	68
	69	/* Buffer quota per queue. Must be large enough such that for minimum sized
	70	* frames taildrop kicks in before the bpool gets depleted, so we compute
	71	* how many 64B frames fit inside the taildrop threshold and add a margin
	72	* to accommodate the buffer refill delay.
	73	*/
	74	#define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64)
	75	#define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256)
	76	#define DPAA2_ETH_REFILL_THRESH DPAA2_ETH_MAX_FRAMES_PER_QUEUE
	77
	78	/* Maximum number of buffers that can be acquired/released through a single
	79	* QBMan command
	80	*/
	81	#define DPAA2_ETH_BUFS_PER_CMD 7
	82
	83	/* Hardware requires alignment for ingress/egress buffer addresses
	84	* and ingress buffer lengths.
	85	*/
	86	#define DPAA2_ETH_RX_BUF_SIZE 2048
	87	#define DPAA2_ETH_TX_BUF_ALIGN 64
	88	#define DPAA2_ETH_RX_BUF_ALIGN 256
	89	#define DPAA2_ETH_NEEDED_HEADROOM(p_priv) \
	90	((p_priv)->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN)
	91
	92	/* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but we need to allocate ingress
	93	* buffers large enough to allow building an skb around them and also account
	94	* for alignment restrictions
	95	*/
	96	#define DPAA2_ETH_BUF_RAW_SIZE \
	97	(DPAA2_ETH_RX_BUF_SIZE + \
	98	SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \
	99	DPAA2_ETH_RX_BUF_ALIGN)
	100
	101	/* We are accommodating a skb backpointer and some S/G info
	102	* in the frame's software annotation. The hardware
	103	* options are either 0 or 64, so we choose the latter.
	104	*/
	105	#define DPAA2_ETH_SWA_SIZE 64
	106
	107	/* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
	108	struct dpaa2_eth_swa {
	109	struct sk_buff *skb;
	110	struct scatterlist *scl;
	111	int num_sg;
112	int num_dma_bufs;
113	};
114
115	/* Annotation valid bits in FD FRC */
116	#define DPAA2_FD_FRC_FASV 0x8000
117	#define DPAA2_FD_FRC_FAEADV 0x4000
118	#define DPAA2_FD_FRC_FAPRV 0x2000
119	#define DPAA2_FD_FRC_FAIADV 0x1000
120	#define DPAA2_FD_FRC_FASWOV 0x0800
121	#define DPAA2_FD_FRC_FAICFDV 0x0400
122
39163c0c IR	123	/* Error bits in FD CTRL */
	124	#define DPAA2_FD_CTRL_UFD 0x00000004
	125	#define DPAA2_FD_CTRL_SBE 0x00000008
	126	#define DPAA2_FD_CTRL_FSE 0x00000010
	127	#define DPAA2_FD_CTRL_FAERR 0x00000020
	128
	129	#define DPAA2_FD_RX_ERR_MASK (DPAA2_FD_CTRL_SBE \| \
	130	DPAA2_FD_CTRL_FAERR)
	131	#define DPAA2_FD_TX_ERR_MASK (DPAA2_FD_CTRL_UFD \| \
	132	DPAA2_FD_CTRL_SBE \| \
	133	DPAA2_FD_CTRL_FSE \| \
	134	DPAA2_FD_CTRL_FAERR)
	135
6e2387e8 IR	136	/* Annotation bits in FD CTRL */
	137	#define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */
	138	#define DPAA2_FD_CTRL_PTA 0x00800000
	139	#define DPAA2_FD_CTRL_PTV1 0x00400000
	140
	141	/* Frame annotation status */
	142	struct dpaa2_fas {
	143	u8 reserved;
	144	u8 ppid;
	145	__le16 ifpid;
	146	__le32 status;
	147	} __packed;
	148
	149	/* Frame annotation status word is located in the first 8 bytes
	150	* of the buffer's hardware annoatation area
	151	*/
	152	#define DPAA2_FAS_OFFSET 0
	153	#define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
	154
d695e764 IR	155	/* Accessors for the hardware annotation fields that we use */
	156	#define dpaa2_get_hwa(buf_addr) \
	157	((void *)(buf_addr) + DPAA2_ETH_SWA_SIZE)
	158	#define dpaa2_get_fas(buf_addr) \
	159	(struct dpaa2_fas *)(dpaa2_get_hwa(buf_addr) + DPAA2_FAS_OFFSET)
	160
6e2387e8 IR	161	/* Error and status bits in the frame annotation status word */
	162	/* Debug frame, otherwise supposed to be discarded */
	163	#define DPAA2_FAS_DISC 0x80000000
	164	/* MACSEC frame */
	165	#define DPAA2_FAS_MS 0x40000000
	166	#define DPAA2_FAS_PTP 0x08000000
	167	/* Ethernet multicast frame */
	168	#define DPAA2_FAS_MC 0x04000000
	169	/* Ethernet broadcast frame */
	170	#define DPAA2_FAS_BC 0x02000000
	171	#define DPAA2_FAS_KSE 0x00040000
	172	#define DPAA2_FAS_EOFHE 0x00020000
	173	#define DPAA2_FAS_MNLE 0x00010000
	174	#define DPAA2_FAS_TIDE 0x00008000
	175	#define DPAA2_FAS_PIEE 0x00004000
	176	/* Frame length error */
	177	#define DPAA2_FAS_FLE 0x00002000
	178	/* Frame physical error */
	179	#define DPAA2_FAS_FPE 0x00001000
	180	#define DPAA2_FAS_PTE 0x00000080
	181	#define DPAA2_FAS_ISP 0x00000040
	182	#define DPAA2_FAS_PHE 0x00000020
	183	#define DPAA2_FAS_BLE 0x00000010
	184	/* L3 csum validation performed */
	185	#define DPAA2_FAS_L3CV 0x00000008
	186	/* L3 csum error */
	187	#define DPAA2_FAS_L3CE 0x00000004
	188	/* L4 csum validation performed */
	189	#define DPAA2_FAS_L4CV 0x00000002
	190	/* L4 csum error */
	191	#define DPAA2_FAS_L4CE 0x00000001
	192	/* Possible errors on the ingress path */
39163c0c	193	#define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE \| \
6e2387e8 IR	194	DPAA2_FAS_EOFHE \| \
	195	DPAA2_FAS_MNLE \| \
	196	DPAA2_FAS_TIDE \| \
	197	DPAA2_FAS_PIEE \| \
	198	DPAA2_FAS_FLE \| \
	199	DPAA2_FAS_FPE \| \
	200	DPAA2_FAS_PTE \| \
	201	DPAA2_FAS_ISP \| \
	202	DPAA2_FAS_PHE \| \
	203	DPAA2_FAS_BLE \| \
	204	DPAA2_FAS_L3CE \| \
	205	DPAA2_FAS_L4CE)
	206	/* Tx errors */
39163c0c	207	#define DPAA2_FAS_TX_ERR_MASK (DPAA2_FAS_KSE \| \
6e2387e8 IR	208	DPAA2_FAS_EOFHE \| \
	209	DPAA2_FAS_MNLE \| \
	210	DPAA2_FAS_TIDE)
	211
	212	/* Time in milliseconds between link state updates */
	213	#define DPAA2_ETH_LINK_STATE_REFRESH 1000
	214
	215	/* Number of times to retry a frame enqueue before giving up.
	216	* Value determined empirically, in order to minimize the number
	217	* of frames dropped on Tx
	218	*/
	219	#define DPAA2_ETH_ENQUEUE_RETRIES 10
	220
85047abd IR	221	/* Driver statistics, other than those in struct rtnl_link_stats64.
	222	* These are usually collected per-CPU and aggregated by ethtool.
	223	*/
	224	struct dpaa2_eth_drv_stats {
	225	__u64 tx_conf_frames;
	226	__u64 tx_conf_bytes;
	227	__u64 tx_sg_frames;
	228	__u64 tx_sg_bytes;
	229	__u64 rx_sg_frames;
	230	__u64 rx_sg_bytes;
	231	/* Enqueues retried due to portal busy */
	232	__u64 tx_portal_busy;
	233	};
	234
	235	/* Per-FQ statistics */
	236	struct dpaa2_eth_fq_stats {
	237	/* Number of frames received on this queue */
	238	__u64 frames;
	239	};
	240
	241	/* Per-channel statistics */
	242	struct dpaa2_eth_ch_stats {
	243	/* Volatile dequeues retried due to portal busy */
	244	__u64 dequeue_portal_busy;
	245	/* Number of CDANs; useful to estimate avg NAPI len */
	246	__u64 cdan;
	247	/* Number of frames received on queues from this channel */
	248	__u64 frames;
	249	/* Pull errors */
	250	__u64 pull_err;
	251	};
	252
6e2387e8 IR	253	/* Maximum number of queues associated with a DPNI */
	254	#define DPAA2_ETH_MAX_RX_QUEUES 16
	255	#define DPAA2_ETH_MAX_TX_QUEUES NR_CPUS
	256	#define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
	257	DPAA2_ETH_MAX_TX_QUEUES)
	258
	259	#define DPAA2_ETH_MAX_DPCONS NR_CPUS
	260
	261	enum dpaa2_eth_fq_type {
	262	DPAA2_RX_FQ = 0,
	263	DPAA2_TX_CONF_FQ,
	264	};
	265
	266	struct dpaa2_eth_priv;
	267
	268	struct dpaa2_eth_fq {
	269	u32 fqid;
	270	u32 tx_qdbin;
	271	u16 flowid;
	272	int target_cpu;
	273	struct dpaa2_eth_channel *channel;
	274	enum dpaa2_eth_fq_type type;
	275
	276	void (consume)(struct dpaa2_eth_priv ,
	277	struct dpaa2_eth_channel *,
	278	const struct dpaa2_fd *,
	279	struct napi_struct *);
85047abd	280	struct dpaa2_eth_fq_stats stats;
6e2387e8 IR	281	};
	282
	283	struct dpaa2_eth_channel {
	284	struct dpaa2_io_notification_ctx nctx;
	285	struct fsl_mc_device *dpcon;
	286	int dpcon_id;
	287	int ch_id;
	288	int dpio_id;
	289	struct napi_struct napi;
	290	struct dpaa2_io_store *store;
	291	struct dpaa2_eth_priv *priv;
	292	int buf_count;
85047abd	293	struct dpaa2_eth_ch_stats stats;
6e2387e8 IR	294	};
	295
	296	struct dpaa2_eth_hash_fields {
	297	u64 rxnfc_field;
	298	enum net_prot cls_prot;
	299	int cls_field;
	300	int size;
	301	};
	302
	303	/* Driver private data */
	304	struct dpaa2_eth_priv {
	305	struct net_device *net_dev;
	306
	307	u8 num_fqs;
	308	struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
	309
	310	u8 num_channels;
	311	struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
	312
6e2387e8	313	struct dpni_attr dpni_attrs;
6e2387e8 IR	314	u16 tx_data_offset;
	315
	316	struct fsl_mc_device *dpbp_dev;
05fa39c6	317	u16 bpid;
08eb2397	318	struct iommu_domain *iommu_domain;
6e2387e8 IR	319
	320	u16 tx_qdid;
	321	struct fsl_mc_io *mc_io;
	322	/* Cores which have an affine DPIO/DPCON.
	323	* This is the cpu set on which Rx and Tx conf frames are processed
	324	*/
	325	struct cpumask dpio_cpumask;
	326
	327	/* Standard statistics */
	328	struct rtnl_link_stats64 __percpu *percpu_stats;
85047abd IR	329	/* Extra stats, in addition to the ones known by the kernel */
85047abd IR	330	struct dpaa2_eth_drv_stats __percpu *percpu_extras;
6e2387e8 IR	331
	332	u16 mc_token;
	333
	334	struct dpni_link_state link_state;
	335	bool do_link_poll;
	336	struct task_struct *poll_thread;
34196740 IR	337
	338	/* enabled ethtool hashing bits */
	339	u64 rx_hash_fields;
6e2387e8 IR	340	};
	341
	342	/* default Rx hash options, set during probing */
	343	#define DPAA2_RXH_SUPPORTED (RXH_L2DA \| RXH_VLAN \| RXH_L3_PROTO \
	344	\| RXH_IP_SRC \| RXH_IP_DST \| RXH_L4_B_0_1 \
	345	\| RXH_L4_B_2_3)
	346
	347	#define dpaa2_eth_hash_enabled(priv) \
	348	((priv)->dpni_attrs.num_queues > 1)
	349
	350	/* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
	351	#define DPAA2_CLASSIFIER_DMA_SIZE 256
	352
34196740 IR	353	extern const struct ethtool_ops dpaa2_ethtool_ops;
	354	extern const char dpaa2_eth_drv_version[];
	355
6e2387e8 IR	356	static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv)
	357	{
	358	return priv->dpni_attrs.num_queues;
	359	}
	360
	361	#endif /* __DPAA2_H */