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1 | /************************************************************************** |
2 | * Copyright (c) 2007, Intel Corporation. | |
3 | * All Rights Reserved. | |
4 | * Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA. | |
5 | * All Rights Reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | * | |
20 | **************************************************************************/ | |
21 | ||
22 | #ifndef _PSB_DRM_H_ | |
23 | #define _PSB_DRM_H_ | |
24 | ||
25 | #if defined(__linux__) && !defined(__KERNEL__) | |
26 | #include<stdint.h> | |
27 | #include <linux/types.h> | |
28 | #include "drm_mode.h" | |
29 | #endif | |
30 | ||
31 | #include "psb_ttm_fence_user.h" | |
32 | #include "psb_ttm_placement_user.h" | |
33 | ||
34 | /* | |
35 | * Menlow/MRST graphics driver package version | |
36 | * a.b.c.xxxx | |
37 | * a - Product Family: 5 - Linux | |
38 | * b - Major Release Version: 0 - non-Gallium (Unbuntu); | |
39 | * 1 - Gallium (Moblin2) | |
40 | * c - Hotfix Release | |
41 | * xxxx - Graphics internal build # | |
42 | */ | |
43 | #define PSB_PACKAGE_VERSION "5.3.0.32L.0036" | |
44 | ||
45 | #define DRM_PSB_SAREA_MAJOR 0 | |
46 | #define DRM_PSB_SAREA_MINOR 2 | |
47 | #define PSB_FIXED_SHIFT 16 | |
48 | ||
49 | #define PSB_NUM_PIPE 3 | |
50 | ||
51 | /* | |
52 | * Public memory types. | |
53 | */ | |
54 | ||
55 | #define DRM_PSB_MEM_MMU TTM_PL_PRIV1 | |
56 | #define DRM_PSB_FLAG_MEM_MMU TTM_PL_FLAG_PRIV1 | |
57 | ||
58 | #define TTM_PL_CI TTM_PL_PRIV0 | |
59 | #define TTM_PL_FLAG_CI TTM_PL_FLAG_PRIV0 | |
60 | ||
61 | #define TTM_PL_RAR TTM_PL_PRIV2 | |
62 | #define TTM_PL_FLAG_RAR TTM_PL_FLAG_PRIV2 | |
63 | ||
64 | typedef int32_t psb_fixed; | |
65 | typedef uint32_t psb_ufixed; | |
66 | ||
67 | static inline int32_t psb_int_to_fixed(int a) | |
68 | { | |
69 | return a * (1 << PSB_FIXED_SHIFT); | |
70 | } | |
71 | ||
72 | static inline uint32_t psb_unsigned_to_ufixed(unsigned int a) | |
73 | { | |
74 | return a << PSB_FIXED_SHIFT; | |
75 | } | |
76 | ||
77 | /*Status of the command sent to the gfx device.*/ | |
78 | typedef enum { | |
79 | DRM_CMD_SUCCESS, | |
80 | DRM_CMD_FAILED, | |
81 | DRM_CMD_HANG | |
82 | } drm_cmd_status_t; | |
83 | ||
84 | struct drm_psb_scanout { | |
85 | uint32_t buffer_id; /* DRM buffer object ID */ | |
86 | uint32_t rotation; /* Rotation as in RR_rotation definitions */ | |
87 | uint32_t stride; /* Buffer stride in bytes */ | |
88 | uint32_t depth; /* Buffer depth in bits (NOT) bpp */ | |
89 | uint32_t width; /* Buffer width in pixels */ | |
90 | uint32_t height; /* Buffer height in lines */ | |
91 | int32_t transform[3][3]; /* Buffer composite transform */ | |
92 | /* (scaling, rot, reflect) */ | |
93 | }; | |
94 | ||
95 | #define DRM_PSB_SAREA_OWNERS 16 | |
96 | #define DRM_PSB_SAREA_OWNER_2D 0 | |
97 | #define DRM_PSB_SAREA_OWNER_3D 1 | |
98 | ||
99 | #define DRM_PSB_SAREA_SCANOUTS 3 | |
100 | ||
101 | struct drm_psb_sarea { | |
102 | /* Track changes of this data structure */ | |
103 | ||
104 | uint32_t major; | |
105 | uint32_t minor; | |
106 | ||
107 | /* Last context to touch part of hw */ | |
108 | uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS]; | |
109 | ||
110 | /* Definition of front- and rotated buffers */ | |
111 | uint32_t num_scanouts; | |
112 | struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS]; | |
113 | ||
114 | int planeA_x; | |
115 | int planeA_y; | |
116 | int planeA_w; | |
117 | int planeA_h; | |
118 | int planeB_x; | |
119 | int planeB_y; | |
120 | int planeB_w; | |
121 | int planeB_h; | |
122 | /* Number of active scanouts */ | |
123 | uint32_t num_active_scanouts; | |
124 | }; | |
125 | ||
126 | #define PSB_RELOC_MAGIC 0x67676767 | |
127 | #define PSB_RELOC_SHIFT_MASK 0x0000FFFF | |
128 | #define PSB_RELOC_SHIFT_SHIFT 0 | |
129 | #define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000 | |
130 | #define PSB_RELOC_ALSHIFT_SHIFT 16 | |
131 | ||
132 | #define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated | |
133 | * buffer | |
134 | */ | |
135 | ||
136 | struct drm_psb_reloc { | |
137 | uint32_t reloc_op; | |
138 | uint32_t where; /* offset in destination buffer */ | |
139 | uint32_t buffer; /* Buffer reloc applies to */ | |
140 | uint32_t mask; /* Destination format: */ | |
141 | uint32_t shift; /* Destination format: */ | |
142 | uint32_t pre_add; /* Destination format: */ | |
143 | uint32_t background; /* Destination add */ | |
144 | uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */ | |
145 | uint32_t arg0; /* Reloc-op dependant */ | |
146 | uint32_t arg1; | |
147 | }; | |
148 | ||
149 | ||
150 | #define PSB_GPU_ACCESS_READ (1ULL << 32) | |
151 | #define PSB_GPU_ACCESS_WRITE (1ULL << 33) | |
152 | #define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE) | |
153 | ||
154 | #define PSB_BO_FLAG_COMMAND (1ULL << 52) | |
155 | ||
156 | #define PSB_ENGINE_2D 0 | |
157 | #define PSB_ENGINE_VIDEO 1 | |
158 | #define LNC_ENGINE_ENCODE 5 | |
159 | ||
160 | /* | |
161 | * For this fence class we have a couple of | |
162 | * fence types. | |
163 | */ | |
164 | ||
165 | #define _PSB_FENCE_EXE_SHIFT 0 | |
166 | #define _PSB_FENCE_FEEDBACK_SHIFT 4 | |
167 | ||
168 | #define _PSB_FENCE_TYPE_EXE (1 << _PSB_FENCE_EXE_SHIFT) | |
169 | #define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT) | |
170 | ||
171 | #define PSB_NUM_ENGINES 6 | |
172 | ||
173 | ||
174 | #define PSB_FEEDBACK_OP_VISTEST (1 << 0) | |
175 | ||
176 | struct drm_psb_extension_rep { | |
177 | int32_t exists; | |
178 | uint32_t driver_ioctl_offset; | |
179 | uint32_t sarea_offset; | |
180 | uint32_t major; | |
181 | uint32_t minor; | |
182 | uint32_t pl; | |
183 | }; | |
184 | ||
185 | #define DRM_PSB_EXT_NAME_LEN 128 | |
186 | ||
187 | union drm_psb_extension_arg { | |
188 | char extension[DRM_PSB_EXT_NAME_LEN]; | |
189 | struct drm_psb_extension_rep rep; | |
190 | }; | |
191 | ||
192 | struct psb_validate_req { | |
193 | uint64_t set_flags; | |
194 | uint64_t clear_flags; | |
195 | uint64_t next; | |
196 | uint64_t presumed_gpu_offset; | |
197 | uint32_t buffer_handle; | |
198 | uint32_t presumed_flags; | |
199 | uint32_t group; | |
200 | uint32_t pad64; | |
201 | }; | |
202 | ||
203 | struct psb_validate_rep { | |
204 | uint64_t gpu_offset; | |
205 | uint32_t placement; | |
206 | uint32_t fence_type_mask; | |
207 | }; | |
208 | ||
209 | #define PSB_USE_PRESUMED (1 << 0) | |
210 | ||
211 | struct psb_validate_arg { | |
212 | int handled; | |
213 | int ret; | |
214 | union { | |
215 | struct psb_validate_req req; | |
216 | struct psb_validate_rep rep; | |
217 | } d; | |
218 | }; | |
219 | ||
220 | ||
221 | #define DRM_PSB_FENCE_NO_USER (1 << 0) | |
222 | ||
223 | struct psb_ttm_fence_rep { | |
224 | uint32_t handle; | |
225 | uint32_t fence_class; | |
226 | uint32_t fence_type; | |
227 | uint32_t signaled_types; | |
228 | uint32_t error; | |
229 | }; | |
230 | ||
231 | typedef struct drm_psb_cmdbuf_arg { | |
232 | uint64_t buffer_list; /* List of buffers to validate */ | |
233 | uint64_t clip_rects; /* See i915 counterpart */ | |
234 | uint64_t scene_arg; | |
235 | uint64_t fence_arg; | |
236 | ||
237 | uint32_t ta_flags; | |
238 | ||
239 | uint32_t ta_handle; /* TA reg-value pairs */ | |
240 | uint32_t ta_offset; | |
241 | uint32_t ta_size; | |
242 | ||
243 | uint32_t oom_handle; | |
244 | uint32_t oom_offset; | |
245 | uint32_t oom_size; | |
246 | ||
247 | uint32_t cmdbuf_handle; /* 2D Command buffer object or, */ | |
248 | uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */ | |
249 | uint32_t cmdbuf_size; | |
250 | ||
251 | uint32_t reloc_handle; /* Reloc buffer object */ | |
252 | uint32_t reloc_offset; | |
253 | uint32_t num_relocs; | |
254 | ||
255 | int32_t damage; /* Damage front buffer with cliprects */ | |
256 | /* Not implemented yet */ | |
257 | uint32_t fence_flags; | |
258 | uint32_t engine; | |
259 | ||
260 | /* | |
261 | * Feedback; | |
262 | */ | |
263 | ||
264 | uint32_t feedback_ops; | |
265 | uint32_t feedback_handle; | |
266 | uint32_t feedback_offset; | |
267 | uint32_t feedback_breakpoints; | |
268 | uint32_t feedback_size; | |
269 | } drm_psb_cmdbuf_arg_t; | |
270 | ||
271 | typedef struct drm_psb_pageflip_arg { | |
272 | uint32_t flip_offset; | |
273 | uint32_t stride; | |
274 | } drm_psb_pageflip_arg_t; | |
275 | ||
276 | typedef enum { | |
277 | LNC_VIDEO_DEVICE_INFO, | |
278 | LNC_VIDEO_GETPARAM_RAR_INFO, | |
279 | LNC_VIDEO_GETPARAM_CI_INFO, | |
280 | LNC_VIDEO_GETPARAM_RAR_HANDLER_OFFSET, | |
281 | LNC_VIDEO_FRAME_SKIP, | |
282 | IMG_VIDEO_DECODE_STATUS, | |
283 | IMG_VIDEO_NEW_CONTEXT, | |
284 | IMG_VIDEO_RM_CONTEXT, | |
285 | IMG_VIDEO_MB_ERROR | |
286 | } lnc_getparam_key_t; | |
287 | ||
288 | struct drm_lnc_video_getparam_arg { | |
289 | lnc_getparam_key_t key; | |
290 | uint64_t arg; /* argument pointer */ | |
291 | uint64_t value; /* feed back pointer */ | |
292 | }; | |
293 | ||
294 | ||
295 | /* | |
296 | * Feedback components: | |
297 | */ | |
298 | ||
299 | /* | |
300 | * Vistest component. The number of these in the feedback buffer | |
301 | * equals the number of vistest breakpoints + 1. | |
302 | * This is currently the only feedback component. | |
303 | */ | |
304 | ||
305 | struct drm_psb_vistest { | |
306 | uint32_t vt[8]; | |
307 | }; | |
308 | ||
309 | struct drm_psb_sizes_arg { | |
310 | uint32_t ta_mem_size; | |
311 | uint32_t mmu_size; | |
312 | uint32_t pds_size; | |
313 | uint32_t rastgeom_size; | |
314 | uint32_t tt_size; | |
315 | uint32_t vram_size; | |
316 | }; | |
317 | ||
318 | struct drm_psb_hist_status_arg { | |
319 | uint32_t buf[32]; | |
320 | }; | |
321 | ||
322 | struct drm_psb_dpst_lut_arg { | |
323 | uint8_t lut[256]; | |
324 | int output_id; | |
325 | }; | |
326 | ||
327 | struct mrst_timing_info { | |
328 | uint16_t pixel_clock; | |
329 | uint8_t hactive_lo; | |
330 | uint8_t hblank_lo; | |
331 | uint8_t hblank_hi:4; | |
332 | uint8_t hactive_hi:4; | |
333 | uint8_t vactive_lo; | |
334 | uint8_t vblank_lo; | |
335 | uint8_t vblank_hi:4; | |
336 | uint8_t vactive_hi:4; | |
337 | uint8_t hsync_offset_lo; | |
338 | uint8_t hsync_pulse_width_lo; | |
339 | uint8_t vsync_pulse_width_lo:4; | |
340 | uint8_t vsync_offset_lo:4; | |
341 | uint8_t vsync_pulse_width_hi:2; | |
342 | uint8_t vsync_offset_hi:2; | |
343 | uint8_t hsync_pulse_width_hi:2; | |
344 | uint8_t hsync_offset_hi:2; | |
345 | uint8_t width_mm_lo; | |
346 | uint8_t height_mm_lo; | |
347 | uint8_t height_mm_hi:4; | |
348 | uint8_t width_mm_hi:4; | |
349 | uint8_t hborder; | |
350 | uint8_t vborder; | |
351 | uint8_t unknown0:1; | |
352 | uint8_t hsync_positive:1; | |
353 | uint8_t vsync_positive:1; | |
354 | uint8_t separate_sync:2; | |
355 | uint8_t stereo:1; | |
356 | uint8_t unknown6:1; | |
357 | uint8_t interlaced:1; | |
358 | } __attribute__((packed)); | |
359 | ||
360 | struct gct_r10_timing_info { | |
361 | uint16_t pixel_clock; | |
362 | uint32_t hactive_lo:8; | |
363 | uint32_t hactive_hi:4; | |
364 | uint32_t hblank_lo:8; | |
365 | uint32_t hblank_hi:4; | |
366 | uint32_t hsync_offset_lo:8; | |
367 | uint16_t hsync_offset_hi:2; | |
368 | uint16_t hsync_pulse_width_lo:8; | |
369 | uint16_t hsync_pulse_width_hi:2; | |
370 | uint16_t hsync_positive:1; | |
371 | uint16_t rsvd_1:3; | |
372 | uint8_t vactive_lo:8; | |
373 | uint16_t vactive_hi:4; | |
374 | uint16_t vblank_lo:8; | |
375 | uint16_t vblank_hi:4; | |
376 | uint16_t vsync_offset_lo:4; | |
377 | uint16_t vsync_offset_hi:2; | |
378 | uint16_t vsync_pulse_width_lo:4; | |
379 | uint16_t vsync_pulse_width_hi:2; | |
380 | uint16_t vsync_positive:1; | |
381 | uint16_t rsvd_2:3; | |
382 | } __attribute__((packed)); | |
383 | ||
384 | struct mrst_panel_descriptor_v1{ | |
385 | uint32_t Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ | |
386 | /* 0x61190 if MIPI */ | |
387 | uint32_t Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ | |
388 | uint32_t Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ | |
389 | uint32_t Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */ | |
390 | /* Register 0x61210 */ | |
391 | struct mrst_timing_info DTD;/*18 bytes, Standard definition */ | |
392 | uint16_t Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */ | |
393 | /* Bit 0, Frequency, 15 bits,0 - 32767Hz */ | |
394 | /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */ | |
395 | uint16_t Panel_MIPI_Display_Descriptor; | |
396 | /*16 bits, Defined as follows: */ | |
397 | /* if MIPI, 0x0000 if LVDS */ | |
398 | /* Bit 0, Type, 2 bits, */ | |
399 | /* 0: Type-1, */ | |
400 | /* 1: Type-2, */ | |
401 | /* 2: Type-3, */ | |
402 | /* 3: Type-4 */ | |
403 | /* Bit 2, Pixel Format, 4 bits */ | |
404 | /* Bit0: 16bpp (not supported in LNC), */ | |
405 | /* Bit1: 18bpp loosely packed, */ | |
406 | /* Bit2: 18bpp packed, */ | |
407 | /* Bit3: 24bpp */ | |
408 | /* Bit 6, Reserved, 2 bits, 00b */ | |
409 | /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ | |
410 | /* Bit 14, Reserved, 2 bits, 00b */ | |
411 | } __attribute__ ((packed)); | |
412 | ||
413 | struct mrst_panel_descriptor_v2{ | |
414 | uint32_t Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ | |
415 | /* 0x61190 if MIPI */ | |
416 | uint32_t Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ | |
417 | uint32_t Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ | |
418 | uint8_t Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */ | |
419 | /* Register 0x61210 */ | |
420 | struct mrst_timing_info DTD;/*18 bytes, Standard definition */ | |
421 | uint16_t Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/ | |
422 | /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/ | |
423 | uint8_t Panel_Initial_Brightness;/* [7:0] 0 - 100% */ | |
424 | /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/ | |
425 | uint16_t Panel_MIPI_Display_Descriptor; | |
426 | /*16 bits, Defined as follows: */ | |
427 | /* if MIPI, 0x0000 if LVDS */ | |
428 | /* Bit 0, Type, 2 bits, */ | |
429 | /* 0: Type-1, */ | |
430 | /* 1: Type-2, */ | |
431 | /* 2: Type-3, */ | |
432 | /* 3: Type-4 */ | |
433 | /* Bit 2, Pixel Format, 4 bits */ | |
434 | /* Bit0: 16bpp (not supported in LNC), */ | |
435 | /* Bit1: 18bpp loosely packed, */ | |
436 | /* Bit2: 18bpp packed, */ | |
437 | /* Bit3: 24bpp */ | |
438 | /* Bit 6, Reserved, 2 bits, 00b */ | |
439 | /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ | |
440 | /* Bit 14, Reserved, 2 bits, 00b */ | |
441 | } __attribute__ ((packed)); | |
442 | ||
443 | union mrst_panel_rx{ | |
444 | struct{ | |
445 | uint16_t NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/ | |
446 | /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */ | |
447 | uint16_t MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */ | |
448 | /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/ | |
449 | uint16_t SupportedVideoTransferMode:2; /*0: Non-burst only */ | |
450 | /* 1: Burst and non-burst */ | |
451 | /* 2/3: Reserved */ | |
452 | uint16_t HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/ | |
453 | uint16_t DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/ | |
454 | uint16_t ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/ | |
455 | uint16_t BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */ | |
456 | uint16_t Rsvd:5;/*5 bits,00000b */ | |
457 | } panelrx; | |
458 | uint16_t panel_receiver; | |
459 | } __attribute__ ((packed)); | |
460 | ||
461 | struct gct_ioctl_arg{ | |
462 | uint8_t bpi; /* boot panel index, number of panel used during boot */ | |
463 | uint8_t pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */ | |
464 | struct mrst_timing_info DTD; /* timing info for the selected panel */ | |
465 | uint32_t Panel_Port_Control; | |
466 | uint32_t PP_On_Sequencing;/*1 dword,Register 0x61208,*/ | |
467 | uint32_t PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/ | |
468 | uint32_t PP_Cycle_Delay; | |
469 | uint16_t Panel_Backlight_Inverter_Descriptor; | |
470 | uint16_t Panel_MIPI_Display_Descriptor; | |
471 | } __attribute__ ((packed)); | |
472 | ||
473 | struct mrst_vbt{ | |
474 | char Signature[4]; /*4 bytes,"$GCT" */ | |
475 | uint8_t Revision; /*1 byte */ | |
476 | uint8_t Size; /*1 byte */ | |
477 | uint8_t Checksum; /*1 byte,Calculated*/ | |
478 | void *mrst_gct; | |
479 | } __attribute__ ((packed)); | |
480 | ||
481 | struct mrst_gct_v1{ /* expect this table to change per customer request*/ | |
482 | union{ /*8 bits,Defined as follows: */ | |
483 | struct{ | |
484 | uint8_t PanelType:4; /*4 bits, Bit field for panels*/ | |
485 | /* 0 - 3: 0 = LVDS, 1 = MIPI*/ | |
486 | /*2 bits,Specifies which of the*/ | |
487 | uint8_t BootPanelIndex:2; | |
488 | /* 4 panels to use by default*/ | |
489 | uint8_t BootMIPI_DSI_RxIndex:2;/*Specifies which of*/ | |
490 | /* the 4 MIPI DSI receivers to use*/ | |
491 | } PD; | |
492 | uint8_t PanelDescriptor; | |
493 | }; | |
494 | struct mrst_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/ | |
495 | union mrst_panel_rx panelrx[4]; /* panel receivers*/ | |
496 | } __attribute__ ((packed)); | |
497 | ||
498 | struct mrst_gct_v2{ /* expect this table to change per customer request*/ | |
499 | union{ /*8 bits,Defined as follows: */ | |
500 | struct{ | |
501 | uint8_t PanelType:4; /*4 bits, Bit field for panels*/ | |
502 | /* 0 - 3: 0 = LVDS, 1 = MIPI*/ | |
503 | /*2 bits,Specifies which of the*/ | |
504 | uint8_t BootPanelIndex:2; | |
505 | /* 4 panels to use by default*/ | |
506 | uint8_t BootMIPI_DSI_RxIndex:2;/*Specifies which of*/ | |
507 | /* the 4 MIPI DSI receivers to use*/ | |
508 | } PD; | |
509 | uint8_t PanelDescriptor; | |
510 | }; | |
511 | struct mrst_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/ | |
512 | union mrst_panel_rx panelrx[4]; /* panel receivers*/ | |
513 | } __attribute__ ((packed)); | |
514 | ||
515 | #define PSB_DC_CRTC_SAVE 0x01 | |
516 | #define PSB_DC_CRTC_RESTORE 0x02 | |
517 | #define PSB_DC_OUTPUT_SAVE 0x04 | |
518 | #define PSB_DC_OUTPUT_RESTORE 0x08 | |
519 | #define PSB_DC_CRTC_MASK 0x03 | |
520 | #define PSB_DC_OUTPUT_MASK 0x0C | |
521 | ||
522 | struct drm_psb_dc_state_arg { | |
523 | uint32_t flags; | |
524 | uint32_t obj_id; | |
525 | }; | |
526 | ||
527 | struct drm_psb_mode_operation_arg { | |
528 | uint32_t obj_id; | |
529 | uint16_t operation; | |
530 | struct drm_mode_modeinfo mode; | |
531 | void *data; | |
532 | }; | |
533 | ||
534 | struct drm_psb_stolen_memory_arg { | |
535 | uint32_t base; | |
536 | uint32_t size; | |
537 | }; | |
538 | ||
539 | /*Display Register Bits*/ | |
540 | #define REGRWBITS_PFIT_CONTROLS (1 << 0) | |
541 | #define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1) | |
542 | #define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2) | |
543 | #define REGRWBITS_PIPEASRC (1 << 3) | |
544 | #define REGRWBITS_PIPEBSRC (1 << 4) | |
545 | #define REGRWBITS_VTOTAL_A (1 << 5) | |
546 | #define REGRWBITS_VTOTAL_B (1 << 6) | |
547 | #define REGRWBITS_DSPACNTR (1 << 8) | |
548 | #define REGRWBITS_DSPBCNTR (1 << 9) | |
549 | #define REGRWBITS_DSPCCNTR (1 << 10) | |
550 | ||
551 | /*Overlay Register Bits*/ | |
552 | #define OV_REGRWBITS_OVADD (1 << 0) | |
553 | #define OV_REGRWBITS_OGAM_ALL (1 << 1) | |
554 | ||
555 | #define OVC_REGRWBITS_OVADD (1 << 2) | |
556 | #define OVC_REGRWBITS_OGAM_ALL (1 << 3) | |
557 | ||
558 | struct drm_psb_register_rw_arg { | |
559 | uint32_t b_force_hw_on; | |
560 | ||
561 | uint32_t display_read_mask; | |
562 | uint32_t display_write_mask; | |
563 | ||
564 | struct { | |
565 | uint32_t pfit_controls; | |
566 | uint32_t pfit_autoscale_ratios; | |
567 | uint32_t pfit_programmed_scale_ratios; | |
568 | uint32_t pipeasrc; | |
569 | uint32_t pipebsrc; | |
570 | uint32_t vtotal_a; | |
571 | uint32_t vtotal_b; | |
572 | } display; | |
573 | ||
574 | uint32_t overlay_read_mask; | |
575 | uint32_t overlay_write_mask; | |
576 | ||
577 | struct { | |
578 | uint32_t OVADD; | |
579 | uint32_t OGAMC0; | |
580 | uint32_t OGAMC1; | |
581 | uint32_t OGAMC2; | |
582 | uint32_t OGAMC3; | |
583 | uint32_t OGAMC4; | |
584 | uint32_t OGAMC5; | |
585 | uint32_t IEP_ENABLED; | |
586 | uint32_t IEP_BLE_MINMAX; | |
587 | uint32_t IEP_BSSCC_CONTROL; | |
588 | uint32_t b_wait_vblank; | |
589 | } overlay; | |
590 | ||
591 | uint32_t sprite_enable_mask; | |
592 | uint32_t sprite_disable_mask; | |
593 | ||
594 | struct { | |
595 | uint32_t dspa_control; | |
596 | uint32_t dspa_key_value; | |
597 | uint32_t dspa_key_mask; | |
598 | uint32_t dspc_control; | |
599 | uint32_t dspc_stride; | |
600 | uint32_t dspc_position; | |
601 | uint32_t dspc_linear_offset; | |
602 | uint32_t dspc_size; | |
603 | uint32_t dspc_surface; | |
604 | } sprite; | |
605 | ||
606 | uint32_t subpicture_enable_mask; | |
607 | uint32_t subpicture_disable_mask; | |
608 | }; | |
609 | ||
610 | struct psb_gtt_mapping_arg { | |
611 | void *hKernelMemInfo; | |
612 | uint32_t offset_pages; | |
613 | }; | |
614 | ||
615 | struct drm_psb_getpageaddrs_arg { | |
616 | uint32_t handle; | |
617 | unsigned long *page_addrs; | |
618 | unsigned long gtt_offset; | |
619 | }; | |
620 | ||
621 | /* Controlling the kernel modesetting buffers */ | |
622 | ||
623 | #define DRM_PSB_KMS_OFF 0x00 | |
624 | #define DRM_PSB_KMS_ON 0x01 | |
625 | #define DRM_PSB_VT_LEAVE 0x02 | |
626 | #define DRM_PSB_VT_ENTER 0x03 | |
627 | #define DRM_PSB_EXTENSION 0x06 | |
628 | #define DRM_PSB_SIZES 0x07 | |
629 | #define DRM_PSB_FUSE_REG 0x08 | |
630 | #define DRM_PSB_VBT 0x09 | |
631 | #define DRM_PSB_DC_STATE 0x0A | |
632 | #define DRM_PSB_ADB 0x0B | |
633 | #define DRM_PSB_MODE_OPERATION 0x0C | |
634 | #define DRM_PSB_STOLEN_MEMORY 0x0D | |
635 | #define DRM_PSB_REGISTER_RW 0x0E | |
636 | #define DRM_PSB_GTT_MAP 0x0F | |
637 | #define DRM_PSB_GTT_UNMAP 0x10 | |
638 | #define DRM_PSB_GETPAGEADDRS 0x11 | |
639 | /** | |
640 | * NOTE: Add new commands here, but increment | |
641 | * the values below and increment their | |
642 | * corresponding defines where they're | |
643 | * defined elsewhere. | |
644 | */ | |
645 | #define DRM_PVR_RESERVED1 0x12 | |
646 | #define DRM_PVR_RESERVED2 0x13 | |
647 | #define DRM_PVR_RESERVED3 0x14 | |
648 | #define DRM_PVR_RESERVED4 0x15 | |
649 | #define DRM_PVR_RESERVED5 0x16 | |
650 | ||
651 | #define DRM_PSB_HIST_ENABLE 0x17 | |
652 | #define DRM_PSB_HIST_STATUS 0x18 | |
653 | #define DRM_PSB_UPDATE_GUARD 0x19 | |
654 | #define DRM_PSB_INIT_COMM 0x1A | |
655 | #define DRM_PSB_DPST 0x1B | |
656 | #define DRM_PSB_GAMMA 0x1C | |
657 | #define DRM_PSB_DPST_BL 0x1D | |
658 | ||
659 | #define DRM_PVR_RESERVED6 0x1E | |
660 | ||
661 | #define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F | |
662 | #define DRM_PSB_DPU_QUERY 0x20 | |
663 | #define DRM_PSB_DPU_DSR_ON 0x21 | |
664 | #define DRM_PSB_DPU_DSR_OFF 0x22 | |
665 | ||
666 | #define DRM_PSB_DSR_ENABLE 0xfffffffe | |
667 | #define DRM_PSB_DSR_DISABLE 0xffffffff | |
668 | ||
669 | struct psb_drm_dpu_rect { | |
670 | int x, y; | |
671 | int width, height; | |
672 | }; | |
673 | ||
674 | struct drm_psb_drv_dsr_off_arg { | |
675 | int screen; | |
676 | struct psb_drm_dpu_rect damage_rect; | |
677 | }; | |
678 | ||
679 | ||
680 | struct drm_psb_dev_info_arg { | |
681 | uint32_t num_use_attribute_registers; | |
682 | }; | |
683 | #define DRM_PSB_DEVINFO 0x01 | |
684 | ||
685 | #define PSB_MODE_OPERATION_MODE_VALID 0x01 | |
686 | #define PSB_MODE_OPERATION_SET_DC_BASE 0x02 | |
687 | ||
688 | struct drm_psb_get_pipe_from_crtc_id_arg { | |
689 | /** ID of CRTC being requested **/ | |
690 | uint32_t crtc_id; | |
691 | ||
692 | /** pipe of requested CRTC **/ | |
693 | uint32_t pipe; | |
694 | }; | |
695 | ||
696 | #endif |