[mirror_ubuntu-zesty-kernel.git] / drivers / staging / gma500 / psb_drm.h

/**************************************************************************
 * Copyright (c) 2007, Intel Corporation.
 * All Rights Reserved.
 * Copyright (c) 2008, Tungsten Graphics Inc.  Cedar Park, TX., USA.
 * All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 **************************************************************************/

#ifndef _PSB_DRM_H_
#define _PSB_DRM_H_

#if defined(__linux__) && !defined(__KERNEL__)
#include<stdint.h>
#include <linux/types.h>
#include "drm_mode.h"
#endif

#include "psb_ttm_fence_user.h"
#include "psb_ttm_placement_user.h"

#define DRM_PSB_SAREA_MAJOR 0
#define DRM_PSB_SAREA_MINOR 2
#define PSB_FIXED_SHIFT 16

#define PSB_NUM_PIPE 3

/*
 * Public memory types.
 */

#define DRM_PSB_MEM_MMU 	TTM_PL_PRIV1
#define DRM_PSB_FLAG_MEM_MMU	TTM_PL_FLAG_PRIV1

#define TTM_PL_CI               TTM_PL_PRIV0
#define TTM_PL_FLAG_CI          TTM_PL_FLAG_PRIV0

#define TTM_PL_RAR              TTM_PL_PRIV2
#define TTM_PL_FLAG_RAR         TTM_PL_FLAG_PRIV2

typedef s32 psb_fixed;
typedef u32 psb_ufixed;

static inline s32 psb_int_to_fixed(int a)
{
	return a * (1 << PSB_FIXED_SHIFT);
}

static inline u32 psb_unsigned_to_ufixed(unsigned int a)
{
	return a << PSB_FIXED_SHIFT;
}

/*Status of the command sent to the gfx device.*/
typedef enum {
	DRM_CMD_SUCCESS,
	DRM_CMD_FAILED,
	DRM_CMD_HANG
} drm_cmd_status_t;

struct drm_psb_scanout {
	u32 buffer_id;	/* DRM buffer object ID */
	u32 rotation;	/* Rotation as in RR_rotation definitions */
	u32 stride;	/* Buffer stride in bytes */
	u32 depth;		/* Buffer depth in bits (NOT) bpp */
	u32 width;		/* Buffer width in pixels */
	u32 height;	/* Buffer height in lines */
	s32 transform[3][3];	/* Buffer composite transform */
	/* (scaling, rot, reflect) */
};

#define DRM_PSB_SAREA_OWNERS 16
#define DRM_PSB_SAREA_OWNER_2D 0
#define DRM_PSB_SAREA_OWNER_3D 1

#define DRM_PSB_SAREA_SCANOUTS 3

struct drm_psb_sarea {
	/* Track changes of this data structure */

	u32 major;
	u32 minor;

	/* Last context to touch part of hw */
	u32 ctx_owners[DRM_PSB_SAREA_OWNERS];

	/* Definition of front- and rotated buffers */
	u32 num_scanouts;
	struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];

	int planeA_x;
	int planeA_y;
	int planeA_w;
	int planeA_h;
	int planeB_x;
	int planeB_y;
	int planeB_w;
	int planeB_h;
	/* Number of active scanouts */
	u32 num_active_scanouts;
};

#define PSB_RELOC_MAGIC         0x67676767
#define PSB_RELOC_SHIFT_MASK    0x0000FFFF
#define PSB_RELOC_SHIFT_SHIFT   0
#define PSB_RELOC_ALSHIFT_MASK  0xFFFF0000
#define PSB_RELOC_ALSHIFT_SHIFT 16

#define PSB_RELOC_OP_OFFSET     0	/* Offset of the indicated
					 * buffer
					 */

struct drm_psb_reloc {
	u32 reloc_op;
	u32 where;		/* offset in destination buffer */
	u32 buffer;	/* Buffer reloc applies to */
	u32 mask;		/* Destination format: */
	u32 shift;		/* Destination format: */
	u32 pre_add;	/* Destination format: */
	u32 background;	/* Destination add */
	u32 dst_buffer;	/* Destination buffer. Index into buffer_list */
	u32 arg0;		/* Reloc-op dependent */
	u32 arg1;
};


#define PSB_GPU_ACCESS_READ         (1ULL << 32)
#define PSB_GPU_ACCESS_WRITE        (1ULL << 33)
#define PSB_GPU_ACCESS_MASK         (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)

#define PSB_BO_FLAG_COMMAND         (1ULL << 52)

#define PSB_ENGINE_2D 0
#define PSB_ENGINE_VIDEO 1
#define LNC_ENGINE_ENCODE 5

/*
 * For this fence class we have a couple of
 * fence types.
 */

#define _PSB_FENCE_EXE_SHIFT           0
#define _PSB_FENCE_FEEDBACK_SHIFT      4

#define _PSB_FENCE_TYPE_EXE         (1 << _PSB_FENCE_EXE_SHIFT)
#define _PSB_FENCE_TYPE_FEEDBACK    (1 << _PSB_FENCE_FEEDBACK_SHIFT)

#define PSB_NUM_ENGINES 6


#define PSB_FEEDBACK_OP_VISTEST (1 << 0)

struct drm_psb_extension_rep {
	s32 exists;
	u32 driver_ioctl_offset;
	u32 sarea_offset;
	u32 major;
	u32 minor;
	u32 pl;
};

#define DRM_PSB_EXT_NAME_LEN 128

union drm_psb_extension_arg {
	char extension[DRM_PSB_EXT_NAME_LEN];
	struct drm_psb_extension_rep rep;
};

struct psb_validate_req {
	u64 set_flags;
	u64 clear_flags;
	u64 next;
	u64 presumed_gpu_offset;
	u32 buffer_handle;
	u32 presumed_flags;
	u32 group;
	u32 pad64;
};

struct psb_validate_rep {
	u64 gpu_offset;
	u32 placement;
	u32 fence_type_mask;
};

#define PSB_USE_PRESUMED     (1 << 0)

struct psb_validate_arg {
	int handled;
	int ret;
	union {
		struct psb_validate_req req;
		struct psb_validate_rep rep;
	} d;
};


#define DRM_PSB_FENCE_NO_USER        (1 << 0)

struct psb_ttm_fence_rep {
	u32 handle;
	u32 fence_class;
	u32 fence_type;
	u32 signaled_types;
	u32 error;
};

/*
 * Feedback components:
 */

struct drm_psb_sizes_arg {
	u32 ta_mem_size;
	u32 mmu_size;
	u32 pds_size;
	u32 rastgeom_size;
	u32 tt_size;
	u32 vram_size;
};

struct drm_psb_dpst_lut_arg {
	uint8_t lut[256];
	int output_id;
};

#define PSB_DC_CRTC_SAVE 0x01
#define PSB_DC_CRTC_RESTORE 0x02
#define PSB_DC_OUTPUT_SAVE 0x04
#define PSB_DC_OUTPUT_RESTORE 0x08
#define PSB_DC_CRTC_MASK 0x03
#define PSB_DC_OUTPUT_MASK 0x0C

struct drm_psb_dc_state_arg {
	u32 flags;
	u32 obj_id;
};

struct drm_psb_mode_operation_arg {
	u32 obj_id;
	u16 operation;
	struct drm_mode_modeinfo mode;
	void *data;
};

struct drm_psb_stolen_memory_arg {
	u32 base;
	u32 size;
};

/*Display Register Bits*/
#define REGRWBITS_PFIT_CONTROLS			(1 << 0)
#define REGRWBITS_PFIT_AUTOSCALE_RATIOS		(1 << 1)
#define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS	(1 << 2)
#define REGRWBITS_PIPEASRC			(1 << 3)
#define REGRWBITS_PIPEBSRC			(1 << 4)
#define REGRWBITS_VTOTAL_A			(1 << 5)
#define REGRWBITS_VTOTAL_B			(1 << 6)
#define REGRWBITS_DSPACNTR	(1 << 8)
#define REGRWBITS_DSPBCNTR	(1 << 9)
#define REGRWBITS_DSPCCNTR	(1 << 10)

/*Overlay Register Bits*/
#define OV_REGRWBITS_OVADD			(1 << 0)
#define OV_REGRWBITS_OGAM_ALL			(1 << 1)

#define OVC_REGRWBITS_OVADD                  (1 << 2)
#define OVC_REGRWBITS_OGAM_ALL			(1 << 3)

struct drm_psb_register_rw_arg {
	u32 b_force_hw_on;

	u32 display_read_mask;
	u32 display_write_mask;

	struct {
		u32 pfit_controls;
		u32 pfit_autoscale_ratios;
		u32 pfit_programmed_scale_ratios;
		u32 pipeasrc;
		u32 pipebsrc;
		u32 vtotal_a;
		u32 vtotal_b;
	} display;

	u32 overlay_read_mask;
	u32 overlay_write_mask;

	struct {
		u32 OVADD;
		u32 OGAMC0;
		u32 OGAMC1;
		u32 OGAMC2;
		u32 OGAMC3;
		u32 OGAMC4;
		u32 OGAMC5;
        	u32 IEP_ENABLED;
        	u32 IEP_BLE_MINMAX;
        	u32 IEP_BSSCC_CONTROL;
                u32 b_wait_vblank;
	} overlay;

	u32 sprite_enable_mask;
	u32 sprite_disable_mask;

	struct {
		u32 dspa_control;
		u32 dspa_key_value;
		u32 dspa_key_mask;
		u32 dspc_control;
		u32 dspc_stride;
		u32 dspc_position;
		u32 dspc_linear_offset;
		u32 dspc_size;
		u32 dspc_surface;
	} sprite;

	u32 subpicture_enable_mask;
	u32 subpicture_disable_mask;
};

struct psb_gtt_mapping_arg {
	void *hKernelMemInfo;
	u32 offset_pages;
};

struct drm_psb_getpageaddrs_arg {
	u32 handle;
	unsigned long *page_addrs;
	unsigned long gtt_offset;
};

/* Controlling the kernel modesetting buffers */

#define DRM_PSB_KMS_OFF		0x00
#define DRM_PSB_KMS_ON		0x01
#define DRM_PSB_VT_LEAVE        0x02
#define DRM_PSB_VT_ENTER        0x03
#define DRM_PSB_EXTENSION       0x06
#define DRM_PSB_SIZES           0x07
#define DRM_PSB_FUSE_REG	0x08
#define DRM_PSB_VBT		0x09
#define DRM_PSB_DC_STATE	0x0A
#define DRM_PSB_ADB		0x0B
#define DRM_PSB_MODE_OPERATION	0x0C
#define DRM_PSB_STOLEN_MEMORY	0x0D
#define DRM_PSB_REGISTER_RW	0x0E
#define DRM_PSB_GTT_MAP         0x0F
#define DRM_PSB_GTT_UNMAP       0x10
#define DRM_PSB_GETPAGEADDRS	0x11
/**
 * NOTE: Add new commands here, but increment
 * the values below and increment their
 * corresponding defines where they're
 * defined elsewhere.
 */
#define DRM_PVR_RESERVED1	0x12
#define DRM_PVR_RESERVED2	0x13
#define DRM_PVR_RESERVED3	0x14
#define DRM_PVR_RESERVED4	0x15
#define DRM_PVR_RESERVED5	0x16

#define DRM_PSB_HIST_ENABLE	0x17
#define DRM_PSB_HIST_STATUS	0x18
#define DRM_PSB_UPDATE_GUARD	0x19
#define DRM_PSB_INIT_COMM	0x1A
#define DRM_PSB_DPST		0x1B
#define DRM_PSB_GAMMA		0x1C
#define DRM_PSB_DPST_BL		0x1D

#define DRM_PVR_RESERVED6	0x1E

#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F

#define PSB_MODE_OPERATION_MODE_VALID	0x01
#define PSB_MODE_OPERATION_SET_DC_BASE  0x02

struct drm_psb_get_pipe_from_crtc_id_arg {
	/** ID of CRTC being requested **/
	u32 crtc_id;

	/** pipe of requested CRTC **/
	u32 pipe;
};

#endif
Commit	Line	Data
0867b421 AC	1	/**************************************************************************
	2	* Copyright (c) 2007, Intel Corporation.
	3	* All Rights Reserved.
	4	* Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA.
	5	* All Rights Reserved.
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	*
	20	**************************************************************************/
	21
	22	#ifndef _PSB_DRM_H_
	23	#define _PSB_DRM_H_
	24
	25	#if defined(__linux__) && !defined(__KERNEL__)
	26	#include<stdint.h>
	27	#include <linux/types.h>
	28	#include "drm_mode.h"
	29	#endif
	30
	31	#include "psb_ttm_fence_user.h"
	32	#include "psb_ttm_placement_user.h"
	33
0867b421 AC	34	#define DRM_PSB_SAREA_MAJOR 0
	35	#define DRM_PSB_SAREA_MINOR 2
	36	#define PSB_FIXED_SHIFT 16
	37
	38	#define PSB_NUM_PIPE 3
	39
	40	/*
	41	* Public memory types.
	42	*/
	43
487e873d AC	44	#define DRM_PSB_MEM_MMU TTM_PL_PRIV1
487e873d AC	45	#define DRM_PSB_FLAG_MEM_MMU TTM_PL_FLAG_PRIV1
0867b421 AC	46
	47	#define TTM_PL_CI TTM_PL_PRIV0
	48	#define TTM_PL_FLAG_CI TTM_PL_FLAG_PRIV0
	49
487e873d AC	50	#define TTM_PL_RAR TTM_PL_PRIV2
487e873d AC	51	#define TTM_PL_FLAG_RAR TTM_PL_FLAG_PRIV2
0867b421	52
487e873d AC	53	typedef s32 psb_fixed;
487e873d AC	54	typedef u32 psb_ufixed;
0867b421	55
487e873d	56	static inline s32 psb_int_to_fixed(int a)
0867b421 AC	57	{
	58	return a * (1 << PSB_FIXED_SHIFT);
	59	}
	60
487e873d	61	static inline u32 psb_unsigned_to_ufixed(unsigned int a)
0867b421 AC	62	{
	63	return a << PSB_FIXED_SHIFT;
	64	}
	65
	66	/Status of the command sent to the gfx device./
	67	typedef enum {
	68	DRM_CMD_SUCCESS,
	69	DRM_CMD_FAILED,
	70	DRM_CMD_HANG
	71	} drm_cmd_status_t;
	72
	73	struct drm_psb_scanout {
487e873d AC	74	u32 buffer_id; /* DRM buffer object ID */
	75	u32 rotation; /* Rotation as in RR_rotation definitions */
	76	u32 stride; /* Buffer stride in bytes */
	77	u32 depth; /* Buffer depth in bits (NOT) bpp */
	78	u32 width; /* Buffer width in pixels */
	79	u32 height; /* Buffer height in lines */
	80	s32 transform[3][3]; /* Buffer composite transform */
0867b421 AC	81	/* (scaling, rot, reflect) */
	82	};
	83
	84	#define DRM_PSB_SAREA_OWNERS 16
	85	#define DRM_PSB_SAREA_OWNER_2D 0
	86	#define DRM_PSB_SAREA_OWNER_3D 1
	87
	88	#define DRM_PSB_SAREA_SCANOUTS 3
	89
	90	struct drm_psb_sarea {
	91	/* Track changes of this data structure */
	92
487e873d AC	93	u32 major;
487e873d AC	94	u32 minor;
0867b421 AC	95
0867b421 AC	96	/* Last context to touch part of hw */
487e873d	97	u32 ctx_owners[DRM_PSB_SAREA_OWNERS];
0867b421 AC	98
0867b421 AC	99	/* Definition of front- and rotated buffers */
487e873d	100	u32 num_scanouts;
0867b421 AC	101	struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
	102
	103	int planeA_x;
	104	int planeA_y;
	105	int planeA_w;
	106	int planeA_h;
	107	int planeB_x;
	108	int planeB_y;
	109	int planeB_w;
	110	int planeB_h;
	111	/* Number of active scanouts */
487e873d	112	u32 num_active_scanouts;
0867b421 AC	113	};
	114
	115	#define PSB_RELOC_MAGIC 0x67676767
	116	#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
	117	#define PSB_RELOC_SHIFT_SHIFT 0
	118	#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
	119	#define PSB_RELOC_ALSHIFT_SHIFT 16
	120
	121	#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
	122	* buffer
	123	*/
	124
	125	struct drm_psb_reloc {
487e873d AC	126	u32 reloc_op;
	127	u32 where; /* offset in destination buffer */
	128	u32 buffer; /* Buffer reloc applies to */
	129	u32 mask; /* Destination format: */
	130	u32 shift; /* Destination format: */
	131	u32 pre_add; /* Destination format: */
	132	u32 background; /* Destination add */
	133	u32 dst_buffer; /* Destination buffer. Index into buffer_list */
25985edc	134	u32 arg0; /* Reloc-op dependent */
487e873d	135	u32 arg1;
0867b421 AC	136	};
	137
	138
	139	#define PSB_GPU_ACCESS_READ (1ULL << 32)
	140	#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
	141	#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ \| PSB_GPU_ACCESS_WRITE)
	142
	143	#define PSB_BO_FLAG_COMMAND (1ULL << 52)
	144
	145	#define PSB_ENGINE_2D 0
	146	#define PSB_ENGINE_VIDEO 1
	147	#define LNC_ENGINE_ENCODE 5
	148
	149	/*
	150	* For this fence class we have a couple of
	151	* fence types.
	152	*/
	153
	154	#define _PSB_FENCE_EXE_SHIFT 0
	155	#define _PSB_FENCE_FEEDBACK_SHIFT 4
	156
	157	#define _PSB_FENCE_TYPE_EXE (1 << _PSB_FENCE_EXE_SHIFT)
	158	#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
	159
	160	#define PSB_NUM_ENGINES 6
	161
	162
	163	#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
	164
	165	struct drm_psb_extension_rep {
487e873d AC	166	s32 exists;
	167	u32 driver_ioctl_offset;
	168	u32 sarea_offset;
	169	u32 major;
	170	u32 minor;
	171	u32 pl;
0867b421 AC	172	};
	173
	174	#define DRM_PSB_EXT_NAME_LEN 128
	175
	176	union drm_psb_extension_arg {
	177	char extension[DRM_PSB_EXT_NAME_LEN];
	178	struct drm_psb_extension_rep rep;
	179	};
	180
	181	struct psb_validate_req {
487e873d AC	182	u64 set_flags;
	183	u64 clear_flags;
	184	u64 next;
	185	u64 presumed_gpu_offset;
	186	u32 buffer_handle;
	187	u32 presumed_flags;
	188	u32 group;
	189	u32 pad64;
0867b421 AC	190	};
	191
	192	struct psb_validate_rep {
487e873d AC	193	u64 gpu_offset;
	194	u32 placement;
	195	u32 fence_type_mask;
0867b421 AC	196	};
	197
	198	#define PSB_USE_PRESUMED (1 << 0)
	199
	200	struct psb_validate_arg {
	201	int handled;
	202	int ret;
	203	union {
	204	struct psb_validate_req req;
	205	struct psb_validate_rep rep;
	206	} d;
	207	};
	208
	209
	210	#define DRM_PSB_FENCE_NO_USER (1 << 0)
	211
	212	struct psb_ttm_fence_rep {
487e873d AC	213	u32 handle;
	214	u32 fence_class;
	215	u32 fence_type;
	216	u32 signaled_types;
	217	u32 error;
0867b421 AC	218	};
0867b421 AC	219
0867b421 AC	220	/*
	221	* Feedback components:
	222	*/
	223
0867b421	224	struct drm_psb_sizes_arg {
487e873d AC	225	u32 ta_mem_size;
	226	u32 mmu_size;
	227	u32 pds_size;
	228	u32 rastgeom_size;
	229	u32 tt_size;
	230	u32 vram_size;
0867b421 AC	231	};
	232
	233	struct drm_psb_dpst_lut_arg {
	234	uint8_t lut[256];
	235	int output_id;
	236	};
	237
0867b421 AC	238	#define PSB_DC_CRTC_SAVE 0x01
	239	#define PSB_DC_CRTC_RESTORE 0x02
	240	#define PSB_DC_OUTPUT_SAVE 0x04
	241	#define PSB_DC_OUTPUT_RESTORE 0x08
	242	#define PSB_DC_CRTC_MASK 0x03
	243	#define PSB_DC_OUTPUT_MASK 0x0C
	244
	245	struct drm_psb_dc_state_arg {
487e873d AC	246	u32 flags;
487e873d AC	247	u32 obj_id;
0867b421 AC	248	};
	249
	250	struct drm_psb_mode_operation_arg {
487e873d AC	251	u32 obj_id;
487e873d AC	252	u16 operation;
0867b421 AC	253	struct drm_mode_modeinfo mode;
	254	void *data;
	255	};
	256
	257	struct drm_psb_stolen_memory_arg {
487e873d AC	258	u32 base;
487e873d AC	259	u32 size;
0867b421 AC	260	};
	261
	262	/Display Register Bits/
	263	#define REGRWBITS_PFIT_CONTROLS (1 << 0)
	264	#define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1)
	265	#define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2)
	266	#define REGRWBITS_PIPEASRC (1 << 3)
	267	#define REGRWBITS_PIPEBSRC (1 << 4)
	268	#define REGRWBITS_VTOTAL_A (1 << 5)
	269	#define REGRWBITS_VTOTAL_B (1 << 6)
	270	#define REGRWBITS_DSPACNTR (1 << 8)
	271	#define REGRWBITS_DSPBCNTR (1 << 9)
	272	#define REGRWBITS_DSPCCNTR (1 << 10)
	273
	274	/Overlay Register Bits/
	275	#define OV_REGRWBITS_OVADD (1 << 0)
	276	#define OV_REGRWBITS_OGAM_ALL (1 << 1)
	277
	278	#define OVC_REGRWBITS_OVADD (1 << 2)
	279	#define OVC_REGRWBITS_OGAM_ALL (1 << 3)
	280
	281	struct drm_psb_register_rw_arg {
487e873d	282	u32 b_force_hw_on;
0867b421	283
487e873d AC	284	u32 display_read_mask;
487e873d AC	285	u32 display_write_mask;
0867b421 AC	286
0867b421 AC	287	struct {
487e873d AC	288	u32 pfit_controls;
	289	u32 pfit_autoscale_ratios;
	290	u32 pfit_programmed_scale_ratios;
	291	u32 pipeasrc;
	292	u32 pipebsrc;
	293	u32 vtotal_a;
	294	u32 vtotal_b;
0867b421 AC	295	} display;
0867b421 AC	296
487e873d AC	297	u32 overlay_read_mask;
487e873d AC	298	u32 overlay_write_mask;
0867b421 AC	299
0867b421 AC	300	struct {
487e873d AC	301	u32 OVADD;
	302	u32 OGAMC0;
	303	u32 OGAMC1;
	304	u32 OGAMC2;
	305	u32 OGAMC3;
	306	u32 OGAMC4;
	307	u32 OGAMC5;
	308	u32 IEP_ENABLED;
	309	u32 IEP_BLE_MINMAX;
	310	u32 IEP_BSSCC_CONTROL;
	311	u32 b_wait_vblank;
0867b421 AC	312	} overlay;
0867b421 AC	313
487e873d AC	314	u32 sprite_enable_mask;
487e873d AC	315	u32 sprite_disable_mask;
0867b421 AC	316
0867b421 AC	317	struct {
487e873d AC	318	u32 dspa_control;
	319	u32 dspa_key_value;
	320	u32 dspa_key_mask;
	321	u32 dspc_control;
	322	u32 dspc_stride;
	323	u32 dspc_position;
	324	u32 dspc_linear_offset;
	325	u32 dspc_size;
	326	u32 dspc_surface;
0867b421 AC	327	} sprite;
0867b421 AC	328
487e873d AC	329	u32 subpicture_enable_mask;
487e873d AC	330	u32 subpicture_disable_mask;
0867b421 AC	331	};
	332
	333	struct psb_gtt_mapping_arg {
	334	void *hKernelMemInfo;
487e873d	335	u32 offset_pages;
0867b421 AC	336	};
	337
	338	struct drm_psb_getpageaddrs_arg {
487e873d	339	u32 handle;
0867b421 AC	340	unsigned long *page_addrs;
	341	unsigned long gtt_offset;
	342	};
	343
	344	/* Controlling the kernel modesetting buffers */
	345
	346	#define DRM_PSB_KMS_OFF 0x00
	347	#define DRM_PSB_KMS_ON 0x01
	348	#define DRM_PSB_VT_LEAVE 0x02
	349	#define DRM_PSB_VT_ENTER 0x03
	350	#define DRM_PSB_EXTENSION 0x06
	351	#define DRM_PSB_SIZES 0x07
	352	#define DRM_PSB_FUSE_REG 0x08
	353	#define DRM_PSB_VBT 0x09
	354	#define DRM_PSB_DC_STATE 0x0A
	355	#define DRM_PSB_ADB 0x0B
	356	#define DRM_PSB_MODE_OPERATION 0x0C
	357	#define DRM_PSB_STOLEN_MEMORY 0x0D
	358	#define DRM_PSB_REGISTER_RW 0x0E
	359	#define DRM_PSB_GTT_MAP 0x0F
	360	#define DRM_PSB_GTT_UNMAP 0x10
	361	#define DRM_PSB_GETPAGEADDRS 0x11
	362	/**
	363	* NOTE: Add new commands here, but increment
	364	* the values below and increment their
	365	* corresponding defines where they're
	366	* defined elsewhere.
	367	*/
	368	#define DRM_PVR_RESERVED1 0x12
	369	#define DRM_PVR_RESERVED2 0x13
	370	#define DRM_PVR_RESERVED3 0x14
	371	#define DRM_PVR_RESERVED4 0x15
	372	#define DRM_PVR_RESERVED5 0x16
	373
	374	#define DRM_PSB_HIST_ENABLE 0x17
	375	#define DRM_PSB_HIST_STATUS 0x18
	376	#define DRM_PSB_UPDATE_GUARD 0x19
	377	#define DRM_PSB_INIT_COMM 0x1A
	378	#define DRM_PSB_DPST 0x1B
	379	#define DRM_PSB_GAMMA 0x1C
	380	#define DRM_PSB_DPST_BL 0x1D
	381
	382	#define DRM_PVR_RESERVED6 0x1E
	383
	384	#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F
0867b421 AC	385
	386	#define PSB_MODE_OPERATION_MODE_VALID 0x01
	387	#define PSB_MODE_OPERATION_SET_DC_BASE 0x02
	388
	389	struct drm_psb_get_pipe_from_crtc_id_arg {
	390	/ ID of CRTC being requested /
487e873d	391	u32 crtc_id;
0867b421 AC	392
0867b421 AC	393	/ pipe of requested CRTC /
487e873d	394	u32 pipe;
0867b421 AC	395	};
	396
	397	#endif