[mirror_ubuntu-jammy-kernel.git] / drivers / staging / hikey9xx / hisi-spmi-controller.c

// SPDX-License-Identifier: GPL-2.0

#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spmi.h>

/*
 * SPMI register addr
 */
#define SPMI_CHANNEL_OFFSET				0x0300
#define SPMI_SLAVE_OFFSET				0x20

#define SPMI_APB_SPMI_CMD_BASE_ADDR			0x0100

#define SPMI_APB_SPMI_WDATA0_BASE_ADDR			0x0104
#define SPMI_APB_SPMI_WDATA1_BASE_ADDR			0x0108
#define SPMI_APB_SPMI_WDATA2_BASE_ADDR			0x010c
#define SPMI_APB_SPMI_WDATA3_BASE_ADDR			0x0110

#define SPMI_APB_SPMI_STATUS_BASE_ADDR			0x0200

#define SPMI_APB_SPMI_RDATA0_BASE_ADDR			0x0204
#define SPMI_APB_SPMI_RDATA1_BASE_ADDR			0x0208
#define SPMI_APB_SPMI_RDATA2_BASE_ADDR			0x020c
#define SPMI_APB_SPMI_RDATA3_BASE_ADDR			0x0210

#define SPMI_PER_DATAREG_BYTE				4
/*
 * SPMI cmd register
 */
#define SPMI_APB_SPMI_CMD_EN				BIT(31)
#define SPMI_APB_SPMI_CMD_TYPE_OFFSET			24
#define SPMI_APB_SPMI_CMD_LENGTH_OFFSET			20
#define SPMI_APB_SPMI_CMD_SLAVEID_OFFSET		16
#define SPMI_APB_SPMI_CMD_ADDR_OFFSET			0

/* Command Opcodes */

enum spmi_controller_cmd_op_code {
	SPMI_CMD_REG_ZERO_WRITE = 0,
	SPMI_CMD_REG_WRITE = 1,
	SPMI_CMD_REG_READ = 2,
	SPMI_CMD_EXT_REG_WRITE = 3,
	SPMI_CMD_EXT_REG_READ = 4,
	SPMI_CMD_EXT_REG_WRITE_L = 5,
	SPMI_CMD_EXT_REG_READ_L = 6,
	SPMI_CMD_REG_RESET = 7,
	SPMI_CMD_REG_SLEEP = 8,
	SPMI_CMD_REG_SHUTDOWN = 9,
	SPMI_CMD_REG_WAKEUP = 10,
};

/*
 * SPMI status register
 */
#define SPMI_APB_TRANS_DONE			BIT(0)
#define SPMI_APB_TRANS_FAIL			BIT(2)

/* Command register fields */
#define SPMI_CONTROLLER_CMD_MAX_BYTE_COUNT	16

/* Maximum number of support PMIC peripherals */
#define SPMI_CONTROLLER_TIMEOUT_US		1000
#define SPMI_CONTROLLER_MAX_TRANS_BYTES		16

struct spmi_controller_dev {
	struct spmi_controller	*controller;
	struct device		*dev;
	void __iomem		*base;
	spinlock_t		lock;
	u32			channel;
};

static int spmi_controller_wait_for_done(struct device *dev,
					 struct spmi_controller_dev *ctrl_dev,
					 void __iomem *base, u8 sid, u16 addr)
{
	u32 timeout = SPMI_CONTROLLER_TIMEOUT_US;
	u32 status, offset;

	offset  = SPMI_APB_SPMI_STATUS_BASE_ADDR;
	offset += SPMI_CHANNEL_OFFSET * ctrl_dev->channel + SPMI_SLAVE_OFFSET * sid;

	do {
		status = readl(base + offset);

		if (status & SPMI_APB_TRANS_DONE) {
			if (status & SPMI_APB_TRANS_FAIL) {
				dev_err(dev, "%s: transaction failed (0x%x)\n",
					__func__, status);
				return -EIO;
			}
			dev_dbg(dev, "%s: status 0x%x\n", __func__, status);
			return 0;
		}
		udelay(1);
	} while (timeout--);

	dev_err(dev, "%s: timeout, status 0x%x\n", __func__, status);
	return -ETIMEDOUT;
}

static int spmi_read_cmd(struct spmi_controller *ctrl,
			 u8 opc, u8 slave_id, u16 slave_addr, u8 *__buf, size_t bc)
{
	struct spmi_controller_dev *spmi_controller = dev_get_drvdata(&ctrl->dev);
	u32 chnl_ofst = SPMI_CHANNEL_OFFSET * spmi_controller->channel;
	unsigned long flags;
	u8 *buf = __buf;
	u32 cmd, data;
	int rc;
	u8 op_code, i;

	if (bc > SPMI_CONTROLLER_MAX_TRANS_BYTES) {
		dev_err(&ctrl->dev,
			"spmi_controller supports 1..%d bytes per trans, but:%zu requested\n",
			SPMI_CONTROLLER_MAX_TRANS_BYTES, bc);
		return  -EINVAL;
	}

	switch (opc) {
	case SPMI_CMD_READ:
		op_code = SPMI_CMD_REG_READ;
		break;
	case SPMI_CMD_EXT_READ:
		op_code = SPMI_CMD_EXT_REG_READ;
		break;
	case SPMI_CMD_EXT_READL:
		op_code = SPMI_CMD_EXT_REG_READ_L;
		break;
	default:
		dev_err(&ctrl->dev, "invalid read cmd 0x%x\n", opc);
		return -EINVAL;
	}

	cmd = SPMI_APB_SPMI_CMD_EN |
	     (op_code << SPMI_APB_SPMI_CMD_TYPE_OFFSET) |
	     ((bc - 1) << SPMI_APB_SPMI_CMD_LENGTH_OFFSET) |
	     ((slave_id & 0xf) << SPMI_APB_SPMI_CMD_SLAVEID_OFFSET) |  /* slvid */
	     ((slave_addr & 0xffff)  << SPMI_APB_SPMI_CMD_ADDR_OFFSET); /* slave_addr */

	spin_lock_irqsave(&spmi_controller->lock, flags);

	writel(cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);

	rc = spmi_controller_wait_for_done(&ctrl->dev, spmi_controller,
					   spmi_controller->base, slave_id, slave_addr);
	if (rc)
		goto done;

	for (i = 0; bc > i * SPMI_PER_DATAREG_BYTE; i++) {
		data = readl(spmi_controller->base + chnl_ofst +
			     SPMI_SLAVE_OFFSET * slave_id +
			     SPMI_APB_SPMI_RDATA0_BASE_ADDR +
			     i * SPMI_PER_DATAREG_BYTE);
		data = be32_to_cpu((__be32 __force)data);
		if ((bc - i * SPMI_PER_DATAREG_BYTE) >> 2) {
			memcpy(buf, &data, sizeof(data));
			buf += sizeof(data);
		} else {
			memcpy(buf, &data, bc % SPMI_PER_DATAREG_BYTE);
			buf += (bc % SPMI_PER_DATAREG_BYTE);
		}
	}

done:
	spin_unlock_irqrestore(&spmi_controller->lock, flags);
	if (rc)
		dev_err(&ctrl->dev,
			"spmi read wait timeout op:0x%x slave_id:%d slave_addr:0x%x bc:%zu\n",
			opc, slave_id, slave_addr, bc + 1);
	else
		dev_dbg(&ctrl->dev, "%s: id:%d slave_addr:0x%x, read value: %*ph\n",
			__func__, slave_id, slave_addr, (int)bc, __buf);

	return rc;
}

static int spmi_write_cmd(struct spmi_controller *ctrl,
			  u8 opc, u8 slave_id, u16 slave_addr, const u8 *__buf, size_t bc)
{
	struct spmi_controller_dev *spmi_controller = dev_get_drvdata(&ctrl->dev);
	u32 chnl_ofst = SPMI_CHANNEL_OFFSET * spmi_controller->channel;
	const u8 *buf = __buf;
	unsigned long flags;
	u32 cmd, data;
	int rc;
	u8 op_code, i;

	if (bc > SPMI_CONTROLLER_MAX_TRANS_BYTES) {
		dev_err(&ctrl->dev,
			"spmi_controller supports 1..%d bytes per trans, but:%zu requested\n",
			SPMI_CONTROLLER_MAX_TRANS_BYTES, bc);
		return  -EINVAL;
	}

	switch (opc) {
	case SPMI_CMD_WRITE:
		op_code = SPMI_CMD_REG_WRITE;
		break;
	case SPMI_CMD_EXT_WRITE:
		op_code = SPMI_CMD_EXT_REG_WRITE;
		break;
	case SPMI_CMD_EXT_WRITEL:
		op_code = SPMI_CMD_EXT_REG_WRITE_L;
		break;
	default:
		dev_err(&ctrl->dev, "invalid write cmd 0x%x\n", opc);
		return -EINVAL;
	}

	cmd = SPMI_APB_SPMI_CMD_EN |
	      (op_code << SPMI_APB_SPMI_CMD_TYPE_OFFSET) |
	      ((bc - 1) << SPMI_APB_SPMI_CMD_LENGTH_OFFSET) |
	      ((slave_id & 0xf) << SPMI_APB_SPMI_CMD_SLAVEID_OFFSET) |
	      ((slave_addr & 0xffff)  << SPMI_APB_SPMI_CMD_ADDR_OFFSET);

	/* Write data to FIFOs */
	spin_lock_irqsave(&spmi_controller->lock, flags);

	for (i = 0; bc > i * SPMI_PER_DATAREG_BYTE; i++) {
		data = 0;
		if ((bc - i * SPMI_PER_DATAREG_BYTE) >> 2) {
			memcpy(&data, buf, sizeof(data));
			buf += sizeof(data);
		} else {
			memcpy(&data, buf, bc % SPMI_PER_DATAREG_BYTE);
			buf += (bc % SPMI_PER_DATAREG_BYTE);
		}

		writel((u32 __force)cpu_to_be32(data),
		       spmi_controller->base + chnl_ofst +
		       SPMI_APB_SPMI_WDATA0_BASE_ADDR +
		       SPMI_PER_DATAREG_BYTE * i);
	}

	/* Start the transaction */
	writel(cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);

	rc = spmi_controller_wait_for_done(&ctrl->dev, spmi_controller,
					   spmi_controller->base, slave_id,
					   slave_addr);
	spin_unlock_irqrestore(&spmi_controller->lock, flags);

	if (rc)
		dev_err(&ctrl->dev, "spmi write wait timeout op:0x%x slave_id:%d slave_addr:0x%x bc:%zu\n",
			opc, slave_id, slave_addr, bc);
	else
		dev_dbg(&ctrl->dev, "%s: id:%d slave_addr:0x%x, wrote value: %*ph\n",
			__func__, slave_id, slave_addr, (int)bc, __buf);

	return rc;
}

static int spmi_controller_probe(struct platform_device *pdev)
{
	struct spmi_controller_dev *spmi_controller;
	struct spmi_controller *ctrl;
	struct resource *iores;
	int ret;

	ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*spmi_controller));
	if (!ctrl) {
		dev_err(&pdev->dev, "can not allocate spmi_controller data\n");
		return -ENOMEM;
	}
	spmi_controller = spmi_controller_get_drvdata(ctrl);
	spmi_controller->controller = ctrl;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iores) {
		dev_err(&pdev->dev, "can not get resource!\n");
		ret = -EINVAL;
		goto err_put_controller;
	}

	spmi_controller->base = devm_ioremap(&pdev->dev, iores->start,
					     resource_size(iores));
	if (!spmi_controller->base) {
		dev_err(&pdev->dev, "can not remap base addr!\n");
		ret = -EADDRNOTAVAIL;
		goto err_put_controller;
	}

	ret = of_property_read_u32(pdev->dev.of_node, "hisilicon,spmi-channel",
				   &spmi_controller->channel);
	if (ret) {
		dev_err(&pdev->dev, "can not get channel\n");
		ret = -ENODEV;
		goto err_put_controller;
	}

	platform_set_drvdata(pdev, spmi_controller);
	dev_set_drvdata(&ctrl->dev, spmi_controller);

	spin_lock_init(&spmi_controller->lock);

	ctrl->nr = spmi_controller->channel;
	ctrl->dev.parent = pdev->dev.parent;
	ctrl->dev.of_node = of_node_get(pdev->dev.of_node);

	/* Callbacks */
	ctrl->read_cmd = spmi_read_cmd;
	ctrl->write_cmd = spmi_write_cmd;

	ret = spmi_controller_add(ctrl);
	if (ret) {
		dev_err(&pdev->dev, "spmi_controller_add failed with error %d!\n", ret);
		goto err_put_controller;
	}

	return 0;

err_put_controller:
	spmi_controller_put(ctrl);
	return ret;
}

static int spmi_del_controller(struct platform_device *pdev)
{
	struct spmi_controller *ctrl = platform_get_drvdata(pdev);

	spmi_controller_remove(ctrl);
	spmi_controller_put(ctrl);
	return 0;
}

static const struct of_device_id spmi_controller_match_table[] = {
	{
		.compatible = "hisilicon,kirin970-spmi-controller",
	},
	{}
};
MODULE_DEVICE_TABLE(of, spmi_controller_match_table);

static struct platform_driver spmi_controller_driver = {
	.probe		= spmi_controller_probe,
	.remove		= spmi_del_controller,
	.driver		= {
		.name	= "hisi_spmi_controller",
		.of_match_table = spmi_controller_match_table,
	},
};

static int __init spmi_controller_init(void)
{
	return platform_driver_register(&spmi_controller_driver);
}
postcore_initcall(spmi_controller_init);

static void __exit spmi_controller_exit(void)
{
	platform_driver_unregister(&spmi_controller_driver);
}
module_exit(spmi_controller_exit);

MODULE_LICENSE("GPL v2");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:spmi_controller");
Commit	Line	Data
2ea3f6a0	1	// SPDX-License-Identifier: GPL-2.0
70f59c90 M	2
	3	#include <linux/delay.h>
	4	#include <linux/err.h>
7f3ac6c5	5	#include <linux/interrupt.h>
70f59c90 M	6	#include <linux/io.h>
70f59c90 M	7	#include <linux/kernel.h>
70f59c90	8	#include <linux/module.h>
7f3ac6c5 MCC	9	#include <linux/of.h>
7f3ac6c5 MCC	10	#include <linux/platform_device.h>
70f59c90	11	#include <linux/seq_file.h>
7f3ac6c5	12	#include <linux/slab.h>
70f59c90	13	#include <linux/spmi.h>
70f59c90	14
70f59c90 M	15	/*
	16	* SPMI register addr
	17	*/
974e3bdc MCC	18	#define SPMI_CHANNEL_OFFSET 0x0300
974e3bdc MCC	19	#define SPMI_SLAVE_OFFSET 0x20
70f59c90	20
974e3bdc	21	#define SPMI_APB_SPMI_CMD_BASE_ADDR 0x0100
2ea3f6a0	22
70f59c90 M	23	#define SPMI_APB_SPMI_WDATA0_BASE_ADDR 0x0104
	24	#define SPMI_APB_SPMI_WDATA1_BASE_ADDR 0x0108
	25	#define SPMI_APB_SPMI_WDATA2_BASE_ADDR 0x010c
	26	#define SPMI_APB_SPMI_WDATA3_BASE_ADDR 0x0110
	27
	28	#define SPMI_APB_SPMI_STATUS_BASE_ADDR 0x0200
	29
	30	#define SPMI_APB_SPMI_RDATA0_BASE_ADDR 0x0204
	31	#define SPMI_APB_SPMI_RDATA1_BASE_ADDR 0x0208
	32	#define SPMI_APB_SPMI_RDATA2_BASE_ADDR 0x020c
	33	#define SPMI_APB_SPMI_RDATA3_BASE_ADDR 0x0210
70f59c90	34
974e3bdc	35	#define SPMI_PER_DATAREG_BYTE 4
70f59c90 M	36	/*
	37	* SPMI cmd register
	38	*/
974e3bdc	39	#define SPMI_APB_SPMI_CMD_EN BIT(31)
70f59c90 M	40	#define SPMI_APB_SPMI_CMD_TYPE_OFFSET 24
70f59c90 M	41	#define SPMI_APB_SPMI_CMD_LENGTH_OFFSET 20
974e3bdc MCC	42	#define SPMI_APB_SPMI_CMD_SLAVEID_OFFSET 16
974e3bdc MCC	43	#define SPMI_APB_SPMI_CMD_ADDR_OFFSET 0
70f59c90 M	44
70f59c90 M	45	/* Command Opcodes */
2ea3f6a0	46
70f59c90 M	47	enum spmi_controller_cmd_op_code {
	48	SPMI_CMD_REG_ZERO_WRITE = 0,
	49	SPMI_CMD_REG_WRITE = 1,
	50	SPMI_CMD_REG_READ = 2,
	51	SPMI_CMD_EXT_REG_WRITE = 3,
	52	SPMI_CMD_EXT_REG_READ = 4,
	53	SPMI_CMD_EXT_REG_WRITE_L = 5,
	54	SPMI_CMD_EXT_REG_READ_L = 6,
	55	SPMI_CMD_REG_RESET = 7,
	56	SPMI_CMD_REG_SLEEP = 8,
	57	SPMI_CMD_REG_SHUTDOWN = 9,
	58	SPMI_CMD_REG_WAKEUP = 10,
	59	};
70f59c90 M	60
	61	/*
	62	* SPMI status register
	63	*/
974e3bdc MCC	64	#define SPMI_APB_TRANS_DONE BIT(0)
974e3bdc MCC	65	#define SPMI_APB_TRANS_FAIL BIT(2)
70f59c90 M	66
	67	/* Command register fields */
	68	#define SPMI_CONTROLLER_CMD_MAX_BYTE_COUNT 16
	69
	70	/* Maximum number of support PMIC peripherals */
	71	#define SPMI_CONTROLLER_TIMEOUT_US 1000
974e3bdc	72	#define SPMI_CONTROLLER_MAX_TRANS_BYTES 16
70f59c90	73
70f59c90 M	74	struct spmi_controller_dev {
	75	struct spmi_controller *controller;
	76	struct device *dev;
	77	void __iomem *base;
	78	spinlock_t lock;
	79	u32 channel;
	80	};
	81
4d914a8c MCC	82	static int spmi_controller_wait_for_done(struct device *dev,
4d914a8c MCC	83	struct spmi_controller_dev *ctrl_dev,
2ea3f6a0	84	void __iomem *base, u8 sid, u16 addr)
70f59c90	85	{
70f59c90	86	u32 timeout = SPMI_CONTROLLER_TIMEOUT_US;
7f3ac6c5	87	u32 status, offset;
974e3bdc MCC	88
	89	offset = SPMI_APB_SPMI_STATUS_BASE_ADDR;
	90	offset += SPMI_CHANNEL_OFFSET * ctrl_dev->channel + SPMI_SLAVE_OFFSET * sid;
70f59c90	91
7f3ac6c5	92	do {
2ea3f6a0	93	status = readl(base + offset);
70f59c90 M	94
	95	if (status & SPMI_APB_TRANS_DONE) {
	96	if (status & SPMI_APB_TRANS_FAIL) {
4d914a8c	97	dev_err(dev, "%s: transaction failed (0x%x)\n",
70f59c90 M	98	__func__, status);
	99	return -EIO;
	100	}
4d914a8c	101	dev_dbg(dev, "%s: status 0x%x\n", __func__, status);
70f59c90 M	102	return 0;
70f59c90 M	103	}
2ea3f6a0	104	udelay(1);
7f3ac6c5	105	} while (timeout--);
70f59c90	106
4d914a8c	107	dev_err(dev, "%s: timeout, status 0x%x\n", __func__, status);
2ea3f6a0 MCC	108	return -ETIMEDOUT;
2ea3f6a0 MCC	109	}
70f59c90 M	110
70f59c90 M	111	static int spmi_read_cmd(struct spmi_controller *ctrl,
7f3ac6c5	112	u8 opc, u8 slave_id, u16 slave_addr, u8 *__buf, size_t bc)
70f59c90 M	113	{
70f59c90 M	114	struct spmi_controller_dev *spmi_controller = dev_get_drvdata(&ctrl->dev);
7f3ac6c5	115	u32 chnl_ofst = SPMI_CHANNEL_OFFSET * spmi_controller->channel;
70f59c90	116	unsigned long flags;
6af36450	117	u8 *buf = __buf;
70f59c90 M	118	u32 cmd, data;
70f59c90 M	119	int rc;
70f59c90 M	120	u8 op_code, i;
	121
	122	if (bc > SPMI_CONTROLLER_MAX_TRANS_BYTES) {
4d914a8c	123	dev_err(&ctrl->dev,
4c6491a3	124	"spmi_controller supports 1..%d bytes per trans, but:%zu requested\n",
4d914a8c	125	SPMI_CONTROLLER_MAX_TRANS_BYTES, bc);
70f59c90 M	126	return -EINVAL;
	127	}
	128
7f3ac6c5 MCC	129	switch (opc) {
7f3ac6c5 MCC	130	case SPMI_CMD_READ:
70f59c90	131	op_code = SPMI_CMD_REG_READ;
7f3ac6c5 MCC	132	break;
7f3ac6c5 MCC	133	case SPMI_CMD_EXT_READ:
70f59c90	134	op_code = SPMI_CMD_EXT_REG_READ;
7f3ac6c5 MCC	135	break;
7f3ac6c5 MCC	136	case SPMI_CMD_EXT_READL:
70f59c90	137	op_code = SPMI_CMD_EXT_REG_READ_L;
7f3ac6c5 MCC	138	break;
	139	default:
	140	dev_err(&ctrl->dev, "invalid read cmd 0x%x\n", opc);
70f59c90 M	141	return -EINVAL;
	142	}
	143
2ea3f6a0 MCC	144	cmd = SPMI_APB_SPMI_CMD_EN \|
	145	(op_code << SPMI_APB_SPMI_CMD_TYPE_OFFSET) \|
	146	((bc - 1) << SPMI_APB_SPMI_CMD_LENGTH_OFFSET) \|
7f3ac6c5 MCC	147	((slave_id & 0xf) << SPMI_APB_SPMI_CMD_SLAVEID_OFFSET) \| /* slvid */
7f3ac6c5 MCC	148	((slave_addr & 0xffff) << SPMI_APB_SPMI_CMD_ADDR_OFFSET); /* slave_addr */
70f59c90	149
2ea3f6a0	150	spin_lock_irqsave(&spmi_controller->lock, flags);
70f59c90	151
2ea3f6a0	152	writel(cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);
70f59c90	153
4d914a8c	154	rc = spmi_controller_wait_for_done(&ctrl->dev, spmi_controller,
7f3ac6c5	155	spmi_controller->base, slave_id, slave_addr);
70f59c90 M	156	if (rc)
	157	goto done;
	158
7f3ac6c5 MCC	159	for (i = 0; bc > i * SPMI_PER_DATAREG_BYTE; i++) {
	160	data = readl(spmi_controller->base + chnl_ofst +
	161	SPMI_SLAVE_OFFSET * slave_id +
	162	SPMI_APB_SPMI_RDATA0_BASE_ADDR +
	163	i * SPMI_PER_DATAREG_BYTE);
1b9419d1	164	data = be32_to_cpu((__be32 __force)data);
2ea3f6a0	165	if ((bc - i * SPMI_PER_DATAREG_BYTE) >> 2) {
70f59c90 M	166	memcpy(buf, &data, sizeof(data));
	167	buf += sizeof(data);
	168	} else {
2ea3f6a0 MCC	169	memcpy(buf, &data, bc % SPMI_PER_DATAREG_BYTE);
2ea3f6a0 MCC	170	buf += (bc % SPMI_PER_DATAREG_BYTE);
70f59c90	171	}
7f3ac6c5	172	}
70f59c90 M	173
	174	done:
	175	spin_unlock_irqrestore(&spmi_controller->lock, flags);
	176	if (rc)
4d914a8c	177	dev_err(&ctrl->dev,
4c6491a3	178	"spmi read wait timeout op:0x%x slave_id:%d slave_addr:0x%x bc:%zu\n",
7f3ac6c5	179	opc, slave_id, slave_addr, bc + 1);
6af36450	180	else
7f3ac6c5 MCC	181	dev_dbg(&ctrl->dev, "%s: id:%d slave_addr:0x%x, read value: %*ph\n",
7f3ac6c5 MCC	182	__func__, slave_id, slave_addr, (int)bc, __buf);
6af36450	183
70f59c90	184	return rc;
2ea3f6a0	185	}
70f59c90	186
70f59c90	187	static int spmi_write_cmd(struct spmi_controller *ctrl,
7f3ac6c5	188	u8 opc, u8 slave_id, u16 slave_addr, const u8 *__buf, size_t bc)
70f59c90 M	189	{
70f59c90 M	190	struct spmi_controller_dev *spmi_controller = dev_get_drvdata(&ctrl->dev);
7f3ac6c5	191	u32 chnl_ofst = SPMI_CHANNEL_OFFSET * spmi_controller->channel;
6af36450	192	const u8 *buf = __buf;
70f59c90	193	unsigned long flags;
8788a30c	194	u32 cmd, data;
70f59c90	195	int rc;
70f59c90 M	196	u8 op_code, i;
70f59c90 M	197
70f59c90	198	if (bc > SPMI_CONTROLLER_MAX_TRANS_BYTES) {
4d914a8c	199	dev_err(&ctrl->dev,
4c6491a3	200	"spmi_controller supports 1..%d bytes per trans, but:%zu requested\n",
4d914a8c	201	SPMI_CONTROLLER_MAX_TRANS_BYTES, bc);
70f59c90 M	202	return -EINVAL;
	203	}
	204
7f3ac6c5 MCC	205	switch (opc) {
7f3ac6c5 MCC	206	case SPMI_CMD_WRITE:
70f59c90	207	op_code = SPMI_CMD_REG_WRITE;
7f3ac6c5 MCC	208	break;
7f3ac6c5 MCC	209	case SPMI_CMD_EXT_WRITE:
70f59c90	210	op_code = SPMI_CMD_EXT_REG_WRITE;
7f3ac6c5 MCC	211	break;
7f3ac6c5 MCC	212	case SPMI_CMD_EXT_WRITEL:
70f59c90	213	op_code = SPMI_CMD_EXT_REG_WRITE_L;
7f3ac6c5 MCC	214	break;
	215	default:
	216	dev_err(&ctrl->dev, "invalid write cmd 0x%x\n", opc);
70f59c90 M	217	return -EINVAL;
	218	}
	219
2ea3f6a0 MCC	220	cmd = SPMI_APB_SPMI_CMD_EN \|
	221	(op_code << SPMI_APB_SPMI_CMD_TYPE_OFFSET) \|
	222	((bc - 1) << SPMI_APB_SPMI_CMD_LENGTH_OFFSET) \|
7f3ac6c5 MCC	223	((slave_id & 0xf) << SPMI_APB_SPMI_CMD_SLAVEID_OFFSET) \|
7f3ac6c5 MCC	224	((slave_addr & 0xffff) << SPMI_APB_SPMI_CMD_ADDR_OFFSET);
70f59c90 M	225
70f59c90 M	226	/* Write data to FIFOs */
2ea3f6a0	227	spin_lock_irqsave(&spmi_controller->lock, flags);
70f59c90	228
7f3ac6c5	229	for (i = 0; bc > i * SPMI_PER_DATAREG_BYTE; i++) {
8788a30c	230	data = 0;
2ea3f6a0	231	if ((bc - i * SPMI_PER_DATAREG_BYTE) >> 2) {
70f59c90	232	memcpy(&data, buf, sizeof(data));
2ea3f6a0	233	buf += sizeof(data);
70f59c90	234	} else {
2ea3f6a0 MCC	235	memcpy(&data, buf, bc % SPMI_PER_DATAREG_BYTE);
2ea3f6a0 MCC	236	buf += (bc % SPMI_PER_DATAREG_BYTE);
70f59c90 M	237	}
70f59c90 M	238
1b9419d1	239	writel((u32 __force)cpu_to_be32(data),
7f3ac6c5 MCC	240	spmi_controller->base + chnl_ofst +
	241	SPMI_APB_SPMI_WDATA0_BASE_ADDR +
	242	SPMI_PER_DATAREG_BYTE * i);
	243	}
70f59c90 M	244
70f59c90 M	245	/* Start the transaction */
2ea3f6a0	246	writel(cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);
70f59c90	247
4d914a8c	248	rc = spmi_controller_wait_for_done(&ctrl->dev, spmi_controller,
7f3ac6c5 MCC	249	spmi_controller->base, slave_id,
7f3ac6c5 MCC	250	slave_addr);
70f59c90 M	251	spin_unlock_irqrestore(&spmi_controller->lock, flags);
	252
	253	if (rc)
4c6491a3	254	dev_err(&ctrl->dev, "spmi write wait timeout op:0x%x slave_id:%d slave_addr:0x%x bc:%zu\n",
7f3ac6c5	255	opc, slave_id, slave_addr, bc);
6af36450	256	else
7f3ac6c5 MCC	257	dev_dbg(&ctrl->dev, "%s: id:%d slave_addr:0x%x, wrote value: %*ph\n",
7f3ac6c5 MCC	258	__func__, slave_id, slave_addr, (int)bc, __buf);
70f59c90 M	259
70f59c90 M	260	return rc;
2ea3f6a0 MCC	261	}
2ea3f6a0 MCC	262
70f59c90 M	263	static int spmi_controller_probe(struct platform_device *pdev)
	264	{
	265	struct spmi_controller_dev *spmi_controller;
	266	struct spmi_controller *ctrl;
	267	struct resource *iores;
7f3ac6c5	268	int ret;
6af36450	269
70f59c90 M	270	ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*spmi_controller));
	271	if (!ctrl) {
	272	dev_err(&pdev->dev, "can not allocate spmi_controller data\n");
2ea3f6a0	273	return -ENOMEM;
70f59c90 M	274	}
	275	spmi_controller = spmi_controller_get_drvdata(ctrl);
	276	spmi_controller->controller = ctrl;
	277
70f59c90 M	278	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
70f59c90 M	279	if (!iores) {
2ea3f6a0	280	dev_err(&pdev->dev, "can not get resource!\n");
12b38ea0 CJ	281	ret = -EINVAL;
12b38ea0 CJ	282	goto err_put_controller;
70f59c90 M	283	}
70f59c90 M	284
dbbc8fdf DC	285	spmi_controller->base = devm_ioremap(&pdev->dev, iores->start,
dbbc8fdf DC	286	resource_size(iores));
70f59c90	287	if (!spmi_controller->base) {
2ea3f6a0	288	dev_err(&pdev->dev, "can not remap base addr!\n");
12b38ea0 CJ	289	ret = -EADDRNOTAVAIL;
12b38ea0 CJ	290	goto err_put_controller;
70f59c90	291	}
70f59c90	292
fcc84fe1	293	ret = of_property_read_u32(pdev->dev.of_node, "hisilicon,spmi-channel",
2ea3f6a0	294	&spmi_controller->channel);
70f59c90	295	if (ret) {
6196331e	296	dev_err(&pdev->dev, "can not get channel\n");
12b38ea0 CJ	297	ret = -ENODEV;
12b38ea0 CJ	298	goto err_put_controller;
70f59c90 M	299	}
	300
	301	platform_set_drvdata(pdev, spmi_controller);
	302	dev_set_drvdata(&ctrl->dev, spmi_controller);
	303
	304	spin_lock_init(&spmi_controller->lock);
	305
	306	ctrl->nr = spmi_controller->channel;
	307	ctrl->dev.parent = pdev->dev.parent;
	308	ctrl->dev.of_node = of_node_get(pdev->dev.of_node);
	309
	310	/* Callbacks */
	311	ctrl->read_cmd = spmi_read_cmd;
	312	ctrl->write_cmd = spmi_write_cmd;
	313
	314	ret = spmi_controller_add(ctrl);
12b38ea0 CJ	315	if (ret) {
	316	dev_err(&pdev->dev, "spmi_controller_add failed with error %d!\n", ret);
	317	goto err_put_controller;
	318	}
	319
	320	return 0;
85eb5344	321
12b38ea0 CJ	322	err_put_controller:
12b38ea0 CJ	323	spmi_controller_put(ctrl);
2ea3f6a0	324	return ret;
70f59c90 M	325	}
	326
	327	static int spmi_del_controller(struct platform_device *pdev)
	328	{
	329	struct spmi_controller *ctrl = platform_get_drvdata(pdev);
	330
70f59c90	331	spmi_controller_remove(ctrl);
12b38ea0	332	spmi_controller_put(ctrl);
70f59c90 M	333	return 0;
	334	}
	335
2ea3f6a0	336	static const struct of_device_id spmi_controller_match_table[] = {
de1a93b6 MCC	337	{
de1a93b6 MCC	338	.compatible = "hisilicon,kirin970-spmi-controller",
2ea3f6a0 MCC	339	},
2ea3f6a0 MCC	340	{}
70f59c90	341	};
85eb5344	342	MODULE_DEVICE_TABLE(of, spmi_controller_match_table);
70f59c90 M	343
	344	static struct platform_driver spmi_controller_driver = {
	345	.probe = spmi_controller_probe,
	346	.remove = spmi_del_controller,
	347	.driver = {
7f3ac6c5	348	.name = "hisi_spmi_controller",
70f59c90	349	.of_match_table = spmi_controller_match_table,
2ea3f6a0 MCC	350	},
	351	};
	352
70f59c90 M	353	static int __init spmi_controller_init(void)
70f59c90 M	354	{
2ea3f6a0	355	return platform_driver_register(&spmi_controller_driver);
70f59c90 M	356	}
	357	postcore_initcall(spmi_controller_init);
	358
	359	static void __exit spmi_controller_exit(void)
	360	{
	361	platform_driver_unregister(&spmi_controller_driver);
	362	}
	363	module_exit(spmi_controller_exit);
2ea3f6a0	364
70f59c90	365	MODULE_LICENSE("GPL v2");
2ea3f6a0	366	MODULE_VERSION("1.0");
e4cebcae	367	MODULE_ALIAS("platform:spmi_controller");