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565e7dc8 HJ |
1 | /* |
2 | * | |
3 | * Copyright (c) 2009, Microsoft Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * | |
18 | * Authors: | |
19 | * Haiyang Zhang <haiyangz@microsoft.com> | |
20 | * Hank Janssen <hjanssen@microsoft.com> | |
21 | * | |
22 | */ | |
6658be6a GKH |
23 | #ifndef __HV_API_H |
24 | #define __HV_API_H | |
565e7dc8 | 25 | |
65452d1f GKH |
26 | |
27 | /* Status codes for hypervisor operations. */ | |
28 | ||
29 | /* | |
30 | * HV_STATUS_SUCCESS | |
31 | * The specified hypercall succeeded | |
32 | */ | |
33 | #define HV_STATUS_SUCCESS ((u16)0x0000) | |
34 | ||
35 | /* | |
36 | * HV_STATUS_INVALID_HYPERCALL_CODE | |
37 | * The hypervisor does not support the operation because the specified | |
38 | * hypercall code is not supported. | |
39 | */ | |
40 | #define HV_STATUS_INVALID_HYPERCALL_CODE ((u16)0x0002) | |
41 | ||
42 | /* | |
43 | * HV_STATUS_INVALID_HYPERCALL_INPUT | |
44 | * The hypervisor does not support the operation because the encoding for the | |
45 | * hypercall input register is not supported. | |
46 | */ | |
47 | #define HV_STATUS_INVALID_HYPERCALL_INPUT ((u16)0x0003) | |
48 | ||
49 | /* | |
50 | * HV_STATUS_INVALID_ALIGNMENT | |
51 | * The hypervisor could not perform the operation beacuse a parameter has an | |
52 | * invalid alignment. | |
53 | */ | |
54 | #define HV_STATUS_INVALID_ALIGNMENT ((u16)0x0004) | |
55 | ||
56 | /* | |
57 | * HV_STATUS_INVALID_PARAMETER | |
58 | * The hypervisor could not perform the operation beacuse an invalid parameter | |
59 | * was specified. | |
60 | */ | |
61 | #define HV_STATUS_INVALID_PARAMETER ((u16)0x0005) | |
62 | ||
63 | /* | |
64 | * HV_STATUS_ACCESS_DENIED | |
65 | * Access to the specified object was denied. | |
66 | */ | |
67 | #define HV_STATUS_ACCESS_DENIED ((u16)0x0006) | |
68 | ||
69 | /* | |
70 | * HV_STATUS_INVALID_PARTITION_STATE | |
71 | * The hypervisor could not perform the operation because the partition is | |
72 | * entering or in an invalid state. | |
73 | */ | |
74 | #define HV_STATUS_INVALID_PARTITION_STATE ((u16)0x0007) | |
75 | ||
76 | /* | |
77 | * HV_STATUS_OPERATION_DENIED | |
78 | * The operation is not allowed in the current state. | |
79 | */ | |
80 | #define HV_STATUS_OPERATION_DENIED ((u16)0x0008) | |
81 | ||
82 | /* | |
83 | * HV_STATUS_UNKNOWN_PROPERTY | |
84 | * The hypervisor does not recognize the specified partition property. | |
85 | */ | |
86 | #define HV_STATUS_UNKNOWN_PROPERTY ((u16)0x0009) | |
87 | ||
88 | /* | |
89 | * HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE | |
90 | * The specified value of a partition property is out of range or violates an | |
91 | * invariant. | |
92 | */ | |
93 | #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE ((u16)0x000A) | |
94 | ||
95 | /* | |
96 | * HV_STATUS_INSUFFICIENT_MEMORY | |
97 | * There is not enough memory in the hypervisor pool to complete the operation. | |
98 | */ | |
99 | #define HV_STATUS_INSUFFICIENT_MEMORY ((u16)0x000B) | |
100 | ||
101 | /* | |
102 | * HV_STATUS_PARTITION_TOO_DEEP | |
103 | * The maximum partition depth has been exceeded for the partition hierarchy. | |
104 | */ | |
105 | #define HV_STATUS_PARTITION_TOO_DEEP ((u16)0x000C) | |
106 | ||
107 | /* | |
108 | * HV_STATUS_INVALID_PARTITION_ID | |
109 | * A partition with the specified partition Id does not exist. | |
110 | */ | |
111 | #define HV_STATUS_INVALID_PARTITION_ID ((u16)0x000D) | |
112 | ||
113 | /* | |
114 | * HV_STATUS_INVALID_VP_INDEX | |
115 | * The hypervisor could not perform the operation because the specified VP | |
116 | * index is invalid. | |
117 | */ | |
118 | #define HV_STATUS_INVALID_VP_INDEX ((u16)0x000E) | |
119 | ||
120 | /* | |
121 | * HV_STATUS_NOT_FOUND | |
122 | * The iteration is complete; no addition items in the iteration could be | |
123 | * found. | |
124 | */ | |
125 | #define HV_STATUS_NOT_FOUND ((u16)0x0010) | |
126 | ||
127 | /* | |
128 | * HV_STATUS_INVALID_PORT_ID | |
129 | * The hypervisor could not perform the operation because the specified port | |
130 | * identifier is invalid. | |
131 | */ | |
132 | #define HV_STATUS_INVALID_PORT_ID ((u16)0x0011) | |
133 | ||
134 | /* | |
135 | * HV_STATUS_INVALID_CONNECTION_ID | |
136 | * The hypervisor could not perform the operation because the specified | |
137 | * connection identifier is invalid. | |
138 | */ | |
139 | #define HV_STATUS_INVALID_CONNECTION_ID ((u16)0x0012) | |
140 | ||
141 | /* | |
142 | * HV_STATUS_INSUFFICIENT_BUFFERS | |
143 | * You did not supply enough message buffers to send a message. | |
144 | */ | |
145 | #define HV_STATUS_INSUFFICIENT_BUFFERS ((u16)0x0013) | |
146 | ||
147 | /* | |
148 | * HV_STATUS_NOT_ACKNOWLEDGED | |
149 | * The previous virtual interrupt has not been acknowledged. | |
150 | */ | |
151 | #define HV_STATUS_NOT_ACKNOWLEDGED ((u16)0x0014) | |
152 | ||
153 | /* | |
154 | * HV_STATUS_INVALID_VP_STATE | |
155 | * A virtual processor is not in the correct state for the performance of the | |
156 | * indicated operation. | |
157 | */ | |
158 | #define HV_STATUS_INVALID_VP_STATE ((u16)0x0015) | |
159 | ||
160 | /* | |
161 | * HV_STATUS_ACKNOWLEDGED | |
162 | * The previous virtual interrupt has already been acknowledged. | |
163 | */ | |
164 | #define HV_STATUS_ACKNOWLEDGED ((u16)0x0016) | |
165 | ||
166 | /* | |
167 | * HV_STATUS_INVALID_SAVE_RESTORE_STATE | |
168 | * The indicated partition is not in a valid state for saving or restoring. | |
169 | */ | |
170 | #define HV_STATUS_INVALID_SAVE_RESTORE_STATE ((u16)0x0017) | |
171 | ||
172 | /* | |
173 | * HV_STATUS_INVALID_SYNIC_STATE | |
174 | * The hypervisor could not complete the operation because a required feature | |
175 | * of the synthetic interrupt controller (SynIC) was disabled. | |
176 | */ | |
177 | #define HV_STATUS_INVALID_SYNIC_STATE ((u16)0x0018) | |
178 | ||
179 | /* | |
180 | * HV_STATUS_OBJECT_IN_USE | |
181 | * The hypervisor could not perform the operation because the object or value | |
182 | * was either already in use or being used for a purpose that would not permit | |
183 | * completing the operation. | |
184 | */ | |
185 | #define HV_STATUS_OBJECT_IN_USE ((u16)0x0019) | |
186 | ||
187 | /* | |
188 | * HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO | |
189 | * The proximity domain information is invalid. | |
190 | */ | |
191 | #define HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO ((u16)0x001A) | |
192 | ||
193 | /* | |
194 | * HV_STATUS_NO_DATA | |
195 | * An attempt to retrieve debugging data failed because none was available. | |
196 | */ | |
197 | #define HV_STATUS_NO_DATA ((u16)0x001B) | |
198 | ||
199 | /* | |
200 | * HV_STATUS_INACTIVE | |
201 | * The physical connection being used for debuggging has not recorded any | |
202 | * receive activity since the last operation. | |
203 | */ | |
204 | #define HV_STATUS_INACTIVE ((u16)0x001C) | |
205 | ||
206 | /* | |
207 | * HV_STATUS_NO_RESOURCES | |
208 | * There are not enough resources to complete the operation. | |
209 | */ | |
210 | #define HV_STATUS_NO_RESOURCES ((u16)0x001D) | |
211 | ||
212 | /* | |
213 | * HV_STATUS_FEATURE_UNAVAILABLE | |
214 | * A hypervisor feature is not available to the user. | |
215 | */ | |
216 | #define HV_STATUS_FEATURE_UNAVAILABLE ((u16)0x001E) | |
217 | ||
218 | /* | |
219 | * HV_STATUS_UNSUCCESSFUL | |
220 | * {Operation Failed} The requested operation was unsuccessful. | |
221 | */ | |
222 | #define HV_STATUS_UNSUCCESSFUL ((u16)0x1001) | |
223 | ||
224 | /* | |
225 | * HV_STATUS_INSUFFICIENT_BUFFER | |
226 | * The specified buffer was too small to contain all of the requested data. | |
227 | */ | |
228 | #define HV_STATUS_INSUFFICIENT_BUFFER ((u16)0x1002) | |
229 | ||
230 | /* | |
231 | * HV_STATUS_GPA_NOT_PRESENT | |
232 | * The guest physical address is not currently associated with a system | |
233 | * physical address. | |
234 | */ | |
235 | #define HV_STATUS_GPA_NOT_PRESENT ((u16)0x1003) | |
236 | ||
237 | /* | |
238 | * HV_STATUS_GUEST_PAGE_FAULT | |
239 | * The operation would have resulted in a page fault in the guest. | |
240 | */ | |
241 | #define HV_STATUS_GUEST_PAGE_FAULT ((u16)0x1004) | |
242 | ||
243 | /* | |
244 | * HV_STATUS_RUNDOWN_DISABLED | |
245 | * The operation cannot proceed as the rundown object was marked disabled. | |
246 | */ | |
247 | #define HV_STATUS_RUNDOWN_DISABLED ((u16)0x1005) | |
248 | ||
249 | /* | |
250 | * HV_STATUS_KEY_ALREADY_EXISTS | |
251 | * The entry cannot be added as another entry with the same key already exists. | |
252 | */ | |
253 | #define HV_STATUS_KEY_ALREADY_EXISTS ((u16)0x1006) | |
254 | ||
255 | /* | |
256 | * HV_STATUS_GPA_INTERCEPT | |
257 | * The operation resulted an intercept on a region of guest physical memory. | |
258 | */ | |
259 | #define HV_STATUS_GPA_INTERCEPT ((u16)0x1007) | |
260 | ||
261 | /* | |
262 | * HV_STATUS_GUEST_GENERAL_PROTECTION_FAULT | |
263 | * The operation would have resulted in a general protection fault in the | |
264 | * guest. | |
265 | */ | |
266 | #define HV_STATUS_GUEST_GENERAL_PROTECTION_FAULT ((u16)0x1008) | |
267 | ||
268 | /* | |
269 | * HV_STATUS_GUEST_STACK_FAULT | |
270 | * The operation would have resulted in a stack fault in the guest. | |
271 | */ | |
272 | #define HV_STATUS_GUEST_STACK_FAULT ((u16)0x1009) | |
273 | ||
274 | /* | |
275 | * HV_STATUS_GUEST_INVALID_OPCODE_FAULT | |
276 | * The operation would have resulted in an invalid opcode fault in the guest. | |
277 | */ | |
278 | #define HV_STATUS_GUEST_INVALID_OPCODE_FAULT ((u16)0x100A) | |
279 | ||
280 | /* | |
281 | * HV_STATUS_FINALIZE_INCOMPLETE | |
282 | * The partition is not completely finalized. | |
283 | */ | |
284 | #define HV_STATUS_FINALIZE_INCOMPLETE ((u16)0x100B) | |
285 | ||
286 | /* | |
287 | * HV_STATUS_GUEST_MACHINE_CHECK_ABORT | |
288 | * The operation would have resulted in an machine check abort in the guest. | |
289 | */ | |
290 | #define HV_STATUS_GUEST_MACHINE_CHECK_ABORT ((u16)0x100C) | |
291 | ||
292 | /* | |
293 | * HV_STATUS_ILLEGAL_OVERLAY_ACCESS | |
294 | * An illegal access was attempted to an overlay page. | |
295 | */ | |
296 | #define HV_STATUS_ILLEGAL_OVERLAY_ACCESS ((u16)0x100D) | |
297 | ||
298 | /* | |
299 | * HV_STATUS_INSUFFICIENT_SYSTEM_VA | |
300 | * There is not enough system VA space available to satisfy the request, | |
301 | */ | |
302 | #define HV_STATUS_INSUFFICIENT_SYSTEM_VA ((u16)0x100E) | |
303 | ||
304 | /* | |
305 | * HV_STATUS_VIRTUAL_ADDRESS_NOT_MAPPED | |
306 | * The passed virtual address was not mapped in the hypervisor address space. | |
307 | */ | |
308 | #define HV_STATUS_VIRTUAL_ADDRESS_NOT_MAPPED ((u16)0x100F) | |
309 | ||
310 | /* | |
311 | * HV_STATUS_NOT_IMPLEMENTED | |
312 | * The requested operation is not implemented in this version of the | |
313 | * hypervisor. | |
314 | */ | |
315 | #define HV_STATUS_NOT_IMPLEMENTED ((u16)0x1010) | |
316 | ||
317 | /* | |
318 | * HV_STATUS_VMX_INSTRUCTION_FAILED | |
bbc9a991 | 319 | * The requested VMX instruction failed to complete successfully. |
65452d1f GKH |
320 | */ |
321 | #define HV_STATUS_VMX_INSTRUCTION_FAILED ((u16)0x1011) | |
322 | ||
323 | /* | |
324 | * HV_STATUS_VMX_INSTRUCTION_FAILED_WITH_STATUS | |
bbc9a991 | 325 | * The requested VMX instruction failed to complete successfully indicating |
65452d1f GKH |
326 | * status. |
327 | */ | |
328 | #define HV_STATUS_VMX_INSTRUCTION_FAILED_WITH_STATUS ((u16)0x1012) | |
329 | ||
330 | /* | |
331 | * HV_STATUS_MSR_ACCESS_FAILED | |
332 | * The requested access to the model specific register failed. | |
333 | */ | |
334 | #define HV_STATUS_MSR_ACCESS_FAILED ((u16)0x1013) | |
335 | ||
336 | /* | |
337 | * HV_STATUS_CR_ACCESS_FAILED | |
338 | * The requested access to the control register failed. | |
339 | */ | |
340 | #define HV_STATUS_CR_ACCESS_FAILED ((u16)0x1014) | |
341 | ||
342 | /* | |
343 | * HV_STATUS_TIMEOUT | |
344 | * The specified timeout expired before the operation completed. | |
345 | */ | |
346 | #define HV_STATUS_TIMEOUT ((u16)0x1016) | |
347 | ||
348 | /* | |
349 | * HV_STATUS_MSR_INTERCEPT | |
350 | * The requested access to the model specific register generated an intercept. | |
351 | */ | |
352 | #define HV_STATUS_MSR_INTERCEPT ((u16)0x1017) | |
353 | ||
354 | /* | |
355 | * HV_STATUS_CPUID_INTERCEPT | |
356 | * The CPUID instruction generated an intercept. | |
357 | */ | |
358 | #define HV_STATUS_CPUID_INTERCEPT ((u16)0x1018) | |
359 | ||
360 | /* | |
361 | * HV_STATUS_REPEAT_INSTRUCTION | |
362 | * The current instruction should be repeated and the instruction pointer not | |
363 | * advanced. | |
364 | */ | |
365 | #define HV_STATUS_REPEAT_INSTRUCTION ((u16)0x1019) | |
366 | ||
367 | /* | |
368 | * HV_STATUS_PAGE_PROTECTION_VIOLATION | |
369 | * The current instruction should be repeated and the instruction pointer not | |
370 | * advanced. | |
371 | */ | |
372 | #define HV_STATUS_PAGE_PROTECTION_VIOLATION ((u16)0x101A) | |
373 | ||
374 | /* | |
375 | * HV_STATUS_PAGE_TABLE_INVALID | |
376 | * The current instruction should be repeated and the instruction pointer not | |
377 | * advanced. | |
378 | */ | |
379 | #define HV_STATUS_PAGE_TABLE_INVALID ((u16)0x101B) | |
380 | ||
381 | /* | |
382 | * HV_STATUS_PAGE_NOT_PRESENT | |
383 | * The current instruction should be repeated and the instruction pointer not | |
384 | * advanced. | |
385 | */ | |
386 | #define HV_STATUS_PAGE_NOT_PRESENT ((u16)0x101C) | |
387 | ||
388 | /* | |
389 | * HV_STATUS_IO_INTERCEPT | |
390 | * The requested access to the I/O port generated an intercept. | |
391 | */ | |
392 | #define HV_STATUS_IO_INTERCEPT ((u16)0x101D) | |
393 | ||
394 | /* | |
395 | * HV_STATUS_NOTHING_TO_DO | |
396 | * There is nothing to do. | |
397 | */ | |
398 | #define HV_STATUS_NOTHING_TO_DO ((u16)0x101E) | |
399 | ||
400 | /* | |
401 | * HV_STATUS_THREAD_TERMINATING | |
402 | * The requested thread is terminating. | |
403 | */ | |
404 | #define HV_STATUS_THREAD_TERMINATING ((u16)0x101F) | |
405 | ||
406 | /* | |
407 | * HV_STATUS_SECTION_ALREADY_CONSTRUCTED | |
408 | * The specified section was already constructed. | |
409 | */ | |
410 | #define HV_STATUS_SECTION_ALREADY_CONSTRUCTED ((u16)0x1020) | |
411 | ||
412 | /* HV_STATUS_SECTION_NOT_ALREADY_CONSTRUCTED | |
413 | * The specified section was not already constructed. | |
414 | */ | |
415 | #define HV_STATUS_SECTION_NOT_ALREADY_CONSTRUCTED ((u16)0x1021) | |
416 | ||
417 | /* | |
418 | * HV_STATUS_PAGE_ALREADY_COMMITTED | |
419 | * The specified virtual address was already backed by physical memory. | |
420 | */ | |
421 | #define HV_STATUS_PAGE_ALREADY_COMMITTED ((u16)0x1022) | |
422 | ||
423 | /* | |
424 | * HV_STATUS_PAGE_NOT_ALREADY_COMMITTED | |
425 | * The specified virtual address was not already backed by physical memory. | |
426 | */ | |
427 | #define HV_STATUS_PAGE_NOT_ALREADY_COMMITTED ((u16)0x1023) | |
428 | ||
429 | /* | |
430 | * HV_STATUS_COMMITTED_PAGES_REMAIN | |
431 | * Committed pages remain in the section. | |
432 | */ | |
433 | #define HV_STATUS_COMMITTED_PAGES_REMAIN ((u16)0x1024) | |
434 | ||
435 | /* | |
436 | * HV_STATUS_NO_REMAINING_COMMITTED_PAGES | |
437 | * No additional committed pages beyond the specified page exist in the | |
438 | * section. | |
439 | */ | |
440 | #define HV_STATUS_NO_REMAINING_COMMITTED_PAGES ((u16)0x1025) | |
441 | ||
442 | /* | |
443 | * HV_STATUS_INSUFFICIENT_COMPARTMENT_VA | |
444 | * The VA space of the compartment is exhausted. | |
445 | */ | |
446 | #define HV_STATUS_INSUFFICIENT_COMPARTMENT_VA ((u16)0x1026) | |
447 | ||
448 | /* | |
449 | * HV_STATUS_DEREF_SPA_LIST_FULL | |
450 | * The SPA dereference list is full, and there are additional entries to be | |
451 | * added to it. | |
452 | */ | |
453 | #define HV_STATUS_DEREF_SPA_LIST_FULL ((u16)0x1027) | |
454 | ||
455 | /* | |
456 | * HV_STATUS_GPA_OUT_OF_RANGE | |
457 | * The supplied GPA is out of range. | |
458 | */ | |
459 | #define HV_STATUS_GPA_OUT_OF_RANGE ((u16)0x1027) | |
460 | ||
461 | /* | |
462 | * HV_STATUS_NONVOLATILE_XMM_STALE | |
463 | * The XMM register that was being accessed is stale. | |
464 | */ | |
465 | #define HV_STATUS_NONVOLATILE_XMM_STALE ((u16)0x1028) | |
466 | ||
467 | /* HV_STATUS_UNSUPPORTED_PROCESSOR | |
468 | * The hypervisor does not support the processors in this system. | |
469 | */ | |
470 | #define HV_STATUS_UNSUPPORTED_PROCESSOR ((u16)0x1029) | |
471 | ||
472 | /* | |
473 | * HV_STATUS_INSUFFICIENT_CROM_SPACE | |
474 | * Insufficient space existed for copying over the CROM contents. | |
475 | */ | |
476 | #define HV_STATUS_INSUFFICIENT_CROM_SPACE ((u16)0x2000) | |
477 | ||
478 | /* | |
479 | * HV_STATUS_BAD_CROM_FORMAT | |
480 | * The contents of the CROM failed validation attempts. | |
481 | */ | |
482 | #define HV_STATUS_BAD_CROM_FORMAT ((u16)0x2001) | |
483 | ||
484 | /* | |
485 | * HV_STATUS_UNSUPPORTED_CROM_FORMAT | |
486 | * The contents of the CROM contain contents the parser doesn't support. | |
487 | */ | |
488 | #define HV_STATUS_UNSUPPORTED_CROM_FORMAT ((u16)0x2002) | |
489 | ||
490 | /* | |
491 | * HV_STATUS_UNSUPPORTED_CONTROLLER | |
492 | * The register format of the OHCI controller specified for debugging is not | |
493 | * supported. | |
494 | */ | |
495 | #define HV_STATUS_UNSUPPORTED_CONTROLLER ((u16)0x2003) | |
496 | ||
497 | /* | |
498 | * HV_STATUS_CROM_TOO_LARGE | |
499 | * The CROM contents were to large to copy over. | |
500 | */ | |
501 | #define HV_STATUS_CROM_TOO_LARGE ((u16)0x2004) | |
502 | ||
503 | /* | |
504 | * HV_STATUS_CONTROLLER_IN_USE | |
505 | * The OHCI controller specified for debugging cannot be used as it is already | |
506 | * in use. | |
507 | */ | |
508 | #define HV_STATUS_CONTROLLER_IN_USE ((u16)0x2005) | |
509 | ||
510 | ||
6658be6a GKH |
511 | /* |
512 | * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent | |
f6feebe0 | 513 | * is set by CPUID(HVCPUID_VERSION_FEATURES). |
6658be6a GKH |
514 | */ |
515 | enum hv_cpuid_function { | |
f6feebe0 HZ |
516 | HVCPUID_VERSION_FEATURES = 0x00000001, |
517 | HVCPUID_VENDOR_MAXFUNCTION = 0x40000000, | |
518 | HVCPUID_INTERFACE = 0x40000001, | |
6658be6a GKH |
519 | |
520 | /* | |
521 | * The remaining functions depend on the value of | |
f6feebe0 | 522 | * HVCPUID_INTERFACE |
6658be6a | 523 | */ |
f6feebe0 HZ |
524 | HVCPUID_VERSION = 0x40000002, |
525 | HVCPUID_FEATURES = 0x40000003, | |
526 | HVCPUID_ENLIGHTENMENT_INFO = 0x40000004, | |
527 | HVCPUID_IMPLEMENTATION_LIMITS = 0x40000005, | |
6658be6a | 528 | }; |
454f18a9 BP |
529 | |
530 | /* Define the virtual APIC registers */ | |
c786a84e GKH |
531 | #define HV_X64_MSR_EOI (0x40000070) |
532 | #define HV_X64_MSR_ICR (0x40000071) | |
533 | #define HV_X64_MSR_TPR (0x40000072) | |
534 | #define HV_X64_MSR_APIC_ASSIST_PAGE (0x40000073) | |
454f18a9 BP |
535 | |
536 | /* Define version of the synthetic interrupt controller. */ | |
c786a84e | 537 | #define HV_SYNIC_VERSION (1) |
454f18a9 BP |
538 | |
539 | /* Define synthetic interrupt controller model specific registers. */ | |
c786a84e GKH |
540 | #define HV_X64_MSR_SCONTROL (0x40000080) |
541 | #define HV_X64_MSR_SVERSION (0x40000081) | |
542 | #define HV_X64_MSR_SIEFP (0x40000082) | |
543 | #define HV_X64_MSR_SIMP (0x40000083) | |
544 | #define HV_X64_MSR_EOM (0x40000084) | |
545 | #define HV_X64_MSR_SINT0 (0x40000090) | |
546 | #define HV_X64_MSR_SINT1 (0x40000091) | |
547 | #define HV_X64_MSR_SINT2 (0x40000092) | |
548 | #define HV_X64_MSR_SINT3 (0x40000093) | |
549 | #define HV_X64_MSR_SINT4 (0x40000094) | |
550 | #define HV_X64_MSR_SINT5 (0x40000095) | |
551 | #define HV_X64_MSR_SINT6 (0x40000096) | |
552 | #define HV_X64_MSR_SINT7 (0x40000097) | |
553 | #define HV_X64_MSR_SINT8 (0x40000098) | |
554 | #define HV_X64_MSR_SINT9 (0x40000099) | |
555 | #define HV_X64_MSR_SINT10 (0x4000009A) | |
556 | #define HV_X64_MSR_SINT11 (0x4000009B) | |
557 | #define HV_X64_MSR_SINT12 (0x4000009C) | |
558 | #define HV_X64_MSR_SINT13 (0x4000009D) | |
559 | #define HV_X64_MSR_SINT14 (0x4000009E) | |
560 | #define HV_X64_MSR_SINT15 (0x4000009F) | |
454f18a9 BP |
561 | |
562 | /* Define the expected SynIC version. */ | |
c786a84e | 563 | #define HV_SYNIC_VERSION_1 (0x1) |
454f18a9 BP |
564 | |
565 | /* Define synthetic interrupt controller message constants. */ | |
c786a84e GKH |
566 | #define HV_MESSAGE_SIZE (256) |
567 | #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) | |
568 | #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) | |
569 | #define HV_ANY_VP (0xFFFFFFFF) | |
454f18a9 BP |
570 | |
571 | /* Define synthetic interrupt controller flag constants. */ | |
c786a84e GKH |
572 | #define HV_EVENT_FLAGS_COUNT (256 * 8) |
573 | #define HV_EVENT_FLAGS_BYTE_COUNT (256) | |
574 | #define HV_EVENT_FLAGS_DWORD_COUNT (256 / sizeof(u32)) | |
454f18a9 BP |
575 | |
576 | /* Define hypervisor message types. */ | |
eacb1b4d | 577 | enum hv_message_type { |
f6feebe0 | 578 | HVMSG_NONE = 0x00000000, |
c786a84e GKH |
579 | |
580 | /* Memory access messages. */ | |
f6feebe0 HZ |
581 | HVMSG_UNMAPPED_GPA = 0x80000000, |
582 | HVMSG_GPA_INTERCEPT = 0x80000001, | |
c786a84e GKH |
583 | |
584 | /* Timer notification messages. */ | |
f6feebe0 | 585 | HVMSG_TIMER_EXPIRED = 0x80000010, |
c786a84e GKH |
586 | |
587 | /* Error messages. */ | |
f6feebe0 HZ |
588 | HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, |
589 | HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, | |
590 | HVMSG_UNSUPPORTED_FEATURE = 0x80000022, | |
c786a84e GKH |
591 | |
592 | /* Trace buffer complete messages. */ | |
f6feebe0 | 593 | HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, |
c786a84e GKH |
594 | |
595 | /* Platform-specific processor intercept messages. */ | |
f6feebe0 HZ |
596 | HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, |
597 | HVMSG_X64_MSR_INTERCEPT = 0x80010001, | |
598 | HVMSG_X64_CPUID_INTERCEPT = 0x80010002, | |
599 | HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, | |
600 | HVMSG_X64_APIC_EOI = 0x80010004, | |
601 | HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 | |
eacb1b4d | 602 | }; |
565e7dc8 | 603 | |
454f18a9 | 604 | /* Define the number of synthetic interrupt sources. */ |
c786a84e GKH |
605 | #define HV_SYNIC_SINT_COUNT (16) |
606 | #define HV_SYNIC_STIMER_COUNT (4) | |
454f18a9 | 607 | |
454f18a9 | 608 | /* Define invalid partition identifier. */ |
eacb1b4d | 609 | #define HV_PARTITION_ID_INVALID ((u64)0x0) |
454f18a9 BP |
610 | |
611 | /* Define connection identifier type. */ | |
eacb1b4d | 612 | union hv_connection_id { |
f6feebe0 | 613 | u32 asu32; |
c786a84e | 614 | struct { |
f6feebe0 HZ |
615 | u32 id:24; |
616 | u32 reserved:8; | |
c786a84e | 617 | } u; |
eacb1b4d | 618 | }; |
565e7dc8 | 619 | |
454f18a9 | 620 | /* Define port identifier type. */ |
eacb1b4d | 621 | union hv_port_id { |
f6feebe0 | 622 | u32 asu32; |
c786a84e | 623 | struct { |
f6feebe0 HZ |
624 | u32 id:24; |
625 | u32 reserved:8; | |
c786a84e | 626 | } u ; |
eacb1b4d | 627 | }; |
565e7dc8 | 628 | |
454f18a9 | 629 | /* Define port type. */ |
eacb1b4d | 630 | enum hv_port_type { |
f6feebe0 HZ |
631 | HVPORT_MSG = 1, |
632 | HVPORT_EVENT = 2, | |
633 | HVPORT_MONITOR = 3 | |
eacb1b4d | 634 | }; |
565e7dc8 | 635 | |
454f18a9 | 636 | /* Define port information structure. */ |
eacb1b4d | 637 | struct hv_port_info { |
f6feebe0 HZ |
638 | enum hv_port_type port_type; |
639 | u32 padding; | |
c786a84e GKH |
640 | union { |
641 | struct { | |
f6feebe0 HZ |
642 | u32 target_sint; |
643 | u32 target_vp; | |
644 | u64 rsvdz; | |
645 | } message_port_info; | |
c786a84e | 646 | struct { |
f6feebe0 HZ |
647 | u32 target_sint; |
648 | u32 target_vp; | |
649 | u16 base_flag_bumber; | |
650 | u16 flag_count; | |
651 | u32 rsvdz; | |
652 | } event_port_info; | |
c786a84e | 653 | struct { |
f6feebe0 HZ |
654 | u64 monitor_address; |
655 | u64 rsvdz; | |
656 | } monitor_port_info; | |
c786a84e | 657 | }; |
eacb1b4d | 658 | }; |
565e7dc8 | 659 | |
eacb1b4d | 660 | struct hv_connection_info { |
f6feebe0 HZ |
661 | enum hv_port_type port_type; |
662 | u32 padding; | |
c786a84e GKH |
663 | union { |
664 | struct { | |
f6feebe0 HZ |
665 | u64 rsvdz; |
666 | } message_connection_info; | |
c786a84e | 667 | struct { |
f6feebe0 HZ |
668 | u64 rsvdz; |
669 | } event_connection_info; | |
c786a84e | 670 | struct { |
f6feebe0 HZ |
671 | u64 monitor_address; |
672 | } monitor_connection_info; | |
c786a84e | 673 | }; |
eacb1b4d | 674 | }; |
565e7dc8 | 675 | |
454f18a9 | 676 | /* Define synthetic interrupt controller message flags. */ |
eacb1b4d | 677 | union hv_message_flags { |
f6feebe0 | 678 | u8 asu8; |
c786a84e | 679 | struct { |
f6feebe0 HZ |
680 | u8 msg_pending:1; |
681 | u8 reserved:7; | |
c786a84e | 682 | }; |
eacb1b4d | 683 | }; |
565e7dc8 | 684 | |
454f18a9 | 685 | /* Define synthetic interrupt controller message header. */ |
eacb1b4d | 686 | struct hv_message_header { |
f6feebe0 HZ |
687 | enum hv_message_type message_type; |
688 | u8 payload_size; | |
689 | union hv_message_flags message_flags; | |
690 | u8 reserved[2]; | |
c786a84e | 691 | union { |
f6feebe0 HZ |
692 | u64 sender; |
693 | union hv_port_id port; | |
c786a84e | 694 | }; |
eacb1b4d | 695 | }; |
565e7dc8 | 696 | |
454f18a9 | 697 | /* Define timer message payload structure. */ |
eacb1b4d | 698 | struct hv_timer_message_payload { |
f6feebe0 HZ |
699 | u32 timer_index; |
700 | u32 reserved; | |
701 | u64 expiration_time; /* When the timer expired */ | |
702 | u64 delivery_time; /* When the message was delivered */ | |
eacb1b4d | 703 | }; |
565e7dc8 | 704 | |
454f18a9 | 705 | /* Define synthetic interrupt controller message format. */ |
eacb1b4d | 706 | struct hv_message { |
f6feebe0 | 707 | struct hv_message_header header; |
c786a84e | 708 | union { |
f6feebe0 | 709 | u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; |
c786a84e | 710 | } u ; |
eacb1b4d | 711 | }; |
565e7dc8 | 712 | |
454f18a9 | 713 | /* Define the number of message buffers associated with each port. */ |
c786a84e | 714 | #define HV_PORT_MESSAGE_BUFFER_COUNT (16) |
454f18a9 BP |
715 | |
716 | /* Define the synthetic interrupt message page layout. */ | |
eacb1b4d | 717 | struct hv_message_page { |
f6feebe0 | 718 | struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; |
eacb1b4d | 719 | }; |
565e7dc8 | 720 | |
454f18a9 | 721 | /* Define the synthetic interrupt controller event flags format. */ |
eacb1b4d | 722 | union hv_synic_event_flags { |
f6feebe0 HZ |
723 | u8 flags8[HV_EVENT_FLAGS_BYTE_COUNT]; |
724 | u32 flags32[HV_EVENT_FLAGS_DWORD_COUNT]; | |
eacb1b4d | 725 | }; |
565e7dc8 | 726 | |
454f18a9 | 727 | /* Define the synthetic interrupt flags page layout. */ |
eacb1b4d | 728 | struct hv_synic_event_flags_page { |
f6feebe0 | 729 | union hv_synic_event_flags sintevent_flags[HV_SYNIC_SINT_COUNT]; |
eacb1b4d | 730 | }; |
565e7dc8 | 731 | |
454f18a9 | 732 | /* Define SynIC control register. */ |
eacb1b4d | 733 | union hv_synic_scontrol { |
f6feebe0 | 734 | u64 as_uint64; |
c786a84e | 735 | struct { |
f6feebe0 HZ |
736 | u64 enable:1; |
737 | u64 reserved:63; | |
c786a84e | 738 | }; |
eacb1b4d | 739 | }; |
565e7dc8 | 740 | |
454f18a9 | 741 | /* Define synthetic interrupt source. */ |
eacb1b4d | 742 | union hv_synic_sint { |
f6feebe0 | 743 | u64 as_uint64; |
c786a84e | 744 | struct { |
f6feebe0 HZ |
745 | u64 vector:8; |
746 | u64 reserved1:8; | |
747 | u64 masked:1; | |
748 | u64 auto_eoi:1; | |
749 | u64 reserved2:46; | |
c786a84e | 750 | }; |
eacb1b4d | 751 | }; |
565e7dc8 | 752 | |
454f18a9 | 753 | /* Define the format of the SIMP register */ |
eacb1b4d | 754 | union hv_synic_simp { |
f6feebe0 | 755 | u64 as_uint64; |
c786a84e | 756 | struct { |
f6feebe0 HZ |
757 | u64 simp_enabled:1; |
758 | u64 preserved:11; | |
759 | u64 base_simp_gpa:52; | |
c786a84e | 760 | }; |
eacb1b4d | 761 | }; |
454f18a9 BP |
762 | |
763 | /* Define the format of the SIEFP register */ | |
eacb1b4d | 764 | union hv_synic_siefp { |
f6feebe0 | 765 | u64 as_uint64; |
c786a84e | 766 | struct { |
f6feebe0 HZ |
767 | u64 siefp_enabled:1; |
768 | u64 preserved:11; | |
769 | u64 base_siefp_gpa:52; | |
c786a84e | 770 | }; |
eacb1b4d | 771 | }; |
565e7dc8 | 772 | |
454f18a9 | 773 | /* Definitions for the monitored notification facility */ |
eacb1b4d | 774 | union hv_monitor_trigger_group { |
f6feebe0 | 775 | u64 as_uint64; |
c786a84e | 776 | struct { |
f6feebe0 HZ |
777 | u32 pending; |
778 | u32 armed; | |
c786a84e | 779 | }; |
eacb1b4d | 780 | }; |
565e7dc8 | 781 | |
eacb1b4d | 782 | struct hv_monitor_parameter { |
f6feebe0 HZ |
783 | union hv_connection_id connectionid; |
784 | u16 flagnumber; | |
785 | u16 rsvdz; | |
eacb1b4d | 786 | }; |
565e7dc8 | 787 | |
eacb1b4d | 788 | union hv_monitor_trigger_state { |
f6feebe0 | 789 | u32 asu32; |
565e7dc8 | 790 | |
c786a84e | 791 | struct { |
f6feebe0 HZ |
792 | u32 group_enable:4; |
793 | u32 rsvdz:28; | |
c786a84e | 794 | }; |
eacb1b4d | 795 | }; |
565e7dc8 | 796 | |
eacb1b4d | 797 | /* struct hv_monitor_page Layout */ |
454f18a9 BP |
798 | /* ------------------------------------------------------ */ |
799 | /* | 0 | TriggerState (4 bytes) | Rsvd1 (4 bytes) | */ | |
800 | /* | 8 | TriggerGroup[0] | */ | |
801 | /* | 10 | TriggerGroup[1] | */ | |
802 | /* | 18 | TriggerGroup[2] | */ | |
803 | /* | 20 | TriggerGroup[3] | */ | |
804 | /* | 28 | Rsvd2[0] | */ | |
805 | /* | 30 | Rsvd2[1] | */ | |
806 | /* | 38 | Rsvd2[2] | */ | |
807 | /* | 40 | NextCheckTime[0][0] | NextCheckTime[0][1] | */ | |
808 | /* | ... | */ | |
809 | /* | 240 | Latency[0][0..3] | */ | |
810 | /* | 340 | Rsvz3[0] | */ | |
811 | /* | 440 | Parameter[0][0] | */ | |
812 | /* | 448 | Parameter[0][1] | */ | |
813 | /* | ... | */ | |
814 | /* | 840 | Rsvd4[0] | */ | |
815 | /* ------------------------------------------------------ */ | |
eacb1b4d | 816 | struct hv_monitor_page { |
f6feebe0 HZ |
817 | union hv_monitor_trigger_state trigger_state; |
818 | u32 rsvdz1; | |
565e7dc8 | 819 | |
f6feebe0 HZ |
820 | union hv_monitor_trigger_group trigger_group[4]; |
821 | u64 rsvdz2[3]; | |
565e7dc8 | 822 | |
f6feebe0 | 823 | s32 next_checktime[4][32]; |
565e7dc8 | 824 | |
f6feebe0 HZ |
825 | u16 latency[4][32]; |
826 | u64 rsvdz3[32]; | |
565e7dc8 | 827 | |
f6feebe0 | 828 | struct hv_monitor_parameter parameter[4][32]; |
565e7dc8 | 829 | |
f6feebe0 | 830 | u8 rsvdz4[1984]; |
eacb1b4d | 831 | }; |
c786a84e | 832 | |
6658be6a GKH |
833 | /* Declare the various hypercall operations. */ |
834 | enum hv_call_code { | |
f6feebe0 HZ |
835 | HVCALL_POST_MESSAGE = 0x005c, |
836 | HVCALL_SIGNAL_EVENT = 0x005d, | |
6658be6a GKH |
837 | }; |
838 | ||
d44890c8 | 839 | /* Definition of the hv_post_message hypercall input structure. */ |
6658be6a | 840 | struct hv_input_post_message { |
f6feebe0 HZ |
841 | union hv_connection_id connectionid; |
842 | u32 reserved; | |
843 | enum hv_message_type message_type; | |
844 | u32 payload_size; | |
845 | u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; | |
6658be6a GKH |
846 | }; |
847 | ||
d44890c8 | 848 | /* Definition of the hv_signal_event hypercall input structure. */ |
6658be6a | 849 | struct hv_input_signal_event { |
f6feebe0 HZ |
850 | union hv_connection_id connectionid; |
851 | u16 flag_number; | |
852 | u16 rsvdz; | |
6658be6a GKH |
853 | }; |
854 | ||
855 | /* | |
856 | * Versioning definitions used for guests reporting themselves to the | |
857 | * hypervisor, and visa versa. | |
858 | */ | |
859 | ||
860 | /* Version info reported by guest OS's */ | |
861 | enum hv_guest_os_vendor { | |
f6feebe0 | 862 | HVGUESTOS_VENDOR_MICROSOFT = 0x0001 |
6658be6a GKH |
863 | }; |
864 | ||
865 | enum hv_guest_os_microsoft_ids { | |
f6feebe0 HZ |
866 | HVGUESTOS_MICROSOFT_UNDEFINED = 0x00, |
867 | HVGUESTOS_MICROSOFT_MSDOS = 0x01, | |
868 | HVGUESTOS_MICROSOFT_WINDOWS3X = 0x02, | |
869 | HVGUESTOS_MICROSOFT_WINDOWS9X = 0x03, | |
870 | HVGUESTOS_MICROSOFT_WINDOWSNT = 0x04, | |
871 | HVGUESTOS_MICROSOFT_WINDOWSCE = 0x05 | |
6658be6a GKH |
872 | }; |
873 | ||
874 | /* | |
875 | * Declare the MSR used to identify the guest OS. | |
876 | */ | |
877 | #define HV_X64_MSR_GUEST_OS_ID 0x40000000 | |
878 | ||
879 | union hv_x64_msr_guest_os_id_contents { | |
f6feebe0 | 880 | u64 as_uint64; |
6658be6a | 881 | struct { |
f6feebe0 HZ |
882 | u64 build_number:16; |
883 | u64 service_version:8; /* Service Pack, etc. */ | |
884 | u64 minor_version:8; | |
885 | u64 major_version:8; | |
886 | u64 os_id:8; /* enum hv_guest_os_microsoft_ids (if Vendor=MS) */ | |
887 | u64 vendor_id:16; /* enum hv_guest_os_vendor */ | |
6658be6a GKH |
888 | }; |
889 | }; | |
890 | ||
891 | /* | |
892 | * Declare the MSR used to setup pages used to communicate with the hypervisor. | |
893 | */ | |
894 | #define HV_X64_MSR_HYPERCALL 0x40000001 | |
895 | ||
896 | union hv_x64_msr_hypercall_contents { | |
f6feebe0 | 897 | u64 as_uint64; |
6658be6a | 898 | struct { |
f6feebe0 HZ |
899 | u64 enable:1; |
900 | u64 reserved:11; | |
901 | u64 guest_physical_address:52; | |
6658be6a GKH |
902 | }; |
903 | }; | |
904 | ||
c786a84e | 905 | #endif |