[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / iio / accel / lis3l02dq_ring.c

#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/mutex.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/export.h>

#include <linux/iio/iio.h>
#include "../ring_sw.h"
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include "lis3l02dq.h"

/**
 * combine_8_to_16() utility function to munge to u8s into u16
 **/
static inline u16 combine_8_to_16(u8 lower, u8 upper)
{
	u16 _lower = lower;
	u16 _upper = upper;
	return _lower | (_upper << 8);
}

/**
 * lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
 **/
irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
{
	struct iio_dev *indio_dev = private;
	struct lis3l02dq_state *st = iio_priv(indio_dev);

	if (st->trigger_on) {
		iio_trigger_poll(st->trig, iio_get_time_ns());
		return IRQ_HANDLED;
	} else
		return IRQ_WAKE_THREAD;
}

static const u8 read_all_tx_array[] = {
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
};

/**
 * lis3l02dq_read_all() Reads all channels currently selected
 * @st:		device specific state
 * @rx_array:	(dma capable) receive array, must be at least
 *		4*number of channels
 **/
static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
{
	struct lis3l02dq_state *st = iio_priv(indio_dev);
	struct spi_transfer *xfers;
	struct spi_message msg;
	int ret, i, j = 0;

	xfers = kcalloc(bitmap_weight(indio_dev->active_scan_mask,
				      indio_dev->masklength) * 2,
			sizeof(*xfers), GFP_KERNEL);
	if (!xfers)
		return -ENOMEM;

	mutex_lock(&st->buf_lock);

	for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
		if (test_bit(i, indio_dev->active_scan_mask)) {
			/* lower byte */
			xfers[j].tx_buf = st->tx + 2*j;
			st->tx[2*j] = read_all_tx_array[i*4];
			st->tx[2*j + 1] = 0;
			if (rx_array)
				xfers[j].rx_buf = rx_array + j*2;
			xfers[j].bits_per_word = 8;
			xfers[j].len = 2;
			xfers[j].cs_change = 1;
			j++;

			/* upper byte */
			xfers[j].tx_buf = st->tx + 2*j;
			st->tx[2*j] = read_all_tx_array[i*4 + 2];
			st->tx[2*j + 1] = 0;
			if (rx_array)
				xfers[j].rx_buf = rx_array + j*2;
			xfers[j].bits_per_word = 8;
			xfers[j].len = 2;
			xfers[j].cs_change = 1;
			j++;
		}

	/* After these are transmitted, the rx_buff should have
	 * values in alternate bytes
	 */
	spi_message_init(&msg);
	for (j = 0; j < bitmap_weight(indio_dev->active_scan_mask,
				      indio_dev->masklength) * 2; j++)
		spi_message_add_tail(&xfers[j], &msg);

	ret = spi_sync(st->us, &msg);
	mutex_unlock(&st->buf_lock);
	kfree(xfers);

	return ret;
}

static int lis3l02dq_get_buffer_element(struct iio_dev *indio_dev,
				u8 *buf)
{
	int ret, i;
	u8 *rx_array ;
	s16 *data = (s16 *)buf;
	int scan_count = bitmap_weight(indio_dev->active_scan_mask,
				       indio_dev->masklength);

	rx_array = kzalloc(4 * scan_count, GFP_KERNEL);
	if (rx_array == NULL)
		return -ENOMEM;
	ret = lis3l02dq_read_all(indio_dev, rx_array);
	if (ret < 0)
		return ret;
	for (i = 0; i < scan_count; i++)
		data[i] = combine_8_to_16(rx_array[i*4+1],
					rx_array[i*4+3]);
	kfree(rx_array);

	return i*sizeof(data[0]);
}

static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct iio_buffer *buffer = indio_dev->buffer;
	int len = 0;
	char *data;

	data = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
	if (data == NULL) {
		dev_err(indio_dev->dev.parent,
			"memory alloc failed in buffer bh");
		goto done;
	}

	if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
		len = lis3l02dq_get_buffer_element(indio_dev, data);

	  /* Guaranteed to be aligned with 8 byte boundary */
	if (indio_dev->scan_timestamp)
		*(s64 *)((u8 *)data + ALIGN(len, sizeof(s64)))
			= pf->timestamp;
	buffer->access->store_to(buffer, (u8 *)data, pf->timestamp);

	kfree(data);
done:
	iio_trigger_notify_done(indio_dev->trig);
	return IRQ_HANDLED;
}

/* Caller responsible for locking as necessary. */
static int
__lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
{
	int ret;
	u8 valold;
	bool currentlyset;
	struct lis3l02dq_state *st = iio_priv(indio_dev);

/* Get the current event mask register */
	ret = lis3l02dq_spi_read_reg_8(indio_dev,
				       LIS3L02DQ_REG_CTRL_2_ADDR,
				       &valold);
	if (ret)
		goto error_ret;
/* Find out if data ready is already on */
	currentlyset
		= valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;

/* Disable requested */
	if (!state && currentlyset) {
		/* disable the data ready signal */
		valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;

		/* The double write is to overcome a hardware bug?*/
		ret = lis3l02dq_spi_write_reg_8(indio_dev,
						LIS3L02DQ_REG_CTRL_2_ADDR,
						valold);
		if (ret)
			goto error_ret;
		ret = lis3l02dq_spi_write_reg_8(indio_dev,
						LIS3L02DQ_REG_CTRL_2_ADDR,
						valold);
		if (ret)
			goto error_ret;
		st->trigger_on = false;
/* Enable requested */
	} else if (state && !currentlyset) {
		/* if not set, enable requested */
		/* first disable all events */
		ret = lis3l02dq_disable_all_events(indio_dev);
		if (ret < 0)
			goto error_ret;

		valold = ret |
			LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;

		st->trigger_on = true;
		ret = lis3l02dq_spi_write_reg_8(indio_dev,
						LIS3L02DQ_REG_CTRL_2_ADDR,
						valold);
		if (ret)
			goto error_ret;
	}

	return 0;
error_ret:
	return ret;
}

/**
 * lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
 *
 * If disabling the interrupt also does a final read to ensure it is clear.
 * This is only important in some cases where the scan enable elements are
 * switched before the buffer is reenabled.
 **/
static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
						bool state)
{
	struct iio_dev *indio_dev = trig->private_data;
	int ret = 0;
	u8 t;

	__lis3l02dq_write_data_ready_config(indio_dev, state);
	if (state == false) {
		/*
		 * A possible quirk with the handler is currently worked around
		 *  by ensuring outstanding read events are cleared.
		 */
		ret = lis3l02dq_read_all(indio_dev, NULL);
	}
	lis3l02dq_spi_read_reg_8(indio_dev,
				 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
				 &t);
	return ret;
}

/**
 * lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
 * @trig:	the datardy trigger
 */
static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
{
	struct iio_dev *indio_dev = trig->private_data;
	struct lis3l02dq_state *st = iio_priv(indio_dev);
	int i;

	/* If gpio still high (or high again) */
	/* In theory possible we will need to do this several times */
	for (i = 0; i < 5; i++)
		if (gpio_get_value(irq_to_gpio(st->us->irq)))
			lis3l02dq_read_all(indio_dev, NULL);
		else
			break;
	if (i == 5)
		printk(KERN_INFO
		       "Failed to clear the interrupt for lis3l02dq\n");

	/* irq reenabled so success! */
	return 0;
}

static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
	.owner = THIS_MODULE,
	.set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
	.try_reenable = &lis3l02dq_trig_try_reen,
};

int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
{
	int ret;
	struct lis3l02dq_state *st = iio_priv(indio_dev);

	st->trig = iio_trigger_alloc("lis3l02dq-dev%d", indio_dev->id);
	if (!st->trig) {
		ret = -ENOMEM;
		goto error_ret;
	}

	st->trig->dev.parent = &st->us->dev;
	st->trig->ops = &lis3l02dq_trigger_ops;
	st->trig->private_data = indio_dev;
	ret = iio_trigger_register(st->trig);
	if (ret)
		goto error_free_trig;

	return 0;

error_free_trig:
	iio_trigger_free(st->trig);
error_ret:
	return ret;
}

void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
{
	struct lis3l02dq_state *st = iio_priv(indio_dev);

	iio_trigger_unregister(st->trig);
	iio_trigger_free(st->trig);
}

void lis3l02dq_unconfigure_buffer(struct iio_dev *indio_dev)
{
	iio_dealloc_pollfunc(indio_dev->pollfunc);
	lis3l02dq_free_buf(indio_dev->buffer);
}

static int lis3l02dq_buffer_postenable(struct iio_dev *indio_dev)
{
	/* Disable unwanted channels otherwise the interrupt will not clear */
	u8 t;
	int ret;
	bool oneenabled = false;

	ret = lis3l02dq_spi_read_reg_8(indio_dev,
				       LIS3L02DQ_REG_CTRL_1_ADDR,
				       &t);
	if (ret)
		goto error_ret;

	if (test_bit(0, indio_dev->active_scan_mask)) {
		t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
		oneenabled = true;
	} else
		t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
	if (test_bit(1, indio_dev->active_scan_mask)) {
		t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
		oneenabled = true;
	} else
		t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
	if (test_bit(2, indio_dev->active_scan_mask)) {
		t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
		oneenabled = true;
	} else
		t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;

	if (!oneenabled) /* what happens in this case is unknown */
		return -EINVAL;
	ret = lis3l02dq_spi_write_reg_8(indio_dev,
					LIS3L02DQ_REG_CTRL_1_ADDR,
					t);
	if (ret)
		goto error_ret;

	return iio_triggered_buffer_postenable(indio_dev);
error_ret:
	return ret;
}

/* Turn all channels on again */
static int lis3l02dq_buffer_predisable(struct iio_dev *indio_dev)
{
	u8 t;
	int ret;

	ret = iio_triggered_buffer_predisable(indio_dev);
	if (ret)
		goto error_ret;

	ret = lis3l02dq_spi_read_reg_8(indio_dev,
				       LIS3L02DQ_REG_CTRL_1_ADDR,
				       &t);
	if (ret)
		goto error_ret;
	t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
		LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
		LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;

	ret = lis3l02dq_spi_write_reg_8(indio_dev,
					LIS3L02DQ_REG_CTRL_1_ADDR,
					t);

error_ret:
	return ret;
}

static const struct iio_buffer_setup_ops lis3l02dq_buffer_setup_ops = {
	.preenable = &iio_sw_buffer_preenable,
	.postenable = &lis3l02dq_buffer_postenable,
	.predisable = &lis3l02dq_buffer_predisable,
};

int lis3l02dq_configure_buffer(struct iio_dev *indio_dev)
{
	int ret;
	struct iio_buffer *buffer;

	buffer = lis3l02dq_alloc_buf(indio_dev);
	if (!buffer)
		return -ENOMEM;

	indio_dev->buffer = buffer;

	buffer->scan_timestamp = true;
	indio_dev->setup_ops = &lis3l02dq_buffer_setup_ops;

	/* Functions are NULL as we set handler below */
	indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
						 &lis3l02dq_trigger_handler,
						 0,
						 indio_dev,
						 "lis3l02dq_consumer%d",
						 indio_dev->id);

	if (indio_dev->pollfunc == NULL) {
		ret = -ENOMEM;
		goto error_iio_sw_rb_free;
	}

	indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
	return 0;

error_iio_sw_rb_free:
	lis3l02dq_free_buf(indio_dev->buffer);
	return ret;
}
Commit	Line	Data
14cd9a73	1	#include <linux/interrupt.h>
14cd9a73	2	#include <linux/gpio.h>
14cd9a73	3	#include <linux/mutex.h>
14cd9a73 JC	4	#include <linux/kernel.h>
14cd9a73 JC	5	#include <linux/spi/spi.h>
5a0e3ad6	6	#include <linux/slab.h>
8e336a72	7	#include <linux/export.h>
14cd9a73	8
06458e27	9	#include <linux/iio/iio.h>
14cd9a73	10	#include "../ring_sw.h"
06458e27 JC	11	#include <linux/iio/kfifo_buf.h>
	12	#include <linux/iio/trigger.h>
	13	#include <linux/iio/trigger_consumer.h>
14cd9a73 JC	14	#include "lis3l02dq.h"
	15
	16	/**
	17	* combine_8_to_16() utility function to munge to u8s into u16
	18	**/
	19	static inline u16 combine_8_to_16(u8 lower, u8 upper)
	20	{
	21	u16 _lower = lower;
	22	u16 _upper = upper;
	23	return _lower \| (_upper << 8);
	24	}
	25
d731aea0 JC	26	/**
	27	* lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
	28	**/
	29	irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
	30	{
	31	struct iio_dev *indio_dev = private;
7b2fdd19	32	struct lis3l02dq_state *st = iio_priv(indio_dev);
d731aea0 JC	33
	34	if (st->trigger_on) {
	35	iio_trigger_poll(st->trig, iio_get_time_ns());
	36	return IRQ_HANDLED;
	37	} else
	38	return IRQ_WAKE_THREAD;
	39	}
	40
26de7208	41	static const u8 read_all_tx_array[] = {
14cd9a73 JC	42	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
	43	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
	44	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
	45	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
	46	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
	47	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
	48	};
	49
	50	/**
	51	* lis3l02dq_read_all() Reads all channels currently selected
	52	* @st: device specific state
25985edc	53	* @rx_array: (dma capable) receive array, must be at least
14cd9a73 JC	54	* 4*number of channels
14cd9a73 JC	55	**/
7b2fdd19	56	static int lis3l02dq_read_all(struct iio_dev indio_dev, u8 rx_array)
14cd9a73	57	{
7b2fdd19	58	struct lis3l02dq_state *st = iio_priv(indio_dev);
14cd9a73 JC	59	struct spi_transfer *xfers;
	60	struct spi_message msg;
	61	int ret, i, j = 0;
	62
550268ca JC	63	xfers = kcalloc(bitmap_weight(indio_dev->active_scan_mask,
	64	indio_dev->masklength) * 2,
	65	sizeof(*xfers), GFP_KERNEL);
14cd9a73 JC	66	if (!xfers)
	67	return -ENOMEM;
	68
	69	mutex_lock(&st->buf_lock);
	70
f3736416	71	for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
550268ca	72	if (test_bit(i, indio_dev->active_scan_mask)) {
14cd9a73 JC	73	/* lower byte */
	74	xfers[j].tx_buf = st->tx + 2*j;
	75	st->tx[2j] = read_all_tx_array[i4];
	76	st->tx[2*j + 1] = 0;
	77	if (rx_array)
	78	xfers[j].rx_buf = rx_array + j*2;
	79	xfers[j].bits_per_word = 8;
	80	xfers[j].len = 2;
	81	xfers[j].cs_change = 1;
	82	j++;
	83
	84	/* upper byte */
	85	xfers[j].tx_buf = st->tx + 2*j;
	86	st->tx[2j] = read_all_tx_array[i4 + 2];
	87	st->tx[2*j + 1] = 0;
	88	if (rx_array)
	89	xfers[j].rx_buf = rx_array + j*2;
	90	xfers[j].bits_per_word = 8;
	91	xfers[j].len = 2;
	92	xfers[j].cs_change = 1;
	93	j++;
	94	}
f3736416	95
14cd9a73 JC	96	/* After these are transmitted, the rx_buff should have
	97	* values in alternate bytes
	98	*/
	99	spi_message_init(&msg);
550268ca JC	100	for (j = 0; j < bitmap_weight(indio_dev->active_scan_mask,
550268ca JC	101	indio_dev->masklength) * 2; j++)
14cd9a73 JC	102	spi_message_add_tail(&xfers[j], &msg);
	103
	104	ret = spi_sync(st->us, &msg);
	105	mutex_unlock(&st->buf_lock);
	106	kfree(xfers);
	107
	108	return ret;
	109	}
	110
6ddbb08a	111	static int lis3l02dq_get_buffer_element(struct iio_dev *indio_dev,
73bce12e JC	112	u8 *buf)
	113	{
	114	int ret, i;
	115	u8 *rx_array ;
	116	s16 data = (s16 )buf;
550268ca JC	117	int scan_count = bitmap_weight(indio_dev->active_scan_mask,
550268ca JC	118	indio_dev->masklength);
14cd9a73	119
550268ca	120	rx_array = kzalloc(4 * scan_count, GFP_KERNEL);
73bce12e JC	121	if (rx_array == NULL)
73bce12e JC	122	return -ENOMEM;
7b2fdd19	123	ret = lis3l02dq_read_all(indio_dev, rx_array);
73bce12e JC	124	if (ret < 0)
73bce12e JC	125	return ret;
550268ca	126	for (i = 0; i < scan_count; i++)
73bce12e JC	127	data[i] = combine_8_to_16(rx_array[i*4+1],
73bce12e JC	128	rx_array[i*4+3]);
14cd9a73	129	kfree(rx_array);
14cd9a73	130
73bce12e	131	return i*sizeof(data[0]);
14cd9a73	132	}
14cd9a73	133
7b2fdd19 JC	134	static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
	135	{
	136	struct iio_poll_func *pf = p;
e65bc6ac	137	struct iio_dev *indio_dev = pf->indio_dev;
6ddbb08a	138	struct iio_buffer *buffer = indio_dev->buffer;
7b2fdd19	139	int len = 0;
420fe2e9	140	char *data;
7b2fdd19	141
420fe2e9	142	data = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
7b2fdd19 JC	143	if (data == NULL) {
7b2fdd19 JC	144	dev_err(indio_dev->dev.parent,
6ddbb08a	145	"memory alloc failed in buffer bh");
0b30246e	146	goto done;
7b2fdd19 JC	147	}
7b2fdd19 JC	148
550268ca	149	if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
6ddbb08a	150	len = lis3l02dq_get_buffer_element(indio_dev, data);
7b2fdd19 JC	151
7b2fdd19 JC	152	/* Guaranteed to be aligned with 8 byte boundary */
fd6487f8	153	if (indio_dev->scan_timestamp)
dcbc3c41	154	(s64 )((u8 *)data + ALIGN(len, sizeof(s64)))
7b2fdd19	155	= pf->timestamp;
6ddbb08a	156	buffer->access->store_to(buffer, (u8 *)data, pf->timestamp);
7b2fdd19	157
7b2fdd19	158	kfree(data);
0b30246e LPC	159	done:
0b30246e LPC	160	iio_trigger_notify_done(indio_dev->trig);
7b2fdd19 JC	161	return IRQ_HANDLED;
	162	}
	163
14cd9a73	164	/* Caller responsible for locking as necessary. */
26de7208	165	static int
8dc5afd8	166	__lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
14cd9a73 JC	167	{
	168	int ret;
	169	u8 valold;
	170	bool currentlyset;
7b2fdd19	171	struct lis3l02dq_state *st = iio_priv(indio_dev);
14cd9a73 JC	172
14cd9a73 JC	173	/* Get the current event mask register */
1b076b52	174	ret = lis3l02dq_spi_read_reg_8(indio_dev,
14cd9a73 JC	175	LIS3L02DQ_REG_CTRL_2_ADDR,
	176	&valold);
	177	if (ret)
	178	goto error_ret;
	179	/* Find out if data ready is already on */
	180	currentlyset
	181	= valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
	182
	183	/* Disable requested */
	184	if (!state && currentlyset) {
1e3345bc	185	/* disable the data ready signal */
14cd9a73	186	valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
1e3345bc	187
14cd9a73	188	/* The double write is to overcome a hardware bug?*/
1b076b52	189	ret = lis3l02dq_spi_write_reg_8(indio_dev,
14cd9a73	190	LIS3L02DQ_REG_CTRL_2_ADDR,
7df86302	191	valold);
14cd9a73 JC	192	if (ret)
14cd9a73 JC	193	goto error_ret;
1b076b52	194	ret = lis3l02dq_spi_write_reg_8(indio_dev,
14cd9a73	195	LIS3L02DQ_REG_CTRL_2_ADDR,
7df86302	196	valold);
14cd9a73 JC	197	if (ret)
14cd9a73 JC	198	goto error_ret;
d731aea0	199	st->trigger_on = false;
14cd9a73 JC	200	/* Enable requested */
	201	} else if (state && !currentlyset) {
	202	/* if not set, enable requested */
1e3345bc JC	203	/* first disable all events */
	204	ret = lis3l02dq_disable_all_events(indio_dev);
	205	if (ret < 0)
	206	goto error_ret;
	207
	208	valold = ret \|
	209	LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
1e3345bc	210
d731aea0	211	st->trigger_on = true;
1b076b52	212	ret = lis3l02dq_spi_write_reg_8(indio_dev,
14cd9a73	213	LIS3L02DQ_REG_CTRL_2_ADDR,
7df86302	214	valold);
d731aea0	215	if (ret)
14cd9a73 JC	216	goto error_ret;
	217	}
	218
	219	return 0;
	220	error_ret:
	221	return ret;
	222	}
	223
	224	/**
	225	* lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
	226	*
	227	* If disabling the interrupt also does a final read to ensure it is clear.
	228	* This is only important in some cases where the scan enable elements are
6ddbb08a	229	* switched before the buffer is reenabled.
14cd9a73 JC	230	**/
	231	static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
	232	bool state)
	233	{
7b2fdd19	234	struct iio_dev *indio_dev = trig->private_data;
14cd9a73 JC	235	int ret = 0;
14cd9a73 JC	236	u8 t;
1e3345bc	237
8dc5afd8	238	__lis3l02dq_write_data_ready_config(indio_dev, state);
14cd9a73	239	if (state == false) {
d1dbf011	240	/*
4abf6f8b	241	* A possible quirk with the handler is currently worked around
d1dbf011 JC	242	* by ensuring outstanding read events are cleared.
d1dbf011 JC	243	*/
7b2fdd19	244	ret = lis3l02dq_read_all(indio_dev, NULL);
14cd9a73	245	}
7b2fdd19	246	lis3l02dq_spi_read_reg_8(indio_dev,
14cd9a73 JC	247	LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
	248	&t);
	249	return ret;
	250	}
9dbfb6f1	251
14cd9a73 JC	252	/**
	253	* lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
	254	* @trig: the datardy trigger
d1dbf011	255	*/
14cd9a73 JC	256	static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
14cd9a73 JC	257	{
7b2fdd19 JC	258	struct iio_dev *indio_dev = trig->private_data;
7b2fdd19 JC	259	struct lis3l02dq_state *st = iio_priv(indio_dev);
d1dbf011 JC	260	int i;
d1dbf011 JC	261
14cd9a73	262	/* If gpio still high (or high again) */
d1dbf011 JC	263	/* In theory possible we will need to do this several times */
	264	for (i = 0; i < 5; i++)
	265	if (gpio_get_value(irq_to_gpio(st->us->irq)))
7b2fdd19	266	lis3l02dq_read_all(indio_dev, NULL);
d1dbf011 JC	267	else
	268	break;
	269	if (i == 5)
	270	printk(KERN_INFO
	271	"Failed to clear the interrupt for lis3l02dq\n");
	272
14cd9a73 JC	273	/* irq reenabled so success! */
	274	return 0;
	275	}
	276
d29f73db JC	277	static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
	278	.owner = THIS_MODULE,
	279	.set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
	280	.try_reenable = &lis3l02dq_trig_try_reen,
	281	};
	282
14cd9a73 JC	283	int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
	284	{
	285	int ret;
7b2fdd19	286	struct lis3l02dq_state *st = iio_priv(indio_dev);
14cd9a73	287
7cbb7537	288	st->trig = iio_trigger_alloc("lis3l02dq-dev%d", indio_dev->id);
d1dbf011 JC	289	if (!st->trig) {
d1dbf011 JC	290	ret = -ENOMEM;
59c85e82	291	goto error_ret;
14cd9a73	292	}
3c9bbf58	293
1b076b52	294	st->trig->dev.parent = &st->us->dev;
d29f73db	295	st->trig->ops = &lis3l02dq_trigger_ops;
7b2fdd19	296	st->trig->private_data = indio_dev;
1b076b52	297	ret = iio_trigger_register(st->trig);
14cd9a73	298	if (ret)
d1dbf011	299	goto error_free_trig;
14cd9a73 JC	300
	301	return 0;
	302
14cd9a73	303	error_free_trig:
7cbb7537	304	iio_trigger_free(st->trig);
d1dbf011	305	error_ret:
14cd9a73 JC	306	return ret;
	307	}
	308
	309	void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
	310	{
7b2fdd19	311	struct lis3l02dq_state *st = iio_priv(indio_dev);
14cd9a73	312
1b076b52	313	iio_trigger_unregister(st->trig);
7cbb7537	314	iio_trigger_free(st->trig);
14cd9a73 JC	315	}
14cd9a73 JC	316
6ddbb08a	317	void lis3l02dq_unconfigure_buffer(struct iio_dev *indio_dev)
14cd9a73	318	{
0ed731d2	319	iio_dealloc_pollfunc(indio_dev->pollfunc);
14555b14	320	lis3l02dq_free_buf(indio_dev->buffer);
14cd9a73 JC	321	}
14cd9a73 JC	322
6ddbb08a	323	static int lis3l02dq_buffer_postenable(struct iio_dev *indio_dev)
f3736416 JC	324	{
	325	/* Disable unwanted channels otherwise the interrupt will not clear */
	326	u8 t;
	327	int ret;
	328	bool oneenabled = false;
	329
1b076b52	330	ret = lis3l02dq_spi_read_reg_8(indio_dev,
f3736416 JC	331	LIS3L02DQ_REG_CTRL_1_ADDR,
	332	&t);
	333	if (ret)
	334	goto error_ret;
	335
550268ca	336	if (test_bit(0, indio_dev->active_scan_mask)) {
f3736416 JC	337	t \|= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
	338	oneenabled = true;
	339	} else
	340	t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
550268ca	341	if (test_bit(1, indio_dev->active_scan_mask)) {
f3736416 JC	342	t \|= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
	343	oneenabled = true;
	344	} else
	345	t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
550268ca	346	if (test_bit(2, indio_dev->active_scan_mask)) {
f3736416 JC	347	t \|= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
	348	oneenabled = true;
	349	} else
	350	t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
	351
	352	if (!oneenabled) /* what happens in this case is unknown */
	353	return -EINVAL;
1b076b52	354	ret = lis3l02dq_spi_write_reg_8(indio_dev,
f3736416	355	LIS3L02DQ_REG_CTRL_1_ADDR,
7df86302	356	t);
f3736416 JC	357	if (ret)
	358	goto error_ret;
	359
3b99fb76	360	return iio_triggered_buffer_postenable(indio_dev);
f3736416 JC	361	error_ret:
	362	return ret;
	363	}
	364
	365	/* Turn all channels on again */
6ddbb08a	366	static int lis3l02dq_buffer_predisable(struct iio_dev *indio_dev)
f3736416 JC	367	{
	368	u8 t;
	369	int ret;
	370
3b99fb76	371	ret = iio_triggered_buffer_predisable(indio_dev);
f3736416 JC	372	if (ret)
	373	goto error_ret;
	374
1b076b52	375	ret = lis3l02dq_spi_read_reg_8(indio_dev,
f3736416 JC	376	LIS3L02DQ_REG_CTRL_1_ADDR,
	377	&t);
	378	if (ret)
	379	goto error_ret;
	380	t \|= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE \|
	381	LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE \|
	382	LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
	383
1b076b52	384	ret = lis3l02dq_spi_write_reg_8(indio_dev,
f3736416	385	LIS3L02DQ_REG_CTRL_1_ADDR,
7df86302	386	t);
f3736416 JC	387
	388	error_ret:
	389	return ret;
	390	}
	391
6ddbb08a	392	static const struct iio_buffer_setup_ops lis3l02dq_buffer_setup_ops = {
14555b14	393	.preenable = &iio_sw_buffer_preenable,
6ddbb08a JC	394	.postenable = &lis3l02dq_buffer_postenable,
6ddbb08a JC	395	.predisable = &lis3l02dq_buffer_predisable,
5565a450	396	};
f3736416	397
6ddbb08a	398	int lis3l02dq_configure_buffer(struct iio_dev *indio_dev)
14cd9a73	399	{
73bce12e	400	int ret;
6ddbb08a	401	struct iio_buffer *buffer;
d1dbf011	402
6ddbb08a JC	403	buffer = lis3l02dq_alloc_buf(indio_dev);
6ddbb08a JC	404	if (!buffer)
73bce12e JC	405	return -ENOMEM;
73bce12e JC	406
6ddbb08a	407	indio_dev->buffer = buffer;
f3736416	408
6ddbb08a	409	buffer->scan_timestamp = true;
1612244f	410	indio_dev->setup_ops = &lis3l02dq_buffer_setup_ops;
14cd9a73	411
d1dbf011	412	/* Functions are NULL as we set handler below */
0ed731d2 JC	413	indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
	414	&lis3l02dq_trigger_handler,
	415	0,
	416	indio_dev,
	417	"lis3l02dq_consumer%d",
	418	indio_dev->id);
d1dbf011 JC	419
	420	if (indio_dev->pollfunc == NULL) {
	421	ret = -ENOMEM;
859171ca	422	goto error_iio_sw_rb_free;
d1dbf011	423	}
d1dbf011	424
ec3afa40	425	indio_dev->modes \|= INDIO_BUFFER_TRIGGERED;
14cd9a73 JC	426	return 0;
	427
	428	error_iio_sw_rb_free:
14555b14	429	lis3l02dq_free_buf(indio_dev->buffer);
14cd9a73 JC	430	return ret;
14cd9a73 JC	431	}