[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / iio / accel / lis3l02dq_ring.c

#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/mutex.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/export.h>

#include <linux/iio/iio.h>
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include "lis3l02dq.h"

/**
 * combine_8_to_16() utility function to munge two u8s into u16
 **/
static inline u16 combine_8_to_16(u8 lower, u8 upper)
{
	u16 _lower = lower;
	u16 _upper = upper;
	return _lower | (_upper << 8);
}

/**
 * lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
 **/
irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
{
	struct iio_dev *indio_dev = private;
	struct lis3l02dq_state *st = iio_priv(indio_dev);

	if (st->trigger_on) {
		iio_trigger_poll(st->trig, iio_get_time_ns());
		return IRQ_HANDLED;
	} else
		return IRQ_WAKE_THREAD;
}

static const u8 read_all_tx_array[] = {
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
};

/**
 * lis3l02dq_read_all() Reads all channels currently selected
 * @indio_dev:	IIO device state
 * @rx_array:	(dma capable) receive array, must be at least
 *		4*number of channels
 **/
static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
{
	struct lis3l02dq_state *st = iio_priv(indio_dev);
	struct spi_transfer *xfers;
	struct spi_message msg;
	int ret, i, j = 0;

	xfers = kcalloc(bitmap_weight(indio_dev->active_scan_mask,
				      indio_dev->masklength) * 2,
			sizeof(*xfers), GFP_KERNEL);
	if (!xfers)
		return -ENOMEM;

	mutex_lock(&st->buf_lock);

	for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
		if (test_bit(i, indio_dev->active_scan_mask)) {
			/* lower byte */
			xfers[j].tx_buf = st->tx + 2*j;
			st->tx[2*j] = read_all_tx_array[i*4];
			st->tx[2*j + 1] = 0;
			if (rx_array)
				xfers[j].rx_buf = rx_array + j*2;
			xfers[j].bits_per_word = 8;
			xfers[j].len = 2;
			xfers[j].cs_change = 1;
			j++;

			/* upper byte */
			xfers[j].tx_buf = st->tx + 2*j;
			st->tx[2*j] = read_all_tx_array[i*4 + 2];
			st->tx[2*j + 1] = 0;
			if (rx_array)
				xfers[j].rx_buf = rx_array + j*2;
			xfers[j].bits_per_word = 8;
			xfers[j].len = 2;
			xfers[j].cs_change = 1;
			j++;
		}

	/* After these are transmitted, the rx_buff should have
	 * values in alternate bytes
	 */
	spi_message_init(&msg);
	for (j = 0; j < bitmap_weight(indio_dev->active_scan_mask,
				      indio_dev->masklength) * 2; j++)
		spi_message_add_tail(&xfers[j], &msg);

	ret = spi_sync(st->us, &msg);
	mutex_unlock(&st->buf_lock);
	kfree(xfers);

	return ret;
}

static int lis3l02dq_get_buffer_element(struct iio_dev *indio_dev,
				u8 *buf)
{
	int ret, i;
	u8 *rx_array;
	s16 *data = (s16 *)buf;
	int scan_count = bitmap_weight(indio_dev->active_scan_mask,
				       indio_dev->masklength);

	rx_array = kzalloc(4 * scan_count, GFP_KERNEL);
	if (rx_array == NULL)
		return -ENOMEM;
	ret = lis3l02dq_read_all(indio_dev, rx_array);
	if (ret < 0) {
		kfree(rx_array);
		return ret;
	}
	for (i = 0; i < scan_count; i++)
		data[i] = combine_8_to_16(rx_array[i*4+1],
					rx_array[i*4+3]);
	kfree(rx_array);

	return i*sizeof(data[0]);
}

static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	int len = 0;
	char *data;

	data = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
	if (data == NULL)
		goto done;

	if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
		len = lis3l02dq_get_buffer_element(indio_dev, data);

	iio_push_to_buffers_with_timestamp(indio_dev, data, pf->timestamp);

	kfree(data);
done:
	iio_trigger_notify_done(indio_dev->trig);
	return IRQ_HANDLED;
}

/* Caller responsible for locking as necessary. */
static int
__lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
{
	int ret;
	u8 valold;
	bool currentlyset;
	struct lis3l02dq_state *st = iio_priv(indio_dev);

	/* Get the current event mask register */
	ret = lis3l02dq_spi_read_reg_8(indio_dev,
				       LIS3L02DQ_REG_CTRL_2_ADDR,
				       &valold);
	if (ret)
		goto error_ret;
	/* Find out if data ready is already on */
	currentlyset
		= valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;

	/* Disable requested */
	if (!state && currentlyset) {
		/* Disable the data ready signal */
		valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;

		/* The double write is to overcome a hardware bug? */
		ret = lis3l02dq_spi_write_reg_8(indio_dev,
						LIS3L02DQ_REG_CTRL_2_ADDR,
						valold);
		if (ret)
			goto error_ret;
		ret = lis3l02dq_spi_write_reg_8(indio_dev,
						LIS3L02DQ_REG_CTRL_2_ADDR,
						valold);
		if (ret)
			goto error_ret;
		st->trigger_on = false;
	/* Enable requested */
	} else if (state && !currentlyset) {
		/* If not set, enable requested
		 * first disable all events */
		ret = lis3l02dq_disable_all_events(indio_dev);
		if (ret < 0)
			goto error_ret;

		valold = ret |
			LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;

		st->trigger_on = true;
		ret = lis3l02dq_spi_write_reg_8(indio_dev,
						LIS3L02DQ_REG_CTRL_2_ADDR,
						valold);
		if (ret)
			goto error_ret;
	}

	return 0;
error_ret:
	return ret;
}

/**
 * lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
 *
 * If disabling the interrupt also does a final read to ensure it is clear.
 * This is only important in some cases where the scan enable elements are
 * switched before the buffer is reenabled.
 **/
static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
						bool state)
{
	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
	int ret = 0;
	u8 t;

	__lis3l02dq_write_data_ready_config(indio_dev, state);
	if (!state) {
		/*
		 * A possible quirk with the handler is currently worked around
		 * by ensuring outstanding read events are cleared.
		 */
		ret = lis3l02dq_read_all(indio_dev, NULL);
	}
	lis3l02dq_spi_read_reg_8(indio_dev,
				 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
				 &t);
	return ret;
}

/**
 * lis3l02dq_trig_try_reen() try reenabling irq for data rdy trigger
 * @trig:	the datardy trigger
 */
static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
{
	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
	struct lis3l02dq_state *st = iio_priv(indio_dev);
	int i;

	/* If gpio still high (or high again)
	 * In theory possible we will need to do this several times */
	for (i = 0; i < 5; i++)
		if (gpio_get_value(st->gpio))
			lis3l02dq_read_all(indio_dev, NULL);
		else
			break;
	if (i == 5)
		pr_info("Failed to clear the interrupt for lis3l02dq\n");

	/* irq reenabled so success! */
	return 0;
}

static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
	.owner = THIS_MODULE,
	.set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
	.try_reenable = &lis3l02dq_trig_try_reen,
};

int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
{
	int ret;
	struct lis3l02dq_state *st = iio_priv(indio_dev);

	st->trig = iio_trigger_alloc("lis3l02dq-dev%d", indio_dev->id);
	if (!st->trig) {
		ret = -ENOMEM;
		goto error_ret;
	}

	st->trig->dev.parent = &st->us->dev;
	st->trig->ops = &lis3l02dq_trigger_ops;
	iio_trigger_set_drvdata(st->trig, indio_dev);
	ret = iio_trigger_register(st->trig);
	if (ret)
		goto error_free_trig;

	return 0;

error_free_trig:
	iio_trigger_free(st->trig);
error_ret:
	return ret;
}

void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
{
	struct lis3l02dq_state *st = iio_priv(indio_dev);

	iio_trigger_unregister(st->trig);
	iio_trigger_free(st->trig);
}

void lis3l02dq_unconfigure_buffer(struct iio_dev *indio_dev)
{
	iio_dealloc_pollfunc(indio_dev->pollfunc);
	iio_kfifo_free(indio_dev->buffer);
}

static int lis3l02dq_buffer_postenable(struct iio_dev *indio_dev)
{
	/* Disable unwanted channels otherwise the interrupt will not clear */
	u8 t;
	int ret;
	bool oneenabled = false;

	ret = lis3l02dq_spi_read_reg_8(indio_dev,
				       LIS3L02DQ_REG_CTRL_1_ADDR,
				       &t);
	if (ret)
		goto error_ret;

	if (test_bit(0, indio_dev->active_scan_mask)) {
		t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
		oneenabled = true;
	} else
		t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
	if (test_bit(1, indio_dev->active_scan_mask)) {
		t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
		oneenabled = true;
	} else
		t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
	if (test_bit(2, indio_dev->active_scan_mask)) {
		t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
		oneenabled = true;
	} else
		t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;

	if (!oneenabled) /* what happens in this case is unknown */
		return -EINVAL;
	ret = lis3l02dq_spi_write_reg_8(indio_dev,
					LIS3L02DQ_REG_CTRL_1_ADDR,
					t);
	if (ret)
		goto error_ret;

	return iio_triggered_buffer_postenable(indio_dev);
error_ret:
	return ret;
}

/* Turn all channels on again */
static int lis3l02dq_buffer_predisable(struct iio_dev *indio_dev)
{
	u8 t;
	int ret;

	ret = iio_triggered_buffer_predisable(indio_dev);
	if (ret)
		goto error_ret;

	ret = lis3l02dq_spi_read_reg_8(indio_dev,
				       LIS3L02DQ_REG_CTRL_1_ADDR,
				       &t);
	if (ret)
		goto error_ret;
	t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
		LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
		LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;

	ret = lis3l02dq_spi_write_reg_8(indio_dev,
					LIS3L02DQ_REG_CTRL_1_ADDR,
					t);

error_ret:
	return ret;
}

static const struct iio_buffer_setup_ops lis3l02dq_buffer_setup_ops = {
	.preenable = &iio_sw_buffer_preenable,
	.postenable = &lis3l02dq_buffer_postenable,
	.predisable = &lis3l02dq_buffer_predisable,
};

int lis3l02dq_configure_buffer(struct iio_dev *indio_dev)
{
	int ret;
	struct iio_buffer *buffer;

	buffer = iio_kfifo_allocate(indio_dev);
	if (!buffer)
		return -ENOMEM;

	iio_device_attach_buffer(indio_dev, buffer);

	buffer->scan_timestamp = true;
	indio_dev->setup_ops = &lis3l02dq_buffer_setup_ops;

	/* Functions are NULL as we set handler below */
	indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
						 &lis3l02dq_trigger_handler,
						 0,
						 indio_dev,
						 "lis3l02dq_consumer%d",
						 indio_dev->id);

	if (indio_dev->pollfunc == NULL) {
		ret = -ENOMEM;
		goto error_iio_sw_rb_free;
	}

	indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
	return 0;

error_iio_sw_rb_free:
	iio_kfifo_free(indio_dev->buffer);
	return ret;
}
Commit	Line	Data
14cd9a73	1	#include <linux/interrupt.h>
14cd9a73	2	#include <linux/gpio.h>
14cd9a73	3	#include <linux/mutex.h>
14cd9a73 JC	4	#include <linux/kernel.h>
14cd9a73 JC	5	#include <linux/spi/spi.h>
5a0e3ad6	6	#include <linux/slab.h>
8e336a72	7	#include <linux/export.h>
14cd9a73	8
06458e27	9	#include <linux/iio/iio.h>
06458e27 JC	10	#include <linux/iio/kfifo_buf.h>
	11	#include <linux/iio/trigger.h>
	12	#include <linux/iio/trigger_consumer.h>
14cd9a73 JC	13	#include "lis3l02dq.h"
	14
	15	/**
91b4171f	16	* combine_8_to_16() utility function to munge two u8s into u16
14cd9a73 JC	17	**/
	18	static inline u16 combine_8_to_16(u8 lower, u8 upper)
	19	{
	20	u16 _lower = lower;
	21	u16 _upper = upper;
	22	return _lower \| (_upper << 8);
	23	}
	24
d731aea0 JC	25	/**
	26	* lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
	27	**/
	28	irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
	29	{
	30	struct iio_dev *indio_dev = private;
7b2fdd19	31	struct lis3l02dq_state *st = iio_priv(indio_dev);
d731aea0 JC	32
	33	if (st->trigger_on) {
	34	iio_trigger_poll(st->trig, iio_get_time_ns());
	35	return IRQ_HANDLED;
	36	} else
	37	return IRQ_WAKE_THREAD;
	38	}
	39
26de7208	40	static const u8 read_all_tx_array[] = {
14cd9a73 JC	41	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
	42	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
	43	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
	44	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
	45	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
	46	LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
	47	};
	48
	49	/**
	50	* lis3l02dq_read_all() Reads all channels currently selected
91b4171f	51	* @indio_dev: IIO device state
25985edc	52	* @rx_array: (dma capable) receive array, must be at least
14cd9a73 JC	53	* 4*number of channels
14cd9a73 JC	54	**/
7b2fdd19	55	static int lis3l02dq_read_all(struct iio_dev indio_dev, u8 rx_array)
14cd9a73	56	{
7b2fdd19	57	struct lis3l02dq_state *st = iio_priv(indio_dev);
14cd9a73 JC	58	struct spi_transfer *xfers;
	59	struct spi_message msg;
	60	int ret, i, j = 0;
	61
550268ca JC	62	xfers = kcalloc(bitmap_weight(indio_dev->active_scan_mask,
	63	indio_dev->masklength) * 2,
	64	sizeof(*xfers), GFP_KERNEL);
14cd9a73 JC	65	if (!xfers)
	66	return -ENOMEM;
	67
	68	mutex_lock(&st->buf_lock);
	69
f3736416	70	for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
550268ca	71	if (test_bit(i, indio_dev->active_scan_mask)) {
14cd9a73 JC	72	/* lower byte */
	73	xfers[j].tx_buf = st->tx + 2*j;
	74	st->tx[2j] = read_all_tx_array[i4];
	75	st->tx[2*j + 1] = 0;
	76	if (rx_array)
	77	xfers[j].rx_buf = rx_array + j*2;
	78	xfers[j].bits_per_word = 8;
	79	xfers[j].len = 2;
	80	xfers[j].cs_change = 1;
	81	j++;
	82
	83	/* upper byte */
	84	xfers[j].tx_buf = st->tx + 2*j;
	85	st->tx[2j] = read_all_tx_array[i4 + 2];
	86	st->tx[2*j + 1] = 0;
	87	if (rx_array)
	88	xfers[j].rx_buf = rx_array + j*2;
	89	xfers[j].bits_per_word = 8;
	90	xfers[j].len = 2;
	91	xfers[j].cs_change = 1;
	92	j++;
	93	}
f3736416	94
14cd9a73 JC	95	/* After these are transmitted, the rx_buff should have
	96	* values in alternate bytes
	97	*/
	98	spi_message_init(&msg);
550268ca JC	99	for (j = 0; j < bitmap_weight(indio_dev->active_scan_mask,
550268ca JC	100	indio_dev->masklength) * 2; j++)
14cd9a73 JC	101	spi_message_add_tail(&xfers[j], &msg);
	102
	103	ret = spi_sync(st->us, &msg);
	104	mutex_unlock(&st->buf_lock);
	105	kfree(xfers);
	106
	107	return ret;
	108	}
	109
6ddbb08a	110	static int lis3l02dq_get_buffer_element(struct iio_dev *indio_dev,
73bce12e JC	111	u8 *buf)
	112	{
	113	int ret, i;
ffb283e1	114	u8 *rx_array;
73bce12e	115	s16 data = (s16 )buf;
550268ca JC	116	int scan_count = bitmap_weight(indio_dev->active_scan_mask,
550268ca JC	117	indio_dev->masklength);
14cd9a73	118
550268ca	119	rx_array = kzalloc(4 * scan_count, GFP_KERNEL);
73bce12e JC	120	if (rx_array == NULL)
73bce12e JC	121	return -ENOMEM;
7b2fdd19	122	ret = lis3l02dq_read_all(indio_dev, rx_array);
d1dc9c12 PM	123	if (ret < 0) {
d1dc9c12 PM	124	kfree(rx_array);
73bce12e	125	return ret;
d1dc9c12	126	}
550268ca	127	for (i = 0; i < scan_count; i++)
73bce12e JC	128	data[i] = combine_8_to_16(rx_array[i*4+1],
73bce12e JC	129	rx_array[i*4+3]);
14cd9a73	130	kfree(rx_array);
14cd9a73	131
73bce12e	132	return i*sizeof(data[0]);
14cd9a73	133	}
14cd9a73	134
7b2fdd19 JC	135	static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
	136	{
	137	struct iio_poll_func *pf = p;
e65bc6ac	138	struct iio_dev *indio_dev = pf->indio_dev;
7b2fdd19	139	int len = 0;
420fe2e9	140	char *data;
7b2fdd19	141
420fe2e9	142	data = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
78110bb8	143	if (data == NULL)
0b30246e	144	goto done;
7b2fdd19	145
550268ca	146	if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
6ddbb08a	147	len = lis3l02dq_get_buffer_element(indio_dev, data);
7b2fdd19	148
fdc8020c	149	iio_push_to_buffers_with_timestamp(indio_dev, data, pf->timestamp);
7b2fdd19	150
7b2fdd19	151	kfree(data);
0b30246e LPC	152	done:
0b30246e LPC	153	iio_trigger_notify_done(indio_dev->trig);
7b2fdd19 JC	154	return IRQ_HANDLED;
	155	}
	156
14cd9a73	157	/* Caller responsible for locking as necessary. */
26de7208	158	static int
8dc5afd8	159	__lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
14cd9a73 JC	160	{
	161	int ret;
	162	u8 valold;
	163	bool currentlyset;
7b2fdd19	164	struct lis3l02dq_state *st = iio_priv(indio_dev);
14cd9a73	165
91b4171f	166	/* Get the current event mask register */
1b076b52	167	ret = lis3l02dq_spi_read_reg_8(indio_dev,
14cd9a73 JC	168	LIS3L02DQ_REG_CTRL_2_ADDR,
	169	&valold);
	170	if (ret)
	171	goto error_ret;
91b4171f	172	/* Find out if data ready is already on */
14cd9a73 JC	173	currentlyset
	174	= valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
	175
91b4171f	176	/* Disable requested */
14cd9a73	177	if (!state && currentlyset) {
91b4171f	178	/* Disable the data ready signal */
14cd9a73	179	valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
1e3345bc	180
91b4171f	181	/* The double write is to overcome a hardware bug? */
1b076b52	182	ret = lis3l02dq_spi_write_reg_8(indio_dev,
14cd9a73	183	LIS3L02DQ_REG_CTRL_2_ADDR,
7df86302	184	valold);
14cd9a73 JC	185	if (ret)
14cd9a73 JC	186	goto error_ret;
1b076b52	187	ret = lis3l02dq_spi_write_reg_8(indio_dev,
14cd9a73	188	LIS3L02DQ_REG_CTRL_2_ADDR,
7df86302	189	valold);
14cd9a73 JC	190	if (ret)
14cd9a73 JC	191	goto error_ret;
d731aea0	192	st->trigger_on = false;
91b4171f	193	/* Enable requested */
14cd9a73	194	} else if (state && !currentlyset) {
91b4171f PM	195	/* If not set, enable requested
91b4171f PM	196	* first disable all events */
1e3345bc JC	197	ret = lis3l02dq_disable_all_events(indio_dev);
	198	if (ret < 0)
	199	goto error_ret;
	200
	201	valold = ret \|
	202	LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
1e3345bc	203
d731aea0	204	st->trigger_on = true;
1b076b52	205	ret = lis3l02dq_spi_write_reg_8(indio_dev,
14cd9a73	206	LIS3L02DQ_REG_CTRL_2_ADDR,
7df86302	207	valold);
d731aea0	208	if (ret)
14cd9a73 JC	209	goto error_ret;
	210	}
	211
	212	return 0;
	213	error_ret:
	214	return ret;
	215	}
	216
	217	/**
	218	* lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
	219	*
	220	* If disabling the interrupt also does a final read to ensure it is clear.
	221	* This is only important in some cases where the scan enable elements are
6ddbb08a	222	* switched before the buffer is reenabled.
14cd9a73 JC	223	**/
	224	static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
	225	bool state)
	226	{
1e9663c6	227	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
14cd9a73 JC	228	int ret = 0;
14cd9a73 JC	229	u8 t;
1e3345bc	230
8dc5afd8	231	__lis3l02dq_write_data_ready_config(indio_dev, state);
6fae58f3	232	if (!state) {
d1dbf011	233	/*
4abf6f8b	234	* A possible quirk with the handler is currently worked around
91b4171f	235	* by ensuring outstanding read events are cleared.
d1dbf011	236	*/
7b2fdd19	237	ret = lis3l02dq_read_all(indio_dev, NULL);
14cd9a73	238	}
7b2fdd19	239	lis3l02dq_spi_read_reg_8(indio_dev,
14cd9a73 JC	240	LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
	241	&t);
	242	return ret;
	243	}
9dbfb6f1	244
14cd9a73	245	/**
91b4171f	246	* lis3l02dq_trig_try_reen() try reenabling irq for data rdy trigger
14cd9a73	247	* @trig: the datardy trigger
d1dbf011	248	*/
14cd9a73 JC	249	static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
14cd9a73 JC	250	{
1e9663c6	251	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
7b2fdd19	252	struct lis3l02dq_state *st = iio_priv(indio_dev);
d1dbf011 JC	253	int i;
d1dbf011 JC	254
91b4171f PM	255	/* If gpio still high (or high again)
91b4171f PM	256	* In theory possible we will need to do this several times */
d1dbf011	257	for (i = 0; i < 5; i++)
65cb587d	258	if (gpio_get_value(st->gpio))
7b2fdd19	259	lis3l02dq_read_all(indio_dev, NULL);
d1dbf011 JC	260	else
	261	break;
	262	if (i == 5)
b4a051d8	263	pr_info("Failed to clear the interrupt for lis3l02dq\n");
d1dbf011	264
14cd9a73 JC	265	/* irq reenabled so success! */
	266	return 0;
	267	}
	268
d29f73db JC	269	static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
	270	.owner = THIS_MODULE,
	271	.set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
	272	.try_reenable = &lis3l02dq_trig_try_reen,
	273	};
	274
14cd9a73 JC	275	int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
	276	{
	277	int ret;
7b2fdd19	278	struct lis3l02dq_state *st = iio_priv(indio_dev);
14cd9a73	279
7cbb7537	280	st->trig = iio_trigger_alloc("lis3l02dq-dev%d", indio_dev->id);
d1dbf011 JC	281	if (!st->trig) {
d1dbf011 JC	282	ret = -ENOMEM;
59c85e82	283	goto error_ret;
14cd9a73	284	}
3c9bbf58	285
1b076b52	286	st->trig->dev.parent = &st->us->dev;
d29f73db	287	st->trig->ops = &lis3l02dq_trigger_ops;
1e9663c6	288	iio_trigger_set_drvdata(st->trig, indio_dev);
1b076b52	289	ret = iio_trigger_register(st->trig);
14cd9a73	290	if (ret)
d1dbf011	291	goto error_free_trig;
14cd9a73 JC	292
	293	return 0;
	294
14cd9a73	295	error_free_trig:
7cbb7537	296	iio_trigger_free(st->trig);
d1dbf011	297	error_ret:
14cd9a73 JC	298	return ret;
	299	}
	300
	301	void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
	302	{
7b2fdd19	303	struct lis3l02dq_state *st = iio_priv(indio_dev);
14cd9a73	304
1b076b52	305	iio_trigger_unregister(st->trig);
7cbb7537	306	iio_trigger_free(st->trig);
14cd9a73 JC	307	}
14cd9a73 JC	308
6ddbb08a	309	void lis3l02dq_unconfigure_buffer(struct iio_dev *indio_dev)
14cd9a73	310	{
0ed731d2	311	iio_dealloc_pollfunc(indio_dev->pollfunc);
a819a0df	312	iio_kfifo_free(indio_dev->buffer);
14cd9a73 JC	313	}
14cd9a73 JC	314
6ddbb08a	315	static int lis3l02dq_buffer_postenable(struct iio_dev *indio_dev)
f3736416 JC	316	{
	317	/* Disable unwanted channels otherwise the interrupt will not clear */
	318	u8 t;
	319	int ret;
	320	bool oneenabled = false;
	321
1b076b52	322	ret = lis3l02dq_spi_read_reg_8(indio_dev,
f3736416 JC	323	LIS3L02DQ_REG_CTRL_1_ADDR,
	324	&t);
	325	if (ret)
	326	goto error_ret;
	327
550268ca	328	if (test_bit(0, indio_dev->active_scan_mask)) {
f3736416 JC	329	t \|= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
	330	oneenabled = true;
	331	} else
	332	t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
550268ca	333	if (test_bit(1, indio_dev->active_scan_mask)) {
f3736416 JC	334	t \|= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
	335	oneenabled = true;
	336	} else
	337	t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
550268ca	338	if (test_bit(2, indio_dev->active_scan_mask)) {
f3736416 JC	339	t \|= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
	340	oneenabled = true;
	341	} else
	342	t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
	343
	344	if (!oneenabled) /* what happens in this case is unknown */
	345	return -EINVAL;
1b076b52	346	ret = lis3l02dq_spi_write_reg_8(indio_dev,
f3736416	347	LIS3L02DQ_REG_CTRL_1_ADDR,
7df86302	348	t);
f3736416 JC	349	if (ret)
	350	goto error_ret;
	351
3b99fb76	352	return iio_triggered_buffer_postenable(indio_dev);
f3736416 JC	353	error_ret:
	354	return ret;
	355	}
	356
	357	/* Turn all channels on again */
6ddbb08a	358	static int lis3l02dq_buffer_predisable(struct iio_dev *indio_dev)
f3736416 JC	359	{
	360	u8 t;
	361	int ret;
	362
3b99fb76	363	ret = iio_triggered_buffer_predisable(indio_dev);
f3736416 JC	364	if (ret)
	365	goto error_ret;
	366
1b076b52	367	ret = lis3l02dq_spi_read_reg_8(indio_dev,
f3736416 JC	368	LIS3L02DQ_REG_CTRL_1_ADDR,
	369	&t);
	370	if (ret)
	371	goto error_ret;
	372	t \|= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE \|
	373	LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE \|
	374	LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
	375
1b076b52	376	ret = lis3l02dq_spi_write_reg_8(indio_dev,
f3736416	377	LIS3L02DQ_REG_CTRL_1_ADDR,
7df86302	378	t);
f3736416 JC	379
	380	error_ret:
	381	return ret;
	382	}
	383
6ddbb08a	384	static const struct iio_buffer_setup_ops lis3l02dq_buffer_setup_ops = {
14555b14	385	.preenable = &iio_sw_buffer_preenable,
6ddbb08a JC	386	.postenable = &lis3l02dq_buffer_postenable,
6ddbb08a JC	387	.predisable = &lis3l02dq_buffer_predisable,
5565a450	388	};
f3736416	389
6ddbb08a	390	int lis3l02dq_configure_buffer(struct iio_dev *indio_dev)
14cd9a73	391	{
73bce12e	392	int ret;
6ddbb08a	393	struct iio_buffer *buffer;
d1dbf011	394
a819a0df	395	buffer = iio_kfifo_allocate(indio_dev);
6ddbb08a	396	if (!buffer)
73bce12e JC	397	return -ENOMEM;
73bce12e JC	398
9e69c935	399	iio_device_attach_buffer(indio_dev, buffer);
f3736416	400
6ddbb08a	401	buffer->scan_timestamp = true;
1612244f	402	indio_dev->setup_ops = &lis3l02dq_buffer_setup_ops;
14cd9a73	403
d1dbf011	404	/* Functions are NULL as we set handler below */
0ed731d2 JC	405	indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
	406	&lis3l02dq_trigger_handler,
	407	0,
	408	indio_dev,
	409	"lis3l02dq_consumer%d",
	410	indio_dev->id);
d1dbf011 JC	411
	412	if (indio_dev->pollfunc == NULL) {
	413	ret = -ENOMEM;
859171ca	414	goto error_iio_sw_rb_free;
d1dbf011	415	}
d1dbf011	416
ec3afa40	417	indio_dev->modes \|= INDIO_BUFFER_TRIGGERED;
14cd9a73 JC	418	return 0;
	419
	420	error_iio_sw_rb_free:
a819a0df	421	iio_kfifo_free(indio_dev->buffer);
14cd9a73 JC	422	return ret;
14cd9a73 JC	423	}