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bc2c90c9 MV |
1 | /* |
2 | * Freescale i.MX28 LRADC driver | |
3 | * | |
4 | * Copyright (c) 2012 DENX Software Engineering, GmbH. | |
5 | * Marek Vasut <marex@denx.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/interrupt.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_device.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <linux/wait.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/stmp_device.h> | |
33 | #include <linux/bitops.h> | |
34 | #include <linux/completion.h> | |
35 | ||
36 | #include <mach/mxs.h> | |
37 | #include <mach/common.h> | |
38 | ||
39 | #include <linux/iio/iio.h> | |
40 | #include <linux/iio/buffer.h> | |
41 | #include <linux/iio/trigger.h> | |
42 | #include <linux/iio/trigger_consumer.h> | |
43 | #include <linux/iio/triggered_buffer.h> | |
44 | ||
45 | #define DRIVER_NAME "mxs-lradc" | |
46 | ||
47 | #define LRADC_MAX_DELAY_CHANS 4 | |
48 | #define LRADC_MAX_MAPPED_CHANS 8 | |
49 | #define LRADC_MAX_TOTAL_CHANS 16 | |
50 | ||
51 | #define LRADC_DELAY_TIMER_HZ 2000 | |
52 | ||
53 | /* | |
54 | * Make this runtime configurable if necessary. Currently, if the buffered mode | |
55 | * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before | |
56 | * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000) | |
57 | * seconds. The result is that the samples arrive every 500mS. | |
58 | */ | |
59 | #define LRADC_DELAY_TIMER_PER 200 | |
60 | #define LRADC_DELAY_TIMER_LOOP 5 | |
61 | ||
62 | static const char * const mxs_lradc_irq_name[] = { | |
63 | "mxs-lradc-touchscreen", | |
64 | "mxs-lradc-thresh0", | |
65 | "mxs-lradc-thresh1", | |
66 | "mxs-lradc-channel0", | |
67 | "mxs-lradc-channel1", | |
68 | "mxs-lradc-channel2", | |
69 | "mxs-lradc-channel3", | |
70 | "mxs-lradc-channel4", | |
71 | "mxs-lradc-channel5", | |
72 | "mxs-lradc-channel6", | |
73 | "mxs-lradc-channel7", | |
74 | "mxs-lradc-button0", | |
75 | "mxs-lradc-button1", | |
76 | }; | |
77 | ||
bc2c90c9 MV |
78 | struct mxs_lradc { |
79 | struct device *dev; | |
80 | void __iomem *base; | |
81 | int irq[13]; | |
82 | ||
83 | uint32_t *buffer; | |
84 | struct iio_trigger *trig; | |
85 | ||
86 | struct mutex lock; | |
87 | ||
bc2c90c9 MV |
88 | struct completion completion; |
89 | }; | |
90 | ||
91 | #define LRADC_CTRL0 0x00 | |
92 | #define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) | |
93 | #define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) | |
94 | ||
95 | #define LRADC_CTRL1 0x10 | |
96 | #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n)) | |
97 | #define LRADC_CTRL1_LRADC_IRQ_MASK 0x1fff | |
98 | #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16)) | |
99 | #define LRADC_CTRL1_LRADC_IRQ_EN_MASK (0x1fff << 16) | |
100 | ||
101 | #define LRADC_CTRL2 0x20 | |
102 | #define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) | |
103 | ||
104 | #define LRADC_CH(n) (0x50 + (0x10 * (n))) | |
105 | #define LRADC_CH_ACCUMULATE (1 << 29) | |
106 | #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) | |
107 | #define LRADC_CH_NUM_SAMPLES_OFFSET 24 | |
108 | #define LRADC_CH_VALUE_MASK 0x3ffff | |
109 | #define LRADC_CH_VALUE_OFFSET 0 | |
110 | ||
111 | #define LRADC_DELAY(n) (0xd0 + (0x10 * (n))) | |
112 | #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) | |
113 | #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 | |
114 | #define LRADC_DELAY_KICK (1 << 20) | |
115 | #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) | |
116 | #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 | |
117 | #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) | |
118 | #define LRADC_DELAY_LOOP_COUNT_OFFSET 11 | |
119 | #define LRADC_DELAY_DELAY_MASK 0x7ff | |
120 | #define LRADC_DELAY_DELAY_OFFSET 0 | |
121 | ||
122 | #define LRADC_CTRL4 0x140 | |
123 | #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4)) | |
124 | #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4) | |
125 | ||
126 | /* | |
127 | * Raw I/O operations | |
128 | */ | |
129 | static int mxs_lradc_read_raw(struct iio_dev *iio_dev, | |
130 | const struct iio_chan_spec *chan, | |
131 | int *val, int *val2, long m) | |
132 | { | |
133 | struct mxs_lradc *lradc = iio_priv(iio_dev); | |
134 | int ret; | |
135 | ||
136 | if (m != IIO_CHAN_INFO_RAW) | |
137 | return -EINVAL; | |
138 | ||
139 | /* Check for invalid channel */ | |
140 | if (chan->channel > LRADC_MAX_TOTAL_CHANS) | |
141 | return -EINVAL; | |
142 | ||
143 | /* | |
144 | * See if there is no buffered operation in progess. If there is, simply | |
145 | * bail out. This can be improved to support both buffered and raw IO at | |
146 | * the same time, yet the code becomes horribly complicated. Therefore I | |
147 | * applied KISS principle here. | |
148 | */ | |
149 | ret = mutex_trylock(&lradc->lock); | |
150 | if (!ret) | |
151 | return -EBUSY; | |
152 | ||
153 | INIT_COMPLETION(lradc->completion); | |
154 | ||
155 | /* | |
156 | * No buffered operation in progress, map the channel and trigger it. | |
157 | * Virtual channel 0 is always used here as the others are always not | |
158 | * used if doing raw sampling. | |
159 | */ | |
160 | writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK, | |
161 | lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); | |
162 | writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); | |
163 | ||
164 | writel(chan->channel, lradc->base + LRADC_CTRL4); | |
165 | writel(0, lradc->base + LRADC_CH(0)); | |
166 | ||
167 | /* Enable the IRQ and start sampling the channel. */ | |
168 | writel(LRADC_CTRL1_LRADC_IRQ_EN(0), | |
169 | lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); | |
170 | writel(1 << 0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); | |
171 | ||
172 | /* Wait for completion on the channel, 1 second max. */ | |
173 | ret = wait_for_completion_killable_timeout(&lradc->completion, HZ); | |
174 | if (!ret) | |
175 | ret = -ETIMEDOUT; | |
176 | if (ret < 0) | |
177 | goto err; | |
178 | ||
179 | /* Read the data. */ | |
180 | *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK; | |
181 | ret = IIO_VAL_INT; | |
182 | ||
183 | err: | |
184 | writel(LRADC_CTRL1_LRADC_IRQ_EN(0), | |
185 | lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); | |
186 | ||
187 | mutex_unlock(&lradc->lock); | |
188 | ||
189 | return ret; | |
190 | } | |
191 | ||
192 | static const struct iio_info mxs_lradc_iio_info = { | |
193 | .driver_module = THIS_MODULE, | |
194 | .read_raw = mxs_lradc_read_raw, | |
195 | }; | |
196 | ||
197 | /* | |
198 | * IRQ Handling | |
199 | */ | |
200 | static irqreturn_t mxs_lradc_handle_irq(int irq, void *data) | |
201 | { | |
202 | struct iio_dev *iio = data; | |
203 | struct mxs_lradc *lradc = iio_priv(iio); | |
204 | unsigned long reg = readl(lradc->base + LRADC_CTRL1); | |
205 | ||
206 | if (!(reg & LRADC_CTRL1_LRADC_IRQ_MASK)) | |
207 | return IRQ_NONE; | |
208 | ||
209 | /* | |
210 | * Touchscreen IRQ handling code shall probably have priority | |
211 | * and therefore shall be placed here. | |
212 | */ | |
213 | ||
214 | if (iio_buffer_enabled(iio)) | |
215 | iio_trigger_poll(iio->trig, iio_get_time_ns()); | |
216 | else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) | |
217 | complete(&lradc->completion); | |
218 | ||
219 | writel(reg & LRADC_CTRL1_LRADC_IRQ_MASK, | |
220 | lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); | |
221 | ||
222 | return IRQ_HANDLED; | |
223 | } | |
224 | ||
225 | /* | |
226 | * Trigger handling | |
227 | */ | |
228 | static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p) | |
229 | { | |
230 | struct iio_poll_func *pf = p; | |
231 | struct iio_dev *iio = pf->indio_dev; | |
232 | struct mxs_lradc *lradc = iio_priv(iio); | |
bc2c90c9 MV |
233 | const uint32_t chan_value = LRADC_CH_ACCUMULATE | |
234 | ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); | |
7b7a4efe | 235 | unsigned int i, j = 0; |
bc2c90c9 MV |
236 | |
237 | for_each_set_bit(i, iio->active_scan_mask, iio->masklength) { | |
238 | lradc->buffer[j] = readl(lradc->base + LRADC_CH(j)); | |
239 | writel(chan_value, lradc->base + LRADC_CH(j)); | |
240 | lradc->buffer[j] &= LRADC_CH_VALUE_MASK; | |
241 | lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP; | |
242 | j++; | |
243 | } | |
244 | ||
245 | if (iio->scan_timestamp) { | |
246 | s64 *timestamp = (s64 *)((u8 *)lradc->buffer + | |
247 | ALIGN(j, sizeof(s64))); | |
248 | *timestamp = pf->timestamp; | |
249 | } | |
250 | ||
84b36ce5 | 251 | iio_push_to_buffers(iio, (u8 *)lradc->buffer); |
bc2c90c9 MV |
252 | |
253 | iio_trigger_notify_done(iio->trig); | |
254 | ||
255 | return IRQ_HANDLED; | |
256 | } | |
257 | ||
258 | static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state) | |
259 | { | |
260 | struct iio_dev *iio = trig->private_data; | |
261 | struct mxs_lradc *lradc = iio_priv(iio); | |
262 | const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; | |
263 | ||
264 | writel(LRADC_DELAY_KICK, lradc->base + LRADC_DELAY(0) + st); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | static const struct iio_trigger_ops mxs_lradc_trigger_ops = { | |
270 | .owner = THIS_MODULE, | |
271 | .set_trigger_state = &mxs_lradc_configure_trigger, | |
272 | }; | |
273 | ||
274 | static int mxs_lradc_trigger_init(struct iio_dev *iio) | |
275 | { | |
276 | int ret; | |
277 | struct iio_trigger *trig; | |
278 | ||
279 | trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id); | |
280 | if (trig == NULL) | |
281 | return -ENOMEM; | |
282 | ||
283 | trig->dev.parent = iio->dev.parent; | |
284 | trig->private_data = iio; | |
285 | trig->ops = &mxs_lradc_trigger_ops; | |
286 | ||
287 | ret = iio_trigger_register(trig); | |
288 | if (ret) { | |
289 | iio_trigger_free(trig); | |
290 | return ret; | |
291 | } | |
292 | ||
293 | iio->trig = trig; | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | static void mxs_lradc_trigger_remove(struct iio_dev *iio) | |
299 | { | |
300 | iio_trigger_unregister(iio->trig); | |
301 | iio_trigger_free(iio->trig); | |
302 | } | |
303 | ||
304 | static int mxs_lradc_buffer_preenable(struct iio_dev *iio) | |
305 | { | |
306 | struct mxs_lradc *lradc = iio_priv(iio); | |
307 | struct iio_buffer *buffer = iio->buffer; | |
308 | int ret = 0, chan, ofs = 0, enable = 0; | |
309 | uint32_t ctrl4 = 0; | |
310 | uint32_t ctrl1_irq = 0; | |
311 | const uint32_t chan_value = LRADC_CH_ACCUMULATE | | |
312 | ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); | |
313 | const int len = bitmap_weight(buffer->scan_mask, LRADC_MAX_TOTAL_CHANS); | |
314 | ||
315 | if (!len) | |
316 | return -EINVAL; | |
317 | ||
318 | /* | |
319 | * Lock the driver so raw access can not be done during buffered | |
320 | * operation. This simplifies the code a lot. | |
321 | */ | |
322 | ret = mutex_trylock(&lradc->lock); | |
323 | if (!ret) | |
324 | return -EBUSY; | |
325 | ||
326 | lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL); | |
327 | if (!lradc->buffer) { | |
328 | ret = -ENOMEM; | |
329 | goto err_mem; | |
330 | } | |
331 | ||
332 | ret = iio_sw_buffer_preenable(iio); | |
333 | if (ret < 0) | |
334 | goto err_buf; | |
335 | ||
336 | writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK, | |
337 | lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); | |
338 | writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); | |
339 | ||
340 | for_each_set_bit(chan, buffer->scan_mask, LRADC_MAX_TOTAL_CHANS) { | |
341 | ctrl4 |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs); | |
342 | ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs); | |
343 | writel(chan_value, lradc->base + LRADC_CH(ofs)); | |
344 | enable |= 1 << ofs; | |
345 | ofs++; | |
73327b4c | 346 | } |
bc2c90c9 MV |
347 | |
348 | writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK, | |
349 | lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); | |
350 | ||
351 | writel(ctrl4, lradc->base + LRADC_CTRL4); | |
352 | writel(ctrl1_irq, lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); | |
353 | ||
354 | writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET, | |
355 | lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET); | |
356 | ||
357 | return 0; | |
358 | ||
359 | err_buf: | |
360 | kfree(lradc->buffer); | |
361 | err_mem: | |
362 | mutex_unlock(&lradc->lock); | |
363 | return ret; | |
364 | } | |
365 | ||
366 | static int mxs_lradc_buffer_postdisable(struct iio_dev *iio) | |
367 | { | |
368 | struct mxs_lradc *lradc = iio_priv(iio); | |
369 | ||
370 | writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK, | |
371 | lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); | |
372 | ||
373 | writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); | |
374 | writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK, | |
375 | lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); | |
376 | ||
377 | kfree(lradc->buffer); | |
378 | mutex_unlock(&lradc->lock); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio, | |
384 | const unsigned long *mask) | |
385 | { | |
386 | const int mw = bitmap_weight(mask, iio->masklength); | |
387 | ||
388 | return mw <= LRADC_MAX_MAPPED_CHANS; | |
389 | } | |
390 | ||
391 | static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = { | |
392 | .preenable = &mxs_lradc_buffer_preenable, | |
393 | .postenable = &iio_triggered_buffer_postenable, | |
394 | .predisable = &iio_triggered_buffer_predisable, | |
395 | .postdisable = &mxs_lradc_buffer_postdisable, | |
396 | .validate_scan_mask = &mxs_lradc_validate_scan_mask, | |
397 | }; | |
398 | ||
399 | /* | |
400 | * Driver initialization | |
401 | */ | |
402 | ||
403 | #define MXS_ADC_CHAN(idx, chan_type) { \ | |
404 | .type = (chan_type), \ | |
405 | .indexed = 1, \ | |
406 | .scan_index = (idx), \ | |
407 | .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT, \ | |
408 | .channel = (idx), \ | |
409 | .scan_type = { \ | |
410 | .sign = 'u', \ | |
411 | .realbits = 18, \ | |
412 | .storagebits = 32, \ | |
413 | }, \ | |
414 | } | |
415 | ||
416 | static const struct iio_chan_spec mxs_lradc_chan_spec[] = { | |
417 | MXS_ADC_CHAN(0, IIO_VOLTAGE), | |
418 | MXS_ADC_CHAN(1, IIO_VOLTAGE), | |
419 | MXS_ADC_CHAN(2, IIO_VOLTAGE), | |
420 | MXS_ADC_CHAN(3, IIO_VOLTAGE), | |
421 | MXS_ADC_CHAN(4, IIO_VOLTAGE), | |
422 | MXS_ADC_CHAN(5, IIO_VOLTAGE), | |
423 | MXS_ADC_CHAN(6, IIO_VOLTAGE), | |
424 | MXS_ADC_CHAN(7, IIO_VOLTAGE), /* VBATT */ | |
425 | MXS_ADC_CHAN(8, IIO_TEMP), /* Temp sense 0 */ | |
426 | MXS_ADC_CHAN(9, IIO_TEMP), /* Temp sense 1 */ | |
427 | MXS_ADC_CHAN(10, IIO_VOLTAGE), /* VDDIO */ | |
428 | MXS_ADC_CHAN(11, IIO_VOLTAGE), /* VTH */ | |
429 | MXS_ADC_CHAN(12, IIO_VOLTAGE), /* VDDA */ | |
430 | MXS_ADC_CHAN(13, IIO_VOLTAGE), /* VDDD */ | |
431 | MXS_ADC_CHAN(14, IIO_VOLTAGE), /* VBG */ | |
432 | MXS_ADC_CHAN(15, IIO_VOLTAGE), /* VDD5V */ | |
433 | }; | |
434 | ||
435 | static void mxs_lradc_hw_init(struct mxs_lradc *lradc) | |
436 | { | |
437 | int i; | |
438 | const uint32_t cfg = | |
439 | (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET); | |
440 | ||
441 | stmp_reset_block(lradc->base); | |
442 | ||
443 | for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++) | |
444 | writel(cfg | (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + i)), | |
445 | lradc->base + LRADC_DELAY(i)); | |
446 | ||
447 | /* Start internal temperature sensing. */ | |
448 | writel(0, lradc->base + LRADC_CTRL2); | |
449 | } | |
450 | ||
451 | static void mxs_lradc_hw_stop(struct mxs_lradc *lradc) | |
452 | { | |
453 | int i; | |
454 | ||
455 | writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK, | |
456 | lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); | |
457 | ||
458 | for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++) | |
459 | writel(0, lradc->base + LRADC_DELAY(i)); | |
460 | } | |
461 | ||
4ae1c61f | 462 | static int mxs_lradc_probe(struct platform_device *pdev) |
bc2c90c9 MV |
463 | { |
464 | struct device *dev = &pdev->dev; | |
465 | struct mxs_lradc *lradc; | |
466 | struct iio_dev *iio; | |
467 | struct resource *iores; | |
468 | int ret = 0; | |
469 | int i; | |
470 | ||
471 | /* Allocate the IIO device. */ | |
472 | iio = iio_device_alloc(sizeof(*lradc)); | |
473 | if (!iio) { | |
474 | dev_err(dev, "Failed to allocate IIO device\n"); | |
475 | return -ENOMEM; | |
476 | } | |
477 | ||
478 | lradc = iio_priv(iio); | |
479 | ||
480 | /* Grab the memory area */ | |
481 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
482 | lradc->dev = &pdev->dev; | |
483 | lradc->base = devm_request_and_ioremap(dev, iores); | |
484 | if (!lradc->base) { | |
485 | ret = -EADDRNOTAVAIL; | |
486 | goto err_addr; | |
487 | } | |
488 | ||
489 | /* Grab all IRQ sources */ | |
490 | for (i = 0; i < 13; i++) { | |
491 | lradc->irq[i] = platform_get_irq(pdev, i); | |
492 | if (lradc->irq[i] < 0) { | |
493 | ret = -EINVAL; | |
494 | goto err_addr; | |
495 | } | |
496 | ||
497 | ret = devm_request_irq(dev, lradc->irq[i], | |
498 | mxs_lradc_handle_irq, 0, | |
499 | mxs_lradc_irq_name[i], iio); | |
500 | if (ret) | |
501 | goto err_addr; | |
502 | } | |
503 | ||
504 | platform_set_drvdata(pdev, iio); | |
505 | ||
506 | init_completion(&lradc->completion); | |
507 | mutex_init(&lradc->lock); | |
508 | ||
509 | iio->name = pdev->name; | |
510 | iio->dev.parent = &pdev->dev; | |
511 | iio->info = &mxs_lradc_iio_info; | |
512 | iio->modes = INDIO_DIRECT_MODE; | |
513 | iio->channels = mxs_lradc_chan_spec; | |
514 | iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec); | |
515 | ||
516 | ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time, | |
517 | &mxs_lradc_trigger_handler, | |
518 | &mxs_lradc_buffer_ops); | |
519 | if (ret) | |
520 | goto err_addr; | |
521 | ||
522 | ret = mxs_lradc_trigger_init(iio); | |
523 | if (ret) | |
524 | goto err_trig; | |
525 | ||
526 | /* Register IIO device. */ | |
527 | ret = iio_device_register(iio); | |
528 | if (ret) { | |
529 | dev_err(dev, "Failed to register IIO device\n"); | |
530 | goto err_dev; | |
531 | } | |
532 | ||
533 | /* Configure the hardware. */ | |
534 | mxs_lradc_hw_init(lradc); | |
535 | ||
536 | return 0; | |
537 | ||
538 | err_dev: | |
539 | mxs_lradc_trigger_remove(iio); | |
540 | err_trig: | |
541 | iio_triggered_buffer_cleanup(iio); | |
542 | err_addr: | |
543 | iio_device_free(iio); | |
544 | return ret; | |
545 | } | |
546 | ||
447d4f29 | 547 | static int mxs_lradc_remove(struct platform_device *pdev) |
bc2c90c9 MV |
548 | { |
549 | struct iio_dev *iio = platform_get_drvdata(pdev); | |
550 | struct mxs_lradc *lradc = iio_priv(iio); | |
551 | ||
552 | mxs_lradc_hw_stop(lradc); | |
553 | ||
554 | iio_device_unregister(iio); | |
555 | iio_triggered_buffer_cleanup(iio); | |
556 | mxs_lradc_trigger_remove(iio); | |
557 | iio_device_free(iio); | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | static const struct of_device_id mxs_lradc_dt_ids[] = { | |
563 | { .compatible = "fsl,imx28-lradc", }, | |
564 | { /* sentinel */ } | |
565 | }; | |
566 | MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids); | |
567 | ||
568 | static struct platform_driver mxs_lradc_driver = { | |
569 | .driver = { | |
570 | .name = DRIVER_NAME, | |
571 | .owner = THIS_MODULE, | |
572 | .of_match_table = mxs_lradc_dt_ids, | |
573 | }, | |
574 | .probe = mxs_lradc_probe, | |
e543acf0 | 575 | .remove = mxs_lradc_remove, |
bc2c90c9 MV |
576 | }; |
577 | ||
578 | module_platform_driver(mxs_lradc_driver); | |
579 | ||
580 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | |
581 | MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver"); | |
582 | MODULE_LICENSE("GPL v2"); |