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Commit | Line | Data |
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54c5be34 BS |
1 | /* |
2 | * AD7150 capacitive sensor driver supporting AD7150/1/6 | |
3 | * | |
4e687ddb | 4 | * Copyright 2010-2011 Analog Devices Inc. |
54c5be34 BS |
5 | * |
6 | * Licensed under the GPL-2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/interrupt.h> | |
54c5be34 BS |
10 | #include <linux/device.h> |
11 | #include <linux/kernel.h> | |
12 | #include <linux/slab.h> | |
54c5be34 | 13 | #include <linux/i2c.h> |
99c97852 | 14 | #include <linux/module.h> |
54c5be34 | 15 | |
06458e27 JC |
16 | #include <linux/iio/iio.h> |
17 | #include <linux/iio/sysfs.h> | |
18 | #include <linux/iio/events.h> | |
54c5be34 BS |
19 | /* |
20 | * AD7150 registers definition | |
21 | */ | |
22 | ||
23 | #define AD7150_STATUS 0 | |
24 | #define AD7150_STATUS_OUT1 (1 << 3) | |
25 | #define AD7150_STATUS_OUT2 (1 << 5) | |
26 | #define AD7150_CH1_DATA_HIGH 1 | |
54c5be34 | 27 | #define AD7150_CH2_DATA_HIGH 3 |
54c5be34 | 28 | #define AD7150_CH1_AVG_HIGH 5 |
54c5be34 | 29 | #define AD7150_CH2_AVG_HIGH 7 |
54c5be34 BS |
30 | #define AD7150_CH1_SENSITIVITY 9 |
31 | #define AD7150_CH1_THR_HOLD_H 9 | |
32 | #define AD7150_CH1_TIMEOUT 10 | |
54c5be34 BS |
33 | #define AD7150_CH1_SETUP 11 |
34 | #define AD7150_CH2_SENSITIVITY 12 | |
35 | #define AD7150_CH2_THR_HOLD_H 12 | |
36 | #define AD7150_CH2_TIMEOUT 13 | |
54c5be34 BS |
37 | #define AD7150_CH2_SETUP 14 |
38 | #define AD7150_CFG 15 | |
39 | #define AD7150_CFG_FIX (1 << 7) | |
40 | #define AD7150_PD_TIMER 16 | |
41 | #define AD7150_CH1_CAPDAC 17 | |
42 | #define AD7150_CH2_CAPDAC 18 | |
43 | #define AD7150_SN3 19 | |
44 | #define AD7150_SN2 20 | |
45 | #define AD7150_SN1 21 | |
46 | #define AD7150_SN0 22 | |
47 | #define AD7150_ID 23 | |
48 | ||
531efd6a JC |
49 | /** |
50 | * struct ad7150_chip_info - instance specific chip data | |
51 | * @client: i2c client for this device | |
52 | * @current_event: device always has one type of event enabled. | |
53 | * This element stores the event code of the current one. | |
54 | * @threshold: thresholds for simple capacitance value events | |
55 | * @thresh_sensitivity: threshold for simple capacitance offset | |
56 | * from 'average' value. | |
57 | * @mag_sensitity: threshold for magnitude of capacitance offset from | |
58 | * from 'average' value. | |
59 | * @thresh_timeout: a timeout, in samples from the moment an | |
60 | * adaptive threshold event occurs to when the average | |
61 | * value jumps to current value. | |
62 | * @mag_timeout: a timeout, in sample from the moment an | |
63 | * adaptive magnitude event occurs to when the average | |
64 | * value jumps to the current value. | |
65 | * @old_state: store state from previous event, allowing confirmation | |
66 | * of new condition. | |
67 | * @conversion_mode: the current conversion mode. | |
68 | * @state_lock: ensure consistent state of this structure wrt the | |
69 | * hardware. | |
70 | */ | |
54c5be34 | 71 | struct ad7150_chip_info { |
54c5be34 | 72 | struct i2c_client *client; |
531efd6a JC |
73 | u64 current_event; |
74 | u16 threshold[2][2]; | |
75 | u8 thresh_sensitivity[2][2]; | |
76 | u8 mag_sensitivity[2][2]; | |
77 | u8 thresh_timeout[2][2]; | |
78 | u8 mag_timeout[2][2]; | |
54c5be34 BS |
79 | int old_state; |
80 | char *conversion_mode; | |
531efd6a | 81 | struct mutex state_lock; |
54c5be34 BS |
82 | }; |
83 | ||
54c5be34 BS |
84 | /* |
85 | * sysfs nodes | |
86 | */ | |
87 | ||
531efd6a JC |
88 | static const u8 ad7150_addresses[][6] = { |
89 | { AD7150_CH1_DATA_HIGH, AD7150_CH1_AVG_HIGH, | |
90 | AD7150_CH1_SETUP, AD7150_CH1_THR_HOLD_H, | |
91 | AD7150_CH1_SENSITIVITY, AD7150_CH1_TIMEOUT }, | |
92 | { AD7150_CH2_DATA_HIGH, AD7150_CH2_AVG_HIGH, | |
93 | AD7150_CH2_SETUP, AD7150_CH2_THR_HOLD_H, | |
94 | AD7150_CH2_SENSITIVITY, AD7150_CH2_TIMEOUT }, | |
95 | }; | |
54c5be34 | 96 | |
531efd6a JC |
97 | static int ad7150_read_raw(struct iio_dev *indio_dev, |
98 | struct iio_chan_spec const *chan, | |
99 | int *val, | |
100 | int *val2, | |
101 | long mask) | |
54c5be34 | 102 | { |
54c5be34 | 103 | int ret; |
531efd6a | 104 | struct ad7150_chip_info *chip = iio_priv(indio_dev); |
54c5be34 | 105 | |
531efd6a | 106 | switch (mask) { |
e33e0750 | 107 | case IIO_CHAN_INFO_RAW: |
531efd6a JC |
108 | ret = i2c_smbus_read_word_data(chip->client, |
109 | ad7150_addresses[chan->channel][0]); | |
110 | if (ret < 0) | |
111 | return ret; | |
112 | *val = swab16(ret); | |
113 | return IIO_VAL_INT; | |
c8a9f805 | 114 | case IIO_CHAN_INFO_AVERAGE_RAW: |
531efd6a JC |
115 | ret = i2c_smbus_read_word_data(chip->client, |
116 | ad7150_addresses[chan->channel][1]); | |
117 | if (ret < 0) | |
118 | return ret; | |
119 | *val = swab16(ret); | |
120 | return IIO_VAL_INT; | |
121 | default: | |
122 | return -EINVAL; | |
54c5be34 | 123 | } |
54c5be34 BS |
124 | } |
125 | ||
1489d629 LPC |
126 | static int ad7150_read_event_config(struct iio_dev *indio_dev, |
127 | const struct iio_chan_spec *chan, enum iio_event_type type, | |
128 | enum iio_event_direction dir) | |
54c5be34 | 129 | { |
54c5be34 | 130 | int ret; |
531efd6a JC |
131 | u8 threshtype; |
132 | bool adaptive; | |
133 | struct ad7150_chip_info *chip = iio_priv(indio_dev); | |
54c5be34 | 134 | |
531efd6a JC |
135 | ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG); |
136 | if (ret < 0) | |
137 | return ret; | |
54c5be34 | 138 | |
531efd6a JC |
139 | threshtype = (ret >> 5) & 0x03; |
140 | adaptive = !!(ret & 0x80); | |
141 | ||
1489d629 | 142 | switch (type) { |
531efd6a | 143 | case IIO_EV_TYPE_MAG_ADAPTIVE: |
1489d629 | 144 | if (dir == IIO_EV_DIR_RISING) |
531efd6a JC |
145 | return adaptive && (threshtype == 0x1); |
146 | else | |
147 | return adaptive && (threshtype == 0x0); | |
148 | case IIO_EV_TYPE_THRESH_ADAPTIVE: | |
1489d629 | 149 | if (dir == IIO_EV_DIR_RISING) |
531efd6a JC |
150 | return adaptive && (threshtype == 0x3); |
151 | else | |
152 | return adaptive && (threshtype == 0x2); | |
153 | ||
154 | case IIO_EV_TYPE_THRESH: | |
1489d629 | 155 | if (dir == IIO_EV_DIR_RISING) |
531efd6a JC |
156 | return !adaptive && (threshtype == 0x1); |
157 | else | |
158 | return !adaptive && (threshtype == 0x0); | |
1489d629 LPC |
159 | default: |
160 | break; | |
73327b4c | 161 | } |
54c5be34 BS |
162 | return -EINVAL; |
163 | } | |
164 | ||
531efd6a | 165 | /* lock should be held */ |
1489d629 LPC |
166 | static int ad7150_write_event_params(struct iio_dev *indio_dev, |
167 | unsigned int chan, enum iio_event_type type, | |
168 | enum iio_event_direction dir) | |
54c5be34 | 169 | { |
54c5be34 | 170 | int ret; |
531efd6a JC |
171 | u16 value; |
172 | u8 sens, timeout; | |
173 | struct ad7150_chip_info *chip = iio_priv(indio_dev); | |
1489d629 LPC |
174 | int rising = (dir == IIO_EV_DIR_RISING); |
175 | u64 event_code; | |
176 | ||
177 | event_code = IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, chan, type, dir); | |
531efd6a JC |
178 | |
179 | if (event_code != chip->current_event) | |
180 | return 0; | |
181 | ||
1489d629 | 182 | switch (type) { |
531efd6a JC |
183 | /* Note completely different from the adaptive versions */ |
184 | case IIO_EV_TYPE_THRESH: | |
185 | value = chip->threshold[rising][chan]; | |
186 | ret = i2c_smbus_write_word_data(chip->client, | |
187 | ad7150_addresses[chan][3], | |
188 | swab16(value)); | |
189 | if (ret < 0) | |
190 | return ret; | |
191 | return 0; | |
192 | case IIO_EV_TYPE_MAG_ADAPTIVE: | |
193 | sens = chip->mag_sensitivity[rising][chan]; | |
194 | timeout = chip->mag_timeout[rising][chan]; | |
195 | break; | |
196 | case IIO_EV_TYPE_THRESH_ADAPTIVE: | |
197 | sens = chip->thresh_sensitivity[rising][chan]; | |
198 | timeout = chip->thresh_timeout[rising][chan]; | |
199 | break; | |
200 | default: | |
201 | return -EINVAL; | |
73327b4c | 202 | } |
531efd6a JC |
203 | ret = i2c_smbus_write_byte_data(chip->client, |
204 | ad7150_addresses[chan][4], | |
205 | sens); | |
206 | if (ret < 0) | |
207 | return ret; | |
54c5be34 | 208 | |
531efd6a JC |
209 | ret = i2c_smbus_write_byte_data(chip->client, |
210 | ad7150_addresses[chan][5], | |
211 | timeout); | |
212 | if (ret < 0) | |
213 | return ret; | |
54c5be34 | 214 | |
531efd6a | 215 | return 0; |
54c5be34 BS |
216 | } |
217 | ||
531efd6a | 218 | static int ad7150_write_event_config(struct iio_dev *indio_dev, |
1489d629 LPC |
219 | const struct iio_chan_spec *chan, enum iio_event_type type, |
220 | enum iio_event_direction dir, int state) | |
54c5be34 | 221 | { |
531efd6a | 222 | u8 thresh_type, cfg, adaptive; |
54c5be34 | 223 | int ret; |
531efd6a | 224 | struct ad7150_chip_info *chip = iio_priv(indio_dev); |
1489d629 LPC |
225 | int rising = (dir == IIO_EV_DIR_RISING); |
226 | u64 event_code; | |
54c5be34 | 227 | |
531efd6a JC |
228 | /* Something must always be turned on */ |
229 | if (state == 0) | |
230 | return -EINVAL; | |
54c5be34 | 231 | |
1489d629 | 232 | event_code = IIO_UNMOD_EVENT_CODE(chan->type, chan->channel, type, dir); |
531efd6a JC |
233 | if (event_code == chip->current_event) |
234 | return 0; | |
235 | mutex_lock(&chip->state_lock); | |
236 | ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG); | |
237 | if (ret < 0) | |
238 | goto error_ret; | |
54c5be34 | 239 | |
531efd6a JC |
240 | cfg = ret & ~((0x03 << 5) | (0x1 << 7)); |
241 | ||
1489d629 | 242 | switch (type) { |
531efd6a JC |
243 | case IIO_EV_TYPE_MAG_ADAPTIVE: |
244 | adaptive = 1; | |
245 | if (rising) | |
246 | thresh_type = 0x1; | |
247 | else | |
248 | thresh_type = 0x0; | |
249 | break; | |
250 | case IIO_EV_TYPE_THRESH_ADAPTIVE: | |
251 | adaptive = 1; | |
252 | if (rising) | |
253 | thresh_type = 0x3; | |
254 | else | |
255 | thresh_type = 0x2; | |
256 | break; | |
257 | case IIO_EV_TYPE_THRESH: | |
258 | adaptive = 0; | |
259 | if (rising) | |
260 | thresh_type = 0x1; | |
261 | else | |
262 | thresh_type = 0x0; | |
263 | break; | |
264 | default: | |
265 | ret = -EINVAL; | |
266 | goto error_ret; | |
73327b4c | 267 | } |
54c5be34 | 268 | |
531efd6a | 269 | cfg |= (!adaptive << 7) | (thresh_type << 5); |
54c5be34 | 270 | |
531efd6a JC |
271 | ret = i2c_smbus_write_byte_data(chip->client, AD7150_CFG, cfg); |
272 | if (ret < 0) | |
273 | goto error_ret; | |
54c5be34 | 274 | |
531efd6a | 275 | chip->current_event = event_code; |
54c5be34 | 276 | |
531efd6a | 277 | /* update control attributes */ |
1489d629 | 278 | ret = ad7150_write_event_params(indio_dev, chan->channel, type, dir); |
531efd6a JC |
279 | error_ret: |
280 | mutex_unlock(&chip->state_lock); | |
54c5be34 | 281 | |
531efd6a | 282 | return 0; |
54c5be34 BS |
283 | } |
284 | ||
531efd6a | 285 | static int ad7150_read_event_value(struct iio_dev *indio_dev, |
1489d629 LPC |
286 | const struct iio_chan_spec *chan, |
287 | enum iio_event_type type, | |
288 | enum iio_event_direction dir, | |
289 | enum iio_event_info info, | |
290 | int *val, int *val2) | |
54c5be34 | 291 | { |
531efd6a | 292 | struct ad7150_chip_info *chip = iio_priv(indio_dev); |
1489d629 | 293 | int rising = (dir == IIO_EV_DIR_RISING); |
54c5be34 | 294 | |
531efd6a | 295 | /* Complex register sharing going on here */ |
1489d629 | 296 | switch (type) { |
531efd6a | 297 | case IIO_EV_TYPE_MAG_ADAPTIVE: |
1489d629 LPC |
298 | *val = chip->mag_sensitivity[rising][chan->channel]; |
299 | return IIO_VAL_INT; | |
531efd6a | 300 | case IIO_EV_TYPE_THRESH_ADAPTIVE: |
1489d629 LPC |
301 | *val = chip->thresh_sensitivity[rising][chan->channel]; |
302 | return IIO_VAL_INT; | |
531efd6a | 303 | case IIO_EV_TYPE_THRESH: |
1489d629 LPC |
304 | *val = chip->threshold[rising][chan->channel]; |
305 | return IIO_VAL_INT; | |
531efd6a JC |
306 | default: |
307 | return -EINVAL; | |
a22526e4 | 308 | } |
54c5be34 BS |
309 | } |
310 | ||
531efd6a | 311 | static int ad7150_write_event_value(struct iio_dev *indio_dev, |
1489d629 LPC |
312 | const struct iio_chan_spec *chan, |
313 | enum iio_event_type type, | |
314 | enum iio_event_direction dir, | |
315 | enum iio_event_info info, | |
316 | int val, int val2) | |
54c5be34 | 317 | { |
54c5be34 | 318 | int ret; |
531efd6a | 319 | struct ad7150_chip_info *chip = iio_priv(indio_dev); |
1489d629 | 320 | int rising = (dir == IIO_EV_DIR_RISING); |
531efd6a JC |
321 | |
322 | mutex_lock(&chip->state_lock); | |
1489d629 | 323 | switch (type) { |
531efd6a | 324 | case IIO_EV_TYPE_MAG_ADAPTIVE: |
1489d629 | 325 | chip->mag_sensitivity[rising][chan->channel] = val; |
531efd6a JC |
326 | break; |
327 | case IIO_EV_TYPE_THRESH_ADAPTIVE: | |
1489d629 | 328 | chip->thresh_sensitivity[rising][chan->channel] = val; |
531efd6a JC |
329 | break; |
330 | case IIO_EV_TYPE_THRESH: | |
1489d629 | 331 | chip->threshold[rising][chan->channel] = val; |
531efd6a JC |
332 | break; |
333 | default: | |
334 | ret = -EINVAL; | |
335 | goto error_ret; | |
73327b4c | 336 | } |
54c5be34 | 337 | |
531efd6a | 338 | /* write back if active */ |
1489d629 | 339 | ret = ad7150_write_event_params(indio_dev, chan->channel, type, dir); |
54c5be34 | 340 | |
531efd6a | 341 | error_ret: |
ee760ab2 | 342 | mutex_unlock(&chip->state_lock); |
531efd6a | 343 | return ret; |
54c5be34 BS |
344 | } |
345 | ||
531efd6a JC |
346 | static ssize_t ad7150_show_timeout(struct device *dev, |
347 | struct device_attribute *attr, | |
348 | char *buf) | |
54c5be34 | 349 | { |
d30a7f9d | 350 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
84f79ecb | 351 | struct ad7150_chip_info *chip = iio_priv(indio_dev); |
531efd6a JC |
352 | struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); |
353 | u8 value; | |
354 | ||
355 | /* use the event code for consistency reasons */ | |
da367160 | 356 | int chan = IIO_EVENT_CODE_EXTRACT_CHAN(this_attr->address); |
531efd6a JC |
357 | int rising = !!(IIO_EVENT_CODE_EXTRACT_DIR(this_attr->address) |
358 | == IIO_EV_DIR_RISING); | |
359 | ||
360 | switch (IIO_EVENT_CODE_EXTRACT_TYPE(this_attr->address)) { | |
361 | case IIO_EV_TYPE_MAG_ADAPTIVE: | |
362 | value = chip->mag_timeout[rising][chan]; | |
363 | break; | |
364 | case IIO_EV_TYPE_THRESH_ADAPTIVE: | |
365 | value = chip->thresh_timeout[rising][chan]; | |
366 | break; | |
367 | default: | |
368 | return -EINVAL; | |
73327b4c | 369 | } |
54c5be34 | 370 | |
531efd6a | 371 | return sprintf(buf, "%d\n", value); |
54c5be34 BS |
372 | } |
373 | ||
531efd6a | 374 | static ssize_t ad7150_store_timeout(struct device *dev, |
54c5be34 BS |
375 | struct device_attribute *attr, |
376 | const char *buf, | |
377 | size_t len) | |
378 | { | |
d30a7f9d | 379 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
531efd6a JC |
380 | struct ad7150_chip_info *chip = iio_priv(indio_dev); |
381 | struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); | |
da367160 | 382 | int chan = IIO_EVENT_CODE_EXTRACT_CHAN(this_attr->address); |
1489d629 LPC |
383 | enum iio_event_direction dir; |
384 | enum iio_event_type type; | |
385 | int rising; | |
531efd6a | 386 | u8 data; |
54c5be34 BS |
387 | int ret; |
388 | ||
1489d629 LPC |
389 | type = IIO_EVENT_CODE_EXTRACT_TYPE(this_attr->address); |
390 | dir = IIO_EVENT_CODE_EXTRACT_DIR(this_attr->address); | |
391 | rising = (dir == IIO_EV_DIR_RISING); | |
392 | ||
531efd6a JC |
393 | ret = kstrtou8(buf, 10, &data); |
394 | if (ret < 0) | |
395 | return ret; | |
54c5be34 | 396 | |
531efd6a | 397 | mutex_lock(&chip->state_lock); |
1489d629 | 398 | switch (type) { |
531efd6a JC |
399 | case IIO_EV_TYPE_MAG_ADAPTIVE: |
400 | chip->mag_timeout[rising][chan] = data; | |
401 | break; | |
402 | case IIO_EV_TYPE_THRESH_ADAPTIVE: | |
403 | chip->thresh_timeout[rising][chan] = data; | |
404 | break; | |
405 | default: | |
406 | ret = -EINVAL; | |
407 | goto error_ret; | |
73327b4c | 408 | } |
54c5be34 | 409 | |
1489d629 | 410 | ret = ad7150_write_event_params(indio_dev, chan, type, dir); |
531efd6a JC |
411 | error_ret: |
412 | mutex_unlock(&chip->state_lock); | |
54c5be34 | 413 | |
531efd6a JC |
414 | if (ret < 0) |
415 | return ret; | |
54c5be34 | 416 | |
531efd6a | 417 | return len; |
54c5be34 BS |
418 | } |
419 | ||
531efd6a JC |
420 | #define AD7150_TIMEOUT(chan, type, dir, ev_type, ev_dir) \ |
421 | IIO_DEVICE_ATTR(in_capacitance##chan##_##type##_##dir##_timeout, \ | |
422 | S_IRUGO | S_IWUSR, \ | |
423 | &ad7150_show_timeout, \ | |
424 | &ad7150_store_timeout, \ | |
425 | IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, \ | |
426 | chan, \ | |
427 | IIO_EV_TYPE_##ev_type, \ | |
428 | IIO_EV_DIR_##ev_dir)) | |
429 | static AD7150_TIMEOUT(0, mag_adaptive, rising, MAG_ADAPTIVE, RISING); | |
430 | static AD7150_TIMEOUT(0, mag_adaptive, falling, MAG_ADAPTIVE, FALLING); | |
431 | static AD7150_TIMEOUT(1, mag_adaptive, rising, MAG_ADAPTIVE, RISING); | |
432 | static AD7150_TIMEOUT(1, mag_adaptive, falling, MAG_ADAPTIVE, FALLING); | |
433 | static AD7150_TIMEOUT(0, thresh_adaptive, rising, THRESH_ADAPTIVE, RISING); | |
434 | static AD7150_TIMEOUT(0, thresh_adaptive, falling, THRESH_ADAPTIVE, FALLING); | |
435 | static AD7150_TIMEOUT(1, thresh_adaptive, rising, THRESH_ADAPTIVE, RISING); | |
436 | static AD7150_TIMEOUT(1, thresh_adaptive, falling, THRESH_ADAPTIVE, FALLING); | |
437 | ||
1489d629 LPC |
438 | static const struct iio_event_spec ad7150_events[] = { |
439 | { | |
440 | .type = IIO_EV_TYPE_THRESH, | |
441 | .dir = IIO_EV_DIR_RISING, | |
442 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | | |
443 | BIT(IIO_EV_INFO_ENABLE), | |
444 | }, { | |
445 | .type = IIO_EV_TYPE_THRESH, | |
446 | .dir = IIO_EV_DIR_FALLING, | |
447 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | | |
448 | BIT(IIO_EV_INFO_ENABLE), | |
449 | }, { | |
450 | .type = IIO_EV_TYPE_THRESH_ADAPTIVE, | |
451 | .dir = IIO_EV_DIR_RISING, | |
452 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | | |
453 | BIT(IIO_EV_INFO_ENABLE), | |
454 | }, { | |
455 | .type = IIO_EV_TYPE_THRESH_ADAPTIVE, | |
456 | .dir = IIO_EV_DIR_FALLING, | |
457 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | | |
458 | BIT(IIO_EV_INFO_ENABLE), | |
459 | }, { | |
460 | .type = IIO_EV_TYPE_MAG_ADAPTIVE, | |
461 | .dir = IIO_EV_DIR_RISING, | |
462 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | | |
463 | BIT(IIO_EV_INFO_ENABLE), | |
464 | }, { | |
465 | .type = IIO_EV_TYPE_MAG_ADAPTIVE, | |
466 | .dir = IIO_EV_DIR_FALLING, | |
467 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | | |
468 | BIT(IIO_EV_INFO_ENABLE), | |
469 | }, | |
470 | }; | |
471 | ||
531efd6a JC |
472 | static const struct iio_chan_spec ad7150_channels[] = { |
473 | { | |
474 | .type = IIO_CAPACITANCE, | |
475 | .indexed = 1, | |
476 | .channel = 0, | |
02215195 JC |
477 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | |
478 | BIT(IIO_CHAN_INFO_AVERAGE_RAW), | |
1489d629 LPC |
479 | .event_spec = ad7150_events, |
480 | .num_event_specs = ARRAY_SIZE(ad7150_events), | |
531efd6a JC |
481 | }, { |
482 | .type = IIO_CAPACITANCE, | |
483 | .indexed = 1, | |
484 | .channel = 1, | |
02215195 JC |
485 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | |
486 | BIT(IIO_CHAN_INFO_AVERAGE_RAW), | |
1489d629 LPC |
487 | .event_spec = ad7150_events, |
488 | .num_event_specs = ARRAY_SIZE(ad7150_events), | |
531efd6a JC |
489 | }, |
490 | }; | |
54c5be34 | 491 | |
54c5be34 BS |
492 | /* |
493 | * threshold events | |
494 | */ | |
495 | ||
9b5d9b06 | 496 | static irqreturn_t ad7150_event_handler(int irq, void *private) |
54c5be34 | 497 | { |
9b5d9b06 | 498 | struct iio_dev *indio_dev = private; |
46a6af38 | 499 | struct ad7150_chip_info *chip = iio_priv(indio_dev); |
54c5be34 | 500 | u8 int_status; |
9b5d9b06 | 501 | s64 timestamp = iio_get_time_ns(); |
531efd6a | 502 | int ret; |
54c5be34 | 503 | |
531efd6a JC |
504 | ret = i2c_smbus_read_byte_data(chip->client, AD7150_STATUS); |
505 | if (ret < 0) | |
506 | return IRQ_HANDLED; | |
507 | ||
508 | int_status = ret; | |
54c5be34 | 509 | |
5aa96188 JC |
510 | if ((int_status & AD7150_STATUS_OUT1) && |
511 | !(chip->old_state & AD7150_STATUS_OUT1)) | |
512 | iio_push_event(indio_dev, | |
1b992320 | 513 | IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, |
d91a0ab0 JC |
514 | 0, |
515 | IIO_EV_TYPE_THRESH, | |
516 | IIO_EV_DIR_RISING), | |
9b5d9b06 | 517 | timestamp); |
5aa96188 JC |
518 | else if ((!(int_status & AD7150_STATUS_OUT1)) && |
519 | (chip->old_state & AD7150_STATUS_OUT1)) | |
520 | iio_push_event(indio_dev, | |
1b992320 | 521 | IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, |
d91a0ab0 JC |
522 | 0, |
523 | IIO_EV_TYPE_THRESH, | |
524 | IIO_EV_DIR_FALLING), | |
525 | timestamp); | |
54c5be34 | 526 | |
5aa96188 JC |
527 | if ((int_status & AD7150_STATUS_OUT2) && |
528 | !(chip->old_state & AD7150_STATUS_OUT2)) | |
529 | iio_push_event(indio_dev, | |
1b992320 | 530 | IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, |
d91a0ab0 JC |
531 | 1, |
532 | IIO_EV_TYPE_THRESH, | |
533 | IIO_EV_DIR_RISING), | |
534 | timestamp); | |
5aa96188 JC |
535 | else if ((!(int_status & AD7150_STATUS_OUT2)) && |
536 | (chip->old_state & AD7150_STATUS_OUT2)) | |
537 | iio_push_event(indio_dev, | |
1b992320 | 538 | IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, |
d91a0ab0 JC |
539 | 1, |
540 | IIO_EV_TYPE_THRESH, | |
541 | IIO_EV_DIR_FALLING), | |
542 | timestamp); | |
531efd6a JC |
543 | /* store the status to avoid repushing same events */ |
544 | chip->old_state = int_status; | |
545 | ||
9b5d9b06 | 546 | return IRQ_HANDLED; |
54c5be34 BS |
547 | } |
548 | ||
531efd6a | 549 | /* Timeouts not currently handled by core */ |
54c5be34 | 550 | static struct attribute *ad7150_event_attributes[] = { |
531efd6a JC |
551 | &iio_dev_attr_in_capacitance0_mag_adaptive_rising_timeout |
552 | .dev_attr.attr, | |
553 | &iio_dev_attr_in_capacitance0_mag_adaptive_falling_timeout | |
554 | .dev_attr.attr, | |
555 | &iio_dev_attr_in_capacitance1_mag_adaptive_rising_timeout | |
556 | .dev_attr.attr, | |
557 | &iio_dev_attr_in_capacitance1_mag_adaptive_falling_timeout | |
558 | .dev_attr.attr, | |
559 | &iio_dev_attr_in_capacitance0_thresh_adaptive_rising_timeout | |
560 | .dev_attr.attr, | |
561 | &iio_dev_attr_in_capacitance0_thresh_adaptive_falling_timeout | |
562 | .dev_attr.attr, | |
563 | &iio_dev_attr_in_capacitance1_thresh_adaptive_rising_timeout | |
564 | .dev_attr.attr, | |
565 | &iio_dev_attr_in_capacitance1_thresh_adaptive_falling_timeout | |
566 | .dev_attr.attr, | |
54c5be34 BS |
567 | NULL, |
568 | }; | |
569 | ||
570 | static struct attribute_group ad7150_event_attribute_group = { | |
571 | .attrs = ad7150_event_attributes, | |
8e7d9672 | 572 | .name = "events", |
54c5be34 BS |
573 | }; |
574 | ||
6fe8135f | 575 | static const struct iio_info ad7150_info = { |
6fe8135f JC |
576 | .event_attrs = &ad7150_event_attribute_group, |
577 | .driver_module = THIS_MODULE, | |
531efd6a | 578 | .read_raw = &ad7150_read_raw, |
cb955852 LPC |
579 | .read_event_config = &ad7150_read_event_config, |
580 | .write_event_config = &ad7150_write_event_config, | |
581 | .read_event_value = &ad7150_read_event_value, | |
582 | .write_event_value = &ad7150_write_event_value, | |
6fe8135f | 583 | }; |
531efd6a | 584 | |
54c5be34 BS |
585 | /* |
586 | * device probe and remove | |
587 | */ | |
588 | ||
4ae1c61f | 589 | static int ad7150_probe(struct i2c_client *client, |
54c5be34 BS |
590 | const struct i2c_device_id *id) |
591 | { | |
26d25ae3 | 592 | int ret; |
46a6af38 JC |
593 | struct ad7150_chip_info *chip; |
594 | struct iio_dev *indio_dev; | |
595 | ||
d15b73c5 SK |
596 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip)); |
597 | if (!indio_dev) | |
598 | return -ENOMEM; | |
46a6af38 | 599 | chip = iio_priv(indio_dev); |
531efd6a | 600 | mutex_init(&chip->state_lock); |
54c5be34 | 601 | /* this is only used for device removal purposes */ |
46a6af38 | 602 | i2c_set_clientdata(client, indio_dev); |
54c5be34 BS |
603 | |
604 | chip->client = client; | |
54c5be34 | 605 | |
46a6af38 | 606 | indio_dev->name = id->name; |
531efd6a JC |
607 | indio_dev->channels = ad7150_channels; |
608 | indio_dev->num_channels = ARRAY_SIZE(ad7150_channels); | |
609 | /* Establish that the iio_dev is a child of the i2c device */ | |
46a6af38 | 610 | indio_dev->dev.parent = &client->dev; |
6fe8135f | 611 | |
46a6af38 | 612 | indio_dev->info = &ad7150_info; |
6fe8135f | 613 | |
46a6af38 | 614 | indio_dev->modes = INDIO_DIRECT_MODE; |
54c5be34 | 615 | |
9b5d9b06 | 616 | if (client->irq) { |
d15b73c5 | 617 | ret = devm_request_threaded_irq(&client->dev, client->irq, |
9b5d9b06 JC |
618 | NULL, |
619 | &ad7150_event_handler, | |
620 | IRQF_TRIGGER_RISING | | |
a91aff1c LPC |
621 | IRQF_TRIGGER_FALLING | |
622 | IRQF_ONESHOT, | |
4e687ddb | 623 | "ad7150_irq1", |
46a6af38 | 624 | indio_dev); |
54c5be34 | 625 | if (ret) |
d15b73c5 | 626 | return ret; |
54c5be34 BS |
627 | } |
628 | ||
4e687ddb | 629 | if (client->dev.platform_data) { |
d15b73c5 | 630 | ret = devm_request_threaded_irq(&client->dev, *(unsigned int *) |
4e687ddb MH |
631 | client->dev.platform_data, |
632 | NULL, | |
633 | &ad7150_event_handler, | |
634 | IRQF_TRIGGER_RISING | | |
a91aff1c LPC |
635 | IRQF_TRIGGER_FALLING | |
636 | IRQF_ONESHOT, | |
4e687ddb MH |
637 | "ad7150_irq2", |
638 | indio_dev); | |
639 | if (ret) | |
d15b73c5 | 640 | return ret; |
4e687ddb MH |
641 | } |
642 | ||
26d25ae3 JC |
643 | ret = iio_device_register(indio_dev); |
644 | if (ret) | |
d15b73c5 | 645 | return ret; |
26d25ae3 | 646 | |
531efd6a JC |
647 | dev_info(&client->dev, "%s capacitive sensor registered,irq: %d\n", |
648 | id->name, client->irq); | |
54c5be34 BS |
649 | |
650 | return 0; | |
54c5be34 BS |
651 | } |
652 | ||
447d4f29 | 653 | static int ad7150_remove(struct i2c_client *client) |
54c5be34 | 654 | { |
46a6af38 | 655 | struct iio_dev *indio_dev = i2c_get_clientdata(client); |
54c5be34 | 656 | |
d2fffd6c | 657 | iio_device_unregister(indio_dev); |
54c5be34 BS |
658 | |
659 | return 0; | |
660 | } | |
661 | ||
662 | static const struct i2c_device_id ad7150_id[] = { | |
663 | { "ad7150", 0 }, | |
664 | { "ad7151", 0 }, | |
665 | { "ad7156", 0 }, | |
666 | {} | |
667 | }; | |
668 | ||
669 | MODULE_DEVICE_TABLE(i2c, ad7150_id); | |
670 | ||
671 | static struct i2c_driver ad7150_driver = { | |
672 | .driver = { | |
673 | .name = "ad7150", | |
674 | }, | |
675 | .probe = ad7150_probe, | |
e543acf0 | 676 | .remove = ad7150_remove, |
54c5be34 BS |
677 | .id_table = ad7150_id, |
678 | }; | |
6e5af184 | 679 | module_i2c_driver(ad7150_driver); |
54c5be34 BS |
680 | |
681 | MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>"); | |
4e687ddb | 682 | MODULE_DESCRIPTION("Analog Devices AD7150/1/6 capacitive sensor driver"); |
54c5be34 | 683 | MODULE_LICENSE("GPL v2"); |