[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / iio / dac / ad5064.c

/*
 * AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1 Digital to analog converters
 * driver
 *
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>

#include "../iio.h"
#include "../sysfs.h"
#include "dac.h"

#define AD5064_MAX_DAC_CHANNELS			4
#define AD5064_MAX_VREFS			4

#define AD5064_ADDR(x)				((x) << 20)
#define AD5064_CMD(x)				((x) << 24)

#define AD5064_ADDR_DAC(chan)			(chan)
#define AD5064_ADDR_ALL_DAC			0xF

#define AD5064_CMD_WRITE_INPUT_N		0x0
#define AD5064_CMD_UPDATE_DAC_N			0x1
#define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL	0x2
#define AD5064_CMD_WRITE_INPUT_N_UPDATE_N	0x3
#define AD5064_CMD_POWERDOWN_DAC		0x4
#define AD5064_CMD_CLEAR			0x5
#define AD5064_CMD_LDAC_MASK			0x6
#define AD5064_CMD_RESET			0x7
#define AD5064_CMD_DAISY_CHAIN_ENABLE		0x8

#define AD5064_LDAC_PWRDN_NONE			0x0
#define AD5064_LDAC_PWRDN_1K			0x1
#define AD5064_LDAC_PWRDN_100K			0x2
#define AD5064_LDAC_PWRDN_3STATE		0x3

/**
 * struct ad5064_chip_info - chip specific information
 * @shared_vref:	whether the vref supply is shared between channels
 * @channel:		channel specification
 * @num_channels:	number of channels
 */

struct ad5064_chip_info {
	bool shared_vref;
	const struct iio_chan_spec *channels;
	unsigned int num_channels;
};

/**
 * struct ad5064_state - driver instance specific data
 * @spi:		spi_device
 * @chip_info:		chip model specific constants, available modes etc
 * @vref_reg:		vref supply regulators
 * @pwr_down:		whether channel is powered down
 * @pwr_down_mode:	channel's current power down mode
 * @dac_cache:		current DAC raw value (chip does not support readback)
 * @data:		spi transfer buffers
 */

struct ad5064_state {
	struct spi_device		*spi;
	const struct ad5064_chip_info	*chip_info;
	struct regulator_bulk_data	vref_reg[AD5064_MAX_VREFS];
	bool				pwr_down[AD5064_MAX_DAC_CHANNELS];
	u8				pwr_down_mode[AD5064_MAX_DAC_CHANNELS];
	unsigned int			dac_cache[AD5064_MAX_DAC_CHANNELS];

	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 */
	__be32 data ____cacheline_aligned;
};

enum ad5064_type {
	ID_AD5024,
	ID_AD5025,
	ID_AD5044,
	ID_AD5045,
	ID_AD5064,
	ID_AD5064_1,
	ID_AD5065,
};

static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd,
	unsigned int addr, unsigned int val, unsigned int shift)
{
	val <<= shift;

	st->data = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val);

	return spi_write(st->spi, &st->data, sizeof(st->data));
}

static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
	unsigned int channel)
{
	unsigned int val;
	int ret;

	val = (0x1 << channel);

	if (st->pwr_down[channel])
		val |= st->pwr_down_mode[channel] << 8;

	ret = ad5064_spi_write(st, AD5064_CMD_POWERDOWN_DAC, 0, val, 0);

	return ret;
}

static const char ad5064_powerdown_modes[][15] = {
	[AD5064_LDAC_PWRDN_NONE]	= "",
	[AD5064_LDAC_PWRDN_1K]		= "1kohm_to_gnd",
	[AD5064_LDAC_PWRDN_100K]	= "100kohm_to_gnd",
	[AD5064_LDAC_PWRDN_3STATE]	= "three_state",
};

static ssize_t ad5064_read_powerdown_mode_available(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, char *buf)
{
	return sprintf(buf, "%s %s %s\n", ad5064_powerdown_modes[1],
		ad5064_powerdown_modes[2], ad5064_powerdown_modes[3]);
}

static ssize_t ad5064_read_powerdown_mode(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, char *buf)
{
	struct ad5064_state *st = iio_priv(indio_dev);

	return sprintf(buf, "%s\n",
		ad5064_powerdown_modes[st->pwr_down_mode[chan->channel]]);
}

static ssize_t ad5064_write_powerdown_mode(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, const char *buf, size_t len)
{
	struct ad5064_state *st = iio_priv(indio_dev);
	unsigned int mode, i;
	int ret;

	mode = 0;

	for (i = 1; i < ARRAY_SIZE(ad5064_powerdown_modes); ++i) {
		if (sysfs_streq(buf, ad5064_powerdown_modes[i])) {
			mode = i;
			break;
		}
	}
	if (mode == 0)
		return  -EINVAL;

	mutex_lock(&indio_dev->mlock);
	st->pwr_down_mode[chan->channel] = mode;

	ret = ad5064_sync_powerdown_mode(st, chan->channel);
	mutex_unlock(&indio_dev->mlock);

	return ret ? ret : len;
}

static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, char *buf)
{
	struct ad5064_state *st = iio_priv(indio_dev);

	return sprintf(buf, "%d\n", st->pwr_down[chan->channel]);
}

static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, const char *buf, size_t len)
{
	struct ad5064_state *st = iio_priv(indio_dev);
	bool pwr_down;
	int ret;

	ret = strtobool(buf, &pwr_down);
	if (ret)
		return ret;

	mutex_lock(&indio_dev->mlock);
	st->pwr_down[chan->channel] = pwr_down;

	ret = ad5064_sync_powerdown_mode(st, chan->channel);
	mutex_unlock(&indio_dev->mlock);
	return ret ? ret : len;
}

static int ad5064_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	struct ad5064_state *st = iio_priv(indio_dev);
	unsigned int vref;
	int scale_uv;

	switch (m) {
	case 0:
		*val = st->dac_cache[chan->channel];
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		vref = st->chip_info->shared_vref ? 0 : chan->channel;
		scale_uv = regulator_get_voltage(st->vref_reg[vref].consumer);
		if (scale_uv < 0)
			return scale_uv;

		scale_uv = (scale_uv * 100) >> chan->scan_type.realbits;
		*val =  scale_uv / 100000;
		*val2 = (scale_uv % 100000) * 10;
		return IIO_VAL_INT_PLUS_MICRO;
	default:
		break;
	}
	return -EINVAL;
}

static int ad5064_write_raw(struct iio_dev *indio_dev,
	struct iio_chan_spec const *chan, int val, int val2, long mask)
{
	struct ad5064_state *st = iio_priv(indio_dev);
	int ret;

	switch (mask) {
	case 0:
		if (val > (1 << chan->scan_type.realbits) || val < 0)
			return -EINVAL;

		mutex_lock(&indio_dev->mlock);
		ret = ad5064_spi_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N,
				chan->address, val, chan->scan_type.shift);
		if (ret == 0)
			st->dac_cache[chan->channel] = val;
		mutex_unlock(&indio_dev->mlock);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static const struct iio_info ad5064_info = {
	.read_raw = ad5064_read_raw,
	.write_raw = ad5064_write_raw,
	.driver_module = THIS_MODULE,
};

static struct iio_chan_spec_ext_info ad5064_ext_info[] = {
	{
		.name = "powerdown",
		.read = ad5064_read_dac_powerdown,
		.write = ad5064_write_dac_powerdown,
	},
	{
		.name = "powerdown_mode",
		.read = ad5064_read_powerdown_mode,
		.write = ad5064_write_powerdown_mode,
	},
	{
		.name = "powerdown_mode_available",
		.shared = true,
		.read = ad5064_read_powerdown_mode_available,
	},
	{ },
};

#define AD5064_CHANNEL(chan, bits) {				\
	.type = IIO_VOLTAGE,					\
	.indexed = 1,						\
	.output = 1,						\
	.channel = (chan),					\
	.info_mask = IIO_CHAN_INFO_SCALE_SEPARATE_BIT,	\
	.address = AD5064_ADDR_DAC(chan),			\
	.scan_type = IIO_ST('u', (bits), 16, 20 - (bits)),	\
	.ext_info = ad5064_ext_info,				\
}

#define DECLARE_AD5064_CHANNELS(name, bits) \
const struct iio_chan_spec name[] = { \
	AD5064_CHANNEL(0, bits), \
	AD5064_CHANNEL(1, bits), \
	AD5064_CHANNEL(2, bits), \
	AD5064_CHANNEL(3, bits), \
}

static DECLARE_AD5064_CHANNELS(ad5024_channels, 12);
static DECLARE_AD5064_CHANNELS(ad5044_channels, 14);
static DECLARE_AD5064_CHANNELS(ad5064_channels, 16);

static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
	[ID_AD5024] = {
		.shared_vref = false,
		.channels = ad5024_channels,
		.num_channels = 4,
	},
	[ID_AD5025] = {
		.shared_vref = false,
		.channels = ad5024_channels,
		.num_channels = 2,
	},
	[ID_AD5044] = {
		.shared_vref = false,
		.channels = ad5044_channels,
		.num_channels = 4,
	},
	[ID_AD5045] = {
		.shared_vref = false,
		.channels = ad5044_channels,
		.num_channels = 2,
	},
	[ID_AD5064] = {
		.shared_vref = false,
		.channels = ad5064_channels,
		.num_channels = 4,
	},
	[ID_AD5064_1] = {
		.shared_vref = true,
		.channels = ad5064_channels,
		.num_channels = 4,
	},
	[ID_AD5065] = {
		.shared_vref = false,
		.channels = ad5064_channels,
		.num_channels = 2,
	},
};

static inline unsigned int ad5064_num_vref(struct ad5064_state *st)
{
	return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels;
}

static const char * const ad5064_vref_names[] = {
	"vrefA",
	"vrefB",
	"vrefC",
	"vrefD",
};

static const char * const ad5064_vref_name(struct ad5064_state *st,
	unsigned int vref)
{
	return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
}

static int __devinit ad5064_probe(struct spi_device *spi)
{
	enum ad5064_type type = spi_get_device_id(spi)->driver_data;
	struct iio_dev *indio_dev;
	struct ad5064_state *st;
	unsigned int i;
	int ret;

	indio_dev = iio_allocate_device(sizeof(*st));
	if (indio_dev == NULL)
		return  -ENOMEM;

	st = iio_priv(indio_dev);
	spi_set_drvdata(spi, indio_dev);

	st->chip_info = &ad5064_chip_info_tbl[type];
	st->spi = spi;

	for (i = 0; i < ad5064_num_vref(st); ++i)
		st->vref_reg[i].supply = ad5064_vref_name(st, i);

	ret = regulator_bulk_get(&st->spi->dev, ad5064_num_vref(st),
		st->vref_reg);
	if (ret)
		goto error_free;

	ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg);
	if (ret)
		goto error_free_reg;

	for (i = 0; i < st->chip_info->num_channels; ++i) {
		st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K;
		st->dac_cache[i] = 0x8000;
	}

	indio_dev->dev.parent = &spi->dev;
	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->info = &ad5064_info;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = st->chip_info->channels;
	indio_dev->num_channels = st->chip_info->num_channels;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_disable_reg;

	return 0;

error_disable_reg:
	regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
error_free_reg:
	regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
error_free:
	iio_free_device(indio_dev);

	return ret;
}


static int __devexit ad5064_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad5064_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);

	regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
	regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);

	iio_free_device(indio_dev);

	return 0;
}

static const struct spi_device_id ad5064_id[] = {
	{"ad5024", ID_AD5024},
	{"ad5025", ID_AD5025},
	{"ad5044", ID_AD5044},
	{"ad5045", ID_AD5045},
	{"ad5064", ID_AD5064},
	{"ad5064-1", ID_AD5064_1},
	{"ad5065", ID_AD5065},
	{}
};
MODULE_DEVICE_TABLE(spi, ad5064_id);

static struct spi_driver ad5064_driver = {
	.driver = {
		   .name = "ad5064",
		   .owner = THIS_MODULE,
	},
	.probe = ad5064_probe,
	.remove = __devexit_p(ad5064_remove),
	.id_table = ad5064_id,
};
module_spi_driver(ad5064_driver);

MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_DESCRIPTION("Analog Devices AD5024/25/44/45/64/64-1/65 DAC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
fcf265d6	1	/*
f8be4af1 LPC	2	* AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1 Digital to analog converters
f8be4af1 LPC	3	* driver
fcf265d6 LPC	4	*
	5	* Copyright 2011 Analog Devices Inc.
	6	*
	7	* Licensed under the GPL-2.
	8	*/
	9
	10	#include <linux/device.h>
	11	#include <linux/err.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/spi/spi.h>
	15	#include <linux/slab.h>
	16	#include <linux/sysfs.h>
	17	#include <linux/regulator/consumer.h>
	18
	19	#include "../iio.h"
	20	#include "../sysfs.h"
	21	#include "dac.h"
	22
83c169d5 LPC	23	#define AD5064_MAX_DAC_CHANNELS 4
83c169d5 LPC	24	#define AD5064_MAX_VREFS 4
fcf265d6 LPC	25
	26	#define AD5064_ADDR(x) ((x) << 20)
	27	#define AD5064_CMD(x) ((x) << 24)
	28
	29	#define AD5064_ADDR_DAC(chan) (chan)
	30	#define AD5064_ADDR_ALL_DAC 0xF
	31
	32	#define AD5064_CMD_WRITE_INPUT_N 0x0
	33	#define AD5064_CMD_UPDATE_DAC_N 0x1
	34	#define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
	35	#define AD5064_CMD_WRITE_INPUT_N_UPDATE_N 0x3
	36	#define AD5064_CMD_POWERDOWN_DAC 0x4
	37	#define AD5064_CMD_CLEAR 0x5
	38	#define AD5064_CMD_LDAC_MASK 0x6
	39	#define AD5064_CMD_RESET 0x7
	40	#define AD5064_CMD_DAISY_CHAIN_ENABLE 0x8
	41
	42	#define AD5064_LDAC_PWRDN_NONE 0x0
	43	#define AD5064_LDAC_PWRDN_1K 0x1
	44	#define AD5064_LDAC_PWRDN_100K 0x2
	45	#define AD5064_LDAC_PWRDN_3STATE 0x3
	46
	47	/**
	48	* struct ad5064_chip_info - chip specific information
	49	* @shared_vref: whether the vref supply is shared between channels
	50	* @channel: channel specification
83c169d5 LPC	51	* @num_channels: number of channels
83c169d5 LPC	52	*/
fcf265d6 LPC	53
	54	struct ad5064_chip_info {
	55	bool shared_vref;
83c169d5 LPC	56	const struct iio_chan_spec *channels;
83c169d5 LPC	57	unsigned int num_channels;
fcf265d6 LPC	58	};
	59
	60	/**
	61	* struct ad5064_state - driver instance specific data
	62	* @spi: spi_device
	63	* @chip_info: chip model specific constants, available modes etc
	64	* @vref_reg: vref supply regulators
	65	* @pwr_down: whether channel is powered down
	66	* @pwr_down_mode: channel's current power down mode
	67	* @dac_cache: current DAC raw value (chip does not support readback)
	68	* @data: spi transfer buffers
	69	*/
	70
	71	struct ad5064_state {
	72	struct spi_device *spi;
	73	const struct ad5064_chip_info *chip_info;
83c169d5 LPC	74	struct regulator_bulk_data vref_reg[AD5064_MAX_VREFS];
	75	bool pwr_down[AD5064_MAX_DAC_CHANNELS];
	76	u8 pwr_down_mode[AD5064_MAX_DAC_CHANNELS];
	77	unsigned int dac_cache[AD5064_MAX_DAC_CHANNELS];
fcf265d6 LPC	78
	79	/*
	80	* DMA (thus cache coherency maintenance) requires the
	81	* transfer buffers to live in their own cache lines.
	82	*/
	83	__be32 data ____cacheline_aligned;
	84	};
	85
	86	enum ad5064_type {
	87	ID_AD5024,
f8be4af1	88	ID_AD5025,
fcf265d6	89	ID_AD5044,
f8be4af1	90	ID_AD5045,
fcf265d6 LPC	91	ID_AD5064,
fcf265d6 LPC	92	ID_AD5064_1,
f8be4af1	93	ID_AD5065,
fcf265d6 LPC	94	};
fcf265d6 LPC	95
fcf265d6 LPC	96	static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd,
	97	unsigned int addr, unsigned int val, unsigned int shift)
	98	{
	99	val <<= shift;
	100
	101	st->data = cpu_to_be32(AD5064_CMD(cmd) \| AD5064_ADDR(addr) \| val);
	102
	103	return spi_write(st->spi, &st->data, sizeof(st->data));
	104	}
	105
	106	static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
	107	unsigned int channel)
	108	{
	109	unsigned int val;
	110	int ret;
	111
	112	val = (0x1 << channel);
	113
	114	if (st->pwr_down[channel])
	115	val \|= st->pwr_down_mode[channel] << 8;
	116
	117	ret = ad5064_spi_write(st, AD5064_CMD_POWERDOWN_DAC, 0, val, 0);
	118
	119	return ret;
	120	}
	121
	122	static const char ad5064_powerdown_modes[][15] = {
	123	[AD5064_LDAC_PWRDN_NONE] = "",
	124	[AD5064_LDAC_PWRDN_1K] = "1kohm_to_gnd",
	125	[AD5064_LDAC_PWRDN_100K] = "100kohm_to_gnd",
	126	[AD5064_LDAC_PWRDN_3STATE] = "three_state",
	127	};
	128
1d0d8794 LPC	129	static ssize_t ad5064_read_powerdown_mode_available(struct iio_dev *indio_dev,
	130	const struct iio_chan_spec chan, char buf)
	131	{
	132	return sprintf(buf, "%s %s %s\n", ad5064_powerdown_modes[1],
	133	ad5064_powerdown_modes[2], ad5064_powerdown_modes[3]);
	134	}
	135
	136	static ssize_t ad5064_read_powerdown_mode(struct iio_dev *indio_dev,
	137	const struct iio_chan_spec chan, char buf)
fcf265d6	138	{
fcf265d6 LPC	139	struct ad5064_state *st = iio_priv(indio_dev);
	140
	141	return sprintf(buf, "%s\n",
1d0d8794	142	ad5064_powerdown_modes[st->pwr_down_mode[chan->channel]]);
fcf265d6 LPC	143	}
fcf265d6 LPC	144
1d0d8794 LPC	145	static ssize_t ad5064_write_powerdown_mode(struct iio_dev *indio_dev,
1d0d8794 LPC	146	const struct iio_chan_spec chan, const char buf, size_t len)
fcf265d6	147	{
fcf265d6 LPC	148	struct ad5064_state *st = iio_priv(indio_dev);
	149	unsigned int mode, i;
	150	int ret;
	151
	152	mode = 0;
	153
	154	for (i = 1; i < ARRAY_SIZE(ad5064_powerdown_modes); ++i) {
	155	if (sysfs_streq(buf, ad5064_powerdown_modes[i])) {
	156	mode = i;
	157	break;
	158	}
	159	}
	160	if (mode == 0)
	161	return -EINVAL;
	162
	163	mutex_lock(&indio_dev->mlock);
1d0d8794	164	st->pwr_down_mode[chan->channel] = mode;
fcf265d6	165
1d0d8794	166	ret = ad5064_sync_powerdown_mode(st, chan->channel);
fcf265d6 LPC	167	mutex_unlock(&indio_dev->mlock);
	168
	169	return ret ? ret : len;
	170	}
	171
1d0d8794 LPC	172	static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
1d0d8794 LPC	173	const struct iio_chan_spec chan, char buf)
fcf265d6	174	{
fcf265d6	175	struct ad5064_state *st = iio_priv(indio_dev);
fcf265d6	176
1d0d8794	177	return sprintf(buf, "%d\n", st->pwr_down[chan->channel]);
fcf265d6 LPC	178	}
fcf265d6 LPC	179
1d0d8794 LPC	180	static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev,
1d0d8794 LPC	181	const struct iio_chan_spec chan, const char buf, size_t len)
fcf265d6	182	{
fcf265d6	183	struct ad5064_state *st = iio_priv(indio_dev);
fcf265d6 LPC	184	bool pwr_down;
	185	int ret;
	186
	187	ret = strtobool(buf, &pwr_down);
	188	if (ret)
	189	return ret;
	190
	191	mutex_lock(&indio_dev->mlock);
1d0d8794	192	st->pwr_down[chan->channel] = pwr_down;
fcf265d6	193
1d0d8794	194	ret = ad5064_sync_powerdown_mode(st, chan->channel);
fcf265d6 LPC	195	mutex_unlock(&indio_dev->mlock);
	196	return ret ? ret : len;
	197	}
	198
fcf265d6 LPC	199	static int ad5064_read_raw(struct iio_dev *indio_dev,
	200	struct iio_chan_spec const *chan,
	201	int *val,
	202	int *val2,
	203	long m)
	204	{
	205	struct ad5064_state *st = iio_priv(indio_dev);
fcf265d6	206	unsigned int vref;
23a3b8cc	207	int scale_uv;
fcf265d6 LPC	208
	209	switch (m) {
	210	case 0:
	211	*val = st->dac_cache[chan->channel];
	212	return IIO_VAL_INT;
c8a9f805	213	case IIO_CHAN_INFO_SCALE:
fcf265d6 LPC	214	vref = st->chip_info->shared_vref ? 0 : chan->channel;
	215	scale_uv = regulator_get_voltage(st->vref_reg[vref].consumer);
	216	if (scale_uv < 0)
	217	return scale_uv;
	218
	219	scale_uv = (scale_uv * 100) >> chan->scan_type.realbits;
	220	*val = scale_uv / 100000;
	221	val2 = (scale_uv % 100000) 10;
	222	return IIO_VAL_INT_PLUS_MICRO;
	223	default:
	224	break;
	225	}
	226	return -EINVAL;
	227	}
	228
	229	static int ad5064_write_raw(struct iio_dev *indio_dev,
	230	struct iio_chan_spec const *chan, int val, int val2, long mask)
	231	{
	232	struct ad5064_state *st = iio_priv(indio_dev);
	233	int ret;
	234
	235	switch (mask) {
	236	case 0:
	237	if (val > (1 << chan->scan_type.realbits) \|\| val < 0)
	238	return -EINVAL;
	239
	240	mutex_lock(&indio_dev->mlock);
	241	ret = ad5064_spi_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N,
	242	chan->address, val, chan->scan_type.shift);
	243	if (ret == 0)
	244	st->dac_cache[chan->channel] = val;
	245	mutex_unlock(&indio_dev->mlock);
	246	break;
	247	default:
	248	ret = -EINVAL;
	249	}
	250
	251	return ret;
	252	}
	253
	254	static const struct iio_info ad5064_info = {
	255	.read_raw = ad5064_read_raw,
	256	.write_raw = ad5064_write_raw,
fcf265d6 LPC	257	.driver_module = THIS_MODULE,
	258	};
	259
1d0d8794 LPC	260	static struct iio_chan_spec_ext_info ad5064_ext_info[] = {
	261	{
	262	.name = "powerdown",
	263	.read = ad5064_read_dac_powerdown,
	264	.write = ad5064_write_dac_powerdown,
	265	},
	266	{
	267	.name = "powerdown_mode",
	268	.read = ad5064_read_powerdown_mode,
	269	.write = ad5064_write_powerdown_mode,
	270	},
	271	{
	272	.name = "powerdown_mode_available",
	273	.shared = true,
	274	.read = ad5064_read_powerdown_mode_available,
	275	},
	276	{ },
	277	};
	278
	279	#define AD5064_CHANNEL(chan, bits) { \
	280	.type = IIO_VOLTAGE, \
	281	.indexed = 1, \
	282	.output = 1, \
	283	.channel = (chan), \
	284	.info_mask = IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \
	285	.address = AD5064_ADDR_DAC(chan), \
	286	.scan_type = IIO_ST('u', (bits), 16, 20 - (bits)), \
	287	.ext_info = ad5064_ext_info, \
	288	}
	289
83c169d5 LPC	290	#define DECLARE_AD5064_CHANNELS(name, bits) \
	291	const struct iio_chan_spec name[] = { \
	292	AD5064_CHANNEL(0, bits), \
	293	AD5064_CHANNEL(1, bits), \
	294	AD5064_CHANNEL(2, bits), \
	295	AD5064_CHANNEL(3, bits), \
	296	}
	297
	298	static DECLARE_AD5064_CHANNELS(ad5024_channels, 12);
	299	static DECLARE_AD5064_CHANNELS(ad5044_channels, 14);
	300	static DECLARE_AD5064_CHANNELS(ad5064_channels, 16);
	301
1d0d8794 LPC	302	static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
	303	[ID_AD5024] = {
	304	.shared_vref = false,
83c169d5 LPC	305	.channels = ad5024_channels,
83c169d5 LPC	306	.num_channels = 4,
1d0d8794	307	},
f8be4af1 LPC	308	[ID_AD5025] = {
	309	.shared_vref = false,
	310	.channels = ad5024_channels,
	311	.num_channels = 2,
	312	},
1d0d8794 LPC	313	[ID_AD5044] = {
1d0d8794 LPC	314	.shared_vref = false,
83c169d5 LPC	315	.channels = ad5044_channels,
83c169d5 LPC	316	.num_channels = 4,
1d0d8794	317	},
f8be4af1 LPC	318	[ID_AD5045] = {
	319	.shared_vref = false,
	320	.channels = ad5044_channels,
	321	.num_channels = 2,
	322	},
1d0d8794 LPC	323	[ID_AD5064] = {
1d0d8794 LPC	324	.shared_vref = false,
83c169d5 LPC	325	.channels = ad5064_channels,
83c169d5 LPC	326	.num_channels = 4,
1d0d8794 LPC	327	},
	328	[ID_AD5064_1] = {
	329	.shared_vref = true,
83c169d5 LPC	330	.channels = ad5064_channels,
83c169d5 LPC	331	.num_channels = 4,
1d0d8794	332	},
f8be4af1 LPC	333	[ID_AD5065] = {
	334	.shared_vref = false,
	335	.channels = ad5064_channels,
	336	.num_channels = 2,
	337	},
1d0d8794 LPC	338	};
1d0d8794 LPC	339
fcf265d6 LPC	340	static inline unsigned int ad5064_num_vref(struct ad5064_state *st)
fcf265d6 LPC	341	{
83c169d5	342	return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels;
fcf265d6 LPC	343	}
	344
	345	static const char * const ad5064_vref_names[] = {
	346	"vrefA",
	347	"vrefB",
	348	"vrefC",
	349	"vrefD",
	350	};
	351
	352	static const char * const ad5064_vref_name(struct ad5064_state *st,
	353	unsigned int vref)
	354	{
	355	return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
	356	}
	357
	358	static int __devinit ad5064_probe(struct spi_device *spi)
	359	{
	360	enum ad5064_type type = spi_get_device_id(spi)->driver_data;
	361	struct iio_dev *indio_dev;
	362	struct ad5064_state *st;
	363	unsigned int i;
	364	int ret;
	365
	366	indio_dev = iio_allocate_device(sizeof(*st));
	367	if (indio_dev == NULL)
	368	return -ENOMEM;
	369
	370	st = iio_priv(indio_dev);
	371	spi_set_drvdata(spi, indio_dev);
	372
	373	st->chip_info = &ad5064_chip_info_tbl[type];
	374	st->spi = spi;
	375
	376	for (i = 0; i < ad5064_num_vref(st); ++i)
	377	st->vref_reg[i].supply = ad5064_vref_name(st, i);
	378
	379	ret = regulator_bulk_get(&st->spi->dev, ad5064_num_vref(st),
	380	st->vref_reg);
	381	if (ret)
	382	goto error_free;
	383
	384	ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg);
	385	if (ret)
	386	goto error_free_reg;
	387
83c169d5	388	for (i = 0; i < st->chip_info->num_channels; ++i) {
fcf265d6 LPC	389	st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K;
	390	st->dac_cache[i] = 0x8000;
	391	}
	392
	393	indio_dev->dev.parent = &spi->dev;
	394	indio_dev->name = spi_get_device_id(spi)->name;
	395	indio_dev->info = &ad5064_info;
	396	indio_dev->modes = INDIO_DIRECT_MODE;
83c169d5 LPC	397	indio_dev->channels = st->chip_info->channels;
83c169d5 LPC	398	indio_dev->num_channels = st->chip_info->num_channels;
fcf265d6 LPC	399
	400	ret = iio_device_register(indio_dev);
	401	if (ret)
	402	goto error_disable_reg;
	403
	404	return 0;
	405
	406	error_disable_reg:
	407	regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
	408	error_free_reg:
	409	regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
	410	error_free:
	411	iio_free_device(indio_dev);
	412
	413	return ret;
	414	}
	415
	416
	417	static int __devexit ad5064_remove(struct spi_device *spi)
	418	{
	419	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	420	struct ad5064_state *st = iio_priv(indio_dev);
	421
	422	iio_device_unregister(indio_dev);
	423
	424	regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
	425	regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
	426
	427	iio_free_device(indio_dev);
	428
	429	return 0;
	430	}
	431
	432	static const struct spi_device_id ad5064_id[] = {
	433	{"ad5024", ID_AD5024},
f8be4af1	434	{"ad5025", ID_AD5025},
fcf265d6	435	{"ad5044", ID_AD5044},
f8be4af1	436	{"ad5045", ID_AD5045},
fcf265d6 LPC	437	{"ad5064", ID_AD5064},
fcf265d6 LPC	438	{"ad5064-1", ID_AD5064_1},
f8be4af1	439	{"ad5065", ID_AD5065},
fcf265d6 LPC	440	{}
	441	};
	442	MODULE_DEVICE_TABLE(spi, ad5064_id);
	443
	444	static struct spi_driver ad5064_driver = {
	445	.driver = {
	446	.name = "ad5064",
	447	.owner = THIS_MODULE,
	448	},
	449	.probe = ad5064_probe,
	450	.remove = __devexit_p(ad5064_remove),
	451	.id_table = ad5064_id,
	452	};
ae6ae6fe	453	module_spi_driver(ad5064_driver);
fcf265d6 LPC	454
fcf265d6 LPC	455	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
f8be4af1	456	MODULE_DESCRIPTION("Analog Devices AD5024/25/44/45/64/64-1/65 DAC");
fcf265d6	457	MODULE_LICENSE("GPL v2");