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aecfbdb1 SH |
1 | /* |
2 | * Copyright 2005-2009 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU Lesser General | |
5 | * Public License. You may obtain a copy of the GNU Lesser General | |
6 | * Public License Version 2.1 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/lgpl-license.html | |
9 | * http://www.gnu.org/copyleft/lgpl.html | |
10 | */ | |
11 | ||
12 | #ifndef __DRM_IPU_H__ | |
13 | #define __DRM_IPU_H__ | |
14 | ||
15 | #include <linux/types.h> | |
16 | #include <linux/videodev2.h> | |
17 | #include <linux/bitmap.h> | |
18 | #include <linux/fb.h> | |
aecfbdb1 SH |
19 | |
20 | struct ipu_soc; | |
21 | ||
22 | enum ipuv3_type { | |
23 | IPUV3EX, | |
24 | IPUV3M, | |
25 | IPUV3H, | |
26 | }; | |
27 | ||
28 | /* | |
29 | * Bitfield of Display Interface signal polarities. | |
30 | */ | |
31 | struct ipu_di_signal_cfg { | |
32 | unsigned datamask_en:1; | |
33 | unsigned interlaced:1; | |
34 | unsigned odd_field_first:1; | |
35 | unsigned clksel_en:1; | |
36 | unsigned clkidle_en:1; | |
37 | unsigned data_pol:1; /* true = inverted */ | |
38 | unsigned clk_pol:1; /* true = rising edge */ | |
39 | unsigned enable_pol:1; | |
40 | unsigned Hsync_pol:1; /* true = active high */ | |
41 | unsigned Vsync_pol:1; | |
42 | ||
43 | u16 width; | |
44 | u16 height; | |
45 | u32 pixel_fmt; | |
46 | u16 h_start_width; | |
47 | u16 h_sync_width; | |
48 | u16 h_end_width; | |
49 | u16 v_start_width; | |
50 | u16 v_sync_width; | |
51 | u16 v_end_width; | |
52 | u32 v_to_h_sync; | |
53 | unsigned long pixelclock; | |
54 | #define IPU_DI_CLKMODE_SYNC (1 << 0) | |
55 | #define IPU_DI_CLKMODE_EXT (1 << 1) | |
56 | unsigned long clkflags; | |
2ea42608 PZ |
57 | |
58 | u8 hsync_pin; | |
59 | u8 vsync_pin; | |
aecfbdb1 SH |
60 | }; |
61 | ||
62 | enum ipu_color_space { | |
63 | IPUV3_COLORSPACE_RGB, | |
64 | IPUV3_COLORSPACE_YUV, | |
65 | IPUV3_COLORSPACE_UNKNOWN, | |
66 | }; | |
67 | ||
68 | struct ipuv3_channel; | |
69 | ||
70 | enum ipu_channel_irq { | |
71 | IPU_IRQ_EOF = 0, | |
72 | IPU_IRQ_NFACK = 64, | |
73 | IPU_IRQ_NFB4EOF = 128, | |
74 | IPU_IRQ_EOS = 192, | |
75 | }; | |
76 | ||
77 | int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, | |
78 | enum ipu_channel_irq irq); | |
79 | ||
80 | #define IPU_IRQ_DP_SF_START (448 + 2) | |
81 | #define IPU_IRQ_DP_SF_END (448 + 3) | |
82 | #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END, | |
83 | #define IPU_IRQ_DC_FC_0 (448 + 8) | |
84 | #define IPU_IRQ_DC_FC_1 (448 + 9) | |
85 | #define IPU_IRQ_DC_FC_2 (448 + 10) | |
86 | #define IPU_IRQ_DC_FC_3 (448 + 11) | |
87 | #define IPU_IRQ_DC_FC_4 (448 + 12) | |
88 | #define IPU_IRQ_DC_FC_6 (448 + 13) | |
89 | #define IPU_IRQ_VSYNC_PRE_0 (448 + 14) | |
90 | #define IPU_IRQ_VSYNC_PRE_1 (448 + 15) | |
91 | ||
92 | /* | |
93 | * IPU Image DMA Controller (idmac) functions | |
94 | */ | |
95 | struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel); | |
96 | void ipu_idmac_put(struct ipuv3_channel *); | |
97 | ||
98 | int ipu_idmac_enable_channel(struct ipuv3_channel *channel); | |
99 | int ipu_idmac_disable_channel(struct ipuv3_channel *channel); | |
fb822a39 | 100 | int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms); |
aecfbdb1 SH |
101 | |
102 | void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, | |
103 | bool doublebuffer); | |
104 | void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num); | |
105 | ||
106 | /* | |
107 | * IPU Display Controller (dc) functions | |
108 | */ | |
109 | struct ipu_dc; | |
110 | struct ipu_di; | |
111 | struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel); | |
112 | void ipu_dc_put(struct ipu_dc *dc); | |
113 | int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, | |
114 | u32 pixel_fmt, u32 width); | |
115 | void ipu_dc_enable_channel(struct ipu_dc *dc); | |
116 | void ipu_dc_disable_channel(struct ipu_dc *dc); | |
117 | ||
118 | /* | |
119 | * IPU Display Interface (di) functions | |
120 | */ | |
121 | struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); | |
122 | void ipu_di_put(struct ipu_di *); | |
123 | int ipu_di_disable(struct ipu_di *); | |
124 | int ipu_di_enable(struct ipu_di *); | |
125 | int ipu_di_get_num(struct ipu_di *); | |
126 | int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig); | |
127 | ||
128 | /* | |
129 | * IPU Display Multi FIFO Controller (dmfc) functions | |
130 | */ | |
131 | struct dmfc_channel; | |
132 | int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc); | |
133 | void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc); | |
134 | int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc, | |
135 | unsigned long bandwidth_mbs, int burstsize); | |
136 | void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc); | |
137 | int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width); | |
138 | struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); | |
139 | void ipu_dmfc_put(struct dmfc_channel *dmfc); | |
140 | ||
141 | /* | |
142 | * IPU Display Processor (dp) functions | |
143 | */ | |
144 | #define IPU_DP_FLOW_SYNC_BG 0 | |
145 | #define IPU_DP_FLOW_SYNC_FG 1 | |
146 | #define IPU_DP_FLOW_ASYNC0_BG 2 | |
147 | #define IPU_DP_FLOW_ASYNC0_FG 3 | |
148 | #define IPU_DP_FLOW_ASYNC1_BG 4 | |
149 | #define IPU_DP_FLOW_ASYNC1_FG 5 | |
150 | ||
151 | struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); | |
152 | void ipu_dp_put(struct ipu_dp *); | |
153 | int ipu_dp_enable_channel(struct ipu_dp *dp); | |
154 | void ipu_dp_disable_channel(struct ipu_dp *dp); | |
155 | int ipu_dp_setup_channel(struct ipu_dp *dp, | |
156 | enum ipu_color_space in, enum ipu_color_space out); | |
157 | int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos); | |
158 | int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha, | |
159 | bool bg_chan); | |
160 | ||
161 | #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size)) | |
162 | ||
163 | #define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22) | |
164 | #define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22) | |
165 | #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4) | |
166 | #define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1) | |
167 | #define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1) | |
168 | #define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14) | |
169 | #define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14) | |
170 | ||
171 | #define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10) | |
172 | #define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9) | |
173 | #define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13) | |
174 | #define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12) | |
175 | #define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1) | |
176 | #define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1) | |
177 | #define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12) | |
178 | #define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11) | |
179 | #define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10) | |
180 | #define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7) | |
181 | #define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10) | |
182 | #define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1) | |
183 | #define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1) | |
184 | #define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7) | |
185 | #define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1) | |
186 | #define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1) | |
187 | #define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3) | |
188 | #define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2) | |
189 | #define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1) | |
190 | #define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3) | |
191 | #define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2) | |
192 | #define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1) | |
193 | #define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1) | |
194 | #define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1) | |
195 | #define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1) | |
196 | #define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1) | |
197 | #define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1) | |
198 | #define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13) | |
199 | #define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12) | |
200 | #define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29) | |
201 | #define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29) | |
202 | #define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20) | |
203 | #define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7) | |
204 | #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4) | |
205 | #define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1) | |
206 | #define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3) | |
207 | #define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2) | |
208 | #define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7) | |
209 | #define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14) | |
210 | #define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3) | |
211 | #define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3) | |
212 | #define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3) | |
213 | #define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3) | |
214 | #define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5) | |
215 | #define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5) | |
216 | #define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5) | |
217 | #define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5) | |
218 | #define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1) | |
219 | #define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1) | |
220 | #define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1) | |
221 | ||
222 | struct ipu_cpmem_word { | |
223 | u32 data[5]; | |
224 | u32 res[3]; | |
225 | }; | |
226 | ||
227 | struct ipu_ch_param { | |
228 | struct ipu_cpmem_word word[2]; | |
229 | }; | |
230 | ||
231 | void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v); | |
232 | u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs); | |
233 | struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel); | |
234 | void ipu_ch_param_dump(struct ipu_ch_param __iomem *p); | |
235 | ||
236 | static inline void ipu_ch_param_zero(struct ipu_ch_param __iomem *p) | |
237 | { | |
238 | int i; | |
239 | void __iomem *base = p; | |
240 | ||
241 | for (i = 0; i < sizeof(*p) / sizeof(u32); i++) | |
242 | writel(0, base + i * sizeof(u32)); | |
243 | } | |
244 | ||
245 | static inline void ipu_cpmem_set_buffer(struct ipu_ch_param __iomem *p, | |
246 | int bufnum, dma_addr_t buf) | |
247 | { | |
248 | if (bufnum) | |
249 | ipu_ch_param_write_field(p, IPU_FIELD_EBA1, buf >> 3); | |
250 | else | |
251 | ipu_ch_param_write_field(p, IPU_FIELD_EBA0, buf >> 3); | |
252 | } | |
253 | ||
254 | static inline void ipu_cpmem_set_resolution(struct ipu_ch_param __iomem *p, | |
255 | int xres, int yres) | |
256 | { | |
257 | ipu_ch_param_write_field(p, IPU_FIELD_FW, xres - 1); | |
258 | ipu_ch_param_write_field(p, IPU_FIELD_FH, yres - 1); | |
259 | } | |
260 | ||
261 | static inline void ipu_cpmem_set_stride(struct ipu_ch_param __iomem *p, | |
262 | int stride) | |
263 | { | |
264 | ipu_ch_param_write_field(p, IPU_FIELD_SLY, stride - 1); | |
265 | } | |
266 | ||
267 | void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel); | |
268 | ||
269 | struct ipu_rgb { | |
270 | struct fb_bitfield red; | |
271 | struct fb_bitfield green; | |
272 | struct fb_bitfield blue; | |
273 | struct fb_bitfield transp; | |
274 | int bits_per_pixel; | |
275 | }; | |
276 | ||
277 | struct ipu_image { | |
278 | struct v4l2_pix_format pix; | |
279 | struct v4l2_rect rect; | |
280 | dma_addr_t phys; | |
281 | }; | |
282 | ||
283 | int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p, | |
284 | int width); | |
285 | ||
286 | int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *, | |
e56af866 | 287 | const struct ipu_rgb *rgb); |
aecfbdb1 SH |
288 | |
289 | static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param *p, | |
290 | int stride) | |
291 | { | |
292 | ipu_ch_param_write_field(p, IPU_FIELD_SO, 1); | |
293 | ipu_ch_param_write_field(p, IPU_FIELD_ILO, stride / 8); | |
294 | ipu_ch_param_write_field(p, IPU_FIELD_SLY, (stride * 2) - 1); | |
295 | }; | |
296 | ||
297 | void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format, | |
298 | int stride, int height); | |
6cadd88a FE |
299 | void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p, |
300 | u32 pixel_format); | |
aecfbdb1 SH |
301 | void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p, |
302 | u32 pixel_format, int stride, int u_offset, int v_offset); | |
303 | int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat); | |
304 | int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem, | |
305 | struct ipu_image *image); | |
306 | ||
7cb17797 | 307 | enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc); |
aecfbdb1 SH |
308 | enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat); |
309 | ||
310 | static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem *p, | |
311 | int burstsize) | |
312 | { | |
313 | ipu_ch_param_write_field(p, IPU_FIELD_NPB, burstsize - 1); | |
314 | }; | |
315 | ||
316 | struct ipu_client_platformdata { | |
317 | int di; | |
318 | int dc; | |
319 | int dp; | |
320 | int dmfc; | |
321 | int dma[2]; | |
322 | }; | |
323 | ||
324 | #endif /* __DRM_IPU_H__ */ |