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1/**
2 * tpci200.h
3 *
4 * driver for the carrier TEWS TPCI-200
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5 *
6 * Copyright (C) 2009-2012 CERN (www.cern.ch)
7 * Author: Nicolas Serafini, EIC2 SA
8 * Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
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9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
b995069a 12 * Software Foundation; version 2 of the License.
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13 */
14
15#ifndef _TPCI200_H_
16#define _TPCI200_H_
17
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18#include <linux/limits.h>
19#include <linux/pci.h>
20#include <linux/spinlock.h>
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21#include <linux/swab.h>
22#include <linux/io.h>
23
24#include "../ipack.h"
25
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26#define TPCI200_NB_SLOT 0x4
27#define TPCI200_NB_BAR 0x6
28
29#define TPCI200_VENDOR_ID 0x1498
30#define TPCI200_DEVICE_ID 0x30C8
31#define TPCI200_SUBVENDOR_ID 0x1498
32#define TPCI200_SUBDEVICE_ID 0x300A
33
cea2f7cd 34#define TPCI200_CFG_MEM_BAR 0
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35#define TPCI200_IP_INTERFACE_BAR 2
36#define TPCI200_IO_ID_INT_SPACES_BAR 3
37#define TPCI200_MEM16_SPACE_BAR 4
38#define TPCI200_MEM8_SPACE_BAR 5
39
28086cbd 40struct tpci200_regs {
7dd73b86 41 __le16 revision;
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42 /* writes to control should occur with the mutex held to protect
43 * read-modify-write operations */
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44 __le16 control[4];
45 __le16 reset;
46 __le16 status;
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47 u8 reserved[242];
48} __packed;
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49
50#define TPCI200_IFACE_SIZE 0x100
51
52#define TPCI200_IO_SPACE_OFF 0x0000
6114aeaa 53#define TPCI200_IO_SPACE_INTERVAL 0x0100
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54#define TPCI200_IO_SPACE_SIZE 0x0080
55#define TPCI200_ID_SPACE_OFF 0x0080
6114aeaa 56#define TPCI200_ID_SPACE_INTERVAL 0x0100
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57#define TPCI200_ID_SPACE_SIZE 0x0040
58#define TPCI200_INT_SPACE_OFF 0x00C0
6114aeaa 59#define TPCI200_INT_SPACE_INTERVAL 0x0100
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60#define TPCI200_INT_SPACE_SIZE 0x0040
61#define TPCI200_IOIDINT_SIZE 0x0400
62
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63#define TPCI200_MEM8_SPACE_INTERVAL 0x00400000
64#define TPCI200_MEM8_SPACE_SIZE 0x00400000
65#define TPCI200_MEM16_SPACE_INTERVAL 0x00800000
66#define TPCI200_MEM16_SPACE_SIZE 0x00800000
0eeca14f 67
28086cbd 68/* control field in tpci200_regs */
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69#define TPCI200_INT0_EN 0x0040
70#define TPCI200_INT1_EN 0x0080
71#define TPCI200_INT0_EDGE 0x0010
72#define TPCI200_INT1_EDGE 0x0020
73#define TPCI200_ERR_INT_EN 0x0008
74#define TPCI200_TIME_INT_EN 0x0004
75#define TPCI200_RECOVER_EN 0x0002
76#define TPCI200_CLK32 0x0001
77
28086cbd 78/* reset field in tpci200_regs */
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79#define TPCI200_A_RESET 0x0001
80#define TPCI200_B_RESET 0x0002
81#define TPCI200_C_RESET 0x0004
82#define TPCI200_D_RESET 0x0008
83
28086cbd 84/* status field in tpci200_regs */
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85#define TPCI200_A_TIMEOUT 0x1000
86#define TPCI200_B_TIMEOUT 0x2000
87#define TPCI200_C_TIMEOUT 0x4000
88#define TPCI200_D_TIMEOUT 0x8000
89
90#define TPCI200_A_ERROR 0x0100
91#define TPCI200_B_ERROR 0x0200
92#define TPCI200_C_ERROR 0x0400
93#define TPCI200_D_ERROR 0x0800
94
95#define TPCI200_A_INT0 0x0001
96#define TPCI200_A_INT1 0x0002
97#define TPCI200_B_INT0 0x0004
98#define TPCI200_B_INT1 0x0008
99#define TPCI200_C_INT0 0x0010
100#define TPCI200_C_INT1 0x0020
101#define TPCI200_D_INT0 0x0040
102#define TPCI200_D_INT1 0x0080
103
104#define TPCI200_SLOT_INT_MASK 0x00FF
105
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106/* PCI Configuration registers. The PCI bridge is a PLX Technology PCI9030. */
107#define LAS1_DESC 0x2C
108#define LAS2_DESC 0x30
109
110/* Bits in the LAS?_DESC registers */
111#define LAS_BIT_BIGENDIAN 24
112
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113#define VME_IOID_SPACE "IOID"
114#define VME_MEM_SPACE "MEM"
115
116/**
117 * struct slot_irq - slot IRQ definition.
118 * @vector Vector number
119 * @handler Handler called when IRQ arrives
120 * @arg Handler argument
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121 *
122 */
123struct slot_irq {
6f2c12ae 124 struct ipack_device *holder;
611b564d 125 int vector;
faa75c40 126 irqreturn_t (*handler)(void *);
611b564d 127 void *arg;
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128};
129
130/**
131 * struct tpci200_slot - data specific to the tpci200 slot.
132 * @slot_id Slot identification gived to external interface
133 * @irq Slot IRQ infos
134 * @io_phys IO physical base address register of the slot
135 * @id_phys ID physical base address register of the slot
e4af9497 136 * @int_phys INT physical base address register of the slot
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137 * @mem_phys MEM physical base address register of the slot
138 *
139 */
140struct tpci200_slot {
bb29ab86 141 struct slot_irq *irq;
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142};
143
144/**
145 * struct tpci200_infos - informations specific of the TPCI200 tpci200.
146 * @pci_dev PCI device
147 * @interface_regs Pointer to IP interface space (Bar 2)
148 * @ioidint_space Pointer to IP ID, IO and INT space (Bar 3)
149 * @mem8_space Pointer to MEM space (Bar 4)
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150 *
151 */
152struct tpci200_infos {
153 struct pci_dev *pdev;
154 struct pci_device_id *id_table;
28086cbd 155 struct tpci200_regs __iomem *interface_regs;
cea2f7cd 156 void __iomem *cfg_regs;
ec440335 157 struct ipack_bus_device *ipack_bus;
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158};
159struct tpci200_board {
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160 unsigned int number;
161 struct mutex mutex;
487e0a60 162 spinlock_t regs_lock;
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163 struct tpci200_slot *slots;
164 struct tpci200_infos *info;
84a08fa9 165 phys_addr_t mod_mem[IPACK_SPACE_COUNT];
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166};
167
168#endif /* _TPCI200_H_ */