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a49d2536 AC |
1 | /* |
2 | * Support for OmniVision OV2680 5M camera sensor. | |
3 | * | |
4 | * Copyright (c) 2013 Intel Corporation. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License version | |
8 | * 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
18 | * 02110-1301, USA. | |
19 | * | |
20 | */ | |
21 | ||
22 | #ifndef __OV2680_H__ | |
23 | #define __OV2680_H__ | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/i2c.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/videodev2.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <media/v4l2-subdev.h> | |
31 | #include <media/v4l2-device.h> | |
32 | #include <media/v4l2-ctrls.h> | |
33 | #include <linux/v4l2-mediabus.h> | |
34 | #include <media/media-entity.h> | |
35 | ||
25016567 | 36 | #include "../include/linux/atomisp_platform.h" |
a49d2536 AC |
37 | |
38 | #define OV2680_NAME "ov2680" | |
39 | #define OV2680B_NAME "ov2680b" | |
40 | #define OV2680F_NAME "ov2680f" | |
41 | ||
42 | /* Defines for register writes and register array processing */ | |
43 | #define I2C_MSG_LENGTH 0x2 | |
44 | #define I2C_RETRY_COUNT 5 | |
45 | ||
46 | #define OV2680_FOCAL_LENGTH_NUM 334 /*3.34mm*/ | |
47 | #define OV2680_FOCAL_LENGTH_DEM 100 | |
48 | #define OV2680_F_NUMBER_DEFAULT_NUM 24 | |
49 | #define OV2680_F_NUMBER_DEM 10 | |
50 | ||
51 | #define OV2680_BIN_FACTOR_MAX 4 | |
52 | ||
53 | #define MAX_FMTS 1 | |
54 | ||
55 | /* sensor_mode_data read_mode adaptation */ | |
56 | #define OV2680_READ_MODE_BINNING_ON 0x0400 | |
57 | #define OV2680_READ_MODE_BINNING_OFF 0x00 | |
58 | #define OV2680_INTEGRATION_TIME_MARGIN 8 | |
59 | ||
60 | #define OV2680_MAX_EXPOSURE_VALUE 0xFFF1 | |
61 | #define OV2680_MAX_GAIN_VALUE 0xFF | |
62 | ||
63 | /* | |
64 | * focal length bits definition: | |
65 | * bits 31-16: numerator, bits 15-0: denominator | |
66 | */ | |
67 | #define OV2680_FOCAL_LENGTH_DEFAULT 0x1B70064 | |
68 | ||
69 | /* | |
70 | * current f-number bits definition: | |
71 | * bits 31-16: numerator, bits 15-0: denominator | |
72 | */ | |
73 | #define OV2680_F_NUMBER_DEFAULT 0x18000a | |
74 | ||
75 | /* | |
76 | * f-number range bits definition: | |
77 | * bits 31-24: max f-number numerator | |
78 | * bits 23-16: max f-number denominator | |
79 | * bits 15-8: min f-number numerator | |
80 | * bits 7-0: min f-number denominator | |
81 | */ | |
82 | #define OV2680_F_NUMBER_RANGE 0x180a180a | |
83 | #define OV2680_ID 0x2680 | |
84 | ||
85 | #define OV2680_FINE_INTG_TIME_MIN 0 | |
86 | #define OV2680_FINE_INTG_TIME_MAX_MARGIN 0 | |
87 | #define OV2680_COARSE_INTG_TIME_MIN 1 | |
88 | #define OV2680_COARSE_INTG_TIME_MAX_MARGIN 6 | |
89 | ||
90 | /* | |
91 | * OV2680 System control registers | |
92 | */ | |
93 | #define OV2680_SW_SLEEP 0x0100 | |
94 | #define OV2680_SW_RESET 0x0103 | |
95 | #define OV2680_SW_STREAM 0x0100 | |
96 | ||
97 | #define OV2680_SC_CMMN_CHIP_ID_H 0x300A | |
98 | #define OV2680_SC_CMMN_CHIP_ID_L 0x300B | |
99 | #define OV2680_SC_CMMN_SCCB_ID 0x302B /* 0x300C*/ | |
100 | #define OV2680_SC_CMMN_SUB_ID 0x302A /* process, version*/ | |
101 | ||
102 | #define OV2680_GROUP_ACCESS 0x3208 /*Bit[7:4] Group control, Bit[3:0] Group ID*/ | |
103 | ||
104 | #define OV2680_EXPOSURE_H 0x3500 /*Bit[3:0] Bit[19:16] of exposure, remaining 16 bits lies in Reg0x3501&Reg0x3502*/ | |
105 | #define OV2680_EXPOSURE_M 0x3501 | |
106 | #define OV2680_EXPOSURE_L 0x3502 | |
107 | #define OV2680_AGC_H 0x350A /*Bit[1:0] means Bit[9:8] of gain*/ | |
108 | #define OV2680_AGC_L 0x350B /*Bit[7:0] of gain*/ | |
109 | ||
110 | #define OV2680_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/ | |
111 | #define OV2680_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/ | |
112 | #define OV2680_VERTICAL_START_H 0x3802 /*Bit[11:8]*/ | |
113 | #define OV2680_VERTICAL_START_L 0x3803 /*Bit[7:0]*/ | |
114 | #define OV2680_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/ | |
115 | #define OV2680_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/ | |
116 | #define OV2680_VERTICAL_END_H 0x3806 /*Bit[11:8]*/ | |
117 | #define OV2680_VERTICAL_END_L 0x3807 /*Bit[7:0]*/ | |
118 | #define OV2680_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/ | |
119 | #define OV2680_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/ | |
120 | #define OV2680_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/ | |
121 | #define OV2680_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/ | |
122 | #define OV2680_TIMING_HTS_H 0x380C /*High 8-bit, and low 8-bit HTS address is 0x380d*/ | |
123 | #define OV2680_TIMING_HTS_L 0x380D /*High 8-bit, and low 8-bit HTS address is 0x380d*/ | |
124 | #define OV2680_TIMING_VTS_H 0x380e /*High 8-bit, and low 8-bit HTS address is 0x380f*/ | |
125 | #define OV2680_TIMING_VTS_L 0x380f /*High 8-bit, and low 8-bit HTS address is 0x380f*/ | |
126 | #define OV2680_FRAME_OFF_NUM 0x4202 | |
127 | ||
128 | /*Flip/Mirror*/ | |
129 | #define OV2680_FLIP_REG 0x3820 | |
130 | #define OV2680_MIRROR_REG 0x3821 | |
131 | #define OV2680_FLIP_BIT 1 | |
132 | #define OV2680_MIRROR_BIT 2 | |
133 | #define OV2680_FLIP_MIRROR_BIT_ENABLE 4 | |
134 | ||
135 | #define OV2680_MWB_RED_GAIN_H 0x5004/*0x3400*/ | |
136 | #define OV2680_MWB_GREEN_GAIN_H 0x5006/*0x3402*/ | |
137 | #define OV2680_MWB_BLUE_GAIN_H 0x5008/*0x3404*/ | |
138 | #define OV2680_MWB_GAIN_MAX 0x0fff | |
139 | ||
140 | #define OV2680_START_STREAMING 0x01 | |
141 | #define OV2680_STOP_STREAMING 0x00 | |
142 | ||
143 | ||
144 | #define OV2680_INVALID_CONFIG 0xffffffff | |
145 | ||
146 | ||
147 | struct regval_list { | |
148 | u16 reg_num; | |
149 | u8 value; | |
150 | }; | |
151 | ||
152 | struct ov2680_resolution { | |
153 | u8 *desc; | |
154 | const struct ov2680_reg *regs; | |
155 | int res; | |
156 | int width; | |
157 | int height; | |
158 | int fps; | |
159 | int pix_clk_freq; | |
160 | u32 skip_frames; | |
161 | u16 pixels_per_line; | |
162 | u16 lines_per_frame; | |
163 | u8 bin_factor_x; | |
164 | u8 bin_factor_y; | |
165 | u8 bin_mode; | |
166 | bool used; | |
167 | }; | |
168 | ||
169 | struct ov2680_format { | |
170 | u8 *desc; | |
171 | u32 pixelformat; | |
172 | struct ov2680_reg *regs; | |
173 | }; | |
174 | ||
175 | /* | |
176 | * ov2680 device structure. | |
177 | */ | |
178 | struct ov2680_device { | |
179 | struct v4l2_subdev sd; | |
180 | struct media_pad pad; | |
181 | struct v4l2_mbus_framefmt format; | |
182 | struct mutex input_lock; | |
183 | struct v4l2_ctrl_handler ctrl_handler; | |
184 | struct camera_sensor_platform_data *platform_data; | |
185 | struct timespec timestamp_t_focus_abs; | |
186 | int vt_pix_clk_freq_mhz; | |
187 | int fmt_idx; | |
188 | int run_mode; | |
189 | u8 res; | |
190 | u8 type; | |
191 | }; | |
192 | ||
193 | enum ov2680_tok_type { | |
194 | OV2680_8BIT = 0x0001, | |
195 | OV2680_16BIT = 0x0002, | |
196 | OV2680_32BIT = 0x0004, | |
197 | OV2680_TOK_TERM = 0xf000, /* terminating token for reg list */ | |
198 | OV2680_TOK_DELAY = 0xfe00, /* delay token for reg list */ | |
199 | OV2680_TOK_MASK = 0xfff0 | |
200 | }; | |
201 | ||
202 | /** | |
203 | * struct ov2680_reg - MI sensor register format | |
204 | * @type: type of the register | |
205 | * @reg: 16-bit offset to register | |
206 | * @val: 8/16/32-bit register value | |
207 | * | |
208 | * Define a structure for sensor register initialization values | |
209 | */ | |
210 | struct ov2680_reg { | |
211 | enum ov2680_tok_type type; | |
212 | u16 reg; | |
213 | u32 val; /* @set value for read/mod/write, @mask */ | |
214 | }; | |
215 | ||
216 | #define to_ov2680_sensor(x) container_of(x, struct ov2680_device, sd) | |
217 | ||
218 | #define OV2680_MAX_WRITE_BUF_SIZE 30 | |
219 | ||
220 | struct ov2680_write_buffer { | |
221 | u16 addr; | |
222 | u8 data[OV2680_MAX_WRITE_BUF_SIZE]; | |
223 | }; | |
224 | ||
225 | struct ov2680_write_ctrl { | |
226 | int index; | |
227 | struct ov2680_write_buffer buffer; | |
228 | }; | |
229 | ||
230 | static const struct i2c_device_id ov2680_id[] = { | |
231 | {OV2680B_NAME, 0}, | |
232 | {OV2680F_NAME, 0}, | |
233 | {} | |
234 | }; | |
235 | ||
236 | static struct ov2680_reg const ov2680_global_setting[] = { | |
237 | {OV2680_8BIT, 0x0103, 0x01}, | |
238 | {OV2680_8BIT, 0x3002, 0x00}, | |
239 | {OV2680_8BIT, 0x3016, 0x1c}, | |
240 | {OV2680_8BIT, 0x3018, 0x44}, | |
241 | {OV2680_8BIT, 0x3020, 0x00}, | |
242 | {OV2680_8BIT, 0x3080, 0x02}, | |
243 | {OV2680_8BIT, 0x3082, 0x45}, | |
244 | {OV2680_8BIT, 0x3084, 0x09}, | |
245 | {OV2680_8BIT, 0x3085, 0x04}, | |
246 | {OV2680_8BIT, 0x3503, 0x03}, | |
247 | {OV2680_8BIT, 0x350b, 0x36}, | |
248 | {OV2680_8BIT, 0x3600, 0xb4}, | |
249 | {OV2680_8BIT, 0x3603, 0x39}, | |
250 | {OV2680_8BIT, 0x3604, 0x24}, | |
251 | {OV2680_8BIT, 0x3605, 0x00}, | |
252 | {OV2680_8BIT, 0x3620, 0x26}, | |
253 | {OV2680_8BIT, 0x3621, 0x37}, | |
254 | {OV2680_8BIT, 0x3622, 0x04}, | |
255 | {OV2680_8BIT, 0x3628, 0x00}, | |
256 | {OV2680_8BIT, 0x3705, 0x3c}, | |
257 | {OV2680_8BIT, 0x370c, 0x50}, | |
258 | {OV2680_8BIT, 0x370d, 0xc0}, | |
259 | {OV2680_8BIT, 0x3718, 0x88}, | |
260 | {OV2680_8BIT, 0x3720, 0x00}, | |
261 | {OV2680_8BIT, 0x3721, 0x00}, | |
262 | {OV2680_8BIT, 0x3722, 0x00}, | |
263 | {OV2680_8BIT, 0x3723, 0x00}, | |
264 | {OV2680_8BIT, 0x3738, 0x00}, | |
265 | {OV2680_8BIT, 0x3717, 0x58}, | |
266 | {OV2680_8BIT, 0x3781, 0x80}, | |
267 | {OV2680_8BIT, 0x3789, 0x60}, | |
268 | {OV2680_8BIT, 0x3800, 0x00}, | |
269 | {OV2680_8BIT, 0x3819, 0x04}, | |
270 | {OV2680_8BIT, 0x4000, 0x81}, | |
271 | {OV2680_8BIT, 0x4001, 0x40}, | |
272 | {OV2680_8BIT, 0x4602, 0x02}, | |
273 | {OV2680_8BIT, 0x481f, 0x36}, | |
274 | {OV2680_8BIT, 0x4825, 0x36}, | |
275 | {OV2680_8BIT, 0x4837, 0x18}, | |
276 | {OV2680_8BIT, 0x5002, 0x30}, | |
277 | {OV2680_8BIT, 0x5004, 0x04},//manual awb 1x | |
278 | {OV2680_8BIT, 0x5005, 0x00}, | |
279 | {OV2680_8BIT, 0x5006, 0x04}, | |
280 | {OV2680_8BIT, 0x5007, 0x00}, | |
281 | {OV2680_8BIT, 0x5008, 0x04}, | |
282 | {OV2680_8BIT, 0x5009, 0x00}, | |
283 | {OV2680_8BIT, 0x5080, 0x00}, | |
284 | {OV2680_8BIT, 0x3701, 0x64}, //add on 14/05/13 | |
285 | {OV2680_8BIT, 0x3784, 0x0c}, //based OV2680_R1A_AM10.ovt add on 14/06/13 | |
286 | {OV2680_8BIT, 0x5780, 0x3e}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 | |
287 | {OV2680_8BIT, 0x5781, 0x0f}, | |
288 | {OV2680_8BIT, 0x5782, 0x04}, | |
289 | {OV2680_8BIT, 0x5783, 0x02}, | |
290 | {OV2680_8BIT, 0x5784, 0x01}, | |
291 | {OV2680_8BIT, 0x5785, 0x01}, | |
292 | {OV2680_8BIT, 0x5786, 0x00}, | |
293 | {OV2680_8BIT, 0x5787, 0x04}, | |
294 | {OV2680_8BIT, 0x5788, 0x02}, | |
295 | {OV2680_8BIT, 0x5789, 0x00}, | |
296 | {OV2680_8BIT, 0x578a, 0x01}, | |
297 | {OV2680_8BIT, 0x578b, 0x02}, | |
298 | {OV2680_8BIT, 0x578c, 0x03}, | |
299 | {OV2680_8BIT, 0x578d, 0x03}, | |
300 | {OV2680_8BIT, 0x578e, 0x08}, | |
301 | {OV2680_8BIT, 0x578f, 0x0c}, | |
302 | {OV2680_8BIT, 0x5790, 0x08}, | |
303 | {OV2680_8BIT, 0x5791, 0x04}, | |
304 | {OV2680_8BIT, 0x5792, 0x00}, | |
305 | {OV2680_8BIT, 0x5793, 0x00}, | |
306 | {OV2680_8BIT, 0x5794, 0x03}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 | |
307 | {OV2680_8BIT, 0x0100, 0x00}, //stream off | |
308 | ||
309 | {OV2680_TOK_TERM, 0, 0} | |
310 | }; | |
311 | ||
312 | ||
313 | /* | |
314 | * 176x144 30fps VBlanking 1lane 10Bit (binning) | |
315 | */ | |
316 | static struct ov2680_reg const ov2680_QCIF_30fps[] = { | |
317 | {OV2680_8BIT, 0x3086, 0x01}, | |
318 | {OV2680_8BIT, 0x3501, 0x24}, | |
319 | {OV2680_8BIT, 0x3502, 0x40}, | |
320 | {OV2680_8BIT, 0x370a, 0x23}, | |
321 | {OV2680_8BIT, 0x3801, 0xa0}, | |
322 | {OV2680_8BIT, 0x3802, 0x00}, | |
323 | {OV2680_8BIT, 0x3803, 0x78}, | |
324 | {OV2680_8BIT, 0x3804, 0x05}, | |
325 | {OV2680_8BIT, 0x3805, 0xaf}, | |
326 | {OV2680_8BIT, 0x3806, 0x04}, | |
327 | {OV2680_8BIT, 0x3807, 0x47}, | |
328 | {OV2680_8BIT, 0x3808, 0x00}, | |
329 | {OV2680_8BIT, 0x3809, 0xC0}, | |
330 | {OV2680_8BIT, 0x380a, 0x00}, | |
331 | {OV2680_8BIT, 0x380b, 0xa0}, | |
332 | {OV2680_8BIT, 0x380c, 0x06}, | |
333 | {OV2680_8BIT, 0x380d, 0xb0}, | |
334 | {OV2680_8BIT, 0x380e, 0x02}, | |
335 | {OV2680_8BIT, 0x380f, 0x84}, | |
336 | {OV2680_8BIT, 0x3810, 0x00}, | |
337 | {OV2680_8BIT, 0x3811, 0x04}, | |
338 | {OV2680_8BIT, 0x3812, 0x00}, | |
339 | {OV2680_8BIT, 0x3813, 0x04}, | |
340 | {OV2680_8BIT, 0x3814, 0x31}, | |
341 | {OV2680_8BIT, 0x3815, 0x31}, | |
342 | {OV2680_8BIT, 0x4000, 0x81}, | |
343 | {OV2680_8BIT, 0x4001, 0x40}, | |
344 | {OV2680_8BIT, 0x4008, 0x00}, | |
345 | {OV2680_8BIT, 0x4009, 0x03}, | |
346 | {OV2680_8BIT, 0x5081, 0x41}, | |
347 | {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 | |
348 | {OV2680_8BIT, 0x5704, 0x10}, | |
349 | {OV2680_8BIT, 0x5705, 0xa0}, | |
350 | {OV2680_8BIT, 0x5706, 0x0c}, | |
351 | {OV2680_8BIT, 0x5707, 0x78}, | |
352 | {OV2680_8BIT, 0x3820, 0xc2}, | |
353 | {OV2680_8BIT, 0x3821, 0x01}, | |
354 | // {OV2680_8BIT, 0x5090, 0x0c}, | |
355 | {OV2680_TOK_TERM, 0, 0} | |
356 | }; | |
357 | ||
358 | /* | |
359 | * 352x288 30fps VBlanking 1lane 10Bit (binning) | |
360 | */ | |
361 | static struct ov2680_reg const ov2680_CIF_30fps[] = { | |
362 | {OV2680_8BIT, 0x3086, 0x01}, | |
363 | {OV2680_8BIT, 0x3501, 0x24}, | |
364 | {OV2680_8BIT, 0x3502, 0x40}, | |
365 | {OV2680_8BIT, 0x370a, 0x23}, | |
366 | {OV2680_8BIT, 0x3801, 0xa0}, | |
367 | {OV2680_8BIT, 0x3802, 0x00}, | |
368 | {OV2680_8BIT, 0x3803, 0x78}, | |
369 | {OV2680_8BIT, 0x3804, 0x03}, | |
370 | {OV2680_8BIT, 0x3805, 0x8f}, | |
371 | {OV2680_8BIT, 0x3806, 0x02}, | |
372 | {OV2680_8BIT, 0x3807, 0xe7}, | |
373 | {OV2680_8BIT, 0x3808, 0x01}, | |
374 | {OV2680_8BIT, 0x3809, 0x70}, | |
375 | {OV2680_8BIT, 0x380a, 0x01}, | |
376 | {OV2680_8BIT, 0x380b, 0x30}, | |
377 | {OV2680_8BIT, 0x380c, 0x06}, | |
378 | {OV2680_8BIT, 0x380d, 0xb0}, | |
379 | {OV2680_8BIT, 0x380e, 0x02}, | |
380 | {OV2680_8BIT, 0x380f, 0x84}, | |
381 | {OV2680_8BIT, 0x3810, 0x00}, | |
382 | {OV2680_8BIT, 0x3811, 0x04}, | |
383 | {OV2680_8BIT, 0x3812, 0x00}, | |
384 | {OV2680_8BIT, 0x3813, 0x04}, | |
385 | {OV2680_8BIT, 0x3814, 0x31}, | |
386 | {OV2680_8BIT, 0x3815, 0x31}, | |
387 | {OV2680_8BIT, 0x4008, 0x00}, | |
388 | {OV2680_8BIT, 0x4009, 0x03}, | |
389 | {OV2680_8BIT, 0x5081, 0x41}, | |
390 | {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 | |
391 | {OV2680_8BIT, 0x5704, 0x10}, | |
392 | {OV2680_8BIT, 0x5705, 0xa0}, | |
393 | {OV2680_8BIT, 0x5706, 0x0c}, | |
394 | {OV2680_8BIT, 0x5707, 0x78}, | |
395 | {OV2680_8BIT, 0x3820, 0xc2}, | |
396 | {OV2680_8BIT, 0x3821, 0x01}, | |
397 | // {OV2680_8BIT, 0x5090, 0x0c}, | |
398 | {OV2680_TOK_TERM, 0, 0} | |
399 | }; | |
400 | ||
401 | /* | |
402 | * 336x256 30fps VBlanking 1lane 10Bit (binning) | |
403 | */ | |
404 | static struct ov2680_reg const ov2680_QVGA_30fps[] = { | |
405 | {OV2680_8BIT, 0x3086, 0x01}, | |
406 | {OV2680_8BIT, 0x3501, 0x24}, | |
407 | {OV2680_8BIT, 0x3502, 0x40}, | |
408 | {OV2680_8BIT, 0x370a, 0x23}, | |
409 | {OV2680_8BIT, 0x3801, 0xa0}, | |
410 | {OV2680_8BIT, 0x3802, 0x00}, | |
411 | {OV2680_8BIT, 0x3803, 0x78}, | |
412 | {OV2680_8BIT, 0x3804, 0x03}, | |
413 | {OV2680_8BIT, 0x3805, 0x4f}, | |
414 | {OV2680_8BIT, 0x3806, 0x02}, | |
415 | {OV2680_8BIT, 0x3807, 0x87}, | |
416 | {OV2680_8BIT, 0x3808, 0x01}, | |
417 | {OV2680_8BIT, 0x3809, 0x50}, | |
418 | {OV2680_8BIT, 0x380a, 0x01}, | |
419 | {OV2680_8BIT, 0x380b, 0x00}, | |
420 | {OV2680_8BIT, 0x380c, 0x06}, | |
421 | {OV2680_8BIT, 0x380d, 0xb0}, | |
422 | {OV2680_8BIT, 0x380e, 0x02}, | |
423 | {OV2680_8BIT, 0x380f, 0x84}, | |
424 | {OV2680_8BIT, 0x3810, 0x00}, | |
425 | {OV2680_8BIT, 0x3811, 0x04}, | |
426 | {OV2680_8BIT, 0x3812, 0x00}, | |
427 | {OV2680_8BIT, 0x3813, 0x04}, | |
428 | {OV2680_8BIT, 0x3814, 0x31}, | |
429 | {OV2680_8BIT, 0x3815, 0x31}, | |
430 | {OV2680_8BIT, 0x4008, 0x00}, | |
431 | {OV2680_8BIT, 0x4009, 0x03}, | |
432 | {OV2680_8BIT, 0x5081, 0x41}, | |
433 | {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 | |
434 | {OV2680_8BIT, 0x5704, 0x10}, | |
435 | {OV2680_8BIT, 0x5705, 0xa0}, | |
436 | {OV2680_8BIT, 0x5706, 0x0c}, | |
437 | {OV2680_8BIT, 0x5707, 0x78}, | |
438 | {OV2680_8BIT, 0x3820, 0xc2}, | |
439 | {OV2680_8BIT, 0x3821, 0x01}, | |
440 | // {OV2680_8BIT, 0x5090, 0x0c}, | |
441 | {OV2680_TOK_TERM, 0, 0} | |
442 | }; | |
443 | ||
444 | ||
445 | /* | |
446 | * 656x496 30fps VBlanking 1lane 10Bit (binning) | |
447 | */ | |
448 | static struct ov2680_reg const ov2680_656x496_30fps[] = { | |
449 | {OV2680_8BIT, 0x3086, 0x01}, | |
450 | {OV2680_8BIT, 0x3501, 0x24}, | |
451 | {OV2680_8BIT, 0x3502, 0x40}, | |
452 | {OV2680_8BIT, 0x370a, 0x23}, | |
453 | {OV2680_8BIT, 0x3801, 0xa0}, | |
454 | {OV2680_8BIT, 0x3802, 0x00}, | |
455 | {OV2680_8BIT, 0x3803, 0x78}, | |
456 | {OV2680_8BIT, 0x3804, 0x05}, | |
457 | {OV2680_8BIT, 0x3805, 0xcf}, | |
458 | {OV2680_8BIT, 0x3806, 0x04}, | |
459 | {OV2680_8BIT, 0x3807, 0x67}, | |
460 | {OV2680_8BIT, 0x3808, 0x02}, | |
461 | {OV2680_8BIT, 0x3809, 0x90}, | |
462 | {OV2680_8BIT, 0x380a, 0x01}, | |
463 | {OV2680_8BIT, 0x380b, 0xf0}, | |
464 | {OV2680_8BIT, 0x380c, 0x06}, | |
465 | {OV2680_8BIT, 0x380d, 0xb0}, | |
466 | {OV2680_8BIT, 0x380e, 0x02}, | |
467 | {OV2680_8BIT, 0x380f, 0x84}, | |
468 | {OV2680_8BIT, 0x3810, 0x00}, | |
469 | {OV2680_8BIT, 0x3811, 0x04}, | |
470 | {OV2680_8BIT, 0x3812, 0x00}, | |
471 | {OV2680_8BIT, 0x3813, 0x04}, | |
472 | {OV2680_8BIT, 0x3814, 0x31}, | |
473 | {OV2680_8BIT, 0x3815, 0x31}, | |
474 | {OV2680_8BIT, 0x4008, 0x00}, | |
475 | {OV2680_8BIT, 0x4009, 0x03}, | |
476 | {OV2680_8BIT, 0x5081, 0x41}, | |
477 | {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 | |
478 | {OV2680_8BIT, 0x5704, 0x10}, | |
479 | {OV2680_8BIT, 0x5705, 0xa0}, | |
480 | {OV2680_8BIT, 0x5706, 0x0c}, | |
481 | {OV2680_8BIT, 0x5707, 0x78}, | |
482 | {OV2680_8BIT, 0x3820, 0xc2}, | |
483 | {OV2680_8BIT, 0x3821, 0x01}, | |
484 | // {OV2680_8BIT, 0x5090, 0x0c}, | |
485 | {OV2680_TOK_TERM, 0, 0} | |
486 | }; | |
487 | /* | |
488 | * 800x600 30fps VBlanking 1lane 10Bit (binning) | |
489 | */ | |
490 | static struct ov2680_reg const ov2680_720x592_30fps[] = { | |
491 | {OV2680_8BIT, 0x3086, 0x01}, | |
492 | {OV2680_8BIT, 0x3501, 0x26}, | |
493 | {OV2680_8BIT, 0x3502, 0x40}, | |
494 | {OV2680_8BIT, 0x370a, 0x23}, | |
495 | {OV2680_8BIT, 0x3801, 0x00}, // X_ADDR_START; | |
496 | {OV2680_8BIT, 0x3802, 0x00}, | |
497 | {OV2680_8BIT, 0x3803, 0x00}, // Y_ADDR_START; | |
498 | {OV2680_8BIT, 0x3804, 0x05}, | |
499 | {OV2680_8BIT, 0x3805, 0xaf}, // X_ADDR_END; | |
500 | {OV2680_8BIT, 0x3806, 0x04}, | |
501 | {OV2680_8BIT, 0x3807, 0xaf}, // Y_ADDR_END; | |
502 | {OV2680_8BIT, 0x3808, 0x02}, | |
503 | {OV2680_8BIT, 0x3809, 0xd0}, // X_OUTPUT_SIZE; | |
504 | {OV2680_8BIT, 0x380a, 0x02}, | |
505 | {OV2680_8BIT, 0x380b, 0x50}, // Y_OUTPUT_SIZE; | |
506 | {OV2680_8BIT, 0x380c, 0x06}, | |
507 | {OV2680_8BIT, 0x380d, 0xac}, // HTS; | |
508 | {OV2680_8BIT, 0x380e, 0x02}, | |
509 | {OV2680_8BIT, 0x380f, 0x84}, // VTS; | |
510 | {OV2680_8BIT, 0x3810, 0x00}, | |
511 | {OV2680_8BIT, 0x3811, 0x00}, | |
512 | {OV2680_8BIT, 0x3812, 0x00}, | |
513 | {OV2680_8BIT, 0x3813, 0x00}, | |
514 | {OV2680_8BIT, 0x3814, 0x31}, | |
515 | {OV2680_8BIT, 0x3815, 0x31}, | |
516 | {OV2680_8BIT, 0x4008, 0x00}, | |
517 | {OV2680_8BIT, 0x4009, 0x03}, | |
518 | {OV2680_8BIT, 0x5708, 0x00}, | |
519 | {OV2680_8BIT, 0x5704, 0x02}, | |
520 | {OV2680_8BIT, 0x5705, 0xd0}, // X_WIN; | |
521 | {OV2680_8BIT, 0x5706, 0x02}, | |
522 | {OV2680_8BIT, 0x5707, 0x50}, // Y_WIN; | |
523 | {OV2680_8BIT, 0x3820, 0xc2}, // FLIP_FORMAT; | |
524 | {OV2680_8BIT, 0x3821, 0x01}, // MIRROR_FORMAT; | |
525 | {OV2680_8BIT, 0x5090, 0x00}, // PRE ISP CTRL16, default value is 0x0C; | |
526 | // BIT[3]: Mirror order, BG or GB; | |
527 | // BIT[2]: Flip order, BR or RB; | |
528 | {OV2680_8BIT, 0x5081, 0x41}, | |
529 | {OV2680_TOK_TERM, 0, 0} | |
530 | }; | |
531 | ||
532 | /* | |
533 | * 800x600 30fps VBlanking 1lane 10Bit (binning) | |
534 | */ | |
535 | static struct ov2680_reg const ov2680_800x600_30fps[] = { | |
536 | {OV2680_8BIT, 0x3086, 0x01}, | |
537 | {OV2680_8BIT, 0x3501, 0x26}, | |
538 | {OV2680_8BIT, 0x3502, 0x40}, | |
539 | {OV2680_8BIT, 0x370a, 0x23}, | |
540 | {OV2680_8BIT, 0x3801, 0x00}, | |
541 | {OV2680_8BIT, 0x3802, 0x00}, | |
542 | {OV2680_8BIT, 0x3803, 0x00}, | |
543 | {OV2680_8BIT, 0x3804, 0x06}, | |
544 | {OV2680_8BIT, 0x3805, 0x4f}, | |
545 | {OV2680_8BIT, 0x3806, 0x04}, | |
546 | {OV2680_8BIT, 0x3807, 0xbf}, | |
547 | {OV2680_8BIT, 0x3808, 0x03}, | |
548 | {OV2680_8BIT, 0x3809, 0x20}, | |
549 | {OV2680_8BIT, 0x380a, 0x02}, | |
550 | {OV2680_8BIT, 0x380b, 0x58}, | |
551 | {OV2680_8BIT, 0x380c, 0x06}, | |
552 | {OV2680_8BIT, 0x380d, 0xac}, | |
553 | {OV2680_8BIT, 0x380e, 0x02}, | |
554 | {OV2680_8BIT, 0x380f, 0x84}, | |
555 | {OV2680_8BIT, 0x3810, 0x00}, | |
556 | {OV2680_8BIT, 0x3811, 0x00}, | |
557 | {OV2680_8BIT, 0x3812, 0x00}, | |
558 | {OV2680_8BIT, 0x3813, 0x00}, | |
559 | {OV2680_8BIT, 0x3814, 0x31}, | |
560 | {OV2680_8BIT, 0x3815, 0x31}, | |
561 | {OV2680_8BIT, 0x5708, 0x00}, | |
562 | {OV2680_8BIT, 0x5704, 0x03}, | |
563 | {OV2680_8BIT, 0x5705, 0x20}, | |
564 | {OV2680_8BIT, 0x5706, 0x02}, | |
565 | {OV2680_8BIT, 0x5707, 0x58}, | |
566 | {OV2680_8BIT, 0x3820, 0xc2}, | |
567 | {OV2680_8BIT, 0x3821, 0x01}, | |
568 | {OV2680_8BIT, 0x5090, 0x00}, | |
569 | {OV2680_8BIT, 0x4008, 0x00}, | |
570 | {OV2680_8BIT, 0x4009, 0x03}, | |
571 | {OV2680_8BIT, 0x5081, 0x41}, | |
572 | {OV2680_TOK_TERM, 0, 0} | |
573 | }; | |
574 | ||
575 | /* | |
576 | * 720p=1280*720 30fps VBlanking 1lane 10Bit (no-Scaling) | |
577 | */ | |
578 | static struct ov2680_reg const ov2680_720p_30fps[] = { | |
579 | {OV2680_8BIT, 0x3086, 0x00}, | |
580 | {OV2680_8BIT, 0x3501, 0x48}, | |
581 | {OV2680_8BIT, 0x3502, 0xe0}, | |
582 | {OV2680_8BIT, 0x370a, 0x21}, | |
583 | {OV2680_8BIT, 0x3801, 0xa0}, | |
584 | {OV2680_8BIT, 0x3802, 0x00}, | |
585 | {OV2680_8BIT, 0x3803, 0xf2}, | |
586 | {OV2680_8BIT, 0x3804, 0x05}, | |
587 | {OV2680_8BIT, 0x3805, 0xbf}, | |
588 | {OV2680_8BIT, 0x3806, 0x03}, | |
589 | {OV2680_8BIT, 0x3807, 0xdd}, | |
590 | {OV2680_8BIT, 0x3808, 0x05}, | |
591 | {OV2680_8BIT, 0x3809, 0x10}, | |
592 | {OV2680_8BIT, 0x380a, 0x02}, | |
593 | {OV2680_8BIT, 0x380b, 0xe0}, | |
594 | {OV2680_8BIT, 0x380c, 0x06}, | |
595 | {OV2680_8BIT, 0x380d, 0xa8}, | |
596 | {OV2680_8BIT, 0x380e, 0x05}, | |
597 | {OV2680_8BIT, 0x380f, 0x0e}, | |
598 | {OV2680_8BIT, 0x3810, 0x00}, | |
599 | {OV2680_8BIT, 0x3811, 0x08}, | |
600 | {OV2680_8BIT, 0x3812, 0x00}, | |
601 | {OV2680_8BIT, 0x3813, 0x06}, | |
602 | {OV2680_8BIT, 0x3814, 0x11}, | |
603 | {OV2680_8BIT, 0x3815, 0x11}, | |
604 | {OV2680_8BIT, 0x4008, 0x02}, | |
605 | {OV2680_8BIT, 0x4009, 0x09}, | |
606 | {OV2680_8BIT, 0x5081, 0x41}, | |
607 | {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 | |
608 | {OV2680_8BIT, 0x5704, 0x10}, | |
609 | {OV2680_8BIT, 0x5705, 0xa0}, | |
610 | {OV2680_8BIT, 0x5706, 0x0c}, | |
611 | {OV2680_8BIT, 0x5707, 0x78}, | |
612 | {OV2680_8BIT, 0x3820, 0xc0}, | |
613 | {OV2680_8BIT, 0x3821, 0x00}, | |
614 | // {OV2680_8BIT, 0x5090, 0x0c}, | |
615 | {OV2680_TOK_TERM, 0, 0} | |
616 | }; | |
617 | ||
618 | /* | |
619 | * 1296x976 30fps VBlanking 1lane 10Bit(no-scaling) | |
620 | */ | |
621 | static struct ov2680_reg const ov2680_1296x976_30fps[] = { | |
622 | {OV2680_8BIT, 0x3086, 0x00}, | |
623 | {OV2680_8BIT, 0x3501, 0x48}, | |
624 | {OV2680_8BIT, 0x3502, 0xe0}, | |
625 | {OV2680_8BIT, 0x370a, 0x21}, | |
626 | {OV2680_8BIT, 0x3801, 0xa0}, | |
627 | {OV2680_8BIT, 0x3802, 0x00}, | |
628 | {OV2680_8BIT, 0x3803, 0x78}, | |
629 | {OV2680_8BIT, 0x3804, 0x05}, | |
630 | {OV2680_8BIT, 0x3805, 0xbf}, | |
631 | {OV2680_8BIT, 0x3806, 0x04}, | |
632 | {OV2680_8BIT, 0x3807, 0x57}, | |
633 | {OV2680_8BIT, 0x3808, 0x05}, | |
634 | {OV2680_8BIT, 0x3809, 0x10}, | |
635 | {OV2680_8BIT, 0x380a, 0x03}, | |
636 | {OV2680_8BIT, 0x380b, 0xd0}, | |
637 | {OV2680_8BIT, 0x380c, 0x06}, | |
638 | {OV2680_8BIT, 0x380d, 0xa8}, | |
639 | {OV2680_8BIT, 0x380e, 0x05}, | |
640 | {OV2680_8BIT, 0x380f, 0x0e}, | |
641 | {OV2680_8BIT, 0x3810, 0x00}, | |
642 | {OV2680_8BIT, 0x3811, 0x08}, | |
643 | {OV2680_8BIT, 0x3812, 0x00}, | |
644 | {OV2680_8BIT, 0x3813, 0x08}, | |
645 | {OV2680_8BIT, 0x3814, 0x11}, | |
646 | {OV2680_8BIT, 0x3815, 0x11}, | |
647 | {OV2680_8BIT, 0x4008, 0x02}, | |
648 | {OV2680_8BIT, 0x4009, 0x09}, | |
649 | {OV2680_8BIT, 0x5081, 0x41}, | |
650 | {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 | |
651 | {OV2680_8BIT, 0x5704, 0x10}, | |
652 | {OV2680_8BIT, 0x5705, 0xa0}, | |
653 | {OV2680_8BIT, 0x5706, 0x0c}, | |
654 | {OV2680_8BIT, 0x5707, 0x78}, | |
655 | {OV2680_8BIT, 0x3820, 0xc0}, | |
656 | {OV2680_8BIT, 0x3821, 0x00}, //miror/flip | |
657 | // {OV2680_8BIT, 0x5090, 0x0c}, | |
658 | {OV2680_TOK_TERM, 0, 0} | |
659 | }; | |
660 | ||
661 | /* | |
662 | * 1456*1096 30fps VBlanking 1lane 10bit(no-scaling) | |
663 | */ | |
664 | static struct ov2680_reg const ov2680_1456x1096_30fps[]= { | |
665 | {OV2680_8BIT, 0x3086, 0x00}, | |
666 | {OV2680_8BIT, 0x3501, 0x48}, | |
667 | {OV2680_8BIT, 0x3502, 0xe0}, | |
668 | {OV2680_8BIT, 0x370a, 0x21}, | |
669 | {OV2680_8BIT, 0x3801, 0x90}, | |
670 | {OV2680_8BIT, 0x3802, 0x00}, | |
671 | {OV2680_8BIT, 0x3803, 0x78}, | |
672 | {OV2680_8BIT, 0x3804, 0x06}, | |
673 | {OV2680_8BIT, 0x3805, 0x4f}, | |
674 | {OV2680_8BIT, 0x3806, 0x04}, | |
675 | {OV2680_8BIT, 0x3807, 0xC0}, | |
676 | {OV2680_8BIT, 0x3808, 0x05}, | |
677 | {OV2680_8BIT, 0x3809, 0xb0}, | |
678 | {OV2680_8BIT, 0x380a, 0x04}, | |
679 | {OV2680_8BIT, 0x380b, 0x48}, | |
680 | {OV2680_8BIT, 0x380c, 0x06}, | |
681 | {OV2680_8BIT, 0x380d, 0xa8}, | |
682 | {OV2680_8BIT, 0x380e, 0x05}, | |
683 | {OV2680_8BIT, 0x380f, 0x0e}, | |
684 | {OV2680_8BIT, 0x3810, 0x00}, | |
685 | {OV2680_8BIT, 0x3811, 0x08}, | |
686 | {OV2680_8BIT, 0x3812, 0x00}, | |
687 | {OV2680_8BIT, 0x3813, 0x00}, | |
688 | {OV2680_8BIT, 0x3814, 0x11}, | |
689 | {OV2680_8BIT, 0x3815, 0x11}, | |
690 | {OV2680_8BIT, 0x4008, 0x02}, | |
691 | {OV2680_8BIT, 0x4009, 0x09}, | |
692 | {OV2680_8BIT, 0x5081, 0x41}, | |
693 | {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 | |
694 | {OV2680_8BIT, 0x5704, 0x10}, | |
695 | {OV2680_8BIT, 0x5705, 0xa0}, | |
696 | {OV2680_8BIT, 0x5706, 0x0c}, | |
697 | {OV2680_8BIT, 0x5707, 0x78}, | |
698 | {OV2680_8BIT, 0x3820, 0xc0}, | |
699 | {OV2680_8BIT, 0x3821, 0x00}, | |
700 | // {OV2680_8BIT, 0x5090, 0x0c}, | |
701 | {OV2680_TOK_TERM, 0, 0} | |
702 | }; | |
703 | ||
704 | /* | |
705 | *1616x916 30fps VBlanking 1lane 10bit | |
706 | */ | |
707 | ||
708 | static struct ov2680_reg const ov2680_1616x916_30fps[] = { | |
709 | ||
710 | {OV2680_8BIT, 0x3086, 0x00}, | |
711 | {OV2680_8BIT, 0x3501, 0x48}, | |
712 | {OV2680_8BIT, 0x3502, 0xe0}, | |
713 | {OV2680_8BIT, 0x370a, 0x21}, | |
714 | {OV2680_8BIT, 0x3801, 0x00}, | |
715 | {OV2680_8BIT, 0x3802, 0x00}, | |
716 | {OV2680_8BIT, 0x3803, 0x96}, | |
717 | {OV2680_8BIT, 0x3804, 0x06}, | |
718 | {OV2680_8BIT, 0x3805, 0x4f}, | |
719 | {OV2680_8BIT, 0x3806, 0x04}, | |
720 | {OV2680_8BIT, 0x3807, 0x39}, | |
721 | {OV2680_8BIT, 0x3808, 0x06}, | |
722 | {OV2680_8BIT, 0x3809, 0x50}, | |
723 | {OV2680_8BIT, 0x380a, 0x03}, | |
724 | {OV2680_8BIT, 0x380b, 0x94}, | |
725 | {OV2680_8BIT, 0x380c, 0x06}, | |
726 | {OV2680_8BIT, 0x380d, 0xa8}, | |
727 | {OV2680_8BIT, 0x380e, 0x05}, | |
728 | {OV2680_8BIT, 0x380f, 0x0e}, | |
729 | {OV2680_8BIT, 0x3810, 0x00}, | |
730 | {OV2680_8BIT, 0x3811, 0x00}, | |
731 | {OV2680_8BIT, 0x3812, 0x00}, | |
732 | {OV2680_8BIT, 0x3813, 0x08}, | |
733 | {OV2680_8BIT, 0x3814, 0x11}, | |
734 | {OV2680_8BIT, 0x3815, 0x11}, | |
735 | {OV2680_8BIT, 0x4008, 0x02}, | |
736 | {OV2680_8BIT, 0x4009, 0x09}, | |
737 | {OV2680_8BIT, 0x5081, 0x41}, | |
738 | {OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 | |
739 | {OV2680_8BIT, 0x5704, 0x06}, | |
740 | {OV2680_8BIT, 0x5705, 0x50}, | |
741 | {OV2680_8BIT, 0x5706, 0x03}, | |
742 | {OV2680_8BIT, 0x5707, 0x94}, | |
743 | {OV2680_8BIT, 0x3820, 0xc0}, | |
744 | {OV2680_8BIT, 0x3821, 0x00}, | |
745 | // {OV2680_8BIT, 0x5090, 0x0C}, | |
746 | {OV2680_TOK_TERM, 0, 0} | |
747 | }; | |
748 | ||
749 | /* | |
750 | * 1612x1212 30fps VBlanking 1lane 10Bit | |
751 | */ | |
752 | static struct ov2680_reg const ov2680_1616x1082_30fps[] = { | |
753 | {OV2680_8BIT, 0x3086, 0x00}, | |
754 | {OV2680_8BIT, 0x3501, 0x48}, | |
755 | {OV2680_8BIT, 0x3502, 0xe0}, | |
756 | {OV2680_8BIT, 0x370a, 0x21}, | |
757 | {OV2680_8BIT, 0x3801, 0x00}, | |
758 | {OV2680_8BIT, 0x3802, 0x00}, | |
759 | {OV2680_8BIT, 0x3803, 0x86}, | |
760 | {OV2680_8BIT, 0x3804, 0x06}, | |
761 | {OV2680_8BIT, 0x3805, 0x4f}, | |
762 | {OV2680_8BIT, 0x3806, 0x04}, | |
763 | {OV2680_8BIT, 0x3807, 0xbf}, | |
764 | {OV2680_8BIT, 0x3808, 0x06}, | |
765 | {OV2680_8BIT, 0x3809, 0x50}, | |
766 | {OV2680_8BIT, 0x380a, 0x04}, | |
767 | {OV2680_8BIT, 0x380b, 0x3a}, | |
768 | {OV2680_8BIT, 0x380c, 0x06}, | |
769 | {OV2680_8BIT, 0x380d, 0xa8}, | |
770 | {OV2680_8BIT, 0x380e, 0x05}, | |
771 | {OV2680_8BIT, 0x380f, 0x0e}, | |
772 | {OV2680_8BIT, 0x3810, 0x00}, | |
773 | {OV2680_8BIT, 0x3811, 0x00}, | |
774 | {OV2680_8BIT, 0x3812, 0x00}, | |
775 | {OV2680_8BIT, 0x3813, 0x00}, | |
776 | {OV2680_8BIT, 0x3814, 0x11}, | |
777 | {OV2680_8BIT, 0x3815, 0x11}, | |
778 | {OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 | |
779 | {OV2680_8BIT, 0x5704, 0x06}, | |
780 | {OV2680_8BIT, 0x5705, 0x50}, | |
781 | {OV2680_8BIT, 0x5706, 0x04}, | |
782 | {OV2680_8BIT, 0x5707, 0x3a}, | |
783 | {OV2680_8BIT, 0x3820, 0xc0}, | |
784 | {OV2680_8BIT, 0x3821, 0x00}, | |
785 | // {OV2680_8BIT, 0x5090, 0x0C}, | |
786 | {OV2680_8BIT, 0x4008, 0x02}, | |
787 | {OV2680_8BIT, 0x4009, 0x09}, | |
788 | {OV2680_8BIT, 0x5081, 0x41}, | |
789 | {OV2680_TOK_TERM, 0, 0} | |
790 | }; | |
791 | /* | |
792 | * 1616x1216 30fps VBlanking 1lane 10Bit | |
793 | */ | |
794 | static struct ov2680_reg const ov2680_1616x1216_30fps[] = { | |
795 | {OV2680_8BIT, 0x3086, 0x00}, | |
796 | {OV2680_8BIT, 0x3501, 0x48}, | |
797 | {OV2680_8BIT, 0x3502, 0xe0}, | |
798 | {OV2680_8BIT, 0x370a, 0x21}, | |
799 | {OV2680_8BIT, 0x3801, 0x00}, | |
800 | {OV2680_8BIT, 0x3802, 0x00}, | |
801 | {OV2680_8BIT, 0x3803, 0x00}, | |
802 | {OV2680_8BIT, 0x3804, 0x06}, | |
803 | {OV2680_8BIT, 0x3805, 0x4f}, | |
804 | {OV2680_8BIT, 0x3806, 0x04}, | |
805 | {OV2680_8BIT, 0x3807, 0xbf}, | |
806 | {OV2680_8BIT, 0x3808, 0x06}, | |
807 | {OV2680_8BIT, 0x3809, 0x50},//50},//4line for mirror and flip | |
808 | {OV2680_8BIT, 0x380a, 0x04}, | |
809 | {OV2680_8BIT, 0x380b, 0xc0},//c0}, | |
810 | {OV2680_8BIT, 0x380c, 0x06}, | |
811 | {OV2680_8BIT, 0x380d, 0xa8}, | |
812 | {OV2680_8BIT, 0x380e, 0x05}, | |
813 | {OV2680_8BIT, 0x380f, 0x0e}, | |
814 | {OV2680_8BIT, 0x3810, 0x00}, | |
815 | {OV2680_8BIT, 0x3811, 0x00}, | |
816 | {OV2680_8BIT, 0x3812, 0x00}, | |
817 | {OV2680_8BIT, 0x3813, 0x00}, | |
818 | {OV2680_8BIT, 0x3814, 0x11}, | |
819 | {OV2680_8BIT, 0x3815, 0x11}, | |
820 | {OV2680_8BIT, 0x4008, 0x00}, | |
821 | {OV2680_8BIT, 0x4009, 0x0b}, | |
822 | {OV2680_8BIT, 0x5081, 0x01}, | |
823 | {OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 | |
824 | {OV2680_8BIT, 0x5704, 0x06}, | |
825 | {OV2680_8BIT, 0x5705, 0x50}, | |
826 | {OV2680_8BIT, 0x5706, 0x04}, | |
827 | {OV2680_8BIT, 0x5707, 0xcc}, | |
828 | {OV2680_8BIT, 0x3820, 0xc0}, | |
829 | {OV2680_8BIT, 0x3821, 0x00}, | |
830 | // {OV2680_8BIT, 0x5090, 0x0C}, | |
831 | {OV2680_TOK_TERM, 0, 0} | |
832 | }; | |
833 | ||
834 | static struct ov2680_resolution ov2680_res_preview[] = { | |
835 | { | |
836 | .desc = "ov2680_1616x1216_30fps", | |
837 | .width = 1616, | |
838 | .height = 1216, | |
839 | .pix_clk_freq = 66, | |
840 | .fps = 30, | |
841 | .used = 0, | |
842 | .pixels_per_line = 1698,//1704, | |
843 | .lines_per_frame = 1294, | |
844 | .bin_factor_x = 0, | |
845 | .bin_factor_y = 0, | |
846 | .bin_mode = 0, | |
847 | .skip_frames = 3, | |
848 | .regs = ov2680_1616x1216_30fps, | |
849 | }, | |
850 | { | |
851 | .desc = "ov2680_1616x916_30fps", | |
852 | .width = 1616, | |
853 | .height = 916, | |
854 | .fps = 30, | |
855 | .pix_clk_freq = 66, | |
856 | .used = 0, | |
857 | .pixels_per_line = 1698,//1704, | |
858 | .lines_per_frame = 1294, | |
859 | .bin_factor_x = 0, | |
860 | .bin_factor_y = 0, | |
861 | .bin_mode = 0, | |
862 | .skip_frames = 3, | |
863 | .regs = ov2680_1616x916_30fps, | |
864 | }, | |
865 | }; | |
866 | #define N_RES_PREVIEW (ARRAY_SIZE(ov2680_res_preview)) | |
867 | ||
868 | static struct ov2680_resolution ov2680_res_still[] = { | |
869 | { | |
870 | .desc = "ov2680_1616x1216_30fps", | |
871 | .width = 1616, | |
872 | .height = 1216, | |
873 | .pix_clk_freq = 66, | |
874 | .fps = 30, | |
875 | .used = 0, | |
876 | .pixels_per_line = 1698,//1704, | |
877 | .lines_per_frame = 1294, | |
878 | .bin_factor_x = 0, | |
879 | .bin_factor_y = 0, | |
880 | .bin_mode = 0, | |
881 | .skip_frames = 3, | |
882 | .regs = ov2680_1616x1216_30fps, | |
883 | }, | |
884 | { | |
885 | .desc = "ov2680_1616x916_30fps", | |
886 | .width = 1616, | |
887 | .height = 916, | |
888 | .fps = 30, | |
889 | .pix_clk_freq = 66, | |
890 | .used = 0, | |
891 | .pixels_per_line = 1698,//1704, | |
892 | .lines_per_frame = 1294, | |
893 | .bin_factor_x = 0, | |
894 | .bin_factor_y = 0, | |
895 | .bin_mode = 0, | |
896 | .skip_frames = 3, | |
897 | .regs = ov2680_1616x916_30fps, | |
898 | }, | |
899 | }; | |
900 | #define N_RES_STILL (ARRAY_SIZE(ov2680_res_still)) | |
901 | ||
902 | static struct ov2680_resolution ov2680_res_video[] = { | |
903 | { | |
904 | .desc = "ov2680_1616x1216_30fps", | |
905 | .width = 1616, | |
906 | .height = 1216, | |
907 | .pix_clk_freq = 66, | |
908 | .fps = 30, | |
909 | .used = 0, | |
910 | .pixels_per_line = 1698,//1704, | |
911 | .lines_per_frame = 1294, | |
912 | .bin_factor_x = 0, | |
913 | .bin_factor_y = 0, | |
914 | .bin_mode = 0, | |
915 | .skip_frames = 3, | |
916 | .regs = ov2680_1616x1216_30fps, | |
917 | }, | |
918 | { | |
919 | .desc = "ov2680_720p_30fps", | |
920 | .width = 1616, | |
921 | .height = 916, | |
922 | .fps = 30, | |
923 | .pix_clk_freq = 66, | |
924 | .used = 0, | |
925 | .pixels_per_line = 1698,//1704, | |
926 | .lines_per_frame = 1294, | |
927 | .bin_factor_x = 0, | |
928 | .bin_factor_y = 0, | |
929 | .bin_mode = 0, | |
930 | .skip_frames = 3, | |
931 | .regs = ov2680_1616x916_30fps, | |
932 | }, | |
933 | }; | |
934 | #define N_RES_VIDEO (ARRAY_SIZE(ov2680_res_video)) | |
935 | ||
936 | static struct ov2680_resolution *ov2680_res = ov2680_res_preview; | |
f3aa6840 | 937 | static unsigned long N_RES = N_RES_PREVIEW; |
a49d2536 AC |
938 | |
939 | #endif |