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[mirror_ubuntu-bionic-kernel.git] / drivers / staging / media / atomisp / i2c / ov8858.h
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a49d2536
AC		 1/*
2 * Support for the Omnivision OV8858 camera sensor.
3 *
4 * Copyright (c) 2014 Intel Corporation. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 *
20 */
21
22#ifndef __OV8858_H__
23#define __OV8858_H__
25016567 24#include "../include/linux/atomisp_platform.h"
a49d2536
AC		 25#include <media/v4l2-ctrls.h>
26
27#define I2C_MSG_LENGTH 0x2
28
29/*
30 * This should be added into include/linux/videodev2.h
31 * NOTE: This is most likely not used anywhere.
32 */
33#define V4L2_IDENT_OV8858 V4L2_IDENT_UNKNOWN
34
35/*
36 * Indexes for VCM driver lists
37 */
38#define OV8858_ID_DEFAULT 0
39#define OV8858_SUNNY 1
40
41#define OV8858_OTP_START_ADDR 0x7010
42#define OV8858_OTP_END_ADDR 0x7186
43
44/*
45 * ov8858 System control registers
46 */
47
48#define OV8858_OTP_LOAD_CTRL 0x3D81
49#define OV8858_OTP_MODE_CTRL 0x3D84
50#define OV8858_OTP_START_ADDR_REG 0x3D88
51#define OV8858_OTP_END_ADDR_REG 0x3D8A
52#define OV8858_OTP_ISP_CTRL2 0x5002
53
54#define OV8858_OTP_MODE_MANUAL BIT(6)
55#define OV8858_OTP_MODE_PROGRAM_DISABLE BIT(7)
56#define OV8858_OTP_LOAD_ENABLE BIT(0)
57#define OV8858_OTP_DPC_ENABLE BIT(3)
58
59#define OV8858_PLL1_PREDIV0 0x030A
60#define OV8858_PLL1_PREDIV 0x0300
61#define OV8858_PLL1_MULTIPLIER 0x0301
62#define OV8858_PLL1_SYS_PRE_DIV 0x0305
63#define OV8858_PLL1_SYS_DIVIDER 0x0306
64
65#define OV8858_PLL1_PREDIV0_MASK BIT(0)
66#define OV8858_PLL1_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2))
67#define OV8858_PLL1_MULTIPLIER_MASK 0x01FF
68#define OV8858_PLL1_SYS_PRE_DIV_MASK (BIT(0) | BIT(1))
69#define OV8858_PLL1_SYS_DIVIDER_MASK BIT(0)
70
71#define OV8858_PLL2_PREDIV0 0x0312
72#define OV8858_PLL2_PREDIV 0x030B
73#define OV8858_PLL2_MULTIPLIER 0x030C
74#define OV8858_PLL2_DAC_DIVIDER 0x0312
75#define OV8858_PLL2_SYS_PRE_DIV 0x030F
76#define OV8858_PLL2_SYS_DIVIDER 0x030E
77
78#define OV8858_PLL2_PREDIV0_MASK BIT(4)
79#define OV8858_PLL2_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2))
80#define OV8858_PLL2_MULTIPLIER_MASK 0x01FF
81#define OV8858_PLL2_DAC_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
82#define OV8858_PLL2_SYS_PRE_DIV_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
83#define OV8858_PLL2_SYS_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2))
84
85#define OV8858_PLL_SCLKSEL1 0x3032
86#define OV8858_PLL_SCLKSEL2 0x3033
87#define OV8858_SRB_HOST_INPUT_DIS 0x3106
88
89#define OV8858_PLL_SCLKSEL1_MASK BIT(7)
90#define OV8858_PLL_SCLKSEL2_MASK BIT(1)
91
92#define OV8858_SYS_PRE_DIV_OFFSET 2
93#define OV8858_SYS_PRE_DIV_MASK (BIT(2) | BIT(3))
94#define OV8858_SCLK_PDIV_OFFSET 4
95#define OV8858_SCLK_PDIV_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7))
96
97#define OV8858_TIMING_HTS 0x380C
98#define OV8858_TIMING_VTS 0x380E
99
100#define OV8858_HORIZONTAL_START_H 0x3800
101#define OV8858_VERTICAL_START_H 0x3802
102#define OV8858_HORIZONTAL_END_H 0x3804
103#define OV8858_VERTICAL_END_H 0x3806
104#define OV8858_HORIZONTAL_OUTPUT_SIZE_H 0x3808
105#define OV8858_VERTICAL_OUTPUT_SIZE_H 0x380A
106
107#define OV8858_GROUP_ACCESS 0x3208
108#define OV8858_GROUP_ZERO 0x00
109#define OV8858_GROUP_ACCESS_HOLD_START 0x00
110#define OV8858_GROUP_ACCESS_HOLD_END 0x10
111#define OV8858_GROUP_ACCESS_DELAY_LAUNCH 0xA0
112#define OV8858_GROUP_ACCESS_QUICK_LAUNCH 0xE0
113
114#define OV_SUBDEV_PREFIX "ov"
115#define OV_ID_DEFAULT 0x0000
a49d2536
AC		 116#define OV8858_CHIP_ID 0x8858
117
118#define OV8858_LONG_EXPO 0x3500
119#define OV8858_LONG_GAIN 0x3508
120#define OV8858_LONG_DIGI_GAIN 0x350A
121#define OV8858_SHORT_GAIN 0x350C
122#define OV8858_SHORT_DIGI_GAIN 0x350E
123
124#define OV8858_FORMAT1 0x3820
125#define OV8858_FORMAT2 0x3821
126
127#define OV8858_FLIP_ENABLE 0x06
128
129#define OV8858_MWB_RED_GAIN_H 0x5032
130#define OV8858_MWB_GREEN_GAIN_H 0x5034
131#define OV8858_MWB_BLUE_GAIN_H 0x5036
132#define OV8858_MWB_GAIN_MAX 0x0FFF
133
134#define OV8858_CHIP_ID_HIGH 0x300B
135#define OV8858_CHIP_ID_LOW 0x300C
136#define OV8858_STREAM_MODE 0x0100
137
138#define OV8858_FOCAL_LENGTH_NUM 294 /* 2.94mm */
139#define OV8858_FOCAL_LENGTH_DEM 100
140#define OV8858_F_NUMBER_DEFAULT_NUM 24 /* 2.4 */
141#define OV8858_F_NUMBER_DEM 10
142
143#define OV8858_H_INC_ODD 0x3814
144#define OV8858_H_INC_EVEN 0x3815
145#define OV8858_V_INC_ODD 0x382A
146#define OV8858_V_INC_EVEN 0x382B
147
148#define OV8858_READ_MODE_BINNING_ON 0x0400 /* ToDo: Check this */
149#define OV8858_READ_MODE_BINNING_OFF 0x00 /* ToDo: Check this */
150#define OV8858_BIN_FACTOR_MAX 2
151#define OV8858_INTEGRATION_TIME_MARGIN 14
152
153#define OV8858_MAX_VTS_VALUE 0xFFFF
154#define OV8858_MAX_EXPOSURE_VALUE \
155 (OV8858_MAX_VTS_VALUE - OV8858_INTEGRATION_TIME_MARGIN)
156#define OV8858_MAX_GAIN_VALUE 0x07FF
157
158#define OV8858_MAX_FOCUS_POS 1023
159
160#define OV8858_TEST_PATTERN_REG 0x5E00
161
162struct ov8858_vcm {
163 int (*power_up)(struct v4l2_subdev *sd);
164 int (*power_down)(struct v4l2_subdev *sd);
165 int (*init)(struct v4l2_subdev *sd);
a49d2536
AC		 166 int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value);
167 int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value);
168 int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value);
169 int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value);
170 int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value);
171 int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value);
172};
173
174/*
175 * Defines for register writes and register array processing
176 * */
177#define OV8858_BYTE_MAX 32
178#define OV8858_SHORT_MAX 16
179#define OV8858_TOK_MASK 0xFFF0
180
181#define MAX_FPS_OPTIONS_SUPPORTED 3
182
183#define OV8858_DEPTH_COMP_CONST 2200
184#define OV8858_DEPTH_VTS_CONST 2573
185
186enum ov8858_tok_type {
187 OV8858_8BIT = 0x0001,
188 OV8858_16BIT = 0x0002,
189 OV8858_TOK_TERM = 0xF000, /* terminating token for reg list */
190 OV8858_TOK_DELAY = 0xFE00 /* delay token for reg list */
191};
192
193/*
194 * If register address or register width is not 32 bit width,
195 * user needs to convert it manually
196 */
197struct s_register_setting {
198 u32 reg;
199 u32 val;
200};
201
202/**
203 * struct ov8858_reg - MI sensor register format
204 * @type: type of the register
205 * @reg: 16-bit offset to register
206 * @val: 8/16/32-bit register value
207 *
208 * Define a structure for sensor register initialization values
209 */
210struct ov8858_reg {
211 enum ov8858_tok_type type;
212 u16 sreg;
213 u32 val; /* @set value for read/mod/write, @mask */
214};
215
216struct ov8858_fps_setting {
217 int fps;
218 unsigned short pixels_per_line;
219 unsigned short lines_per_frame;
220 const struct ov8858_reg *regs; /* regs that the fps setting needs */
221};
222
223struct ov8858_resolution {
224 u8 *desc;
225 const struct ov8858_reg *regs;
226 int res;
227 int width;
228 int height;
229 bool used;
230 u8 bin_factor_x;
231 u8 bin_factor_y;
232 unsigned short skip_frames;
233 const struct ov8858_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED];
234};
235
236/*
237 * ov8858 device structure
238 * */
239struct ov8858_device {
240 struct v4l2_subdev sd;
241 struct media_pad pad;
242 struct v4l2_mbus_framefmt format;
243
244 struct camera_sensor_platform_data *platform_data;
245 struct mutex input_lock; /* serialize sensor's ioctl */
246 int fmt_idx;
247 int streaming;
248 int vt_pix_clk_freq_mhz;
249 int fps_index;
250 u16 sensor_id; /* Sensor id from registers */
251 u16 i2c_id; /* Sensor id from i2c_device_id */
252 int exposure;
253 int gain;
254 u16 digital_gain;
255 u16 pixels_per_line;
256 u16 lines_per_frame;
257 u8 fps;
258 u8 *otp_data;
259 /* Prevent the framerate from being lowered in low light scenes. */
260 int limit_exposure_flag;
261 bool hflip;
262 bool vflip;
263
264 const struct ov8858_reg *regs;
265 struct ov8858_vcm *vcm_driver;
266 const struct ov8858_resolution *curr_res_table;
8033120f 267 unsigned long entries_curr_table;
a49d2536
AC		 268
269 struct v4l2_ctrl_handler ctrl_handler;
270 struct v4l2_ctrl *run_mode;
271};
272
273#define to_ov8858_sensor(x) container_of(x, struct ov8858_device, sd)
274
275#define OV8858_MAX_WRITE_BUF_SIZE 32
276struct ov8858_write_buffer {
277 u16 addr;
278 u8 data[OV8858_MAX_WRITE_BUF_SIZE];
279};
280
281struct ov8858_write_ctrl {
282 int index;
283 struct ov8858_write_buffer buffer;
284};
285
286static const struct ov8858_reg ov8858_soft_standby[] = {
287 {OV8858_8BIT, 0x0100, 0x00},
288 {OV8858_TOK_TERM, 0, 0}
289};
290
291static const struct ov8858_reg ov8858_streaming[] = {
292 {OV8858_8BIT, 0x0100, 0x01},
293 {OV8858_TOK_TERM, 0, 0}
294};
295
296static const struct ov8858_reg ov8858_param_hold[] = {
297 {OV8858_8BIT, OV8858_GROUP_ACCESS,
298 OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_START},
299 {OV8858_TOK_TERM, 0, 0}
300};
301
302static const struct ov8858_reg ov8858_param_update[] = {
303 {OV8858_8BIT, OV8858_GROUP_ACCESS,
304 OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_END},
305 {OV8858_8BIT, OV8858_GROUP_ACCESS,
306 OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_DELAY_LAUNCH},
307 {OV8858_TOK_TERM, 0, 0}
308};
309
310extern int dw9718_vcm_power_up(struct v4l2_subdev *sd);
311extern int dw9718_vcm_power_down(struct v4l2_subdev *sd);
312extern int dw9718_vcm_init(struct v4l2_subdev *sd);
a49d2536
AC		 313extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value);
314extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value);
315extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value);
316extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value);
317extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value);
318extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value);
319
320extern int vcm_power_up(struct v4l2_subdev *sd);
321extern int vcm_power_down(struct v4l2_subdev *sd);
322
323static struct ov8858_vcm ov8858_vcms[] = {
324 [OV8858_SUNNY] = {
325 .power_up = dw9718_vcm_power_up,
326 .power_down = dw9718_vcm_power_down,
327 .init = dw9718_vcm_init,
a49d2536
AC		 328 .t_focus_abs = dw9718_t_focus_abs,
329 .t_focus_rel = dw9718_t_focus_rel,
330 .q_focus_status = dw9718_q_focus_status,
331 .q_focus_abs = dw9718_q_focus_abs,
332 .t_vcm_slew = dw9718_t_vcm_slew,
333 .t_vcm_timing = dw9718_t_vcm_timing,
334 },
335 [OV8858_ID_DEFAULT] = {
336 .power_up = NULL,
337 .power_down = NULL,
338 },
339};
340
341
342#define OV8858_RES_WIDTH_MAX 3280
343#define OV8858_RES_HEIGHT_MAX 2464
344
345static struct ov8858_reg ov8858_BasicSettings[] = {
346 {OV8858_8BIT, 0x0103, 0x01}, /* software_reset */
347 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */
348 /* PLL settings */
349 {OV8858_8BIT, 0x0300, 0x05}, /* pll1_pre_div = /4 */
350 {OV8858_8BIT, 0x0302, 0xAF}, /* pll1_multiplier = 175 */
351 {OV8858_8BIT, 0x0303, 0x00}, /* pll1_divm = /(1 + 0) */
352 {OV8858_8BIT, 0x0304, 0x03}, /* pll1_div_mipi = /8 */
353 {OV8858_8BIT, 0x030B, 0x02}, /* pll2_pre_div = /2 */
354 {OV8858_8BIT, 0x030D, 0x4E}, /* pll2_r_divp = 78 */
355 {OV8858_8BIT, 0x030E, 0x00}, /* pll2_r_divs = /1 */
356 {OV8858_8BIT, 0x030F, 0x04}, /* pll2_r_divsp = /(1 + 4) */
357 /* pll2_pre_div0 = /1, pll2_r_divdac = /(1 + 1) */
358 {OV8858_8BIT, 0x0312, 0x01},
359 {OV8858_8BIT, 0x031E, 0x0C}, /* pll1_no_lat = 1, mipi_bitsel_man = 0 */
360
361 /* PAD OEN2, VSYNC out enable=0x80, disable=0x00 */
362 {OV8858_8BIT, 0x3002, 0x80},
363 /* PAD OUT2, VSYNC pulse direction low-to-high = 1 */
364 {OV8858_8BIT, 0x3007, 0x01},
365 /* PAD SEL2, VSYNC out value = 0 */
366 {OV8858_8BIT, 0x300D, 0x00},
367 /* PAD OUT2, VSYNC out select = 0 */
368 {OV8858_8BIT, 0x3010, 0x00},
369
370 /* Npump clock div = /2, Ppump clock div = /4 */
371 {OV8858_8BIT, 0x3015, 0x01},
372 /*
373 * mipi_lane_mode = 1+3, mipi_lvds_sel = 1 = MIPI enable,
374 * r_phy_pd_mipi_man = 0, lane_dis_option = 0
375 */
376 {OV8858_8BIT, 0x3018, 0x72},
377 /* Clock switch output = normal, pclk_div = /1 */
378 {OV8858_8BIT, 0x3020, 0x93},
379 /*
380 * lvds_mode_o = 0, clock lane disable when pd_mipi = 0,
381 * pd_mipi enable when rst_sync = 1
382 */
383 {OV8858_8BIT, 0x3022, 0x01},
384 {OV8858_8BIT, 0x3031, 0x0A}, /* mipi_bit_sel = 10 */
385 {OV8858_8BIT, 0x3034, 0x00}, /* Unknown */
386 /* sclk_div = /1, sclk_pre_div = /1, chip debug = 1 */
387 {OV8858_8BIT, 0x3106, 0x01},
388
389 {OV8858_8BIT, 0x3305, 0xF1}, /* Unknown */
390 {OV8858_8BIT, 0x3307, 0x04}, /* Unknown */
391 {OV8858_8BIT, 0x3308, 0x00}, /* Unknown */
392 {OV8858_8BIT, 0x3309, 0x28}, /* Unknown */
393 {OV8858_8BIT, 0x330A, 0x00}, /* Unknown */
394 {OV8858_8BIT, 0x330B, 0x20}, /* Unknown */
395 {OV8858_8BIT, 0x330C, 0x00}, /* Unknown */
396 {OV8858_8BIT, 0x330D, 0x00}, /* Unknown */
397 {OV8858_8BIT, 0x330E, 0x00}, /* Unknown */
398 {OV8858_8BIT, 0x330F, 0x40}, /* Unknown */
399
400 {OV8858_8BIT, 0x3500, 0x00}, /* long exposure = 0x9A20 */
401 {OV8858_8BIT, 0x3501, 0x9A}, /* long exposure = 0x9A20 */
402 {OV8858_8BIT, 0x3502, 0x20}, /* long exposure = 0x9A20 */
403 /*
404 * Digital fraction gain delay option = Delay 1 frame,
405 * Gain change delay option = Delay 1 frame,
406 * Gain delay option = Delay 1 frame,
407 * Gain manual as sensor gain = Input gain as real gain format,
408 * Exposure delay option (must be 0 = Delay 1 frame,
409 * Exposure change delay option (must be 0) = Delay 1 frame
410 */
411 {OV8858_8BIT, 0x3503, 0x00},
412 {OV8858_8BIT, 0x3505, 0x80}, /* gain conversation option */
413 /*
414 * [10:7] are integer gain, [6:0] are fraction gain. For example:
415 * 0x80 is 1x gain, 0x100 is 2x gain, 0x1C0 is 3.5x gain
416 */
417 {OV8858_8BIT, 0x3508, 0x02}, /* long gain = 0x0200 */
418 {OV8858_8BIT, 0x3509, 0x00}, /* long gain = 0x0200 */
419 {OV8858_8BIT, 0x350C, 0x00}, /* short gain = 0x0080 */
420 {OV8858_8BIT, 0x350D, 0x80}, /* short gain = 0x0080 */
421 {OV8858_8BIT, 0x3510, 0x00}, /* short exposure = 0x000200 */
422 {OV8858_8BIT, 0x3511, 0x02}, /* short exposure = 0x000200 */
423 {OV8858_8BIT, 0x3512, 0x00}, /* short exposure = 0x000200 */
424
425 {OV8858_8BIT, 0x3600, 0x00}, /* Unknown */
426 {OV8858_8BIT, 0x3601, 0x00}, /* Unknown */
427 {OV8858_8BIT, 0x3602, 0x00}, /* Unknown */
428 {OV8858_8BIT, 0x3603, 0x00}, /* Unknown */
429 {OV8858_8BIT, 0x3604, 0x22}, /* Unknown */
430 {OV8858_8BIT, 0x3605, 0x30}, /* Unknown */
431 {OV8858_8BIT, 0x3606, 0x00}, /* Unknown */
432 {OV8858_8BIT, 0x3607, 0x20}, /* Unknown */
433 {OV8858_8BIT, 0x3608, 0x11}, /* Unknown */
434 {OV8858_8BIT, 0x3609, 0x28}, /* Unknown */
435 {OV8858_8BIT, 0x360A, 0x00}, /* Unknown */
436 {OV8858_8BIT, 0x360B, 0x06}, /* Unknown */
437 {OV8858_8BIT, 0x360C, 0xDC}, /* Unknown */
438 {OV8858_8BIT, 0x360D, 0x40}, /* Unknown */
439 {OV8858_8BIT, 0x360E, 0x0C}, /* Unknown */
440 {OV8858_8BIT, 0x360F, 0x20}, /* Unknown */
441 {OV8858_8BIT, 0x3610, 0x07}, /* Unknown */
442 {OV8858_8BIT, 0x3611, 0x20}, /* Unknown */
443 {OV8858_8BIT, 0x3612, 0x88}, /* Unknown */
444 {OV8858_8BIT, 0x3613, 0x80}, /* Unknown */
445 {OV8858_8BIT, 0x3614, 0x58}, /* Unknown */
446 {OV8858_8BIT, 0x3615, 0x00}, /* Unknown */
447 {OV8858_8BIT, 0x3616, 0x4A}, /* Unknown */
448 {OV8858_8BIT, 0x3617, 0x90}, /* Unknown */
449 {OV8858_8BIT, 0x3618, 0x56}, /* Unknown */
450 {OV8858_8BIT, 0x3619, 0x70}, /* Unknown */
451 {OV8858_8BIT, 0x361A, 0x99}, /* Unknown */
452 {OV8858_8BIT, 0x361B, 0x00}, /* Unknown */
453 {OV8858_8BIT, 0x361C, 0x07}, /* Unknown */
454 {OV8858_8BIT, 0x361D, 0x00}, /* Unknown */
455 {OV8858_8BIT, 0x361E, 0x00}, /* Unknown */
456 {OV8858_8BIT, 0x361F, 0x00}, /* Unknown */
457 {OV8858_8BIT, 0x3633, 0x0C}, /* Unknown */
458 {OV8858_8BIT, 0x3634, 0x0C}, /* Unknown */
459 {OV8858_8BIT, 0x3635, 0x0C}, /* Unknown */
460 {OV8858_8BIT, 0x3636, 0x0C}, /* Unknown */
461 {OV8858_8BIT, 0x3638, 0xFF}, /* Unknown */
462 {OV8858_8BIT, 0x3645, 0x13}, /* Unknown */
463 {OV8858_8BIT, 0x3646, 0x83}, /* Unknown */
464 {OV8858_8BIT, 0x364A, 0x07}, /* Unknown */
465
466 {OV8858_8BIT, 0x3700, 0x30}, /* Unknown */
467 {OV8858_8BIT, 0x3701, 0x18}, /* Unknown */
468 {OV8858_8BIT, 0x3702, 0x50}, /* Unknown */
469 {OV8858_8BIT, 0x3703, 0x32}, /* Unknown */
470 {OV8858_8BIT, 0x3704, 0x28}, /* Unknown */
471 {OV8858_8BIT, 0x3705, 0x00}, /* Unknown */
472 {OV8858_8BIT, 0x3706, 0x6A}, /* Unknown */
473 {OV8858_8BIT, 0x3707, 0x08}, /* Unknown */
474 {OV8858_8BIT, 0x3708, 0x48}, /* Unknown */
475 {OV8858_8BIT, 0x3709, 0x66}, /* Unknown */
476 {OV8858_8BIT, 0x370A, 0x01}, /* Unknown */
477 {OV8858_8BIT, 0x370B, 0x6A}, /* Unknown */
478 {OV8858_8BIT, 0x370C, 0x07}, /* Unknown */
479 {OV8858_8BIT, 0x3712, 0x44}, /* Unknown */
480 {OV8858_8BIT, 0x3714, 0x24}, /* Unknown */
481 {OV8858_8BIT, 0x3718, 0x14}, /* Unknown */
482 {OV8858_8BIT, 0x3719, 0x31}, /* Unknown */
483 {OV8858_8BIT, 0x371E, 0x31}, /* Unknown */
484 {OV8858_8BIT, 0x371F, 0x7F}, /* Unknown */
485 {OV8858_8BIT, 0x3720, 0x0A}, /* Unknown */
486 {OV8858_8BIT, 0x3721, 0x0A}, /* Unknown */
487 {OV8858_8BIT, 0x3724, 0x0C}, /* Unknown */
488 {OV8858_8BIT, 0x3725, 0x02}, /* Unknown */
489 {OV8858_8BIT, 0x3726, 0x0C}, /* Unknown */
490 {OV8858_8BIT, 0x3728, 0x0A}, /* Unknown */
491 {OV8858_8BIT, 0x3729, 0x03}, /* Unknown */
492 {OV8858_8BIT, 0x372A, 0x06}, /* Unknown */
493 {OV8858_8BIT, 0x372B, 0xA6}, /* Unknown */
494 {OV8858_8BIT, 0x372C, 0xA6}, /* Unknown */
495 {OV8858_8BIT, 0x372D, 0xA6}, /* Unknown */
496 {OV8858_8BIT, 0x372E, 0x0C}, /* Unknown */
497 {OV8858_8BIT, 0x372F, 0x20}, /* Unknown */
498 {OV8858_8BIT, 0x3730, 0x02}, /* Unknown */
499 {OV8858_8BIT, 0x3731, 0x0C}, /* Unknown */
500 {OV8858_8BIT, 0x3732, 0x28}, /* Unknown */
501 {OV8858_8BIT, 0x3733, 0x10}, /* Unknown */
502 {OV8858_8BIT, 0x3734, 0x40}, /* Unknown */
503 {OV8858_8BIT, 0x3736, 0x30}, /* Unknown */
504 {OV8858_8BIT, 0x373A, 0x0A}, /* Unknown */
505 {OV8858_8BIT, 0x373B, 0x0B}, /* Unknown */
506 {OV8858_8BIT, 0x373C, 0x14}, /* Unknown */
507 {OV8858_8BIT, 0x373E, 0x06}, /* Unknown */
508 {OV8858_8BIT, 0x3755, 0x10}, /* Unknown */
509 {OV8858_8BIT, 0x3758, 0x00}, /* Unknown */
510 {OV8858_8BIT, 0x3759, 0x4C}, /* Unknown */
511 {OV8858_8BIT, 0x375A, 0x0C}, /* Unknown */
512 {OV8858_8BIT, 0x375B, 0x26}, /* Unknown */
513 {OV8858_8BIT, 0x375C, 0x20}, /* Unknown */
514 {OV8858_8BIT, 0x375D, 0x04}, /* Unknown */
515 {OV8858_8BIT, 0x375E, 0x00}, /* Unknown */
516 {OV8858_8BIT, 0x375F, 0x28}, /* Unknown */
517 {OV8858_8BIT, 0x3760, 0x00}, /* Unknown */
518 {OV8858_8BIT, 0x3761, 0x00}, /* Unknown */
519 {OV8858_8BIT, 0x3762, 0x00}, /* Unknown */
520 {OV8858_8BIT, 0x3763, 0x00}, /* Unknown */
521 {OV8858_8BIT, 0x3766, 0xFF}, /* Unknown */
522 {OV8858_8BIT, 0x3768, 0x22}, /* Unknown */
523 {OV8858_8BIT, 0x3769, 0x44}, /* Unknown */
524 {OV8858_8BIT, 0x376A, 0x44}, /* Unknown */
525 {OV8858_8BIT, 0x376B, 0x00}, /* Unknown */
526 {OV8858_8BIT, 0x376F, 0x01}, /* Unknown */
527 {OV8858_8BIT, 0x3772, 0x46}, /* Unknown */
528 {OV8858_8BIT, 0x3773, 0x04}, /* Unknown */
529 {OV8858_8BIT, 0x3774, 0x2C}, /* Unknown */
530 {OV8858_8BIT, 0x3775, 0x13}, /* Unknown */
531 {OV8858_8BIT, 0x3776, 0x08}, /* Unknown */
532 {OV8858_8BIT, 0x3777, 0x00}, /* Unknown */
533 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */
534 {OV8858_8BIT, 0x37A0, 0x88}, /* Unknown */
535 {OV8858_8BIT, 0x37A1, 0x7A}, /* Unknown */
536 {OV8858_8BIT, 0x37A2, 0x7A}, /* Unknown */
537 {OV8858_8BIT, 0x37A3, 0x00}, /* Unknown */
538 {OV8858_8BIT, 0x37A4, 0x00}, /* Unknown */
539 {OV8858_8BIT, 0x37A5, 0x00}, /* Unknown */
540 {OV8858_8BIT, 0x37A6, 0x00}, /* Unknown */
541 {OV8858_8BIT, 0x37A7, 0x88}, /* Unknown */
542 {OV8858_8BIT, 0x37A8, 0x98}, /* Unknown */
543 {OV8858_8BIT, 0x37A9, 0x98}, /* Unknown */
544 {OV8858_8BIT, 0x37AA, 0x88}, /* Unknown */
545 {OV8858_8BIT, 0x37AB, 0x5C}, /* Unknown */
546 {OV8858_8BIT, 0x37AC, 0x5C}, /* Unknown */
547 {OV8858_8BIT, 0x37AD, 0x55}, /* Unknown */
548 {OV8858_8BIT, 0x37AE, 0x19}, /* Unknown */
549 {OV8858_8BIT, 0x37AF, 0x19}, /* Unknown */
550 {OV8858_8BIT, 0x37B0, 0x00}, /* Unknown */
551 {OV8858_8BIT, 0x37B1, 0x00}, /* Unknown */
552 {OV8858_8BIT, 0x37B2, 0x00}, /* Unknown */
553 {OV8858_8BIT, 0x37B3, 0x84}, /* Unknown */
554 {OV8858_8BIT, 0x37B4, 0x84}, /* Unknown */
555 {OV8858_8BIT, 0x37B5, 0x66}, /* Unknown */
556 {OV8858_8BIT, 0x37B6, 0x00}, /* Unknown */
557 {OV8858_8BIT, 0x37B7, 0x00}, /* Unknown */
558 {OV8858_8BIT, 0x37B8, 0x00}, /* Unknown */
559 {OV8858_8BIT, 0x37B9, 0xFF}, /* Unknown */
560
561 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */
562 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */
563 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */
564 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */
565 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */
566 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */
567 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */
568 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */
569 {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high */
570 {OV8858_8BIT, 0x3809, 0xC0}, /* h_output_size low */
571 {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */
572 {OV8858_8BIT, 0x380B, 0x90}, /* v_output_size low */
573 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */
574 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */
575 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */
576 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */
577 {OV8858_8BIT, 0x3810, 0x00}, /* h_win offset high */
578 {OV8858_8BIT, 0x3811, 0x04}, /* h_win offset low */
579 {OV8858_8BIT, 0x3812, 0x00}, /* v_win offset high */
580 {OV8858_8BIT, 0x3813, 0x02}, /* v_win offset low */
581 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */
582 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */
583 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */
584 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */
585 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */
586 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */
587
588 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */
589 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */
590 {OV8858_8BIT, 0x3837, 0x18}, /* Unknown */
591 {OV8858_8BIT, 0x3841, 0xFF}, /* AUTO_SIZE_CTRL */
592 {OV8858_8BIT, 0x3846, 0x48}, /* Unknown */
593
594 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */
595 {OV8858_8BIT, 0x3D8C, 0x73}, /* OTP_SETTING_STT_ADDRESS */
596 {OV8858_8BIT, 0x3D8D, 0xDE}, /* OTP_SETTING_STT_ADDRESS */
597 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */
598 {OV8858_8BIT, 0x3F0A, 0x80}, /* PSRAM control register */
599
600 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */
601 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */
602 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */
603 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */
604 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */
605 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */
606 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */
607 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */
608 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */
609 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */
610 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */
611 {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */
612 {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */
613 {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */
614 {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */
615 {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */
616 {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */
617 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */
618 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */
619 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */
620 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */
621 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */
622 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */
623 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */
624 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */
625
626 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */
627 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */
628 {OV8858_8BIT, 0x4300, 0xFF}, /* clip_max[11:4] = 0xFFF */
629 {OV8858_8BIT, 0x4301, 0x00}, /* clip_min[11:4] = 0 */
630 {OV8858_8BIT, 0x4302, 0x0F}, /* clip_min/max[3:0] */
631 {OV8858_8BIT, 0x4307, 0x01}, /* Unknown */
632 {OV8858_8BIT, 0x4316, 0x00}, /* CTRL16 = default */
633 {OV8858_8BIT, 0x4503, 0x18}, /* Unknown */
634 {OV8858_8BIT, 0x4500, 0x38}, /* Unknown */
635 {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */
636 {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */
637 /* wkup_dly = Mark1 wakeup delay/2^10 = 0x25 */
638 {OV8858_8BIT, 0x4808, 0x25},
639 {OV8858_8BIT, 0x4816, 0x52}, /* Embedded data type*/
640 {OV8858_8BIT, 0x481F, 0x32}, /* clk_prepare_min = 0x32 */
641 {OV8858_8BIT, 0x4825, 0x3A}, /* lpx_p_min = 0x3A */
642 {OV8858_8BIT, 0x4826, 0x40}, /* hs_prepare_min = 0x40 */
643 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */
644 {OV8858_8BIT, 0x4850, 0x10}, /* LANE SEL01 */
645 {OV8858_8BIT, 0x4851, 0x32}, /* LANE SEL02 */
646
647 {OV8858_8BIT, 0x4B00, 0x2A}, /* Unknown */
648 {OV8858_8BIT, 0x4B0D, 0x00}, /* Unknown */
649 {OV8858_8BIT, 0x4D00, 0x04}, /* TPM_CTRL_REG */
650 {OV8858_8BIT, 0x4D01, 0x18}, /* TPM_CTRL_REG */
651 {OV8858_8BIT, 0x4D02, 0xC3}, /* TPM_CTRL_REG */
652 {OV8858_8BIT, 0x4D03, 0xFF}, /* TPM_CTRL_REG */
653 {OV8858_8BIT, 0x4D04, 0xFF}, /* TPM_CTRL_REG */
654 {OV8858_8BIT, 0x4D05, 0xFF}, /* TPM_CTRL_REG */
655
656 /*
657 * Lens correction (LENC) function enable = 0
658 * Slave sensor AWB Gain function enable = 1
659 * Slave sensor AWB Statistics function enable = 1
660 * Master sensor AWB Gain function enable = 1
661 * Master sensor AWB Statistics function enable = 1
662 * Black DPC function enable = 1
663 * White DPC function enable =1
664 */
665 {OV8858_8BIT, 0x5000, 0x7E},
666 {OV8858_8BIT, 0x5001, 0x01}, /* BLC function enable = 1 */
667 /*
668 * Horizontal scale function enable = 0
669 * WBMATCH bypass mode = Select slave sensor's gain
670 * WBMATCH function enable = 0
671 * Master MWB gain support RGBC = 0
672 * OTP_DPC function enable = 1
673 * Manual mode of VarioPixel function enable = 0
674 * Manual enable of VarioPixel function enable = 0
675 * Use VSYNC to latch ISP modules's function enable signals = 0
676 */
677 {OV8858_8BIT, 0x5002, 0x08},
678 /*
679 * Bypass all ISP modules after BLC module = 0
680 * DPC_DBC buffer control enable = 1
681 * WBMATCH VSYNC selection = Select master sensor's VSYNC fall
682 * Select master AWB gain to embed line = AWB gain before manual mode
683 * Enable BLC's input flip_i signal = 0
684 */
685 {OV8858_8BIT, 0x5003, 0x20},
686 {OV8858_8BIT, 0x5041, 0x1D}, /* ISP CTRL41 - embedded data=on */
687 {OV8858_8BIT, 0x5046, 0x12}, /* ISP CTRL46 = default */
688 /*
689 * Tail enable = 1
690 * Saturate cross cluster enable = 1
691 * Remove cross cluster enable = 1
692 * Enable to remove connected defect pixels in same channel = 1
693 * Enable to remove connected defect pixels in different channel = 1
694 * Smooth enable, use average G for recovery = 1
695 * Black/white sensor mode enable = 0
696 * Manual mode enable = 0
697 */
698 {OV8858_8BIT, 0x5780, 0xFC},
699 {OV8858_8BIT, 0x5784, 0x0C}, /* DPC CTRL04 */
700 {OV8858_8BIT, 0x5787, 0x40}, /* DPC CTRL07 */
701 {OV8858_8BIT, 0x5788, 0x08}, /* DPC CTRL08 */
702 {OV8858_8BIT, 0x578A, 0x02}, /* DPC CTRL0A */
703 {OV8858_8BIT, 0x578B, 0x01}, /* DPC CTRL0B */
704 {OV8858_8BIT, 0x578C, 0x01}, /* DPC CTRL0C */
705 {OV8858_8BIT, 0x578E, 0x02}, /* DPC CTRL0E */
706 {OV8858_8BIT, 0x578F, 0x01}, /* DPC CTRL0F */
707 {OV8858_8BIT, 0x5790, 0x01}, /* DPC CTRL10 */
708 {OV8858_8BIT, 0x5901, 0x00}, /* VAP CTRL01 = default */
709 /* WINC CTRL08 = embedded data in 1st line*/
710 {OV8858_8BIT, 0x5A08, 0x00},
711 {OV8858_8BIT, 0x5B00, 0x02}, /* OTP CTRL00 */
712 {OV8858_8BIT, 0x5B01, 0x10}, /* OTP CTRL01 */
713 {OV8858_8BIT, 0x5B02, 0x03}, /* OTP CTRL02 */
714 {OV8858_8BIT, 0x5B03, 0xCF}, /* OTP CTRL03 */
715 {OV8858_8BIT, 0x5B05, 0x6C}, /* OTP CTRL05 = default */
716 {OV8858_8BIT, 0x5E00, 0x00}, /* PRE CTRL00 = default */
717 {OV8858_8BIT, 0x5E01, 0x41}, /* PRE_CTRL01 = default */
718
719 {OV8858_TOK_TERM, 0, 0}
720};
721
722/*****************************STILL********************************/
723
724static const struct ov8858_reg ov8858_8M[] = {
725 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */
726 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */
727 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */
728 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */
729 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */
730 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */
731 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */
732 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low 3283 */
733 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */
734 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */
735 {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 2464 */
736 {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */
737 {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */
738 {OV8858_8BIT, 0x380B, 0xa0}, /* v_output_size low */
739 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */
740 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */
741 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */
742 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */
743 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */
744 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */
745 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */
746 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */
747 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */
748 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */
749 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */
750 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */
751 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */
752 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */
753 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */
754 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */
755 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */
756 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */
757 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */
758 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */
759 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */
760 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */
761 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */
762 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */
763 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */
764 {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */
765 {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */
766 {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */
767 {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */
768 {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */
769 {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */
770 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */
771 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */
772 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */
773 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */
774 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */
775 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */
776 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */
777 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */
778 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */
779 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */
780 {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */
781 {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */
782 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */
783 {OV8858_TOK_TERM, 0, 0}
784};
785
786static const struct ov8858_reg ov8858_3276x1848[] = {
787 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */
788 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */
789 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */
790 {OV8858_8BIT, 0x3801, 0x10}, /* h_crop_start low 0c->10*/
791 {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */
792 {OV8858_8BIT, 0x3803, 0x42}, /* v_crop_start low 3e->42*/
793 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */
794 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */
795 {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */
796 {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */
797 {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3276 x 1848 */
798 {OV8858_8BIT, 0x3809, 0xCC}, /* h_output_size low d0->cc*/
799 {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */
800 {OV8858_8BIT, 0x380B, 0x38}, /* v_output_size low 3c->38*/
801 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */
802 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */
803 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */
804 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */
805 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */
806 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */
807 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */
808 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */
809 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */
810 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */
811 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */
812 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */
813 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */
814 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */
815 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */
816 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */
817 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */
818 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */
819 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */
820 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */
821 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */
822 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */
823 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */
824 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */
825 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */
826 {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */
827 {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */
828 {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */
829 {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */
830 {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */
831 {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */
832 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */
833 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */
834 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */
835 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */
836 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */
837 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */
838 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */
839 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */
840 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */
841 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */
842 {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */
843 {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */
844 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */
845 {OV8858_TOK_TERM, 0, 0}
846};
847
848static const struct ov8858_reg ov8858_6M[] = {
849 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */
850 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */
851 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */
852 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */
853 {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */
854 {OV8858_8BIT, 0x3803, 0x3E}, /* v_crop_start low */
855 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */
856 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */
857 {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */
858 {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */
859 {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 1852 */
860 {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */
861 {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */
862 {OV8858_8BIT, 0x380B, 0x3C}, /* v_output_size low */
863 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */
864 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */
865 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */
866 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */
867 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */
868 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */
869 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */
870 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */
871 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */
872 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */
873 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */
874 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */
875 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */
876 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */
877 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */
878 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */
879 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */
880 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */
881 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */
882 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */
883 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */
884 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */
885 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */
886 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */
887 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */
888 {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */
889 {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */
890 {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */
891 {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */
892 {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */
893 {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */
894 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */
895 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */
896 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */
897 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */
898 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */
899 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */
900 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */
901 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */
902 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */
903 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */
904 {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */
905 {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */
906 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */
907 {OV8858_TOK_TERM, 0, 0}
908};
909
910static const struct ov8858_reg ov8858_1080P_60[] = {
911 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */
912 {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */
913 {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */
914 {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */
915 {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */
916 {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */
917 {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */
918 {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */
919 {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */
920 {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */
921 {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/
922 {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */
923 {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */
924 {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */
925 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */
926 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */
927 {OV8858_8BIT, 0x380E, 0x04}, /* vertical timing size high */
928 {OV8858_8BIT, 0x380F, 0xEC}, /* vertical timing size low */
929 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */
930 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */
931 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */
932 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */
933 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */
934 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */
935 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */
936 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */
937 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */
938 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */
939 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */
940 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */
941 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */
942 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */
943 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */
944 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */
945 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */
946 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */
947 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */
948 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */
949 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */
950 {OV8858_8BIT, 0x4022, 0x07}, /* Anchor left end = 0x072D */
951 {OV8858_8BIT, 0x4023, 0x2D}, /* Anchor left end = 0x072D */
952 {OV8858_8BIT, 0x4024, 0x07}, /* Anchor right start = 0x079E */
953 {OV8858_8BIT, 0x4025, 0x9E}, /* Anchor right start = 0x079E */
954 {OV8858_8BIT, 0x4026, 0x07}, /* Anchor right end = 0x079F */
955 {OV8858_8BIT, 0x4027, 0x9F}, /* Anchor right end = 0x079F */
956 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */
957 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */
958 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */
959 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */
960 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */
961 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */
962 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */
963 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */
964 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */
965 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */
966 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */
967 {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */
968 {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */
969 {OV8858_TOK_TERM, 0, 0}
970};
971
972static const struct ov8858_reg ov8858_1080P_30[] = {
973 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */
974 {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */
975 {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */
976 {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */
977 {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */
978 {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */
979 {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */
980 {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */
981 {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */
982 {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */
983 {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/
984 {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */
985 {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */
986 {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */
987 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */
988 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */
989 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */
990 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */
991 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */
992 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */
993 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */
994 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */
995 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */
996 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */
997 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */
998 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */
999 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */
1000 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */
1001 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */
1002 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */
1003 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */
1004 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */
1005 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */
1006 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */
1007 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */
1008 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */
1009 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */
1010 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */
1011 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */
1012 {OV8858_8BIT, 0x4022, 0x07}, /* Anchor left end = 0x072D */
1013 {OV8858_8BIT, 0x4023, 0x2D}, /* Anchor left end = 0x072D */
1014 {OV8858_8BIT, 0x4024, 0x07}, /* Anchor right start = 0x079E */
1015 {OV8858_8BIT, 0x4025, 0x9E}, /* Anchor right start = 0x079E */
1016 {OV8858_8BIT, 0x4026, 0x07}, /* Anchor right end = 0x079F */
1017 {OV8858_8BIT, 0x4027, 0x9F}, /* Anchor right end = 0x079F */
1018 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */
1019 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */
1020 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */
1021 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */
1022 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */
1023 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */
1024 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */
1025 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */
1026 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */
1027 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */
1028 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */
1029 {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */
1030 {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */
1031 {OV8858_TOK_TERM, 0, 0}
1032};
1033
1034static const struct ov8858_reg ov8858_1640x1232[] = {
1035 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */
1036 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */
1037 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */
1038 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */
1039 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */
1040 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */
1041 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */
1042 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */
1043 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */
1044 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */
1045 {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1232 */
1046 {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */
1047 {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */
1048 {OV8858_8BIT, 0x380B, 0xD0}, /* v_output_size low */
1049 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */
1050 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */
1051 {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */
1052 {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */
1053 {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */
1054 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */
1055 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */
1056 {OV8858_8BIT, 0x3821, 0x67}, /* format2 */
1057 {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */
1058 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */
1059 {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */
1060 {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */
1061 {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */
1062 {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */
1063 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */
1064 {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */
1065 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */
1066 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */
1067 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */
1068 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */
1069 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */
1070 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */
1071 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */
1072 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */
1073 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */
1074 {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */
1075 {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */
1076 {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */
1077 {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */
1078 {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */
1079 {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */
1080 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */
1081 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */
1082 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */
1083 {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */
1084 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */
1085 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */
1086 {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */
1087 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */
1088 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */
1089 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */
1090 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */
1091 {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */
1092 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */
1093 {OV8858_TOK_TERM, 0, 0}
1094};
1095
1096static const struct ov8858_reg ov8858_1640x1096[] = {
1097 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */
1098 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */
1099 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */
1100 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */
1101 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */
1102 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */
1103 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */
1104 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */
1105 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */
1106 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */
1107 {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1096 */
1108 {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */
1109 {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */
1110 {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */
1111 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */
1112 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */
1113 {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */
1114 {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */
1115 {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */
1116 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */
1117 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */
1118 {OV8858_8BIT, 0x3821, 0x67}, /* format2 */
1119 {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */
1120 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */
1121 {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */
1122 {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */
1123 {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */
1124 {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */
1125 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */
1126 {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */
1127 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */
1128 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */
1129 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */
1130 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */
1131 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */
1132 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */
1133 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */
1134 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */
1135 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */
1136 {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */
1137 {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */
1138 {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */
1139 {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */
1140 {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */
1141 {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */
1142 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */
1143 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */
1144 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */
1145 {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */
1146 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */
1147 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */
1148 {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */
1149 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */
1150 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */
1151 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */
1152 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */
1153 {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */
1154 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */
1155 {OV8858_TOK_TERM, 0, 0}
1156};
1157
1158
1159static const struct ov8858_reg ov8858_1640x926[] = {
1160 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */
1161 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */
1162 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */
1163 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */
1164 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */
1165 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */
1166 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */
1167 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */
1168 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */
1169 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */
1170 {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 926 */
1171 {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */
1172 {OV8858_8BIT, 0x380A, 0x03}, /* v_output_size high */
1173 {OV8858_8BIT, 0x380B, 0x9E}, /* v_output_size low */
1174 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */
1175 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */
1176 {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */
1177 {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */
1178 {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */
1179 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */
1180 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */
1181 {OV8858_8BIT, 0x3821, 0x67}, /* format2 */
1182 {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */
1183 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */
1184 {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */
1185 {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */
1186 {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */
1187 {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */
1188 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */
1189 {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */
1190 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */
1191 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */
1192 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */
1193 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */
1194 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */
1195 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */
1196 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */
1197 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */
1198 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */
1199 {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */
1200 {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */
1201 {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */
1202 {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */
1203 {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */
1204 {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */
1205 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */
1206 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */
1207 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */
1208 {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */
1209 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */
1210 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */
1211 {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */
1212 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */
1213 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */
1214 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */
1215 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */
1216 {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */
1217 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */
1218 {OV8858_TOK_TERM, 0, 0}
1219};
1220
1221static struct ov8858_resolution ov8858_res_preview[] = {
1222 {
1223 .desc = "ov8858_1640x926_PREVIEW",
1224 .width = 1640,
1225 .height = 926,
1226 .used = 0,
1227 .regs = ov8858_1640x926,
1228 .bin_factor_x = 0,
1229 .bin_factor_y = 0,
1230 .skip_frames = 0,
1231 .fps_options = {
1232 {
1233 .fps = 30,
1234 .pixels_per_line = 3880,
1235 .lines_per_frame = 2573,
1236 },
1237 {
1238 }
1239 },
1240 },
1241 {
1242 .desc = "ov8858_1640x1232_PREVIEW",
1243 .width = 1640,
1244 .height = 1232,
1245 .used = 0,
1246 .regs = ov8858_1640x1232,
1247 .bin_factor_x = 0,
1248 .bin_factor_y = 0,
1249 .skip_frames = 0,
1250 .fps_options = {
1251 {
1252 .fps = 30,
1253 .pixels_per_line = 3880,
1254 .lines_per_frame = 2573,
1255 },
1256 {
1257 }
1258 },
1259 },
1260 {
1261 .desc = "ov8858_3276x1848_PREVIEW",
1262 .width = 3276,
1263 .height = 1848,
1264 .used = 0,
1265 .regs = ov8858_3276x1848,
1266 .bin_factor_x = 0,
1267 .bin_factor_y = 0,
1268 .skip_frames = 0,
1269 .fps_options = {
1270 {
1271 .fps = 30,
1272 .pixels_per_line = 3880,
1273 .lines_per_frame = 2573,
1274 },
1275 {
1276 }
1277 },
1278 },
1279 {
1280 .desc = "ov8858_8M_PREVIEW",
1281 .width = 3280,
1282 .height = 2464,
1283 .used = 0,
1284 .regs = ov8858_8M,
1285 .bin_factor_x = 0,
1286 .bin_factor_y = 0,
1287 .skip_frames = 0,
1288 .fps_options = {
1289 {
1290 .fps = 30,
1291 .pixels_per_line = 3880,
1292 .lines_per_frame = 2573,
1293 },
1294 {
1295 }
1296 },
1297 },
1298};
1299
1300static struct ov8858_resolution ov8858_res_still[] = {
1301 {
1302 .desc = "ov8858_1640x1232_STILL",
1303 .width = 1640,
1304 .height = 1232,
1305 .used = 0,
1306 .regs = ov8858_1640x1232,
1307 .bin_factor_x = 0,
1308 .bin_factor_y = 0,
1309 .skip_frames = 0,
1310 .fps_options = {
1311 {
1312 .fps = 30,
1313 .pixels_per_line = 3880,
1314 .lines_per_frame = 2573,
1315 },
1316 {
1317 }
1318 },
1319 },
1320 {
1321 .desc = "ov8858_1640x926_STILL",
1322 .width = 1640,
1323 .height = 926,
1324 .used = 0,
1325 .regs = ov8858_1640x926,
1326 .bin_factor_x = 0,
1327 .bin_factor_y = 0,
1328 .skip_frames = 1,
1329 .fps_options = {
1330 {
1331 .fps = 30,
1332 .pixels_per_line = 3880,
1333 .lines_per_frame = 2573,
1334 },
1335 {
1336 }
1337 },
1338 },
1339 {
1340 .desc = "ov8858_3276X1848_STILL",
1341 .width = 3276,
1342 .height = 1848,
1343 .used = 0,
1344 .regs = ov8858_3276x1848,
1345 .bin_factor_x = 0,
1346 .bin_factor_y = 0,
1347 .skip_frames = 1,
1348 .fps_options = {
1349 {
1350 .fps = 30,
1351 .pixels_per_line = 3880,
1352 .lines_per_frame = 2573,
1353 },
1354 {
1355 }
1356 },
1357 },
1358 {
1359 .desc = "ov8858_8M_STILL",
1360 .width = 3280,
1361 .height = 2464,
1362 .used = 0,
1363 .regs = ov8858_8M,
1364 .bin_factor_x = 0,
1365 .bin_factor_y = 0,
1366 .skip_frames = 1,
1367 .fps_options = {
1368 {
1369 /* Pixel clock: 149.76MHZ */
1370 .fps = 10,
1371 .pixels_per_line = 3880,
1372 .lines_per_frame = 3859,
1373 },
1374 {
1375 }
1376 },
1377 },
1378};
1379
1380static struct ov8858_resolution ov8858_res_video[] = {
1381 {
1382 .desc = "ov8858_1640x926_VIDEO",
1383 .width = 1640,
1384 .height = 926,
1385 .used = 0,
1386 .regs = ov8858_1640x926,
1387 .bin_factor_x = 0,
1388 .bin_factor_y = 0,
1389 .skip_frames = 1,
1390 .fps_options = {
1391 {
1392 .fps = 30,
1393 .pixels_per_line = 3880,
1394 .lines_per_frame = 2573,
1395 },
1396 {
1397 }
1398 },
1399 },
1400 {
1401 .desc = "ov8858_1640x1232_VIDEO",
1402 .width = 1640,
1403 .height = 1232,
1404 .used = 0,
1405 .regs = ov8858_1640x1232,
1406 .bin_factor_x = 0,
1407 .bin_factor_y = 0,
1408 .skip_frames = 1,
1409 .fps_options = {
1410 {
1411 .fps = 30,
1412 .pixels_per_line = 3880,
1413 .lines_per_frame = 2573,
1414 },
1415 {
1416 }
1417 },
1418 },
1419 {
1420 .desc = "ov8858_1640x1096_VIDEO",
1421 .width = 1640,
1422 .height = 1096,
1423 .used = 0,
1424 .regs = ov8858_1640x1096,
1425 .bin_factor_x = 0,
1426 .bin_factor_y = 0,
1427 .skip_frames = 1,
1428 .fps_options = {
1429 {
1430 .fps = 30,
1431 .pixels_per_line = 3880,
1432 .lines_per_frame = 2573,
1433 },
1434 {
1435 }
1436 },
1437 },
1438 {
1439 .desc = "ov8858_6M_VIDEO",
1440 .width = 3280,
1441 .height = 1852,
1442 .used = 0,
1443 .regs = ov8858_6M,
1444 .bin_factor_x = 0,
1445 .bin_factor_y = 0,
1446 .skip_frames = 1,
1447 .fps_options = {
1448 {
1449 .fps = 30,
1450 .pixels_per_line = 3880,
1451 .lines_per_frame = 2573,
1452 },
1453 {
1454 }
1455 },
1456 },
1457 {
1458 .desc = "ov8858_8M_VIDEO",
1459 .width = 3280,
1460 .height = 2464,
1461 .used = 0,
1462 .regs = ov8858_8M,
1463 .bin_factor_x = 0,
1464 .bin_factor_y = 0,
1465 .skip_frames = 1,
1466 .fps_options = {
1467 {
1468 .fps = 30,
1469 .pixels_per_line = 3880,
1470 .lines_per_frame = 2573,
1471 },
1472 {
1473 }
1474 },
1475 },
1476};
1477
1478#endif /* __OV8858_H__ */
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