[mirror_ubuntu-focal-kernel.git] / drivers / staging / media / atomisp / include / asm / intel_mid_pcihelpers.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Access to message bus through three registers
 * in CUNIT(0:0:0) PCI configuration space.
 * MSGBUS_CTRL_REG(0xD0):
 *   31:24      = message bus opcode
 *   23:16      = message bus port
 *   15:8       = message bus address, low 8 bits.
 *   7:4        = message bus byte enables
 * MSGBUS_CTRL_EXT_REG(0xD8):
 *   31:8       = message bus address, high 24 bits.
 * MSGBUS_DATA_REG(0xD4):
 *   hold the data for write or read
 */
#define PCI_ROOT_MSGBUS_CTRL_REG        0xD0
#define PCI_ROOT_MSGBUS_DATA_REG        0xD4
#define PCI_ROOT_MSGBUS_CTRL_EXT_REG    0xD8
#define PCI_ROOT_MSGBUS_READ            0x10
#define PCI_ROOT_MSGBUS_WRITE           0x11
#define PCI_ROOT_MSGBUS_DWORD_ENABLE    0xf0

/* In BYT platform for all internal PCI devices d3 delay
 * of 3 ms is sufficient. Default value of 10 ms is overkill.
 */
#define INTERNAL_PCI_PM_D3_WAIT		3

#define ISP_SUB_CLASS			0x80
#define SUB_CLASS_MASK			0xFF00

u32 intel_mid_msgbus_read32_raw(u32 cmd);
u32 intel_mid_msgbus_read32(u8 port, u32 addr);
void intel_mid_msgbus_write32_raw(u32 cmd, u32 data);
void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data);
u32 intel_mid_msgbus_read32_raw_ext(u32 cmd, u32 cmd_ext);
void intel_mid_msgbus_write32_raw_ext(u32 cmd, u32 cmd_ext, u32 data);
u32 intel_mid_soc_stepping(void);
int intel_mid_dw_i2c_acquire_ownership(void);
int intel_mid_dw_i2c_release_ownership(void);
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
a49d2536 AC	2	/*
	3	* Access to message bus through three registers
	4	* in CUNIT(0:0:0) PCI configuration space.
	5	* MSGBUS_CTRL_REG(0xD0):
	6	* 31:24 = message bus opcode
	7	* 23:16 = message bus port
	8	* 15:8 = message bus address, low 8 bits.
	9	* 7:4 = message bus byte enables
	10	* MSGBUS_CTRL_EXT_REG(0xD8):
	11	* 31:8 = message bus address, high 24 bits.
	12	* MSGBUS_DATA_REG(0xD4):
	13	* hold the data for write or read
	14	*/
	15	#define PCI_ROOT_MSGBUS_CTRL_REG 0xD0
	16	#define PCI_ROOT_MSGBUS_DATA_REG 0xD4
	17	#define PCI_ROOT_MSGBUS_CTRL_EXT_REG 0xD8
	18	#define PCI_ROOT_MSGBUS_READ 0x10
	19	#define PCI_ROOT_MSGBUS_WRITE 0x11
	20	#define PCI_ROOT_MSGBUS_DWORD_ENABLE 0xf0
	21
	22	/* In BYT platform for all internal PCI devices d3 delay
	23	* of 3 ms is sufficient. Default value of 10 ms is overkill.
	24	*/
	25	#define INTERNAL_PCI_PM_D3_WAIT 3
	26
	27	#define ISP_SUB_CLASS 0x80
	28	#define SUB_CLASS_MASK 0xFF00
	29
	30	u32 intel_mid_msgbus_read32_raw(u32 cmd);
	31	u32 intel_mid_msgbus_read32(u8 port, u32 addr);
	32	void intel_mid_msgbus_write32_raw(u32 cmd, u32 data);
	33	void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data);
	34	u32 intel_mid_msgbus_read32_raw_ext(u32 cmd, u32 cmd_ext);
	35	void intel_mid_msgbus_write32_raw_ext(u32 cmd, u32 cmd_ext, u32 data);
	36	u32 intel_mid_soc_stepping(void);
	37	int intel_mid_dw_i2c_acquire_ownership(void);
	38	int intel_mid_dw_i2c_release_ownership(void);