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Commit | Line | Data |
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a49d2536 AC |
1 | /* |
2 | * Access to message bus through three registers | |
3 | * in CUNIT(0:0:0) PCI configuration space. | |
4 | * MSGBUS_CTRL_REG(0xD0): | |
5 | * 31:24 = message bus opcode | |
6 | * 23:16 = message bus port | |
7 | * 15:8 = message bus address, low 8 bits. | |
8 | * 7:4 = message bus byte enables | |
9 | * MSGBUS_CTRL_EXT_REG(0xD8): | |
10 | * 31:8 = message bus address, high 24 bits. | |
11 | * MSGBUS_DATA_REG(0xD4): | |
12 | * hold the data for write or read | |
13 | */ | |
14 | #define PCI_ROOT_MSGBUS_CTRL_REG 0xD0 | |
15 | #define PCI_ROOT_MSGBUS_DATA_REG 0xD4 | |
16 | #define PCI_ROOT_MSGBUS_CTRL_EXT_REG 0xD8 | |
17 | #define PCI_ROOT_MSGBUS_READ 0x10 | |
18 | #define PCI_ROOT_MSGBUS_WRITE 0x11 | |
19 | #define PCI_ROOT_MSGBUS_DWORD_ENABLE 0xf0 | |
20 | ||
a49d2536 AC |
21 | u32 intel_mid_msgbus_read32_raw(u32 cmd); |
22 | u32 intel_mid_msgbus_read32(u8 port, u32 addr); | |
23 | void intel_mid_msgbus_write32_raw(u32 cmd, u32 data); | |
24 | void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data); | |
25 | u32 intel_mid_msgbus_read32_raw_ext(u32 cmd, u32 cmd_ext); | |
26 | void intel_mid_msgbus_write32_raw_ext(u32 cmd, u32 cmd_ext, u32 data); |