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[mirror_ubuntu-bionic-kernel.git] / drivers / staging / media / atomisp / pci / atomisp2 / atomisp_v4l2.c
CommitLineData
a49d2536
AC		 1/*
2 * Support for Medifield PNW Camera Imaging ISP subsystem.
3 *
4 * Copyright (c) 2010 Intel Corporation. All Rights Reserved.
5 *
6 * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License version
10 * 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA.
21 *
22 */
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/pm_runtime.h>
26#include <linux/pm_qos.h>
27#include <linux/timer.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/intel_mid_pm.h>
31
32#include <linux/atomisp_gmin_platform.h>
33
34#include "atomisp_cmd.h"
35#include "atomisp_common.h"
36#include "atomisp_fops.h"
37#include "atomisp_file.h"
38#include "atomisp_ioctl.h"
39#include "atomisp_internal.h"
40#include "atomisp_acc.h"
41#include "atomisp-regs.h"
42#include "atomisp_dfs_tables.h"
43#include "atomisp_drvfs.h"
44#include "hmm/hmm.h"
45#include "atomisp_trace_event.h"
46
47#include "hrt/hive_isp_css_mm_hrt.h"
48
49#include "device_access.h"
50#include <linux/intel_mid_pm.h>
51#include <asm/intel-mid.h>
52
53/* G-Min addition: pull this in from intel_mid_pm.h */
54#define CSTATE_EXIT_LATENCY_C1 1
55
56/* Moorefield lacks PCI PM, BYT advertises it but it's broken, use PUNIT */
57#define ATOMISP_INTERNAL_PM (IS_MOFD || IS_BYT || IS_CHT)
58
59#ifdef ISP2401
60static uint skip_fwload = 0;
61module_param(skip_fwload, uint, 0644);
62MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load for COS");
63
64#endif
65/* set reserved memory pool size in page */
66unsigned int repool_pgnr;
67module_param(repool_pgnr, uint, 0644);
68MODULE_PARM_DESC(repool_pgnr,
69 "Set the reserved memory pool size in page (default:0)");
70
71/* set dynamic memory pool size in page */
72unsigned int dypool_pgnr = UINT_MAX;
73module_param(dypool_pgnr, uint, 0644);
74MODULE_PARM_DESC(dypool_pgnr,
75 "Set the dynamic memory pool size in page (default:0)");
76
77bool dypool_enable;
78module_param(dypool_enable, bool, 0644);
79MODULE_PARM_DESC(dypool_enable,
80 "dynamic memory pool enable/disable (default:disable)");
81
82/* memory optimization: deferred firmware loading */
83bool defer_fw_load;
84module_param(defer_fw_load, bool, 0644);
85MODULE_PARM_DESC(defer_fw_load,
86 "Defer FW loading until device is opened (default:disable)");
87
88/* cross componnet debug message flag */
89int dbg_level;
90module_param(dbg_level, int, 0644);
91MODULE_PARM_DESC(dbg_level, "debug message on/off (default:off)");
92
93/* log function switch */
94int dbg_func = 2;
95module_param(dbg_func, int, 0644);
96MODULE_PARM_DESC(dbg_func,
97 "log function switch non/trace_printk/printk (default:printk)");
98
99int mipicsi_flag;
100module_param(mipicsi_flag, int, 0644);
101MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm");
102
103/*set to 16x16 since this is the amount of lines and pixels the sensor
104exports extra. If these are kept at the 10x8 that they were on, in yuv
105downscaling modes incorrect resolutions where requested to the sensor
106driver with strange outcomes as a result. The proper way tot do this
107would be to have a list of tables the specify the sensor res, mipi rec,
108output res, and isp output res. however since we do not have this yet,
109the chosen solution is the next best thing. */
110int pad_w = 16;
111module_param(pad_w, int, 0644);
112MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
113
114int pad_h = 16;
115module_param(pad_h, int, 0644);
116MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
117
118struct device *atomisp_dev;
119
120void __iomem *atomisp_io_base;
121
122int atomisp_video_init(struct atomisp_video_pipe *video, const char *name)
123{
124 int ret;
125 const char *direction;
126
127 switch (video->type) {
128 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
129 direction = "output";
130 video->pad.flags = MEDIA_PAD_FL_SINK;
131 video->vdev.fops = &atomisp_fops;
132 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
133 break;
134 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
135 direction = "input";
136 video->pad.flags = MEDIA_PAD_FL_SOURCE;
137 video->vdev.fops = &atomisp_file_fops;
138 video->vdev.ioctl_ops = &atomisp_file_ioctl_ops;
139 break;
140 default:
141 return -EINVAL;
142 }
143
144 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
145 if (ret < 0)
146 return ret;
147
148 /* Initialize the video device. */
149 snprintf(video->vdev.name, sizeof(video->vdev.name),
150 "ATOMISP ISP %s %s", name, direction);
151 video->vdev.release = video_device_release_empty;
152 video_set_drvdata(&video->vdev, video->isp);
153
154 return 0;
155}
156
157void atomisp_acc_init(struct atomisp_acc_pipe *video, const char *name)
158{
159 video->vdev.fops = &atomisp_fops;
160 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
161
162 /* Initialize the video device. */
163 snprintf(video->vdev.name, sizeof(video->vdev.name),
164 "ATOMISP ISP %s", name);
165 video->vdev.release = video_device_release_empty;
166 video_set_drvdata(&video->vdev, video->isp);
167}
168
169int atomisp_video_register(struct atomisp_video_pipe *video,
170 struct v4l2_device *vdev)
171{
172 int ret;
173
174 video->vdev.v4l2_dev = vdev;
175
176 ret = video_register_device(&video->vdev, VFL_TYPE_GRABBER, -1);
177 if (ret < 0)
178 dev_err(vdev->dev, "%s: could not register video device (%d)\n",
179 __func__, ret);
180
181 return ret;
182}
183
184int atomisp_acc_register(struct atomisp_acc_pipe *video,
185 struct v4l2_device *vdev)
186{
187 int ret;
188
189 video->vdev.v4l2_dev = vdev;
190
191 ret = video_register_device(&video->vdev, VFL_TYPE_GRABBER, -1);
192 if (ret < 0)
193 dev_err(vdev->dev, "%s: could not register video device (%d)\n",
194 __func__, ret);
195
196 return ret;
197}
198
199void atomisp_video_unregister(struct atomisp_video_pipe *video)
200{
201 if (video_is_registered(&video->vdev)) {
202 media_entity_cleanup(&video->vdev.entity);
203 video_unregister_device(&video->vdev);
204 }
205}
206
207void atomisp_acc_unregister(struct atomisp_acc_pipe *video)
208{
209 if (video_is_registered(&video->vdev))
210 video_unregister_device(&video->vdev);
211}
212
213static int atomisp_save_iunit_reg(struct atomisp_device *isp)
214{
215 struct pci_dev *dev = isp->pdev;
216
217 dev_dbg(isp->dev, "%s\n", __func__);
218
219 pci_read_config_word(dev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
220 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
221 pci_read_config_dword(dev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
222 pci_read_config_dword(dev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
223 pci_read_config_word(dev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
224 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
225 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL,
226 &isp->saved_regs.interrupt_control);
227
228 pci_read_config_dword(dev, MRFLD_PCI_PMCS,
229 &isp->saved_regs.pmcs);
230 /* Ensure read/write combining is enabled. */
231 pci_read_config_dword(dev, PCI_I_CONTROL,
232 &isp->saved_regs.i_control);
233 isp->saved_regs.i_control |=
234 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
235 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
236 pci_read_config_dword(dev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
237 &isp->saved_regs.csi_access_viol);
238 pci_read_config_dword(dev, MRFLD_PCI_CSI_RCOMP_CONTROL,
239 &isp->saved_regs.csi_rcomp_config);
240 /*
241 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
242 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path
243 * and sensor sending "continuous clock".
244 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence
245 * is missed, and IUNIT can hang.
246 * For both issues, setting this bit is a workaround.
247 */
248 isp->saved_regs.csi_rcomp_config |=
249 MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
250 pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
251 &isp->saved_regs.csi_afe_dly);
252 pci_read_config_dword(dev, MRFLD_PCI_CSI_CONTROL,
253 &isp->saved_regs.csi_control);
254 if (isp->media_dev.hw_revision >=
255 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
256 isp->saved_regs.csi_control |=
257 MRFLD_PCI_CSI_CONTROL_PARPATHEN;
258 /*
259 * On CHT CSI_READY bit should be enabled before stream on
260 */
261 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
262 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
263 isp->saved_regs.csi_control |=
264 MRFLD_PCI_CSI_CONTROL_CSI_READY;
265 pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
266 &isp->saved_regs.csi_afe_rcomp_config);
267 pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
268 &isp->saved_regs.csi_afe_hs_control);
269 pci_read_config_dword(dev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
270 &isp->saved_regs.csi_deadline_control);
271 return 0;
272}
273
274static int atomisp_restore_iunit_reg(struct atomisp_device *isp)
275{
276 struct pci_dev *dev = isp->pdev;
277
278 dev_dbg(isp->dev, "%s\n", __func__);
279
280 pci_write_config_word(dev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
281 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
282 isp->saved_regs.ispmmadr);
283 pci_write_config_dword(dev, PCI_MSI_CAPID, isp->saved_regs.msicap);
284 pci_write_config_dword(dev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
285 pci_write_config_word(dev, PCI_MSI_DATA, isp->saved_regs.msi_data);
286 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
287 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL,
288 isp->saved_regs.interrupt_control);
289 pci_write_config_dword(dev, PCI_I_CONTROL,
290 isp->saved_regs.i_control);
291
292 pci_write_config_dword(dev, MRFLD_PCI_PMCS,
293 isp->saved_regs.pmcs);
294 pci_write_config_dword(dev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
295 isp->saved_regs.csi_access_viol);
296 pci_write_config_dword(dev, MRFLD_PCI_CSI_RCOMP_CONTROL,
297 isp->saved_regs.csi_rcomp_config);
298 pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
299 isp->saved_regs.csi_afe_dly);
300 pci_write_config_dword(dev, MRFLD_PCI_CSI_CONTROL,
301 isp->saved_regs.csi_control);
302 pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
303 isp->saved_regs.csi_afe_rcomp_config);
304 pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
305 isp->saved_regs.csi_afe_hs_control);
306 pci_write_config_dword(dev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
307 isp->saved_regs.csi_deadline_control);
308
309 /*
310 * for MRFLD, Software/firmware needs to write a 1 to bit0
311 * of the register at CSI_RECEIVER_SELECTION_REG to enable
312 * SH CSI backend write 0 will enable Arasan CSI backend,
313 * which has bugs(like sighting:4567697 and 4567699) and
314 * will be removed in B0
315 */
316 atomisp_store_uint32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
317 return 0;
318}
319
320#ifdef CONFIG_PM
321static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
322{
323 struct pci_dev *dev = isp->pdev;
324 u32 irq;
325 unsigned long flags;
326
327 spin_lock_irqsave(&isp->lock, flags);
328 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) {
329 spin_unlock_irqrestore(&isp->lock, flags);
330 dev_dbg(isp->dev, "<%s %d.\n", __func__, __LINE__);
331 return 0;
332 }
333 /*
334 * MRFLD HAS requirement: cannot power off i-unit if
335 * ISP has IRQ not serviced.
336 * So, here we need to check if there is any pending
337 * IRQ, if so, waiting for it to be served
338 */
339 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
340 irq = irq & 1 << INTR_IIR;
341 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
342
343 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
344 if (!(irq & (1 << INTR_IIR)))
345 goto done;
346
347 atomisp_store_uint32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
348 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
349 if (irq != 0) {
350 dev_err(isp->dev,
351 "%s: fail to clear isp interrupt status reg=0x%x\n",
352 __func__, irq);
353 spin_unlock_irqrestore(&isp->lock, flags);
354 return -EAGAIN;
355 } else {
356 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
357 irq = irq & 1 << INTR_IIR;
358 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
359
360 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
361 if (!(irq & (1 << INTR_IIR))) {
362 atomisp_store_uint32(MRFLD_INTR_ENABLE_REG, 0x0);
363 goto done;
364 }
365 dev_err(isp->dev,
366 "%s: error in iunit interrupt. status reg=0x%x\n",
367 __func__, irq);
368 spin_unlock_irqrestore(&isp->lock, flags);
369 return -EAGAIN;
370 }
371done:
372 /*
373 * MRFLD WORKAROUND:
374 * before powering off IUNIT, clear the pending interrupts
375 * and disable the interrupt. driver should avoid writing 0
376 * to IIR. It could block subsequent interrupt messages.
377 * HW sighting:4568410.
378 */
379 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
380 irq &= ~(1 << INTR_IER);
381 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
382
383 atomisp_msi_irq_uninit(isp, dev);
384 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
385 spin_unlock_irqrestore(&isp->lock, flags);
386
387 return 0;
388}
389
390
391 /*
392 * WA for DDR DVFS enable/disable
393 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS
394 */
395void punit_ddr_dvfs_enable(bool enable)
396{
397 int reg = intel_mid_msgbus_read32(PUNIT_PORT, MRFLD_ISPSSDVFS);
398 int door_bell = 1 << 8;
399 int max_wait = 30;
400
401 if (enable) {
402 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
403 } else {
404 reg |= (MRFLD_BIT1 | door_bell);
405 reg &= ~(MRFLD_BIT0);
406 }
407
408 intel_mid_msgbus_write32(PUNIT_PORT, MRFLD_ISPSSDVFS, reg);
409
410 /*Check Req_ACK to see freq status, wait until door_bell is cleared*/
411 if (reg & door_bell) {
412 while (max_wait--) {
413 if (0 == (intel_mid_msgbus_read32(PUNIT_PORT,
414 MRFLD_ISPSSDVFS) & door_bell))
415 break;
416
417 usleep_range(100, 500);
418 }
419 }
420
421 if (max_wait == 0)
422 pr_info("DDR DVFS, door bell is not cleared within 3ms\n");
423}
424
425/* Workaround for pmu_nc_set_power_state not ready in MRFLD */
426int atomisp_mrfld_power_down(struct atomisp_device *isp)
427{
428 unsigned long timeout;
429 u32 reg_value;
430
431 /* writing 0x3 to ISPSSPM0 bit[1:0] to power off the IUNIT */
432 reg_value = intel_mid_msgbus_read32(PUNIT_PORT, MRFLD_ISPSSPM0);
433 reg_value &= ~MRFLD_ISPSSPM0_ISPSSC_MASK;
434 reg_value |= MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
435 intel_mid_msgbus_write32(PUNIT_PORT, MRFLD_ISPSSPM0, reg_value);
436
437 /*WA:Enable DVFS*/
438 if (IS_CHT)
439 punit_ddr_dvfs_enable(true);
440
441 /*
442 * There should be no iunit access while power-down is
443 * in progress HW sighting: 4567865
444 * FIXME: msecs_to_jiffies(50)- experienced value
445 */
446 timeout = jiffies + msecs_to_jiffies(50);
447 while (1) {
448 reg_value = intel_mid_msgbus_read32(PUNIT_PORT,
449 MRFLD_ISPSSPM0);
450 dev_dbg(isp->dev, "power-off in progress, ISPSSPM0: 0x%x\n",
451 reg_value);
452 /* wait until ISPSSPM0 bit[25:24] shows 0x3 */
453 if ((reg_value >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) ==
454 MRFLD_ISPSSPM0_IUNIT_POWER_OFF) {
455 trace_ipu_cstate(0);
456 return 0;
457 }
458
459 if (time_after(jiffies, timeout)) {
460 dev_err(isp->dev, "power-off iunit timeout.\n");
461 return -EBUSY;
462 }
463 /* FIXME: experienced value for delay */
464 usleep_range(100, 150);
d89f191e 465 }
a49d2536
AC		 466}
467
468
469/* Workaround for pmu_nc_set_power_state not ready in MRFLD */
470int atomisp_mrfld_power_up(struct atomisp_device *isp)
471{
472 unsigned long timeout;
473 u32 reg_value;
474
475 /*WA for PUNIT, if DVFS enabled, ISP timeout observed*/
476 if (IS_CHT)
477 punit_ddr_dvfs_enable(false);
478
479 /*
480 * FIXME:WA for ECS28A, with this sleep, CTS
481 * android.hardware.camera2.cts.CameraDeviceTest#testCameraDeviceAbort
482 * PASS, no impact on other platforms
483 */
484 if (IS_BYT)
485 msleep(10);
486
487 /* writing 0x0 to ISPSSPM0 bit[1:0] to power off the IUNIT */
488 reg_value = intel_mid_msgbus_read32(PUNIT_PORT, MRFLD_ISPSSPM0);
489 reg_value &= ~MRFLD_ISPSSPM0_ISPSSC_MASK;
490 intel_mid_msgbus_write32(PUNIT_PORT, MRFLD_ISPSSPM0, reg_value);
491
492 /* FIXME: experienced value for delay */
493 timeout = jiffies + msecs_to_jiffies(50);
494 while (1) {
495 reg_value = intel_mid_msgbus_read32(PUNIT_PORT, MRFLD_ISPSSPM0);
496 dev_dbg(isp->dev, "power-on in progress, ISPSSPM0: 0x%x\n",
497 reg_value);
498 /* wait until ISPSSPM0 bit[25:24] shows 0x0 */
499 if ((reg_value >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) ==
500 MRFLD_ISPSSPM0_IUNIT_POWER_ON) {
501 trace_ipu_cstate(1);
502 return 0;
503 }
504
505 if (time_after(jiffies, timeout)) {
506 dev_err(isp->dev, "power-on iunit timeout.\n");
507 return -EBUSY;
508 }
509 /* FIXME: experienced value for delay */
510 usleep_range(100, 150);
d89f191e 511 }
a49d2536
AC		 512}
513
514int atomisp_runtime_suspend(struct device *dev)
515{
516 struct atomisp_device *isp = (struct atomisp_device *)
517 dev_get_drvdata(dev);
518 int ret;
519
520 ret = atomisp_mrfld_pre_power_down(isp);
521 if (ret)
522 return ret;
523
524 /*Turn off the ISP d-phy*/
525 ret = atomisp_ospm_dphy_down(isp);
526 if (ret)
527 return ret;
528 pm_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
529 if (ATOMISP_INTERNAL_PM)
530 ret = atomisp_mrfld_power_down(isp);
531
532 return ret;
533}
534
535int atomisp_runtime_resume(struct device *dev)
536{
537 struct atomisp_device *isp = (struct atomisp_device *)
538 dev_get_drvdata(dev);
539 int ret;
540
541 if (ATOMISP_INTERNAL_PM) {
542 ret = atomisp_mrfld_power_up(isp);
543 if (ret)
544 return ret;
545 }
546
547 pm_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
548 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) {
549 /*Turn on ISP d-phy */
550 ret = atomisp_ospm_dphy_up(isp);
551 if (ret) {
552 dev_err(isp->dev, "Failed to power up ISP!.\n");
553 return -EINVAL;
554 }
555 }
556
557 /*restore register values for iUnit and iUnitPHY registers*/
558 if (isp->saved_regs.pcicmdsts)
559 atomisp_restore_iunit_reg(isp);
560
561 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
562 return 0;
563}
564
565static int atomisp_suspend(struct device *dev)
566{
567 struct atomisp_device *isp = (struct atomisp_device *)
568 dev_get_drvdata(dev);
569 /* FIXME: only has one isp_subdev at present */
570 struct atomisp_sub_device *asd = &isp->asd[0];
571 unsigned long flags;
572 int ret;
573
574 /*
575 * FIXME: Suspend is not supported by sensors. Abort if any video
576 * node was opened.
577 */
578 if (atomisp_dev_users(isp))
579 return -EBUSY;
580
581 spin_lock_irqsave(&isp->lock, flags);
582 if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) {
583 spin_unlock_irqrestore(&isp->lock, flags);
584 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
585 return -EINVAL;
586 }
587 spin_unlock_irqrestore(&isp->lock, flags);
588
589 ret = atomisp_mrfld_pre_power_down(isp);
590 if (ret)
591 return ret;
592
593 /*Turn off the ISP d-phy */
594 ret = atomisp_ospm_dphy_down(isp);
595 if (ret) {
596 dev_err(isp->dev, "fail to power off ISP\n");
597 return ret;
598 }
599 pm_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
600 if (ATOMISP_INTERNAL_PM)
601 ret = atomisp_mrfld_power_down(isp);
602
603 return ret;
604}
605
606static int atomisp_resume(struct device *dev)
607{
608 struct atomisp_device *isp = (struct atomisp_device *)
609 dev_get_drvdata(dev);
610 int ret;
611
612 if (ATOMISP_INTERNAL_PM) {
613 ret = atomisp_mrfld_power_up(isp);
614 if (ret)
615 return ret;
616 }
617
618 pm_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
619
620 /*Turn on ISP d-phy */
621 ret = atomisp_ospm_dphy_up(isp);
622 if (ret) {
623 dev_err(isp->dev, "Failed to power up ISP!.\n");
624 return -EINVAL;
625 }
626
627 /*restore register values for iUnit and iUnitPHY registers*/
628 if (isp->saved_regs.pcicmdsts)
629 atomisp_restore_iunit_reg(isp);
630
631 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
632 return 0;
633}
634#endif
635
636int atomisp_csi_lane_config(struct atomisp_device *isp)
637{
638 static const struct {
639 u8 code;
640 u8 lanes[MRFLD_PORT_NUM];
641 } portconfigs[] = {
642 /* Tangier/Merrifield available lane configurations */
643 { 0x00, { 4, 1, 0 } }, /* 00000 */
644 { 0x01, { 3, 1, 0 } }, /* 00001 */
645 { 0x02, { 2, 1, 0 } }, /* 00010 */
646 { 0x03, { 1, 1, 0 } }, /* 00011 */
647 { 0x04, { 2, 1, 2 } }, /* 00100 */
648 { 0x08, { 3, 1, 1 } }, /* 01000 */
649 { 0x09, { 2, 1, 1 } }, /* 01001 */
650 { 0x0a, { 1, 1, 1 } }, /* 01010 */
651
652 /* Anniedale/Moorefield only configurations */
653 { 0x10, { 4, 2, 0 } }, /* 10000 */
654 { 0x11, { 3, 2, 0 } }, /* 10001 */
655 { 0x12, { 2, 2, 0 } }, /* 10010 */
656 { 0x13, { 1, 2, 0 } }, /* 10011 */
657 { 0x14, { 2, 2, 2 } }, /* 10100 */
658 { 0x18, { 3, 2, 1 } }, /* 11000 */
659 { 0x19, { 2, 2, 1 } }, /* 11001 */
660 { 0x1a, { 1, 2, 1 } }, /* 11010 */
661 };
662
663 unsigned int i, j;
664 u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 };
665 u32 csi_control;
666 int nportconfigs;
667 u32 port_config_mask;
668 int port3_lanes_shift;
669
670 if (isp->media_dev.hw_revision <
671 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
672 ATOMISP_HW_REVISION_SHIFT) {
673 /* Merrifield */
674 port_config_mask = MRFLD_PORT_CONFIG_MASK;
675 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
676 } else {
677 /* Moorefield / Cherryview */
678 port_config_mask = CHV_PORT_CONFIG_MASK;
679 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
680 }
681
682 if (isp->media_dev.hw_revision <
683 ATOMISP_HW_REVISION_ISP2401 <<
684 ATOMISP_HW_REVISION_SHIFT) {
685 /* Merrifield / Moorefield legacy input system */
686 nportconfigs = MRFLD_PORT_CONFIG_NUM;
687 } else {
688 /* Moorefield / Cherryview new input system */
689 nportconfigs = ARRAY_SIZE(portconfigs);
690 }
691
692 for (i = 0; i < isp->input_cnt; i++) {
693 struct camera_mipi_info *mipi_info;
694
695 if (isp->inputs[i].type != RAW_CAMERA &&
696 isp->inputs[i].type != SOC_CAMERA)
697 continue;
698
699 mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera);
700 if (!mipi_info)
701 continue;
702
703 switch (mipi_info->port) {
704 case ATOMISP_CAMERA_PORT_PRIMARY:
705 sensor_lanes[0] = mipi_info->num_lanes;
706 break;
707 case ATOMISP_CAMERA_PORT_SECONDARY:
708 sensor_lanes[1] = mipi_info->num_lanes;
709 break;
710 case ATOMISP_CAMERA_PORT_TERTIARY:
711 sensor_lanes[2] = mipi_info->num_lanes;
712 break;
713 default:
714 dev_err(isp->dev,
715 "%s: invalid port: %d for the %dth sensor\n",
716 __func__, mipi_info->port, i);
717 return -EINVAL;
718 }
719 }
720
721 for (i = 0; i < nportconfigs; i++) {
722 for (j = 0; j < MRFLD_PORT_NUM; j++)
723 if (sensor_lanes[j] &&
724 sensor_lanes[j] != portconfigs[i].lanes[j])
725 break;
726
727 if (j == MRFLD_PORT_NUM)
728 break; /* Found matching setting */
729 }
730
731 if (i >= nportconfigs) {
732 dev_err(isp->dev,
733 "%s: could not find the CSI port setting for %d-%d-%d\n",
734 __func__,
735 sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]);
736 return -EINVAL;
737 }
738
739 pci_read_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
740 csi_control &= ~port_config_mask;
741 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
742 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
743 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
744 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
745 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
746 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
747 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
748
749 pci_write_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
750
751 dev_dbg(isp->dev,
752 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
753 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
754 portconfigs[i].lanes[2], csi_control);
755
756 return 0;
757}
758
759static int atomisp_subdev_probe(struct atomisp_device *isp)
760{
761 const struct atomisp_platform_data *pdata;
762 struct intel_v4l2_subdev_table *subdevs;
763 int ret, raw_index = -1;
764
765 pdata = atomisp_get_platform_data();
766 if (pdata == NULL) {
767 dev_err(isp->dev, "no platform data available\n");
768 return 0;
769 }
770
771 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) {
772 struct v4l2_subdev *subdev;
773 struct i2c_board_info *board_info =
774 &subdevs->v4l2_subdev.board_info;
775 struct i2c_adapter *adapter =
776 i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id);
777 struct camera_sensor_platform_data *sensor_pdata;
778 int sensor_num, i;
779
780 if (adapter == NULL) {
781 dev_err(isp->dev,
782 "Failed to find i2c adapter for subdev %s\n",
783 board_info->type);
784 break;
785 }
786
787 /* In G-Min, the sensor devices will already be probed
788 * (via ACPI) and registered, do not create new
789 * ones */
790 subdev = atomisp_gmin_find_subdev(adapter, board_info);
791 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdev);
792 if (ret) {
793 dev_warn(isp->dev, "Subdev %s detection fail\n",
794 board_info->type);
795 continue;
796 }
797
798 if (subdev == NULL) {
799 dev_warn(isp->dev, "Subdev %s detection fail\n",
800 board_info->type);
801 continue;
802 }
803
804 dev_info(isp->dev, "Subdev %s successfully register\n",
805 board_info->type);
806
807 switch (subdevs->type) {
808 case RAW_CAMERA:
809 raw_index = isp->input_cnt;
810 dev_dbg(isp->dev, "raw_index: %d\n", raw_index);
811 case SOC_CAMERA:
812 dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt);
813 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) {
814 dev_warn(isp->dev,
815 "too many atomisp inputs, ignored\n");
816 break;
817 }
818
819 isp->inputs[isp->input_cnt].type = subdevs->type;
820 isp->inputs[isp->input_cnt].port = subdevs->port;
821 isp->inputs[isp->input_cnt].camera = subdev;
822 isp->inputs[isp->input_cnt].sensor_index = 0;
823 /*
824 * initialize the subdev frame size, then next we can
825 * judge whether frame_size store effective value via
826 * pixel_format.
827 */
828 isp->inputs[isp->input_cnt].frame_size.pixel_format = 0;
829 sensor_pdata = (struct camera_sensor_platform_data *)
830 board_info->platform_data;
831 if (sensor_pdata->get_camera_caps)
832 isp->inputs[isp->input_cnt].camera_caps =
833 sensor_pdata->get_camera_caps();
834 else
835 isp->inputs[isp->input_cnt].camera_caps =
836 atomisp_get_default_camera_caps();
837 sensor_num = isp->inputs[isp->input_cnt]
838 .camera_caps->sensor_num;
839 isp->input_cnt++;
840 for (i = 1; i < sensor_num; i++) {
841 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) {
842 dev_warn(isp->dev,
843 "atomisp inputs out of range\n");
844 break;
845 }
846 isp->inputs[isp->input_cnt] =
847 isp->inputs[isp->input_cnt - 1];
848 isp->inputs[isp->input_cnt].sensor_index = i;
849 isp->input_cnt++;
850 }
851 break;
852 case CAMERA_MOTOR:
853 isp->motor = subdev;
854 break;
855 case LED_FLASH:
856 case XENON_FLASH:
857 isp->flash = subdev;
858 break;
859 default:
860 dev_dbg(isp->dev, "unknown subdev probed\n");
861 break;
862 }
863
864 }
865
866 /*
867 * HACK: Currently VCM belongs to primary sensor only, but correct
868 * approach must be to acquire from platform code which sensor
869 * owns it.
870 */
871 if (isp->motor && raw_index >= 0)
872 isp->inputs[raw_index].motor = isp->motor;
873
874 /* Proceed even if no modules detected. For COS mode and no modules. */
875 if (!isp->inputs[0].camera)
876 dev_warn(isp->dev, "no camera attached or fail to detect\n");
877
878 return atomisp_csi_lane_config(isp);
879}
880
881static void atomisp_unregister_entities(struct atomisp_device *isp)
882{
883 unsigned int i;
884 struct v4l2_subdev *sd, *next;
885
886 for (i = 0; i < isp->num_of_streams; i++)
887 atomisp_subdev_unregister_entities(&isp->asd[i]);
888 atomisp_tpg_unregister_entities(&isp->tpg);
889 atomisp_file_input_unregister_entities(&isp->file_dev);
890 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
891 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
892
893 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
894 v4l2_device_unregister_subdev(sd);
895
896 v4l2_device_unregister(&isp->v4l2_dev);
897 media_device_unregister(&isp->media_dev);
898}
899
900static int atomisp_register_entities(struct atomisp_device *isp)
901{
902 int ret = 0;
903 unsigned int i;
904
905 isp->media_dev.dev = isp->dev;
906
907 strlcpy(isp->media_dev.model, "Intel Atom ISP",
908 sizeof(isp->media_dev.model));
a49d2536 909
a49d2536
AC		 910 media_device_init(&isp->media_dev);
911 isp->v4l2_dev.mdev = &isp->media_dev;
912 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
913 if (ret < 0) {
914 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
915 __func__, ret);
916 goto v4l2_device_failed;
917 }
918
919 ret = atomisp_subdev_probe(isp);
920 if (ret < 0)
921 goto csi_and_subdev_probe_failed;
922
923 /* Register internal entities */
924 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
925 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
926 &isp->v4l2_dev);
927 if (ret == 0)
928 continue;
929
930 /* error case */
931 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
932 /* deregister all registered CSI ports */
933 while (i--)
934 atomisp_mipi_csi2_unregister_entities(
935 &isp->csi2_port[i]);
936
937 goto csi_and_subdev_probe_failed;
938 }
939
940 ret =
941 atomisp_file_input_register_entities(&isp->file_dev, &isp->v4l2_dev);
942 if (ret < 0) {
943 dev_err(isp->dev, "atomisp_file_input_register_entities\n");
944 goto file_input_register_failed;
945 }
946
947 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev);
948 if (ret < 0) {
949 dev_err(isp->dev, "atomisp_tpg_register_entities\n");
950 goto tpg_register_failed;
951 }
952
953 for (i = 0; i < isp->num_of_streams; i++) {
954 struct atomisp_sub_device *asd = &isp->asd[i];
955
956 ret = atomisp_subdev_register_entities(asd, &isp->v4l2_dev);
957 if (ret < 0) {
958 dev_err(isp->dev,
959 "atomisp_subdev_register_entities fail\n");
960 for (; i > 0; i--)
961 atomisp_subdev_unregister_entities(
962 &isp->asd[i - 1]);
963 goto subdev_register_failed;
964 }
965 }
966
967 for (i = 0; i < isp->num_of_streams; i++) {
968 struct atomisp_sub_device *asd = &isp->asd[i];
969
970 init_completion(&asd->init_done);
971
972 asd->delayed_init_workq =
973 alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE,
974 1);
975 if (asd->delayed_init_workq == NULL) {
976 dev_err(isp->dev,
977 "Failed to initialize delayed init workq\n");
978 ret = -ENOMEM;
979
980 for (; i > 0; i--)
981 destroy_workqueue(isp->asd[i - 1].
982 delayed_init_workq);
983 goto wq_alloc_failed;
984 }
985 INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work);
986 }
987
988 for (i = 0; i < isp->input_cnt; i++) {
989 if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) {
990 dev_err(isp->dev, "isp->inputs port %d not supported\n",
991 isp->inputs[i].port);
992 ret = -EINVAL;
993 goto link_failed;
994 }
995 }
996
997 dev_dbg(isp->dev,
998 "FILE_INPUT enable, camera_cnt: %d\n", isp->input_cnt);
999 isp->inputs[isp->input_cnt].type = FILE_INPUT;
1000 isp->inputs[isp->input_cnt].port = -1;
1001 isp->inputs[isp->input_cnt].camera_caps =
1002 atomisp_get_default_camera_caps();
1003 isp->inputs[isp->input_cnt++].camera = &isp->file_dev.sd;
1004
1005 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) {
1006 dev_dbg(isp->dev,
1007 "TPG detected, camera_cnt: %d\n", isp->input_cnt);
1008 isp->inputs[isp->input_cnt].type = TEST_PATTERN;
1009 isp->inputs[isp->input_cnt].port = -1;
1010 isp->inputs[isp->input_cnt].camera_caps =
1011 atomisp_get_default_camera_caps();
1012 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd;
1013 } else {
1014 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n");
1015 }
1016
1017 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1018 if (ret < 0)
1019 goto link_failed;
1020
1021 return media_device_register(&isp->media_dev);
1022
1023link_failed:
1024 for (i = 0; i < isp->num_of_streams; i++)
1025 destroy_workqueue(isp->asd[i].
1026 delayed_init_workq);
1027wq_alloc_failed:
1028 for (i = 0; i < isp->num_of_streams; i++)
1029 atomisp_subdev_unregister_entities(
1030 &isp->asd[i]);
1031subdev_register_failed:
1032 atomisp_tpg_unregister_entities(&isp->tpg);
1033tpg_register_failed:
1034 atomisp_file_input_unregister_entities(&isp->file_dev);
1035file_input_register_failed:
1036 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
1037 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
1038csi_and_subdev_probe_failed:
1039 v4l2_device_unregister(&isp->v4l2_dev);
1040v4l2_device_failed:
1041 media_device_unregister(&isp->media_dev);
1042 media_device_cleanup(&isp->media_dev);
1043 return ret;
1044}
1045
1046static int atomisp_initialize_modules(struct atomisp_device *isp)
1047{
1048 int ret;
1049
1050 ret = atomisp_mipi_csi2_init(isp);
1051 if (ret < 0) {
1052 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1053 goto error_mipi_csi2;
1054 }
1055
1056 ret = atomisp_file_input_init(isp);
1057 if (ret < 0) {
1058 dev_err(isp->dev,
1059 "file input device initialization failed\n");
1060 goto error_file_input;
1061 }
1062
1063 ret = atomisp_tpg_init(isp);
1064 if (ret < 0) {
1065 dev_err(isp->dev, "tpg initialization failed\n");
1066 goto error_tpg;
1067 }
1068
1069 ret = atomisp_subdev_init(isp);
1070 if (ret < 0) {
1071 dev_err(isp->dev, "ISP subdev initialization failed\n");
1072 goto error_isp_subdev;
1073 }
1074
1075
1076 return 0;
1077
1078error_isp_subdev:
1079error_tpg:
1080 atomisp_tpg_cleanup(isp);
1081error_file_input:
1082 atomisp_file_input_cleanup(isp);
1083error_mipi_csi2:
1084 atomisp_mipi_csi2_cleanup(isp);
1085 return ret;
1086}
1087
1088static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1089{
1090 atomisp_tpg_cleanup(isp);
1091 atomisp_file_input_cleanup(isp);
1092 atomisp_mipi_csi2_cleanup(isp);
1093}
1094
1095const struct firmware *
1096atomisp_load_firmware(struct atomisp_device *isp)
1097{
1098 const struct firmware *fw;
1099 int rc;
1100 char *fw_path = NULL;
1101
1102#ifdef ISP2401
1103 if (skip_fwload)
1104 return NULL;
1105
1106#endif
1107#if defined(ATOMISP_FWNAME)
1108 fw_path = ATOMISP_FWNAME;
1109#else
1110 if (isp->media_dev.driver_version == ATOMISP_CSS_VERSION_21) {
1111 if (isp->media_dev.hw_revision ==
1112 ((ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT)
1113 | ATOMISP_HW_STEPPING_A0))
1114 fw_path = "shisp_2401a0_v21.bin";
1115
1116 if (isp->media_dev.hw_revision ==
1117 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT)
1118 | ATOMISP_HW_STEPPING_A0))
1119 fw_path = "shisp_2401a0_legacy_v21.bin";
1120
1121 if (isp->media_dev.hw_revision ==
1122 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT)
1123 | ATOMISP_HW_STEPPING_B0))
1124 fw_path = "shisp_2400b0_v21.bin";
1125 }
1126#endif
1127
1128 if (!fw_path) {
1129 dev_err(isp->dev,
1130 "Unsupported driver_version 0x%x, hw_revision 0x%x\n",
1131 isp->media_dev.driver_version,
1132 isp->media_dev.hw_revision);
1133 return NULL;
1134 }
1135
1136 rc = request_firmware(&fw, fw_path, isp->dev);
1137 if (rc) {
1138 dev_err(isp->dev,
1139 "atomisp: Error %d while requesting firmware %s\n",
1140 rc, fw_path);
1141 return NULL;
1142 }
1143
1144 return fw;
1145}
1146
1147/*
1148 * Check for flags the driver was compiled with against the PCI
1149 * device. Always returns true on other than ISP 2400.
1150 */
1151static bool is_valid_device(struct pci_dev *dev,
1152 const struct pci_device_id *id)
1153{
1154 unsigned int a0_max_id;
1155
1156 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1157 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1158 a0_max_id = ATOMISP_PCI_REV_MRFLD_A0_MAX;
1159 break;
1160 case ATOMISP_PCI_DEVICE_SOC_BYT:
1161 a0_max_id = ATOMISP_PCI_REV_BYT_A0_MAX;
1162 break;
1163 default:
1164 return true;
1165 }
1166
1167 return dev->revision > a0_max_id;
1168}
1169
1170static int init_atomisp_wdts(struct atomisp_device *isp)
1171{
1172 int i, err;
1173
1174 atomic_set(&isp->wdt_work_queued, 0);
1175 isp->wdt_work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1);
1176 if (isp->wdt_work_queue == NULL) {
1177 dev_err(isp->dev, "Failed to initialize wdt work queue\n");
1178 err = -ENOMEM;
1179 goto alloc_fail;
1180 }
1181 INIT_WORK(&isp->wdt_work, atomisp_wdt_work);
1182
1183 for (i = 0; i < isp->num_of_streams; i++) {
1184 struct atomisp_sub_device *asd = &isp->asd[i];
1185 asd = &isp->asd[i];
1186#ifndef ISP2401
1187 setup_timer(&asd->wdt, atomisp_wdt, (unsigned long)isp);
1188#else
1189 setup_timer(&asd->video_out_capture.wdt,
1190 atomisp_wdt, (unsigned long)&asd->video_out_capture);
1191 setup_timer(&asd->video_out_preview.wdt,
1192 atomisp_wdt, (unsigned long)&asd->video_out_preview);
1193 setup_timer(&asd->video_out_vf.wdt,
1194 atomisp_wdt, (unsigned long)&asd->video_out_vf);
1195 setup_timer(&asd->video_out_video_capture.wdt,
1196 atomisp_wdt,
1197 (unsigned long)&asd->video_out_video_capture);
1198#endif
1199 }
1200 return 0;
1201alloc_fail:
1202 return err;
1203}
1204
1205static struct pci_driver atomisp_pci_driver;
1206
1207#define ATOM_ISP_PCI_BAR 0
1208
1209static int atomisp_pci_probe(struct pci_dev *dev,
1210 const struct pci_device_id *id)
1211{
1212 const struct atomisp_platform_data *pdata;
1213 struct atomisp_device *isp;
1214 unsigned int start;
1215 void __iomem *base;
1216 int err, val;
1217 u32 irq;
1218
1219 if (!dev) {
1220 dev_err(&dev->dev, "atomisp: error device ptr\n");
1221 return -EINVAL;
1222 }
1223
1224 if (!is_valid_device(dev, id))
1225 return -ENODEV;
1226 /* Pointer to struct device. */
1227 atomisp_dev = &dev->dev;
1228
1229 pdata = atomisp_get_platform_data();
1230 if (pdata == NULL)
1231 dev_warn(&dev->dev, "no platform data available\n");
1232
1233 err = pcim_enable_device(dev);
1234 if (err) {
1235 dev_err(&dev->dev, "Failed to enable CI ISP device (%d)\n",
1236 err);
1237 return err;
1238 }
1239
1240 start = pci_resource_start(dev, ATOM_ISP_PCI_BAR);
1241 dev_dbg(&dev->dev, "start: 0x%x\n", start);
1242
1243 err = pcim_iomap_regions(dev, 1 << ATOM_ISP_PCI_BAR, pci_name(dev));
1244 if (err) {
1245 dev_err(&dev->dev, "Failed to I/O memory remapping (%d)\n",
1246 err);
1247 return err;
1248 }
1249
1250 base = pcim_iomap_table(dev)[ATOM_ISP_PCI_BAR];
1251 dev_dbg(&dev->dev, "base: %p\n", base);
1252
1253 atomisp_io_base = base;
1254
1255 dev_dbg(&dev->dev, "atomisp_io_base: %p\n", atomisp_io_base);
1256
1257 isp = devm_kzalloc(&dev->dev, sizeof(struct atomisp_device), GFP_KERNEL);
1258 if (!isp) {
1259 dev_err(&dev->dev, "Failed to alloc CI ISP structure\n");
1260 return -ENOMEM;
1261 }
1262 isp->pdev = dev;
1263 isp->dev = &dev->dev;
1264 isp->sw_contex.power_state = ATOM_ISP_POWER_UP;
1265 isp->pci_root = pci_get_bus_and_slot(0, 0);
1266 if (!isp->pci_root) {
1267 dev_err(&dev->dev, "Unable to find PCI host\n");
1268 return -ENODEV;
1269 }
1270 isp->saved_regs.ispmmadr = start;
1271
1272 rt_mutex_init(&isp->mutex);
1273 mutex_init(&isp->streamoff_mutex);
1274 spin_lock_init(&isp->lock);
1275
1276 /* This is not a true PCI device on SoC, so the delay is not needed. */
1277 isp->pdev->d3_delay = 0;
1278
1279 isp->media_dev.driver_version = ATOMISP_CSS_VERSION_21;
1280 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1281 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1282 isp->media_dev.hw_revision =
1283 (ATOMISP_HW_REVISION_ISP2400
1284 << ATOMISP_HW_REVISION_SHIFT) |
1285 ATOMISP_HW_STEPPING_B0;
1286
1287 switch (id->device) {
1288 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1289 isp->dfs = &dfs_config_merr_1179;
1290 break;
1291 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1292 isp->dfs = &dfs_config_merr_117a;
1293 break;
1294 default:
1295 isp->dfs = &dfs_config_merr;
1296 break;
1297 }
1298 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1299 break;
1300 case ATOMISP_PCI_DEVICE_SOC_BYT:
1301 isp->media_dev.hw_revision =
1302 (ATOMISP_HW_REVISION_ISP2400
1303 << ATOMISP_HW_REVISION_SHIFT) |
1304 ATOMISP_HW_STEPPING_B0;
1305#ifdef FIXME
1306 if (INTEL_MID_BOARD(3, TABLET, BYT, BLK, PRO, CRV2) ||
1307 INTEL_MID_BOARD(3, TABLET, BYT, BLK, ENG, CRV2)) {
1308 isp->dfs = &dfs_config_byt_cr;
1309 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1310 } else
1311#endif
1312 {
1313 isp->dfs = &dfs_config_byt;
1314 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1315 }
1316 /* HPLL frequency is known to be device-specific, but we don't
1317 * have specs yet for exactly how it varies. Default to
1318 * BYT-CR but let provisioning set it via EFI variable */
1319 isp->hpll_freq = gmin_get_var_int(&dev->dev, "HpllFreq",
1320 HPLL_FREQ_2000MHZ);
1321
1322 /*
1323 * for BYT/CHT we are put isp into D3cold to avoid pci registers access
1324 * in power off. Set d3cold_delay to 0 since default 100ms is not
1325 * necessary.
1326 */
1327 isp->pdev->d3cold_delay = 0;
1328 break;
1329 case ATOMISP_PCI_DEVICE_SOC_ANN:
1330 isp->media_dev.hw_revision = (
1331#ifdef ISP2401_NEW_INPUT_SYSTEM
1332 ATOMISP_HW_REVISION_ISP2401
1333#else
1334 ATOMISP_HW_REVISION_ISP2401_LEGACY
1335#endif
1336 << ATOMISP_HW_REVISION_SHIFT);
1337 isp->media_dev.hw_revision |= isp->pdev->revision < 2 ?
1338 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1339 isp->dfs = &dfs_config_merr;
1340 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1341 break;
1342 case ATOMISP_PCI_DEVICE_SOC_CHT:
1343 isp->media_dev.hw_revision = (
1344#ifdef ISP2401_NEW_INPUT_SYSTEM
1345 ATOMISP_HW_REVISION_ISP2401
1346#else
1347 ATOMISP_HW_REVISION_ISP2401_LEGACY
1348#endif
1349 << ATOMISP_HW_REVISION_SHIFT);
1350 isp->media_dev.hw_revision |= isp->pdev->revision < 2 ?
1351 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1352
1353 isp->dfs = &dfs_config_cht;
1354 isp->pdev->d3cold_delay = 0;
1355
1356 val = intel_mid_msgbus_read32(CCK_PORT, CCK_FUSE_REG_0);
1357 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1358 case 0x00:
1359 isp->hpll_freq = HPLL_FREQ_800MHZ;
1360 break;
1361 case 0x01:
1362 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1363 break;
1364 case 0x02:
1365 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1366 break;
1367 default:
1368 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1369 dev_warn(isp->dev,
1370 "read HPLL from cck failed.default 1600MHz.\n");
1371 }
1372 break;
1373 default:
1374 dev_err(&dev->dev, "un-supported IUNIT device\n");
1375 return -ENODEV;
1376 }
1377
1378 dev_info(&dev->dev, "ISP HPLL frequency base = %d MHz\n",
1379 isp->hpll_freq);
1380
1381 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1382
1383 /* Load isp firmware from user space */
1384 if (!defer_fw_load) {
1385 isp->firmware = atomisp_load_firmware(isp);
1386 if (!isp->firmware) {
1387 err = -ENOENT;
1388 goto load_fw_fail;
1389 }
1390
1391 err = atomisp_css_check_firmware_version(isp);
1392 if (err) {
1393 dev_dbg(&dev->dev, "Firmware version check failed\n");
1394 goto fw_validation_fail;
1395 }
1396 }
1397
1398 pci_set_master(dev);
1399 pci_set_drvdata(dev, isp);
1400
1401 err = pci_enable_msi(dev);
1402 if (err) {
1403 dev_err(&dev->dev, "Failed to enable msi (%d)\n", err);
1404 goto enable_msi_fail;
1405 }
1406
1407 atomisp_msi_irq_init(isp, dev);
1408
1409 pm_qos_add_request(&isp->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1410 PM_QOS_DEFAULT_VALUE);
1411
1412 /*
1413 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of
1414 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI
1415 * backend write 0 will enable Arasan CSI backend, which has
1416 * bugs(like sighting:4567697 and 4567699) and will be removed
1417 * in B0
1418 */
1419 atomisp_store_uint32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1420
1421 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) ==
1422 ATOMISP_PCI_DEVICE_SOC_MRFLD) {
1423 u32 csi_afe_trim;
1424
1425 /*
1426 * Workaround for imbalance data eye issue which is observed
1427 * on TNG B0.
1428 */
1429 pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
1430 &csi_afe_trim);
1431 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1432 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1433 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1434 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1435 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1436 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1437 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM <<
1438 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1439 (MRFLD_PCI_CSI2_HSRXCLKTRIM <<
1440 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1441 (MRFLD_PCI_CSI3_HSRXCLKTRIM <<
1442 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1443 pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
1444 csi_afe_trim);
1445 }
1446
1447 err = atomisp_initialize_modules(isp);
1448 if (err < 0) {
1449 dev_err(&dev->dev, "atomisp_initialize_modules (%d)\n", err);
1450 goto initialize_modules_fail;
1451 }
1452
1453 err = atomisp_register_entities(isp);
1454 if (err < 0) {
1455 dev_err(&dev->dev, "atomisp_register_entities failed (%d)\n",
1456 err);
1457 goto register_entities_fail;
1458 }
1459 err = atomisp_create_pads_links(isp);
1460 if (err < 0)
1461 goto register_entities_fail;
1462 /* init atomisp wdts */
1463 if (init_atomisp_wdts(isp) != 0)
1464 goto wdt_work_queue_fail;
1465
1466 /* save the iunit context only once after all the values are init'ed. */
1467 atomisp_save_iunit_reg(isp);
1468
1469 pm_runtime_put_noidle(&dev->dev);
1470 pm_runtime_allow(&dev->dev);
1471
1472 hmm_init_mem_stat(repool_pgnr, dypool_enable, dypool_pgnr);
1473 err = hmm_pool_register(repool_pgnr, HMM_POOL_TYPE_RESERVED);
1474 if (err) {
1475 dev_err(&dev->dev, "Failed to register reserved memory pool.\n");
1476 goto hmm_pool_fail;
1477 }
1478
1479 /* Init ISP memory management */
1480 hrt_isp_css_mm_init();
1481
1482 err = devm_request_threaded_irq(&dev->dev, dev->irq,
1483 atomisp_isr, atomisp_isr_thread,
1484 IRQF_SHARED, "isp_irq", isp);
1485 if (err) {
1486 dev_err(&dev->dev, "Failed to request irq (%d)\n", err);
1487 goto request_irq_fail;
1488 }
1489
1490 /* Load firmware into ISP memory */
1491 if (!defer_fw_load) {
1492 err = atomisp_css_load_firmware(isp);
1493 if (err) {
1494 dev_err(&dev->dev, "Failed to init css.\n");
1495 goto css_init_fail;
1496 }
1497 } else {
1498 dev_dbg(&dev->dev, "Skip css init.\n");
1499 }
1500 /* Clear FW image from memory */
1501 release_firmware(isp->firmware);
1502 isp->firmware = NULL;
1503 isp->css_env.isp_css_fw.data = NULL;
1504
1505 atomisp_drvfs_init(&atomisp_pci_driver, isp);
1506
1507 return 0;
1508
1509css_init_fail:
1510 devm_free_irq(&dev->dev, dev->irq, isp);
1511request_irq_fail:
1512 hrt_isp_css_mm_clear();
1513 hmm_pool_unregister(HMM_POOL_TYPE_RESERVED);
1514hmm_pool_fail:
1515 destroy_workqueue(isp->wdt_work_queue);
1516wdt_work_queue_fail:
1517 atomisp_acc_cleanup(isp);
1518 atomisp_unregister_entities(isp);
1519register_entities_fail:
1520 atomisp_uninitialize_modules(isp);
1521initialize_modules_fail:
1522 pm_qos_remove_request(&isp->pm_qos);
1523 atomisp_msi_irq_uninit(isp, dev);
1524enable_msi_fail:
1525fw_validation_fail:
1526 release_firmware(isp->firmware);
1527load_fw_fail:
1528 /*
1529 * Switch off ISP, as keeping it powered on would prevent
1530 * reaching S0ix states.
1531 *
1532 * The following lines have been copied from atomisp suspend path
1533 */
1534
1535 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
1536 irq = irq & 1 << INTR_IIR;
1537 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
1538
1539 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
1540 irq &= ~(1 << INTR_IER);
1541 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
1542
1543 atomisp_msi_irq_uninit(isp, dev);
1544
1545 atomisp_ospm_dphy_down(isp);
cc4e33d9 1546
a49d2536 1547 /* Address later when we worry about the ...field chips */
a49d2536
AC		 1548 if (ATOMISP_INTERNAL_PM) {
1549 if (atomisp_mrfld_power_down(isp))
1550 dev_err(&dev->dev, "Failed to switch off ISP\n");
1551 }
a49d2536
AC		 1552 pci_dev_put(isp->pci_root);
1553 return err;
1554}
1555
1556static void atomisp_pci_remove(struct pci_dev *dev)
1557{
1558 struct atomisp_device *isp = (struct atomisp_device *)
1559 pci_get_drvdata(dev);
1560
1561 atomisp_drvfs_exit();
1562
1563 atomisp_acc_cleanup(isp);
1564
1565 atomisp_css_unload_firmware(isp);
1566 hrt_isp_css_mm_clear();
1567
1568 pm_runtime_forbid(&dev->dev);
1569 pm_runtime_get_noresume(&dev->dev);
1570 pm_qos_remove_request(&isp->pm_qos);
1571
1572 atomisp_msi_irq_uninit(isp, dev);
1573 pci_dev_put(isp->pci_root);
1574
1575 atomisp_unregister_entities(isp);
1576
1577 destroy_workqueue(isp->wdt_work_queue);
1578 atomisp_file_input_cleanup(isp);
1579
1580 release_firmware(isp->firmware);
1581
1582 hmm_pool_unregister(HMM_POOL_TYPE_RESERVED);
1583}
1584
1585static const struct pci_device_id atomisp_pci_tbl[] = {
1586#if defined(ISP2400) || defined(ISP2400B0)
1587 /* Merrifield */
1588 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1178)},
1589 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1179)},
1590 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x117a)},
1591 /* Baytrail */
1592 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)},
1593#elif defined(ISP2401)
1594 /* Anniedale (Merrifield+ / Moorefield) */
1595 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1478)},
1596 /* Cherrytrail */
1597 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)},
1598#endif
1599 {0,}
1600};
1601
1602MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1603
1604#ifdef CONFIG_PM
1605static const struct dev_pm_ops atomisp_pm_ops = {
1606 .runtime_suspend = atomisp_runtime_suspend,
1607 .runtime_resume = atomisp_runtime_resume,
1608 .suspend = atomisp_suspend,
1609 .resume = atomisp_resume,
1610};
1611
1612#define DEV_PM_OPS (&atomisp_pm_ops)
1613#else
1614#define DEV_PM_OPS NULL
1615#endif
1616
1617static struct pci_driver atomisp_pci_driver = {
1618 .driver = {
1619 .pm = DEV_PM_OPS,
1620 },
1621 .name = "atomisp-isp2",
1622 .id_table = atomisp_pci_tbl,
1623 .probe = atomisp_pci_probe,
1624 .remove = atomisp_pci_remove,
1625};
1626
1627static int __init atomisp_init(void)
1628{
1629 return pci_register_driver(&atomisp_pci_driver);
1630}
1631
1632static void __exit atomisp_exit(void)
1633{
1634 pci_unregister_driver(&atomisp_pci_driver);
1635}
1636
1637module_init(atomisp_init);
1638module_exit(atomisp_exit);
1639
1640MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>");
1641MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>");
1642MODULE_LICENSE("GPL");
1643MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
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