[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / media / atomisp / pci / atomisp2 / css2400 / css_2401_csi2p_system / host / pixelgen_private.h

/*
 * Support for Intel Camera Imaging ISP subsystem.
 * Copyright (c) 2015, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef __PIXELGEN_PRIVATE_H_INCLUDED__
#define __PIXELGEN_PRIVATE_H_INCLUDED__
#include "pixelgen_public.h"
#include "hive_isp_css_host_ids_hrt.h"
#include "PixelGen_SysBlock_defs.h"
#include "device_access.h"	/* ia_css_device_load_uint32 */
#include "assert_support.h" /* assert */


/*****************************************************
 *
 * Native command interface (NCI).
 *
 *****************************************************/
/**
 * @brief Get the pixelgen state.
 * Refer to "pixelgen_public.h" for details.
 */
STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_get_state(
		const pixelgen_ID_t ID,
		pixelgen_ctrl_state_t *state)
{

	state->com_enable =
		pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX);
	state->prbs_rstval0 =
		pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG0_IDX);
	state->prbs_rstval1 =
		pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG1_IDX);
	state->syng_sid =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_SID_REG_IDX);
	state->syng_free_run =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_FREE_RUN_REG_IDX);
	state->syng_pause =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_PAUSE_REG_IDX);
	state->syng_nof_frames =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_FRAME_REG_IDX);
	state->syng_nof_pixels =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_PIXEL_REG_IDX);
	state->syng_nof_line =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_LINE_REG_IDX);
	state->syng_hblank_cyc =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_HBLANK_CYC_REG_IDX);
	state->syng_vblank_cyc =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_VBLANK_CYC_REG_IDX);
	state->syng_stat_hcnt =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_HCNT_REG_IDX);
	state->syng_stat_vcnt =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_VCNT_REG_IDX);
	state->syng_stat_fcnt =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_FCNT_REG_IDX);
	state->syng_stat_done =
		pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_DONE_REG_IDX);
	state->tpg_mode =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_MODE_REG_IDX);
	state->tpg_hcnt_mask =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_MASK_REG_IDX);
	state->tpg_vcnt_mask =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_MASK_REG_IDX);
	state->tpg_xycnt_mask =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_XYCNT_MASK_REG_IDX);
	state->tpg_hcnt_delta =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_DELTA_REG_IDX);
	state->tpg_vcnt_delta =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_DELTA_REG_IDX);
	state->tpg_r1 =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_R1_REG_IDX);
	state->tpg_g1 =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_G1_REG_IDX);
	state->tpg_b1 =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_B1_REG_IDX);
	state->tpg_r2 =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_R2_REG_IDX);
	state->tpg_g2 =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_G2_REG_IDX);
	state->tpg_b2 =
		pixelgen_ctrl_reg_load(ID, _PXG_TPG_B2_REG_IDX);
}
/**
 * @brief Dump the pixelgen state.
 * Refer to "pixelgen_public.h" for details.
 */
STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_dump_state(
		const pixelgen_ID_t ID,
		pixelgen_ctrl_state_t *state)
{
	ia_css_print("Pixel Generator ID %d Enable  0x%x \n", ID, state->com_enable);
	ia_css_print("Pixel Generator ID %d PRBS reset vlue 0 0x%x \n", ID, state->prbs_rstval0);
	ia_css_print("Pixel Generator ID %d PRBS reset vlue 1 0x%x \n", ID, state->prbs_rstval1);
	ia_css_print("Pixel Generator ID %d SYNC SID 0x%x \n", ID, state->syng_sid);
	ia_css_print("Pixel Generator ID %d syng free run 0x%x \n", ID, state->syng_free_run);
	ia_css_print("Pixel Generator ID %d syng pause 0x%x \n", ID, state->syng_pause);
	ia_css_print("Pixel Generator ID %d syng no of frames 0x%x \n", ID, state->syng_nof_frames);
	ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x \n", ID, state->syng_nof_pixels);
	ia_css_print("Pixel Generator ID %d syng no of line 0x%x \n", ID, state->syng_nof_line);
	ia_css_print("Pixel Generator ID %d syng hblank cyc  0x%x \n", ID, state->syng_hblank_cyc);
	ia_css_print("Pixel Generator ID %d syng vblank cyc  0x%x \n", ID, state->syng_vblank_cyc);
	ia_css_print("Pixel Generator ID %d syng stat hcnt  0x%x \n", ID, state->syng_stat_hcnt);
	ia_css_print("Pixel Generator ID %d syng stat vcnt  0x%x \n", ID, state->syng_stat_vcnt);
	ia_css_print("Pixel Generator ID %d syng stat fcnt  0x%x \n", ID, state->syng_stat_fcnt);
	ia_css_print("Pixel Generator ID %d syng stat done  0x%x \n", ID, state->syng_stat_done);
	ia_css_print("Pixel Generator ID %d tpg modee  0x%x \n", ID, state->tpg_mode);
	ia_css_print("Pixel Generator ID %d tpg hcnt mask  0x%x \n", ID, state->tpg_hcnt_mask);
	ia_css_print("Pixel Generator ID %d tpg hcnt mask  0x%x \n", ID, state->tpg_hcnt_mask);
	ia_css_print("Pixel Generator ID %d tpg xycnt mask  0x%x \n", ID, state->tpg_xycnt_mask);
	ia_css_print("Pixel Generator ID %d tpg hcnt delta  0x%x \n", ID, state->tpg_hcnt_delta);
	ia_css_print("Pixel Generator ID %d tpg vcnt delta  0x%x \n", ID, state->tpg_vcnt_delta);
	ia_css_print("Pixel Generator ID %d tpg r1 0x%x \n", ID, state->tpg_r1);
	ia_css_print("Pixel Generator ID %d tpg g1 0x%x \n", ID, state->tpg_g1);
	ia_css_print("Pixel Generator ID %d tpg b1 0x%x \n", ID, state->tpg_b1);
	ia_css_print("Pixel Generator ID %d tpg r2 0x%x \n", ID, state->tpg_r2);
	ia_css_print("Pixel Generator ID %d tpg g2 0x%x \n", ID, state->tpg_g2);
	ia_css_print("Pixel Generator ID %d tpg b2 0x%x \n", ID, state->tpg_b2);
}
/* end of NCI */
/*****************************************************
 *
 * Device level interface (DLI).
 *
 *****************************************************/
/**
 * @brief Load the register value.
 * Refer to "pixelgen_public.h" for details.
 */
STORAGE_CLASS_PIXELGEN_C hrt_data pixelgen_ctrl_reg_load(
	const pixelgen_ID_t ID,
	const hrt_address reg)
{
	assert(ID < N_PIXELGEN_ID);
	assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);
	return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data));
}


/**
 * @brief Store a value to the register.
 * Refer to "pixelgen_ctrl_public.h" for details.
 */
STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_reg_store(
	const pixelgen_ID_t ID,
	const hrt_address reg,
	const hrt_data value)
{
	assert(ID < N_PIXELGEN_ID);
	assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);

	ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
}
/* end of DLI */
#endif /* __PIXELGEN_PRIVATE_H_INCLUDED__ */
Commit	Line	Data
a49d2536 AC	1	/*
	2	* Support for Intel Camera Imaging ISP subsystem.
	3	* Copyright (c) 2015, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#ifndef __PIXELGEN_PRIVATE_H_INCLUDED__
	16	#define __PIXELGEN_PRIVATE_H_INCLUDED__
	17	#include "pixelgen_public.h"
	18	#include "hive_isp_css_host_ids_hrt.h"
	19	#include "PixelGen_SysBlock_defs.h"
	20	#include "device_access.h" /* ia_css_device_load_uint32 */
	21	#include "assert_support.h" /* assert */
	22
	23
	24	/*****************************************************
	25	*
	26	* Native command interface (NCI).
	27	*
	28	*****************************************************/
	29	/**
	30	* @brief Get the pixelgen state.
	31	* Refer to "pixelgen_public.h" for details.
	32	*/
	33	STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_get_state(
	34	const pixelgen_ID_t ID,
	35	pixelgen_ctrl_state_t *state)
	36	{
	37
	38	state->com_enable =
	39	pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX);
	40	state->prbs_rstval0 =
	41	pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG0_IDX);
	42	state->prbs_rstval1 =
	43	pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG1_IDX);
	44	state->syng_sid =
	45	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_SID_REG_IDX);
	46	state->syng_free_run =
	47	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_FREE_RUN_REG_IDX);
	48	state->syng_pause =
	49	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_PAUSE_REG_IDX);
	50	state->syng_nof_frames =
	51	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_FRAME_REG_IDX);
	52	state->syng_nof_pixels =
	53	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_PIXEL_REG_IDX);
	54	state->syng_nof_line =
	55	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_LINE_REG_IDX);
	56	state->syng_hblank_cyc =
	57	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_HBLANK_CYC_REG_IDX);
	58	state->syng_vblank_cyc =
	59	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_VBLANK_CYC_REG_IDX);
	60	state->syng_stat_hcnt =
	61	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_HCNT_REG_IDX);
	62	state->syng_stat_vcnt =
	63	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_VCNT_REG_IDX);
	64	state->syng_stat_fcnt =
65	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_FCNT_REG_IDX);
66	state->syng_stat_done =
67	pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_DONE_REG_IDX);
68	state->tpg_mode =
69	pixelgen_ctrl_reg_load(ID, _PXG_TPG_MODE_REG_IDX);
70	state->tpg_hcnt_mask =
71	pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_MASK_REG_IDX);
72	state->tpg_vcnt_mask =
73	pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_MASK_REG_IDX);
74	state->tpg_xycnt_mask =
75	pixelgen_ctrl_reg_load(ID, _PXG_TPG_XYCNT_MASK_REG_IDX);
76	state->tpg_hcnt_delta =
77	pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_DELTA_REG_IDX);
78	state->tpg_vcnt_delta =
79	pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_DELTA_REG_IDX);
80	state->tpg_r1 =
81	pixelgen_ctrl_reg_load(ID, _PXG_TPG_R1_REG_IDX);
82	state->tpg_g1 =
83	pixelgen_ctrl_reg_load(ID, _PXG_TPG_G1_REG_IDX);
84	state->tpg_b1 =
85	pixelgen_ctrl_reg_load(ID, _PXG_TPG_B1_REG_IDX);
86	state->tpg_r2 =
87	pixelgen_ctrl_reg_load(ID, _PXG_TPG_R2_REG_IDX);
88	state->tpg_g2 =
89	pixelgen_ctrl_reg_load(ID, _PXG_TPG_G2_REG_IDX);
90	state->tpg_b2 =
91	pixelgen_ctrl_reg_load(ID, _PXG_TPG_B2_REG_IDX);
92	}
93	/**
94	* @brief Dump the pixelgen state.
95	* Refer to "pixelgen_public.h" for details.
96	*/
97	STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_dump_state(
98	const pixelgen_ID_t ID,
99	pixelgen_ctrl_state_t *state)
100	{
101	ia_css_print("Pixel Generator ID %d Enable 0x%x \n", ID, state->com_enable);
102	ia_css_print("Pixel Generator ID %d PRBS reset vlue 0 0x%x \n", ID, state->prbs_rstval0);
103	ia_css_print("Pixel Generator ID %d PRBS reset vlue 1 0x%x \n", ID, state->prbs_rstval1);
104	ia_css_print("Pixel Generator ID %d SYNC SID 0x%x \n", ID, state->syng_sid);
105	ia_css_print("Pixel Generator ID %d syng free run 0x%x \n", ID, state->syng_free_run);
106	ia_css_print("Pixel Generator ID %d syng pause 0x%x \n", ID, state->syng_pause);
107	ia_css_print("Pixel Generator ID %d syng no of frames 0x%x \n", ID, state->syng_nof_frames);
108	ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x \n", ID, state->syng_nof_pixels);
109	ia_css_print("Pixel Generator ID %d syng no of line 0x%x \n", ID, state->syng_nof_line);
110	ia_css_print("Pixel Generator ID %d syng hblank cyc 0x%x \n", ID, state->syng_hblank_cyc);
111	ia_css_print("Pixel Generator ID %d syng vblank cyc 0x%x \n", ID, state->syng_vblank_cyc);
112	ia_css_print("Pixel Generator ID %d syng stat hcnt 0x%x \n", ID, state->syng_stat_hcnt);
113	ia_css_print("Pixel Generator ID %d syng stat vcnt 0x%x \n", ID, state->syng_stat_vcnt);
114	ia_css_print("Pixel Generator ID %d syng stat fcnt 0x%x \n", ID, state->syng_stat_fcnt);
115	ia_css_print("Pixel Generator ID %d syng stat done 0x%x \n", ID, state->syng_stat_done);
116	ia_css_print("Pixel Generator ID %d tpg modee 0x%x \n", ID, state->tpg_mode);
117	ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask);
118	ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask);
119	ia_css_print("Pixel Generator ID %d tpg xycnt mask 0x%x \n", ID, state->tpg_xycnt_mask);
120	ia_css_print("Pixel Generator ID %d tpg hcnt delta 0x%x \n", ID, state->tpg_hcnt_delta);
121	ia_css_print("Pixel Generator ID %d tpg vcnt delta 0x%x \n", ID, state->tpg_vcnt_delta);
122	ia_css_print("Pixel Generator ID %d tpg r1 0x%x \n", ID, state->tpg_r1);
123	ia_css_print("Pixel Generator ID %d tpg g1 0x%x \n", ID, state->tpg_g1);
124	ia_css_print("Pixel Generator ID %d tpg b1 0x%x \n", ID, state->tpg_b1);
125	ia_css_print("Pixel Generator ID %d tpg r2 0x%x \n", ID, state->tpg_r2);
126	ia_css_print("Pixel Generator ID %d tpg g2 0x%x \n", ID, state->tpg_g2);
127	ia_css_print("Pixel Generator ID %d tpg b2 0x%x \n", ID, state->tpg_b2);
128	}
129	/* end of NCI */
130	/*****************************************************
131	*
132	* Device level interface (DLI).
133	*
134	*****************************************************/
135	/**
136	* @brief Load the register value.
137	* Refer to "pixelgen_public.h" for details.
138	*/
139	STORAGE_CLASS_PIXELGEN_C hrt_data pixelgen_ctrl_reg_load(
140	const pixelgen_ID_t ID,
141	const hrt_address reg)
142	{
143	assert(ID < N_PIXELGEN_ID);
144	assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);
145	return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data));
146	}
147
148
149	/**
150	* @brief Store a value to the register.
151	* Refer to "pixelgen_ctrl_public.h" for details.
152	*/
153	STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_reg_store(
154	const pixelgen_ID_t ID,
155	const hrt_address reg,
156	const hrt_data value)
157	{
158	assert(ID < N_PIXELGEN_ID);
159	assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);
160
161	ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
162	}
d929fb4e	163	/* end of DLI */
a49d2536	164	#endif /* __PIXELGEN_PRIVATE_H_INCLUDED__ */