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a49d2536 AC |
1 | /* |
2 | * Support for Intel Camera Imaging ISP subsystem. | |
3 | * Copyright (c) 2015, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #ifndef __IA_CSS_SDIS_COMMON_TYPES_H | |
16 | #define __IA_CSS_SDIS_COMMON_TYPES_H | |
17 | ||
d929fb4e | 18 | /* @file |
a49d2536 AC |
19 | * CSS-API header file for DVS statistics parameters. |
20 | */ | |
21 | ||
22 | #include <type_support.h> | |
23 | ||
d929fb4e | 24 | /* DVS statistics grid dimensions in number of cells. |
a49d2536 AC |
25 | */ |
26 | ||
27 | struct ia_css_dvs_grid_dim { | |
d929fb4e MCC |
28 | uint32_t width; /** Width of DVS grid table in cells */ |
29 | uint32_t height; /** Height of DVS grid table in cells */ | |
a49d2536 AC |
30 | }; |
31 | ||
d929fb4e | 32 | /* DVS statistics dimensions in number of cells for |
a49d2536 AC |
33 | * grid, coeffieicient and projection. |
34 | */ | |
35 | ||
36 | struct ia_css_sdis_info { | |
37 | struct { | |
38 | struct ia_css_dvs_grid_dim dim; /* Dimensions */ | |
39 | struct ia_css_dvs_grid_dim pad; /* Padded dimensions */ | |
40 | } grid, coef, proj; | |
41 | uint32_t deci_factor_log2; | |
42 | }; | |
43 | ||
44 | #define IA_CSS_DEFAULT_SDIS_INFO \ | |
45 | { \ | |
46 | { { 0, 0 }, /* dim */ \ | |
47 | { 0, 0 }, /* pad */ \ | |
48 | }, /* grid */ \ | |
49 | { { 0, 0 }, /* dim */ \ | |
50 | { 0, 0 }, /* pad */ \ | |
51 | }, /* coef */ \ | |
52 | { { 0, 0 }, /* dim */ \ | |
53 | { 0, 0 }, /* pad */ \ | |
54 | }, /* proj */ \ | |
55 | 0, /* dis_deci_factor_log2 */ \ | |
56 | } | |
57 | ||
d929fb4e | 58 | /* DVS statistics grid |
a49d2536 AC |
59 | * |
60 | * ISP block: SDVS1 (DIS/DVS Support for DIS/DVS ver.1 (2-axes)) | |
61 | * SDVS2 (DVS Support for DVS ver.2 (6-axes)) | |
62 | * ISP1: SDVS1 is used. | |
63 | * ISP2: SDVS2 is used. | |
64 | */ | |
65 | struct ia_css_dvs_grid_res { | |
d929fb4e | 66 | uint32_t width; /** Width of DVS grid table. |
a49d2536 AC |
67 | (= Horizontal number of grid cells |
68 | in table, which cells have effective | |
69 | statistics.) | |
70 | For DVS1, this is equal to | |
71 | the number of vertical statistics. */ | |
d929fb4e | 72 | uint32_t aligned_width; /** Stride of each grid line. |
a49d2536 AC |
73 | (= Horizontal number of grid cells |
74 | in table, which means | |
75 | the allocated width.) */ | |
d929fb4e | 76 | uint32_t height; /** Height of DVS grid table. |
a49d2536 AC |
77 | (= Vertical number of grid cells |
78 | in table, which cells have effective | |
79 | statistics.) | |
80 | For DVS1, This is equal to | |
81 | the number of horizontal statistics. */ | |
d929fb4e | 82 | uint32_t aligned_height;/** Stride of each grid column. |
a49d2536 AC |
83 | (= Vertical number of grid cells |
84 | in table, which means | |
85 | the allocated height.) */ | |
86 | }; | |
87 | ||
88 | /* TODO: use ia_css_dvs_grid_res in here. | |
89 | * However, that implies driver I/F changes | |
90 | */ | |
91 | struct ia_css_dvs_grid_info { | |
d929fb4e | 92 | uint32_t enable; /** DVS statistics enabled. |
a49d2536 | 93 | 0:disabled, 1:enabled */ |
d929fb4e | 94 | uint32_t width; /** Width of DVS grid table. |
a49d2536 AC |
95 | (= Horizontal number of grid cells |
96 | in table, which cells have effective | |
97 | statistics.) | |
98 | For DVS1, this is equal to | |
99 | the number of vertical statistics. */ | |
d929fb4e | 100 | uint32_t aligned_width; /** Stride of each grid line. |
a49d2536 AC |
101 | (= Horizontal number of grid cells |
102 | in table, which means | |
103 | the allocated width.) */ | |
d929fb4e | 104 | uint32_t height; /** Height of DVS grid table. |
a49d2536 AC |
105 | (= Vertical number of grid cells |
106 | in table, which cells have effective | |
107 | statistics.) | |
108 | For DVS1, This is equal to | |
109 | the number of horizontal statistics. */ | |
d929fb4e | 110 | uint32_t aligned_height;/** Stride of each grid column. |
a49d2536 AC |
111 | (= Vertical number of grid cells |
112 | in table, which means | |
113 | the allocated height.) */ | |
d929fb4e | 114 | uint32_t bqs_per_grid_cell; /** Grid cell size in BQ(Bayer Quad) unit. |
a49d2536 AC |
115 | (1BQ means {Gr,R,B,Gb}(2x2 pixels).) |
116 | For DVS1, valid value is 64. | |
117 | For DVS2, valid value is only 64, | |
118 | currently. */ | |
d929fb4e MCC |
119 | uint32_t num_hor_coefs; /** Number of horizontal coefficients. */ |
120 | uint32_t num_ver_coefs; /** Number of vertical coefficients. */ | |
a49d2536 AC |
121 | }; |
122 | ||
d929fb4e | 123 | /* Number of DVS statistics levels |
a49d2536 AC |
124 | */ |
125 | #define IA_CSS_DVS_STAT_NUM_OF_LEVELS 3 | |
126 | ||
d929fb4e | 127 | /* DVS statistics generated by accelerator global configuration |
a49d2536 AC |
128 | */ |
129 | struct dvs_stat_public_dvs_global_cfg { | |
130 | unsigned char kappa; | |
d929fb4e | 131 | /** DVS statistics global configuration - kappa */ |
a49d2536 | 132 | unsigned char match_shift; |
d929fb4e | 133 | /** DVS statistics global configuration - match_shift */ |
a49d2536 | 134 | unsigned char ybin_mode; |
d929fb4e | 135 | /** DVS statistics global configuration - y binning mode */ |
a49d2536 AC |
136 | }; |
137 | ||
d929fb4e | 138 | /* DVS statistics generated by accelerator level grid |
a49d2536 AC |
139 | * configuration |
140 | */ | |
141 | struct dvs_stat_public_dvs_level_grid_cfg { | |
142 | unsigned char grid_width; | |
d929fb4e | 143 | /** DVS statistics grid width */ |
a49d2536 | 144 | unsigned char grid_height; |
d929fb4e | 145 | /** DVS statistics grid height */ |
a49d2536 | 146 | unsigned char block_width; |
d929fb4e | 147 | /** DVS statistics block width */ |
a49d2536 | 148 | unsigned char block_height; |
d929fb4e | 149 | /** DVS statistics block height */ |
a49d2536 AC |
150 | }; |
151 | ||
d929fb4e | 152 | /* DVS statistics generated by accelerator level grid start |
a49d2536 AC |
153 | * configuration |
154 | */ | |
155 | struct dvs_stat_public_dvs_level_grid_start { | |
156 | unsigned short x_start; | |
d929fb4e | 157 | /** DVS statistics level x start */ |
a49d2536 | 158 | unsigned short y_start; |
d929fb4e | 159 | /** DVS statistics level y start */ |
a49d2536 | 160 | unsigned char enable; |
d929fb4e | 161 | /** DVS statistics level enable */ |
a49d2536 AC |
162 | }; |
163 | ||
d929fb4e | 164 | /* DVS statistics generated by accelerator level grid end |
a49d2536 AC |
165 | * configuration |
166 | */ | |
167 | struct dvs_stat_public_dvs_level_grid_end { | |
168 | unsigned short x_end; | |
d929fb4e | 169 | /** DVS statistics level x end */ |
a49d2536 | 170 | unsigned short y_end; |
d929fb4e | 171 | /** DVS statistics level y end */ |
a49d2536 AC |
172 | }; |
173 | ||
d929fb4e | 174 | /* DVS statistics generated by accelerator Feature Extraction |
a49d2536 AC |
175 | * Region Of Interest (FE-ROI) configuration |
176 | */ | |
177 | struct dvs_stat_public_dvs_level_fe_roi_cfg { | |
178 | unsigned char x_start; | |
d929fb4e | 179 | /** DVS statistics fe-roi level x start */ |
a49d2536 | 180 | unsigned char y_start; |
d929fb4e | 181 | /** DVS statistics fe-roi level y start */ |
a49d2536 | 182 | unsigned char x_end; |
d929fb4e | 183 | /** DVS statistics fe-roi level x end */ |
a49d2536 | 184 | unsigned char y_end; |
d929fb4e | 185 | /** DVS statistics fe-roi level y end */ |
a49d2536 AC |
186 | }; |
187 | ||
d929fb4e | 188 | /* DVS statistics generated by accelerator public configuration |
a49d2536 AC |
189 | */ |
190 | struct dvs_stat_public_dvs_grd_cfg { | |
191 | struct dvs_stat_public_dvs_level_grid_cfg grd_cfg; | |
d929fb4e | 192 | /** DVS statistics level grid configuration */ |
a49d2536 | 193 | struct dvs_stat_public_dvs_level_grid_start grd_start; |
d929fb4e | 194 | /** DVS statistics level grid start configuration */ |
a49d2536 | 195 | struct dvs_stat_public_dvs_level_grid_end grd_end; |
d929fb4e | 196 | /** DVS statistics level grid end configuration */ |
a49d2536 AC |
197 | }; |
198 | ||
d929fb4e | 199 | /* DVS statistics grid generated by accelerator |
a49d2536 AC |
200 | */ |
201 | struct ia_css_dvs_stat_grid_info { | |
202 | struct dvs_stat_public_dvs_global_cfg dvs_gbl_cfg; | |
d929fb4e | 203 | /** DVS statistics global configuration (kappa, match, binning) */ |
a49d2536 | 204 | struct dvs_stat_public_dvs_grd_cfg grd_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; |
d929fb4e | 205 | /** DVS statistics grid configuration (blocks and grids) */ |
a49d2536 | 206 | struct dvs_stat_public_dvs_level_fe_roi_cfg fe_roi_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; |
d929fb4e | 207 | /** DVS statistics FE ROI (region of interest) configuration */ |
a49d2536 AC |
208 | }; |
209 | ||
d929fb4e | 210 | /* DVS statistics generated by accelerator default grid info |
a49d2536 AC |
211 | */ |
212 | #define DEFAULT_DVS_GRID_INFO { \ | |
213 | { \ | |
214 | { 0, 0, 0}, /* GBL CFG reg: kappa, match_shifrt, binning mode*/ \ | |
215 | {{{0, 0, 0, 0}, {0, 0, 0}, {0, 0} }, \ | |
216 | {{0, 0, 0, 0}, {0, 0, 0}, {0, 0} }, \ | |
217 | {{0, 0, 0, 0}, {0, 0, 0}, {0, 0} } }, \ | |
218 | {{0, 0, 0, 0}, {4, 0, 0, 0}, {0, 0, 0, 0} } } \ | |
219 | } | |
220 | ||
221 | ||
d929fb4e | 222 | /* Union that holds all types of DVS statistics grid info in |
a49d2536 AC |
223 | * CSS format |
224 | * */ | |
225 | union ia_css_dvs_grid_u { | |
226 | struct ia_css_dvs_stat_grid_info dvs_stat_grid_info; | |
d929fb4e | 227 | /** DVS statistics produced by accelerator grid info */ |
a49d2536 | 228 | struct ia_css_dvs_grid_info dvs_grid_info; |
d929fb4e | 229 | /** DVS (DVS1/DVS2) grid info */ |
a49d2536 AC |
230 | }; |
231 | ||
232 | #endif /* __IA_CSS_SDIS_COMMON_TYPES_H */ |