[mirror_ubuntu-bionic-kernel.git] / drivers / staging / media / atomisp / platform / intel-mid / intel_mid_pcihelpers.c

#include <linux/export.h>
#include <linux/pci.h>
#include <linux/pm_qos.h>
#include <linux/delay.h>

/* G-Min addition: "platform_is()" lives in intel_mid_pm.h in the MCG
 * tree, but it's just platform ID info and we don't want to pull in
 * the whole SFI-based PM architecture.
 */
#define INTEL_ATOM_MRST 0x26
#define INTEL_ATOM_MFLD 0x27
#define INTEL_ATOM_CLV 0x35
#define INTEL_ATOM_MRFLD 0x4a
#define INTEL_ATOM_BYT 0x37
#define INTEL_ATOM_MOORFLD 0x5a
#define INTEL_ATOM_CHT 0x4c
static inline int platform_is(u8 model)
{
	return (boot_cpu_data.x86_model == model);
}

#include "../../include/asm/intel_mid_pcihelpers.h"

/* Unified message bus read/write operation */
static DEFINE_SPINLOCK(msgbus_lock);

static struct pci_dev *pci_root;
static struct pm_qos_request pm_qos;

#define DW_I2C_NEED_QOS	(platform_is(INTEL_ATOM_BYT))

static int intel_mid_msgbus_init(void)
{
	pci_root = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	if (!pci_root) {
		pr_err("%s: Error: msgbus PCI handle NULL\n", __func__);
		return -ENODEV;
	}

	if (DW_I2C_NEED_QOS) {
		pm_qos_add_request(&pm_qos,
			PM_QOS_CPU_DMA_LATENCY,
			PM_QOS_DEFAULT_VALUE);
	}
	return 0;
}
fs_initcall(intel_mid_msgbus_init);

u32 intel_mid_msgbus_read32(u8 port, u32 addr)
{
	unsigned long irq_flags;
	u32 data;
	u32 cmd;
	u32 cmdext;

	cmd = (PCI_ROOT_MSGBUS_READ << 24) | (port << 16) |
		((addr & 0xff) << 8) | PCI_ROOT_MSGBUS_DWORD_ENABLE;
	cmdext = addr & 0xffffff00;

	spin_lock_irqsave(&msgbus_lock, irq_flags);

	if (cmdext) {
		/* This resets to 0 automatically, no need to write 0 */
		pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG,
					cmdext);
	}

	pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd);
	pci_read_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, &data);
	spin_unlock_irqrestore(&msgbus_lock, irq_flags);

	return data;
}
EXPORT_SYMBOL(intel_mid_msgbus_read32);

void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data)
{
	unsigned long irq_flags;
	u32 cmd;
	u32 cmdext;

	cmd = (PCI_ROOT_MSGBUS_WRITE << 24) | (port << 16) |
		((addr & 0xFF) << 8) | PCI_ROOT_MSGBUS_DWORD_ENABLE;
	cmdext = addr & 0xffffff00;

	spin_lock_irqsave(&msgbus_lock, irq_flags);
	pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, data);

	if (cmdext) {
		/* This resets to 0 automatically, no need to write 0 */
		pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG,
					cmdext);
	}

	pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd);
	spin_unlock_irqrestore(&msgbus_lock, irq_flags);
}
EXPORT_SYMBOL(intel_mid_msgbus_write32);
Commit	Line	Data
a49d2536 AC	1	#include <linux/export.h>
	2	#include <linux/pci.h>
	3	#include <linux/pm_qos.h>
	4	#include <linux/delay.h>
	5
	6	/* G-Min addition: "platform_is()" lives in intel_mid_pm.h in the MCG
	7	* tree, but it's just platform ID info and we don't want to pull in
8c7e9a73 AS	8	* the whole SFI-based PM architecture.
8c7e9a73 AS	9	*/
a49d2536 AC	10	#define INTEL_ATOM_MRST 0x26
	11	#define INTEL_ATOM_MFLD 0x27
	12	#define INTEL_ATOM_CLV 0x35
	13	#define INTEL_ATOM_MRFLD 0x4a
	14	#define INTEL_ATOM_BYT 0x37
	15	#define INTEL_ATOM_MOORFLD 0x5a
	16	#define INTEL_ATOM_CHT 0x4c
a49d2536 AC	17	static inline int platform_is(u8 model)
a49d2536 AC	18	{
b739d024	19	return (boot_cpu_data.x86_model == model);
a49d2536 AC	20	}
a49d2536 AC	21
25016567	22	#include "../../include/asm/intel_mid_pcihelpers.h"
a49d2536 AC	23
	24	/* Unified message bus read/write operation */
	25	static DEFINE_SPINLOCK(msgbus_lock);
	26
	27	static struct pci_dev *pci_root;
	28	static struct pm_qos_request pm_qos;
a49d2536 AC	29
	30	#define DW_I2C_NEED_QOS (platform_is(INTEL_ATOM_BYT))
	31
	32	static int intel_mid_msgbus_init(void)
	33	{
	34	pci_root = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	35	if (!pci_root) {
	36	pr_err("%s: Error: msgbus PCI handle NULL\n", __func__);
	37	return -ENODEV;
	38	}
	39
	40	if (DW_I2C_NEED_QOS) {
	41	pm_qos_add_request(&pm_qos,
	42	PM_QOS_CPU_DMA_LATENCY,
	43	PM_QOS_DEFAULT_VALUE);
	44	}
	45	return 0;
	46	}
	47	fs_initcall(intel_mid_msgbus_init);
	48
a49d2536 AC	49	u32 intel_mid_msgbus_read32(u8 port, u32 addr)
	50	{
	51	unsigned long irq_flags;
	52	u32 data;
	53	u32 cmd;
	54	u32 cmdext;
	55
	56	cmd = (PCI_ROOT_MSGBUS_READ << 24) \| (port << 16) \|
	57	((addr & 0xff) << 8) \| PCI_ROOT_MSGBUS_DWORD_ENABLE;
	58	cmdext = addr & 0xffffff00;
	59
	60	spin_lock_irqsave(&msgbus_lock, irq_flags);
	61
	62	if (cmdext) {
	63	/* This resets to 0 automatically, no need to write 0 */
	64	pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG,
	65	cmdext);
	66	}
	67
	68	pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd);
	69	pci_read_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, &data);
	70	spin_unlock_irqrestore(&msgbus_lock, irq_flags);
	71
	72	return data;
	73	}
a49d2536	74	EXPORT_SYMBOL(intel_mid_msgbus_read32);
8c7e9a73	75
a49d2536 AC	76	void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data)
	77	{
	78	unsigned long irq_flags;
	79	u32 cmd;
	80	u32 cmdext;
	81
	82	cmd = (PCI_ROOT_MSGBUS_WRITE << 24) \| (port << 16) \|
	83	((addr & 0xFF) << 8) \| PCI_ROOT_MSGBUS_DWORD_ENABLE;
	84	cmdext = addr & 0xffffff00;
	85
	86	spin_lock_irqsave(&msgbus_lock, irq_flags);
	87	pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, data);
	88
	89	if (cmdext) {
	90	/* This resets to 0 automatically, no need to write 0 */
	91	pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG,
	92	cmdext);
	93	}
	94
	95	pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd);
	96	spin_unlock_irqrestore(&msgbus_lock, irq_flags);
	97	}
	98	EXPORT_SYMBOL(intel_mid_msgbus_write32);