[mirror_ubuntu-artful-kernel.git] / drivers / staging / media / cxd2099 / cxd2099.c

/*
 * cxd2099.c: Driver for the CXD2099AR Common Interface Controller
 *
 * Copyright (C) 2010-2013 Digital Devices GmbH
 *
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 only, as published by the Free Software Foundation.
 *
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA
 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/io.h>

#include "cxd2099.h"

/* comment this line to deactivate the cxd2099ar buffer mode */
#define BUFFER_MODE 1

static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);

struct cxd {
	struct dvb_ca_en50221 en;

	struct i2c_adapter *i2c;
	struct cxd2099_cfg cfg;

	u8     regs[0x23];
	u8     lastaddress;
	u8     clk_reg_f;
	u8     clk_reg_b;
	int    mode;
	int    ready;
	int    dr;
	int    write_busy;
	int    slot_stat;

	u8     amem[1024];
	int    amem_read;

	int    cammode;
	struct mutex lock;

	u8     rbuf[1028];
	u8     wbuf[1028];
};

static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
			 u8 reg, u8 data)
{
	u8 m[2] = {reg, data};
	struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};

	if (i2c_transfer(adapter, &msg, 1) != 1) {
		dev_err(&adapter->dev,
			"Failed to write to I2C register %02x@%02x!\n",
			reg, adr);
		return -1;
	}
	return 0;
}

static int i2c_write(struct i2c_adapter *adapter, u8 adr,
		     u8 *data, u16 len)
{
	struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};

	if (i2c_transfer(adapter, &msg, 1) != 1) {
		dev_err(&adapter->dev, "Failed to write to I2C!\n");
		return -1;
	}
	return 0;
}

static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
			u8 reg, u8 *val)
{
	struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
				   .buf = &reg, .len = 1},
				  {.addr = adr, .flags = I2C_M_RD,
				   .buf = val, .len = 1} };

	if (i2c_transfer(adapter, msgs, 2) != 2) {
		dev_err(&adapter->dev, "error in i2c_read_reg\n");
		return -1;
	}
	return 0;
}

static int i2c_read(struct i2c_adapter *adapter, u8 adr,
		    u8 reg, u8 *data, u16 n)
{
	struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
				   .buf = &reg, .len = 1},
				  {.addr = adr, .flags = I2C_M_RD,
				   .buf = data, .len = n} };

	if (i2c_transfer(adapter, msgs, 2) != 2) {
		dev_err(&adapter->dev, "error in i2c_read\n");
		return -1;
	}
	return 0;
}

static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
{
	int status = 0;

	if (ci->lastaddress != adr)
		status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
	if (!status) {
		ci->lastaddress = adr;

		while (n) {
			int len = n;

			if (ci->cfg.max_i2c && (len > ci->cfg.max_i2c))
				len = ci->cfg.max_i2c;
			status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, len);
			if (status)
				return status;
			data += len;
			n -= len;
		}
	}
	return status;
}

static int read_reg(struct cxd *ci, u8 reg, u8 *val)
{
	return read_block(ci, reg, val, 1);
}

static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
	int status;
	u8 addr[3] = {2, address & 0xff, address >> 8};

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status)
		status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
	return status;
}

static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
	int status;
	u8 addr[3] = {2, address & 0xff, address >> 8};

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status) {
		u8 buf[256] = {3};

		memcpy(buf + 1, data, n);
		status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
	}
	return status;
}

static int read_io(struct cxd *ci, u16 address, u8 *val)
{
	int status;
	u8 addr[3] = {2, address & 0xff, address >> 8};

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status)
		status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1);
	return status;
}

static int write_io(struct cxd *ci, u16 address, u8 val)
{
	int status;
	u8 addr[3] = {2, address & 0xff, address >> 8};
	u8 buf[2] = {3, val};

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status)
		status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2);
	return status;
}

static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
{
	int status = 0;

	if (ci->lastaddress != reg)
		status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
	if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
		status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
	ci->lastaddress = reg;
	ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
	if (!status)
		status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]);
	if (reg == 0x20)
		ci->regs[reg] &= 0x7f;
	return status;
}

static int write_reg(struct cxd *ci, u8 reg, u8 val)
{
	return write_regm(ci, reg, val, 0xff);
}

#ifdef BUFFER_MODE
static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
{
	int status = 0;
	u8 *buf = ci->wbuf;

	if (ci->lastaddress != adr)
		status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
	if (status)
		return status;

	ci->lastaddress = adr;
	buf[0] = 1;
	while (n) {
		int len = n;

		if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
			len = ci->cfg.max_i2c - 1;
		memcpy(buf + 1, data, len);
		status = i2c_write(ci->i2c, ci->cfg.adr, buf, len + 1);
		if (status)
			return status;
		n -= len;
		data += len;
	}
	return status;
}
#endif

static void set_mode(struct cxd *ci, int mode)
{
	if (mode == ci->mode)
		return;

	switch (mode) {
	case 0x00: /* IO mem */
		write_regm(ci, 0x06, 0x00, 0x07);
		break;
	case 0x01: /* ATT mem */
		write_regm(ci, 0x06, 0x02, 0x07);
		break;
	default:
		break;
	}
	ci->mode = mode;
}

static void cam_mode(struct cxd *ci, int mode)
{
	u8 dummy;

	if (mode == ci->cammode)
		return;

	switch (mode) {
	case 0x00:
		write_regm(ci, 0x20, 0x80, 0x80);
		break;
	case 0x01:
		if (!ci->en.read_data)
			return;
		ci->write_busy = 0;
		dev_info(&ci->i2c->dev, "enable cam buffer mode\n");
		write_reg(ci, 0x0d, 0x00);
		write_reg(ci, 0x0e, 0x01);
		write_regm(ci, 0x08, 0x40, 0x40);
		read_reg(ci, 0x12, &dummy);
		write_regm(ci, 0x08, 0x80, 0x80);
		break;
	default:
		break;
	}
	ci->cammode = mode;
}

static int init(struct cxd *ci)
{
	int status;

	mutex_lock(&ci->lock);
	ci->mode = -1;
	do {
		status = write_reg(ci, 0x00, 0x00);
		if (status < 0)
			break;
		status = write_reg(ci, 0x01, 0x00);
		if (status < 0)
			break;
		status = write_reg(ci, 0x02, 0x10);
		if (status < 0)
			break;
		status = write_reg(ci, 0x03, 0x00);
		if (status < 0)
			break;
		status = write_reg(ci, 0x05, 0xFF);
		if (status < 0)
			break;
		status = write_reg(ci, 0x06, 0x1F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x07, 0x1F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x08, 0x28);
		if (status < 0)
			break;
		status = write_reg(ci, 0x14, 0x20);
		if (status < 0)
			break;

		/* TOSTRT = 8, Mode B (gated clock), falling Edge,
		 * Serial, POL=HIGH, MSB
		 */
		status = write_reg(ci, 0x0A, 0xA7);
		if (status < 0)
			break;

		status = write_reg(ci, 0x0B, 0x33);
		if (status < 0)
			break;
		status = write_reg(ci, 0x0C, 0x33);
		if (status < 0)
			break;

		status = write_regm(ci, 0x14, 0x00, 0x0F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x15, ci->clk_reg_b);
		if (status < 0)
			break;
		status = write_regm(ci, 0x16, 0x00, 0x0F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x17, ci->clk_reg_f);
		if (status < 0)
			break;

		if (ci->cfg.clock_mode == 2) {
			/* bitrate*2^13/ 72000 */
			u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;

			if (ci->cfg.polarity) {
				status = write_reg(ci, 0x09, 0x6f);
				if (status < 0)
					break;
			} else {
				status = write_reg(ci, 0x09, 0x6d);
				if (status < 0)
					break;
			}
			status = write_reg(ci, 0x20, 0x08);
			if (status < 0)
				break;
			status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
			if (status < 0)
				break;
			status = write_reg(ci, 0x22, reg & 0xff);
			if (status < 0)
				break;
		} else if (ci->cfg.clock_mode == 1) {
			if (ci->cfg.polarity) {
				status = write_reg(ci, 0x09, 0x6f); /* D */
				if (status < 0)
					break;
			} else {
				status = write_reg(ci, 0x09, 0x6d);
				if (status < 0)
					break;
			}
			status = write_reg(ci, 0x20, 0x68);
			if (status < 0)
				break;
			status = write_reg(ci, 0x21, 0x00);
			if (status < 0)
				break;
			status = write_reg(ci, 0x22, 0x02);
			if (status < 0)
				break;
		} else {
			if (ci->cfg.polarity) {
				status = write_reg(ci, 0x09, 0x4f); /* C */
				if (status < 0)
					break;
			} else {
				status = write_reg(ci, 0x09, 0x4d);
				if (status < 0)
					break;
			}
			status = write_reg(ci, 0x20, 0x28);
			if (status < 0)
				break;
			status = write_reg(ci, 0x21, 0x00);
			if (status < 0)
				break;
			status = write_reg(ci, 0x22, 0x07);
			if (status < 0)
				break;
		}

		status = write_regm(ci, 0x20, 0x80, 0x80);
		if (status < 0)
			break;
		status = write_regm(ci, 0x03, 0x02, 0x02);
		if (status < 0)
			break;
		status = write_reg(ci, 0x01, 0x04);
		if (status < 0)
			break;
		status = write_reg(ci, 0x00, 0x31);
		if (status < 0)
			break;

		/* Put TS in bypass */
		status = write_regm(ci, 0x09, 0x08, 0x08);
		if (status < 0)
			break;
		ci->cammode = -1;
		cam_mode(ci, 0);
	} while (0);
	mutex_unlock(&ci->lock);

	return 0;
}

static int read_attribute_mem(struct dvb_ca_en50221 *ca,
			      int slot, int address)
{
	struct cxd *ci = ca->data;
	u8 val;

	mutex_lock(&ci->lock);
	set_mode(ci, 1);
	read_pccard(ci, address, &val, 1);
	mutex_unlock(&ci->lock);
	return val;
}

static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
			       int address, u8 value)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	set_mode(ci, 1);
	write_pccard(ci, address, &value, 1);
	mutex_unlock(&ci->lock);
	return 0;
}

static int read_cam_control(struct dvb_ca_en50221 *ca,
			    int slot, u8 address)
{
	struct cxd *ci = ca->data;
	u8 val;

	mutex_lock(&ci->lock);
	set_mode(ci, 0);
	read_io(ci, address, &val);
	mutex_unlock(&ci->lock);
	return val;
}

static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
			     u8 address, u8 value)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	set_mode(ci, 0);
	write_io(ci, address, value);
	mutex_unlock(&ci->lock);
	return 0;
}

static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
{
	struct cxd *ci = ca->data;

	if (ci->cammode)
		read_data(ca, slot, ci->rbuf, 0);

	mutex_lock(&ci->lock);
	cam_mode(ci, 0);
	write_reg(ci, 0x00, 0x21);
	write_reg(ci, 0x06, 0x1F);
	write_reg(ci, 0x00, 0x31);
	write_regm(ci, 0x20, 0x80, 0x80);
	write_reg(ci, 0x03, 0x02);
	ci->ready = 0;
	ci->mode = -1;
	{
		int i;

		for (i = 0; i < 100; i++) {
			usleep_range(10000, 11000);
			if (ci->ready)
				break;
		}
	}
	mutex_unlock(&ci->lock);
	return 0;
}

static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
{
	struct cxd *ci = ca->data;

	dev_info(&ci->i2c->dev, "%s\n", __func__);
	if (ci->cammode)
		read_data(ca, slot, ci->rbuf, 0);
	mutex_lock(&ci->lock);
	write_reg(ci, 0x00, 0x21);
	write_reg(ci, 0x06, 0x1F);
	msleep(300);

	write_regm(ci, 0x09, 0x08, 0x08);
	write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
	write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */

	ci->mode = -1;
	ci->write_busy = 0;
	mutex_unlock(&ci->lock);
	return 0;
}

static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	write_regm(ci, 0x09, 0x00, 0x08);
	set_mode(ci, 0);
	cam_mode(ci, 1);
	mutex_unlock(&ci->lock);
	return 0;
}

static int campoll(struct cxd *ci)
{
	u8 istat;

	read_reg(ci, 0x04, &istat);
	if (!istat)
		return 0;
	write_reg(ci, 0x05, istat);

	if (istat & 0x40)
		ci->dr = 1;
	if (istat & 0x20)
		ci->write_busy = 0;

	if (istat & 2) {
		u8 slotstat;

		read_reg(ci, 0x01, &slotstat);
		if (!(2 & slotstat)) {
			if (!ci->slot_stat) {
				ci->slot_stat |=
					      DVB_CA_EN50221_POLL_CAM_PRESENT;
				write_regm(ci, 0x03, 0x08, 0x08);
			}

		} else {
			if (ci->slot_stat) {
				ci->slot_stat = 0;
				write_regm(ci, 0x03, 0x00, 0x08);
				dev_info(&ci->i2c->dev, "NO CAM\n");
				ci->ready = 0;
			}
		}
		if ((istat & 8) &&
		    (ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT)) {
			ci->ready = 1;
			ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
		}
	}
	return 0;
}

static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
{
	struct cxd *ci = ca->data;
	u8 slotstat;

	mutex_lock(&ci->lock);
	campoll(ci);
	read_reg(ci, 0x01, &slotstat);
	mutex_unlock(&ci->lock);

	return ci->slot_stat;
}

static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
	struct cxd *ci = ca->data;
	u8 msb, lsb;
	u16 len;

	mutex_lock(&ci->lock);
	campoll(ci);
	mutex_unlock(&ci->lock);

	if (!ci->dr)
		return 0;

	mutex_lock(&ci->lock);
	read_reg(ci, 0x0f, &msb);
	read_reg(ci, 0x10, &lsb);
	len = ((u16)msb << 8) | lsb;
	if (len > ecount || len < 2) {
		/* read it anyway or cxd may hang */
		read_block(ci, 0x12, ci->rbuf, len);
		mutex_unlock(&ci->lock);
		return -EIO;
	}
	read_block(ci, 0x12, ebuf, len);
	ci->dr = 0;
	mutex_unlock(&ci->lock);
	return len;
}

#ifdef BUFFER_MODE

static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
	struct cxd *ci = ca->data;

	if (ci->write_busy)
		return -EAGAIN;
	mutex_lock(&ci->lock);
	write_reg(ci, 0x0d, ecount >> 8);
	write_reg(ci, 0x0e, ecount & 0xff);
	write_block(ci, 0x11, ebuf, ecount);
	ci->write_busy = 1;
	mutex_unlock(&ci->lock);
	return ecount;
}
#endif

static struct dvb_ca_en50221 en_templ = {
	.read_attribute_mem  = read_attribute_mem,
	.write_attribute_mem = write_attribute_mem,
	.read_cam_control    = read_cam_control,
	.write_cam_control   = write_cam_control,
	.slot_reset          = slot_reset,
	.slot_shutdown       = slot_shutdown,
	.slot_ts_enable      = slot_ts_enable,
	.poll_slot_status    = poll_slot_status,
#ifdef BUFFER_MODE
	.read_data           = read_data,
	.write_data          = write_data,
#endif

};

struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
				      void *priv,
				      struct i2c_adapter *i2c)
{
	struct cxd *ci;
	u8 val;

	if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) {
		dev_info(&i2c->dev, "No CXD2099 detected at %02x\n", cfg->adr);
		return NULL;
	}

	ci = kzalloc(sizeof(*ci), GFP_KERNEL);
	if (!ci)
		return NULL;

	mutex_init(&ci->lock);
	ci->cfg = *cfg;
	ci->i2c = i2c;
	ci->lastaddress = 0xff;
	ci->clk_reg_b = 0x4a;
	ci->clk_reg_f = 0x1b;

	ci->en = en_templ;
	ci->en.data = ci;
	init(ci);
	dev_info(&i2c->dev, "Attached CXD2099AR at %02x\n", ci->cfg.adr);
	return &ci->en;
}
EXPORT_SYMBOL(cxd2099_attach);

MODULE_DESCRIPTION("cxd2099");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");
Commit	Line	Data
0f0b270f RM	1	/*
	2	* cxd2099.c: Driver for the CXD2099AR Common Interface Controller
	3	*
dd3c5d00	4	* Copyright (C) 2010-2013 Digital Devices GmbH
0f0b270f RM	5	*
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 only, as published by the Free Software Foundation.
	10	*
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	21	* 02110-1301, USA
	22	* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
	23	*/
	24
0f0b270f RM	25	#include <linux/slab.h>
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
0f0b270f RM	28	#include <linux/i2c.h>
	29	#include <linux/wait.h>
	30	#include <linux/delay.h>
	31	#include <linux/mutex.h>
	32	#include <linux/io.h>
	33
	34	#include "cxd2099.h"
	35
2748e76d JJ	36	/* comment this line to deactivate the cxd2099ar buffer mode */
2748e76d JJ	37	#define BUFFER_MODE 1
dd3c5d00 RM	38
dd3c5d00 RM	39	static int read_data(struct dvb_ca_en50221 ca, int slot, u8 ebuf, int ecount);
0f0b270f RM	40
	41	struct cxd {
	42	struct dvb_ca_en50221 en;
	43
	44	struct i2c_adapter *i2c;
6eb94193 RM	45	struct cxd2099_cfg cfg;
6eb94193 RM	46
0f0b270f RM	47	u8 regs[0x23];
	48	u8 lastaddress;
	49	u8 clk_reg_f;
	50	u8 clk_reg_b;
	51	int mode;
0f0b270f RM	52	int ready;
0f0b270f RM	53	int dr;
dd3c5d00	54	int write_busy;
0f0b270f RM	55	int slot_stat;
	56
	57	u8 amem[1024];
	58	int amem_read;
	59
	60	int cammode;
	61	struct mutex lock;
dd3c5d00 RM	62
	63	u8 rbuf[1028];
	64	u8 wbuf[1028];
0f0b270f RM	65	};
	66
	67	static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
	68	u8 reg, u8 data)
	69	{
	70	u8 m[2] = {reg, data};
	71	struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};
	72
	73	if (i2c_transfer(adapter, &msg, 1) != 1) {
011b2aad YT	74	dev_err(&adapter->dev,
	75	"Failed to write to I2C register %02x@%02x!\n",
	76	reg, adr);
0f0b270f RM	77	return -1;
	78	}
	79	return 0;
	80	}
	81
	82	static int i2c_write(struct i2c_adapter *adapter, u8 adr,
dd3c5d00	83	u8 *data, u16 len)
0f0b270f RM	84	{
	85	struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};
	86
	87	if (i2c_transfer(adapter, &msg, 1) != 1) {
011b2aad	88	dev_err(&adapter->dev, "Failed to write to I2C!\n");
0f0b270f RM	89	return -1;
	90	}
	91	return 0;
	92	}
	93
	94	static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
	95	u8 reg, u8 *val)
	96	{
	97	struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
6eb94193	98	.buf = &reg, .len = 1},
0f0b270f	99	{.addr = adr, .flags = I2C_M_RD,
9daf9bcc	100	.buf = val, .len = 1} };
0f0b270f RM	101
0f0b270f RM	102	if (i2c_transfer(adapter, msgs, 2) != 2) {
011b2aad	103	dev_err(&adapter->dev, "error in i2c_read_reg\n");
0f0b270f RM	104	return -1;
	105	}
	106	return 0;
	107	}
	108
	109	static int i2c_read(struct i2c_adapter *adapter, u8 adr,
dd3c5d00	110	u8 reg, u8 *data, u16 n)
0f0b270f RM	111	{
0f0b270f RM	112	struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
dd3c5d00 RM	113	.buf = &reg, .len = 1},
	114	{.addr = adr, .flags = I2C_M_RD,
	115	.buf = data, .len = n} };
0f0b270f RM	116
0f0b270f RM	117	if (i2c_transfer(adapter, msgs, 2) != 2) {
011b2aad	118	dev_err(&adapter->dev, "error in i2c_read\n");
0f0b270f RM	119	return -1;
	120	}
	121	return 0;
	122	}
	123
dd3c5d00	124	static int read_block(struct cxd ci, u8 adr, u8 data, u16 n)
0f0b270f	125	{
dd3c5d00	126	int status = 0;
0f0b270f	127
dd3c5d00 RM	128	if (ci->lastaddress != adr)
dd3c5d00 RM	129	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
0f0b270f RM	130	if (!status) {
0f0b270f RM	131	ci->lastaddress = adr;
dd3c5d00 RM	132
	133	while (n) {
	134	int len = n;
	135
	136	if (ci->cfg.max_i2c && (len > ci->cfg.max_i2c))
	137	len = ci->cfg.max_i2c;
	138	status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, len);
	139	if (status)
	140	return status;
	141	data += len;
	142	n -= len;
	143	}
0f0b270f RM	144	}
	145	return status;
	146	}
	147
	148	static int read_reg(struct cxd ci, u8 reg, u8 val)
	149	{
	150	return read_block(ci, reg, val, 1);
	151	}
	152
0f0b270f RM	153	static int read_pccard(struct cxd ci, u16 address, u8 data, u8 n)
	154	{
	155	int status;
6eb94193	156	u8 addr[3] = {2, address & 0xff, address >> 8};
0f0b270f	157
9daf9bcc	158	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
0f0b270f	159	if (!status)
6eb94193	160	status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
0f0b270f RM	161	return status;
	162	}
	163
	164	static int write_pccard(struct cxd ci, u16 address, u8 data, u8 n)
	165	{
	166	int status;
6eb94193	167	u8 addr[3] = {2, address & 0xff, address >> 8};
0f0b270f	168
9daf9bcc	169	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
0f0b270f RM	170	if (!status) {
0f0b270f RM	171	u8 buf[256] = {3};
fcf1b73d	172
03173b48 TD	173	memcpy(buf + 1, data, n);
03173b48 TD	174	status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
0f0b270f RM	175	}
	176	return status;
	177	}
	178
	179	static int read_io(struct cxd ci, u16 address, u8 val)
	180	{
	181	int status;
6eb94193	182	u8 addr[3] = {2, address & 0xff, address >> 8};
0f0b270f	183
6eb94193	184	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
0f0b270f	185	if (!status)
6eb94193	186	status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1);
0f0b270f RM	187	return status;
	188	}
	189
	190	static int write_io(struct cxd *ci, u16 address, u8 val)
	191	{
	192	int status;
6eb94193 RM	193	u8 addr[3] = {2, address & 0xff, address >> 8};
6eb94193 RM	194	u8 buf[2] = {3, val};
0f0b270f	195
6eb94193	196	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
0f0b270f	197	if (!status)
6eb94193	198	status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2);
0f0b270f RM	199	return status;
	200	}
	201
0f0b270f RM	202	static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
0f0b270f RM	203	{
dd3c5d00	204	int status = 0;
0f0b270f	205
dd3c5d00 RM	206	if (ci->lastaddress != reg)
dd3c5d00 RM	207	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
0f0b270f	208	if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
6eb94193	209	status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
dd3c5d00	210	ci->lastaddress = reg;
6eb94193	211	ci->regs[reg] = (ci->regs[reg] & (~mask)) \| val;
dd3c5d00	212	if (!status)
6eb94193	213	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]);
0f0b270f RM	214	if (reg == 0x20)
	215	ci->regs[reg] &= 0x7f;
	216	return status;
	217	}
	218
	219	static int write_reg(struct cxd *ci, u8 reg, u8 val)
	220	{
	221	return write_regm(ci, reg, val, 0xff);
	222	}
	223
	224	#ifdef BUFFER_MODE
dd3c5d00	225	static int write_block(struct cxd ci, u8 adr, u8 data, u16 n)
0f0b270f	226	{
dd3c5d00 RM	227	int status = 0;
	228	u8 *buf = ci->wbuf;
	229
	230	if (ci->lastaddress != adr)
	231	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
	232	if (status)
	233	return status;
dd3c5d00 RM	234
	235	ci->lastaddress = adr;
	236	buf[0] = 1;
	237	while (n) {
	238	int len = n;
	239
	240	if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
	241	len = ci->cfg.max_i2c - 1;
dd3c5d00 RM	242	memcpy(buf + 1, data, len);
	243	status = i2c_write(ci->i2c, ci->cfg.adr, buf, len + 1);
	244	if (status)
	245	return status;
	246	n -= len;
	247	data += len;
0f0b270f RM	248	}
	249	return status;
	250	}
	251	#endif
	252
	253	static void set_mode(struct cxd *ci, int mode)
	254	{
	255	if (mode == ci->mode)
	256	return;
	257
	258	switch (mode) {
	259	case 0x00: /* IO mem */
	260	write_regm(ci, 0x06, 0x00, 0x07);
	261	break;
	262	case 0x01: /* ATT mem */
	263	write_regm(ci, 0x06, 0x02, 0x07);
	264	break;
	265	default:
	266	break;
	267	}
	268	ci->mode = mode;
	269	}
	270
	271	static void cam_mode(struct cxd *ci, int mode)
	272	{
dd3c5d00 RM	273	u8 dummy;
dd3c5d00 RM	274
0f0b270f RM	275	if (mode == ci->cammode)
	276	return;
	277
	278	switch (mode) {
	279	case 0x00:
	280	write_regm(ci, 0x20, 0x80, 0x80);
	281	break;
	282	case 0x01:
6eb94193 RM	283	if (!ci->en.read_data)
6eb94193 RM	284	return;
dd3c5d00	285	ci->write_busy = 0;
011b2aad	286	dev_info(&ci->i2c->dev, "enable cam buffer mode\n");
dd3c5d00 RM	287	write_reg(ci, 0x0d, 0x00);
dd3c5d00 RM	288	write_reg(ci, 0x0e, 0x01);
0f0b270f	289	write_regm(ci, 0x08, 0x40, 0x40);
dd3c5d00	290	read_reg(ci, 0x12, &dummy);
0f0b270f RM	291	write_regm(ci, 0x08, 0x80, 0x80);
	292	break;
	293	default:
	294	break;
	295	}
	296	ci->cammode = mode;
	297	}
	298
0f0b270f RM	299	static int init(struct cxd *ci)
	300	{
	301	int status;
	302
	303	mutex_lock(&ci->lock);
	304	ci->mode = -1;
	305	do {
af070bd6 MCC	306	status = write_reg(ci, 0x00, 0x00);
	307	if (status < 0)
	308	break;
	309	status = write_reg(ci, 0x01, 0x00);
	310	if (status < 0)
	311	break;
	312	status = write_reg(ci, 0x02, 0x10);
	313	if (status < 0)
	314	break;
	315	status = write_reg(ci, 0x03, 0x00);
	316	if (status < 0)
	317	break;
	318	status = write_reg(ci, 0x05, 0xFF);
	319	if (status < 0)
	320	break;
	321	status = write_reg(ci, 0x06, 0x1F);
	322	if (status < 0)
	323	break;
	324	status = write_reg(ci, 0x07, 0x1F);
	325	if (status < 0)
	326	break;
	327	status = write_reg(ci, 0x08, 0x28);
	328	if (status < 0)
	329	break;
	330	status = write_reg(ci, 0x14, 0x20);
	331	if (status < 0)
	332	break;
	333
4fe130f2	334	/* TOSTRT = 8, Mode B (gated clock), falling Edge,
0907bb2c EL	335	* Serial, POL=HIGH, MSB
0907bb2c EL	336	*/
4fe130f2	337	status = write_reg(ci, 0x0A, 0xA7);
af070bd6 MCC	338	if (status < 0)
	339	break;
	340
	341	status = write_reg(ci, 0x0B, 0x33);
	342	if (status < 0)
	343	break;
	344	status = write_reg(ci, 0x0C, 0x33);
	345	if (status < 0)
	346	break;
	347
	348	status = write_regm(ci, 0x14, 0x00, 0x0F);
	349	if (status < 0)
	350	break;
	351	status = write_reg(ci, 0x15, ci->clk_reg_b);
	352	if (status < 0)
	353	break;
	354	status = write_regm(ci, 0x16, 0x00, 0x0F);
	355	if (status < 0)
	356	break;
	357	status = write_reg(ci, 0x17, ci->clk_reg_f);
	358	if (status < 0)
	359	break;
0f0b270f	360
dd3c5d00 RM	361	if (ci->cfg.clock_mode == 2) {
	362	/* bitrate2^13/ 72000 /
	363	u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
	364
6eb94193	365	if (ci->cfg.polarity) {
af070bd6 MCC	366	status = write_reg(ci, 0x09, 0x6f);
	367	if (status < 0)
	368	break;
6eb94193	369	} else {
af070bd6 MCC	370	status = write_reg(ci, 0x09, 0x6d);
	371	if (status < 0)
	372	break;
6eb94193	373	}
dd3c5d00 RM	374	status = write_reg(ci, 0x20, 0x08);
	375	if (status < 0)
	376	break;
	377	status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
	378	if (status < 0)
	379	break;
	380	status = write_reg(ci, 0x22, reg & 0xff);
	381	if (status < 0)
	382	break;
	383	} else if (ci->cfg.clock_mode == 1) {
	384	if (ci->cfg.polarity) {
	385	status = write_reg(ci, 0x09, 0x6f); /* D */
	386	if (status < 0)
	387	break;
	388	} else {
	389	status = write_reg(ci, 0x09, 0x6d);
	390	if (status < 0)
	391	break;
	392	}
af070bd6 MCC	393	status = write_reg(ci, 0x20, 0x68);
	394	if (status < 0)
	395	break;
	396	status = write_reg(ci, 0x21, 0x00);
	397	if (status < 0)
	398	break;
	399	status = write_reg(ci, 0x22, 0x02);
	400	if (status < 0)
	401	break;
6eb94193 RM	402	} else {
6eb94193 RM	403	if (ci->cfg.polarity) {
dd3c5d00	404	status = write_reg(ci, 0x09, 0x4f); /* C */
af070bd6 MCC	405	if (status < 0)
af070bd6 MCC	406	break;
6eb94193	407	} else {
af070bd6 MCC	408	status = write_reg(ci, 0x09, 0x4d);
	409	if (status < 0)
	410	break;
6eb94193	411	}
af070bd6 MCC	412	status = write_reg(ci, 0x20, 0x28);
	413	if (status < 0)
	414	break;
	415	status = write_reg(ci, 0x21, 0x00);
	416	if (status < 0)
	417	break;
	418	status = write_reg(ci, 0x22, 0x07);
	419	if (status < 0)
	420	break;
6eb94193	421	}
0f0b270f	422
af070bd6 MCC	423	status = write_regm(ci, 0x20, 0x80, 0x80);
	424	if (status < 0)
	425	break;
	426	status = write_regm(ci, 0x03, 0x02, 0x02);
	427	if (status < 0)
	428	break;
	429	status = write_reg(ci, 0x01, 0x04);
	430	if (status < 0)
	431	break;
	432	status = write_reg(ci, 0x00, 0x31);
	433	if (status < 0)
	434	break;
0f0b270f	435
6eb94193	436	/* Put TS in bypass */
af070bd6 MCC	437	status = write_regm(ci, 0x09, 0x08, 0x08);
	438	if (status < 0)
	439	break;
0f0b270f	440	ci->cammode = -1;
0f0b270f	441	cam_mode(ci, 0);
0f0b270f RM	442	} while (0);
	443	mutex_unlock(&ci->lock);
	444
	445	return 0;
	446	}
	447
0f0b270f RM	448	static int read_attribute_mem(struct dvb_ca_en50221 *ca,
	449	int slot, int address)
	450	{
	451	struct cxd *ci = ca->data;
	452	u8 val;
fcf1b73d	453
0f0b270f RM	454	mutex_lock(&ci->lock);
	455	set_mode(ci, 1);
	456	read_pccard(ci, address, &val, 1);
	457	mutex_unlock(&ci->lock);
	458	return val;
	459	}
	460
0f0b270f RM	461	static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
	462	int address, u8 value)
	463	{
	464	struct cxd *ci = ca->data;
	465
	466	mutex_lock(&ci->lock);
	467	set_mode(ci, 1);
	468	write_pccard(ci, address, &value, 1);
	469	mutex_unlock(&ci->lock);
	470	return 0;
	471	}
	472
	473	static int read_cam_control(struct dvb_ca_en50221 *ca,
	474	int slot, u8 address)
	475	{
	476	struct cxd *ci = ca->data;
	477	u8 val;
	478
	479	mutex_lock(&ci->lock);
	480	set_mode(ci, 0);
	481	read_io(ci, address, &val);
	482	mutex_unlock(&ci->lock);
	483	return val;
	484	}
	485
	486	static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
	487	u8 address, u8 value)
	488	{
	489	struct cxd *ci = ca->data;
	490
	491	mutex_lock(&ci->lock);
	492	set_mode(ci, 0);
	493	write_io(ci, address, value);
	494	mutex_unlock(&ci->lock);
	495	return 0;
	496	}
	497
	498	static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
	499	{
	500	struct cxd *ci = ca->data;
	501
dd3c5d00 RM	502	if (ci->cammode)
	503	read_data(ca, slot, ci->rbuf, 0);
	504
0f0b270f RM	505	mutex_lock(&ci->lock);
	506	cam_mode(ci, 0);
	507	write_reg(ci, 0x00, 0x21);
	508	write_reg(ci, 0x06, 0x1F);
	509	write_reg(ci, 0x00, 0x31);
	510	write_regm(ci, 0x20, 0x80, 0x80);
	511	write_reg(ci, 0x03, 0x02);
	512	ci->ready = 0;
	513	ci->mode = -1;
	514	{
	515	int i;
1f9f72f4	516
0f0b270f	517	for (i = 0; i < 100; i++) {
c3cefd3c	518	usleep_range(10000, 11000);
0f0b270f RM	519	if (ci->ready)
	520	break;
	521	}
	522	}
	523	mutex_unlock(&ci->lock);
0f0b270f RM	524	return 0;
	525	}
	526
	527	static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
	528	{
	529	struct cxd *ci = ca->data;
	530
74058c59	531	dev_info(&ci->i2c->dev, "%s\n", __func__);
dd3c5d00 RM	532	if (ci->cammode)
dd3c5d00 RM	533	read_data(ca, slot, ci->rbuf, 0);
0f0b270f	534	mutex_lock(&ci->lock);
dd3c5d00 RM	535	write_reg(ci, 0x00, 0x21);
	536	write_reg(ci, 0x06, 0x1F);
	537	msleep(300);
	538
6eb94193 RM	539	write_regm(ci, 0x09, 0x08, 0x08);
	540	write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
	541	write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
dd3c5d00	542
0f0b270f	543	ci->mode = -1;
dd3c5d00	544	ci->write_busy = 0;
0f0b270f	545	mutex_unlock(&ci->lock);
6eb94193	546	return 0;
0f0b270f RM	547	}
	548
	549	static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
	550	{
	551	struct cxd *ci = ca->data;
	552
	553	mutex_lock(&ci->lock);
	554	write_regm(ci, 0x09, 0x00, 0x08);
	555	set_mode(ci, 0);
0f0b270f	556	cam_mode(ci, 1);
0f0b270f RM	557	mutex_unlock(&ci->lock);
	558	return 0;
	559	}
	560
0f0b270f RM	561	static int campoll(struct cxd *ci)
	562	{
	563	u8 istat;
	564
	565	read_reg(ci, 0x04, &istat);
	566	if (!istat)
	567	return 0;
	568	write_reg(ci, 0x05, istat);
	569
64754837	570	if (istat & 0x40)
0f0b270f	571	ci->dr = 1;
64754837	572	if (istat & 0x20)
dd3c5d00	573	ci->write_busy = 0;
0f0b270f	574
03173b48	575	if (istat & 2) {
0f0b270f RM	576	u8 slotstat;
	577
	578	read_reg(ci, 0x01, &slotstat);
03173b48	579	if (!(2 & slotstat)) {
0f0b270f	580	if (!ci->slot_stat) {
dd3c5d00 RM	581	ci->slot_stat \|=
dd3c5d00 RM	582	DVB_CA_EN50221_POLL_CAM_PRESENT;
0f0b270f RM	583	write_regm(ci, 0x03, 0x08, 0x08);
	584	}
	585
	586	} else {
	587	if (ci->slot_stat) {
	588	ci->slot_stat = 0;
	589	write_regm(ci, 0x03, 0x00, 0x08);
011b2aad	590	dev_info(&ci->i2c->dev, "NO CAM\n");
0f0b270f RM	591	ci->ready = 0;
	592	}
	593	}
dd3c5d00 RM	594	if ((istat & 8) &&
dd3c5d00 RM	595	(ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT)) {
0f0b270f RM	596	ci->ready = 1;
0f0b270f RM	597	ci->slot_stat \|= DVB_CA_EN50221_POLL_CAM_READY;
0f0b270f RM	598	}
	599	}
	600	return 0;
	601	}
	602
0f0b270f RM	603	static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
	604	{
	605	struct cxd *ci = ca->data;
	606	u8 slotstat;
	607
	608	mutex_lock(&ci->lock);
	609	campoll(ci);
	610	read_reg(ci, 0x01, &slotstat);
	611	mutex_unlock(&ci->lock);
	612
	613	return ci->slot_stat;
	614	}
	615
0f0b270f RM	616	static int read_data(struct dvb_ca_en50221 ca, int slot, u8 ebuf, int ecount)
	617	{
	618	struct cxd *ci = ca->data;
	619	u8 msb, lsb;
	620	u16 len;
	621
	622	mutex_lock(&ci->lock);
	623	campoll(ci);
	624	mutex_unlock(&ci->lock);
	625
0f0b270f RM	626	if (!ci->dr)
	627	return 0;
	628
	629	mutex_lock(&ci->lock);
	630	read_reg(ci, 0x0f, &msb);
	631	read_reg(ci, 0x10, &lsb);
dd3c5d00 RM	632	len = ((u16)msb << 8) \| lsb;
	633	if (len > ecount \|\| len < 2) {
	634	/* read it anyway or cxd may hang */
	635	read_block(ci, 0x12, ci->rbuf, len);
	636	mutex_unlock(&ci->lock);
	637	return -EIO;
	638	}
0f0b270f RM	639	read_block(ci, 0x12, ebuf, len);
	640	ci->dr = 0;
	641	mutex_unlock(&ci->lock);
0f0b270f RM	642	return len;
	643	}
	644
dd3c5d00 RM	645	#ifdef BUFFER_MODE
dd3c5d00 RM	646
0f0b270f RM	647	static int write_data(struct dvb_ca_en50221 ca, int slot, u8 ebuf, int ecount)
	648	{
	649	struct cxd *ci = ca->data;
	650
dd3c5d00 RM	651	if (ci->write_busy)
dd3c5d00 RM	652	return -EAGAIN;
0f0b270f	653	mutex_lock(&ci->lock);
03173b48 TD	654	write_reg(ci, 0x0d, ecount >> 8);
03173b48 TD	655	write_reg(ci, 0x0e, ecount & 0xff);
0f0b270f	656	write_block(ci, 0x11, ebuf, ecount);
dd3c5d00	657	ci->write_busy = 1;
0f0b270f RM	658	mutex_unlock(&ci->lock);
	659	return ecount;
	660	}
	661	#endif
	662
	663	static struct dvb_ca_en50221 en_templ = {
	664	.read_attribute_mem = read_attribute_mem,
	665	.write_attribute_mem = write_attribute_mem,
	666	.read_cam_control = read_cam_control,
	667	.write_cam_control = write_cam_control,
	668	.slot_reset = slot_reset,
	669	.slot_shutdown = slot_shutdown,
	670	.slot_ts_enable = slot_ts_enable,
	671	.poll_slot_status = poll_slot_status,
	672	#ifdef BUFFER_MODE
	673	.read_data = read_data,
	674	.write_data = write_data,
	675	#endif
	676
	677	};
	678
6eb94193 RM	679	struct dvb_ca_en50221 cxd2099_attach(struct cxd2099_cfg cfg,
6eb94193 RM	680	void *priv,
0f0b270f RM	681	struct i2c_adapter *i2c)
0f0b270f RM	682	{
4aff355c	683	struct cxd *ci;
0f0b270f RM	684	u8 val;
0f0b270f RM	685
9daf9bcc	686	if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) {
011b2aad	687	dev_info(&i2c->dev, "No CXD2099 detected at %02x\n", cfg->adr);
4aff355c	688	return NULL;
0f0b270f RM	689	}
0f0b270f RM	690
783dd92b	691	ci = kzalloc(sizeof(*ci), GFP_KERNEL);
0f0b270f	692	if (!ci)
4aff355c	693	return NULL;
0f0b270f RM	694
0f0b270f RM	695	mutex_init(&ci->lock);
8d9b2584	696	ci->cfg = *cfg;
0f0b270f	697	ci->i2c = i2c;
0f0b270f RM	698	ci->lastaddress = 0xff;
	699	ci->clk_reg_b = 0x4a;
	700	ci->clk_reg_f = 0x1b;
0f0b270f	701
8d9b2584	702	ci->en = en_templ;
0f0b270f RM	703	ci->en.data = ci;
0f0b270f RM	704	init(ci);
011b2aad	705	dev_info(&i2c->dev, "Attached CXD2099AR at %02x\n", ci->cfg.adr);
0f0b270f RM	706	return &ci->en;
	707	}
	708	EXPORT_SYMBOL(cxd2099_attach);
	709
	710	MODULE_DESCRIPTION("cxd2099");
6eb94193	711	MODULE_AUTHOR("Ralph Metzler");
0f0b270f	712	MODULE_LICENSE("GPL");