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717f4a5f MM |
1 | /*************************************************************************** |
2 | * Copyright (C) 2006-2010 by Marin Mitov * | |
3 | * mitov@issp.bas.bg * | |
4 | * * | |
5 | * This program is free software; you can redistribute it and/or modify * | |
6 | * it under the terms of the GNU General Public License as published by * | |
7 | * the Free Software Foundation; either version 2 of the License, or * | |
8 | * (at your option) any later version. * | |
9 | * * | |
10 | * This program is distributed in the hope that it will be useful, * | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
13 | * GNU General Public License for more details. * | |
14 | * * | |
15 | * You should have received a copy of the GNU General Public License * | |
16 | * along with this program; if not, write to the * | |
17 | * Free Software Foundation, Inc., * | |
18 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * | |
19 | ***************************************************************************/ | |
20 | ||
99c97852 | 21 | #include <linux/module.h> |
d42bffb8 MM |
22 | #include <linux/version.h> |
23 | #include <linux/stringify.h> | |
7ec21181 | 24 | #include <linux/delay.h> |
d42bffb8 | 25 | #include <linux/kthread.h> |
dac95cb8 | 26 | #include <linux/slab.h> |
a57941c2 MM |
27 | #include <media/v4l2-dev.h> |
28 | #include <media/v4l2-ioctl.h> | |
0dcb953a | 29 | #include <media/v4l2-common.h> |
8ded351a | 30 | #include <media/videobuf2-dma-contig.h> |
d42bffb8 MM |
31 | |
32 | #include "dt3155v4l.h" | |
d42bffb8 | 33 | |
d42bffb8 MM |
34 | #define DT3155_DEVICE_ID 0x1223 |
35 | ||
a57941c2 MM |
36 | /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */ |
37 | #define DT3155_CHUNK_SIZE (1U << 22) | |
38 | ||
39 | #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN) | |
40 | ||
41 | #define DT3155_BUF_SIZE (768 * 576) | |
42 | ||
8ded351a MM |
43 | #ifdef CONFIG_DT3155_STREAMING |
44 | #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING | |
45 | #else | |
46 | #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE | |
47 | #endif | |
48 | ||
d42bffb8 MM |
49 | /* global initializers (for all boards) */ |
50 | #ifdef CONFIG_DT3155_CCIR | |
51 | static const u8 csr2_init = VT_50HZ; | |
52 | #define DT3155_CURRENT_NORM V4L2_STD_625_50 | |
53 | static const unsigned int img_width = 768; | |
54 | static const unsigned int img_height = 576; | |
55 | static const unsigned int frames_per_sec = 25; | |
56 | static const struct v4l2_fmtdesc frame_std[] = { | |
57 | { | |
58 | .index = 0, | |
59 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
60 | .flags = 0, | |
61 | .description = "CCIR/50Hz 8 bits gray", | |
62 | .pixelformat = V4L2_PIX_FMT_GREY, | |
63 | }, | |
64 | }; | |
65 | #else | |
66 | static const u8 csr2_init = VT_60HZ; | |
67 | #define DT3155_CURRENT_NORM V4L2_STD_525_60 | |
68 | static const unsigned int img_width = 640; | |
69 | static const unsigned int img_height = 480; | |
70 | static const unsigned int frames_per_sec = 30; | |
71 | static const struct v4l2_fmtdesc frame_std[] = { | |
72 | { | |
73 | .index = 0, | |
74 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
75 | .flags = 0, | |
76 | .description = "RS-170/60Hz 8 bits gray", | |
77 | .pixelformat = V4L2_PIX_FMT_GREY, | |
78 | }, | |
79 | }; | |
80 | #endif | |
81 | ||
82 | #define NUM_OF_FORMATS ARRAY_SIZE(frame_std) | |
83 | ||
84 | static u8 config_init = ACQ_MODE_EVEN; | |
85 | ||
86 | /** | |
87 | * read_i2c_reg - reads an internal i2c register | |
88 | * | |
89 | * @addr: dt3155 mmio base address | |
90 | * @index: index (internal address) of register to read | |
91 | * @data: pointer to byte the read data will be placed in | |
92 | * | |
93 | * returns: zero on success or error code | |
94 | * | |
95 | * This function starts reading the specified (by index) register | |
96 | * and busy waits for the process to finish. The result is placed | |
97 | * in a byte pointed by data. | |
98 | */ | |
99 | static int | |
2342df0e | 100 | read_i2c_reg(void __iomem *addr, u8 index, u8 *data) |
d42bffb8 MM |
101 | { |
102 | u32 tmp = index; | |
103 | ||
104 | iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2); | |
105 | mmiowb(); | |
106 | udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */ | |
c94a2e47 HS |
107 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
108 | return -EIO; /* error: NEW_CYCLE not cleared */ | |
d42bffb8 MM |
109 | tmp = ioread32(addr + IIC_CSR1); |
110 | if (tmp & DIRECT_ABORT) { | |
d42bffb8 MM |
111 | /* reset DIRECT_ABORT bit */ |
112 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
c94a2e47 | 113 | return -EIO; /* error: DIRECT_ABORT set */ |
d42bffb8 MM |
114 | } |
115 | *data = tmp>>24; | |
116 | return 0; | |
117 | } | |
118 | ||
119 | /** | |
120 | * write_i2c_reg - writes to an internal i2c register | |
121 | * | |
122 | * @addr: dt3155 mmio base address | |
123 | * @index: index (internal address) of register to read | |
124 | * @data: data to be written | |
125 | * | |
126 | * returns: zero on success or error code | |
127 | * | |
128 | * This function starts writting the specified (by index) register | |
129 | * and busy waits for the process to finish. | |
130 | */ | |
131 | static int | |
2342df0e | 132 | write_i2c_reg(void __iomem *addr, u8 index, u8 data) |
d42bffb8 MM |
133 | { |
134 | u32 tmp = index; | |
135 | ||
136 | iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2); | |
137 | mmiowb(); | |
138 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ | |
c94a2e47 HS |
139 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
140 | return -EIO; /* error: NEW_CYCLE not cleared */ | |
d42bffb8 | 141 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { |
d42bffb8 MM |
142 | /* reset DIRECT_ABORT bit */ |
143 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
c94a2e47 | 144 | return -EIO; /* error: DIRECT_ABORT set */ |
d42bffb8 MM |
145 | } |
146 | return 0; | |
147 | } | |
148 | ||
149 | /** | |
150 | * write_i2c_reg_nowait - writes to an internal i2c register | |
151 | * | |
152 | * @addr: dt3155 mmio base address | |
153 | * @index: index (internal address) of register to read | |
154 | * @data: data to be written | |
155 | * | |
156 | * This function starts writting the specified (by index) register | |
157 | * and then returns. | |
158 | */ | |
2342df0e | 159 | static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data) |
d42bffb8 MM |
160 | { |
161 | u32 tmp = index; | |
162 | ||
163 | iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2); | |
164 | mmiowb(); | |
165 | } | |
166 | ||
167 | /** | |
168 | * wait_i2c_reg - waits the read/write to finish | |
169 | * | |
170 | * @addr: dt3155 mmio base address | |
171 | * | |
172 | * returns: zero on success or error code | |
173 | * | |
174 | * This function waits reading/writting to finish. | |
175 | */ | |
2342df0e | 176 | static int wait_i2c_reg(void __iomem *addr) |
d42bffb8 MM |
177 | { |
178 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) | |
179 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ | |
c94a2e47 HS |
180 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
181 | return -EIO; /* error: NEW_CYCLE not cleared */ | |
d42bffb8 | 182 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { |
d42bffb8 MM |
183 | /* reset DIRECT_ABORT bit */ |
184 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
c94a2e47 | 185 | return -EIO; /* error: DIRECT_ABORT set */ |
d42bffb8 MM |
186 | } |
187 | return 0; | |
188 | } | |
189 | ||
d42bffb8 MM |
190 | static int |
191 | dt3155_start_acq(struct dt3155_priv *pd) | |
192 | { | |
8ded351a | 193 | struct vb2_buffer *vb = pd->curr_buf; |
d42bffb8 MM |
194 | dma_addr_t dma_addr; |
195 | ||
1f28291c | 196 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); |
d42bffb8 | 197 | iowrite32(dma_addr, pd->regs + EVEN_DMA_START); |
8ded351a MM |
198 | iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START); |
199 | iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE); | |
200 | iowrite32(img_width, pd->regs + ODD_DMA_STRIDE); | |
d42bffb8 MM |
201 | /* enable interrupts, clear all irq flags */ |
202 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | | |
203 | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); | |
204 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | | |
205 | FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD, | |
206 | pd->regs + CSR1); | |
207 | wait_i2c_reg(pd->regs); | |
208 | write_i2c_reg(pd->regs, CONFIG, pd->config); | |
209 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); | |
210 | write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); | |
211 | ||
212 | /* start the board */ | |
213 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); | |
214 | return 0; /* success */ | |
215 | } | |
216 | ||
8ded351a MM |
217 | /* |
218 | * driver-specific callbacks (vb2_ops) | |
219 | */ | |
d42bffb8 | 220 | static int |
527f18be DC |
221 | dt3155_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt, |
222 | unsigned int *num_buffers, unsigned int *num_planes, | |
223 | unsigned int sizes[], void *alloc_ctxs[]) | |
224 | ||
8ded351a MM |
225 | { |
226 | struct dt3155_priv *pd = vb2_get_drv_priv(q); | |
227 | void *ret; | |
228 | ||
229 | if (*num_buffers == 0) | |
230 | *num_buffers = 1; | |
231 | *num_planes = 1; | |
232 | sizes[0] = img_width * img_height; | |
233 | if (pd->q->alloc_ctx[0]) | |
234 | return 0; | |
235 | ret = vb2_dma_contig_init_ctx(&pd->pdev->dev); | |
236 | if (IS_ERR(ret)) | |
237 | return PTR_ERR(ret); | |
238 | pd->q->alloc_ctx[0] = ret; | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static void | |
243 | dt3155_wait_prepare(struct vb2_queue *q) | |
d42bffb8 | 244 | { |
8ded351a | 245 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
d42bffb8 | 246 | |
8ded351a MM |
247 | mutex_unlock(pd->vdev->lock); |
248 | } | |
d42bffb8 | 249 | |
8ded351a MM |
250 | static void |
251 | dt3155_wait_finish(struct vb2_queue *q) | |
252 | { | |
253 | struct dt3155_priv *pd = vb2_get_drv_priv(q); | |
254 | ||
255 | mutex_lock(pd->vdev->lock); | |
d42bffb8 MM |
256 | } |
257 | ||
d42bffb8 | 258 | static int |
8ded351a | 259 | dt3155_buf_prepare(struct vb2_buffer *vb) |
d42bffb8 | 260 | { |
8ded351a | 261 | vb2_set_plane_payload(vb, 0, img_width * img_height); |
d42bffb8 MM |
262 | return 0; |
263 | } | |
264 | ||
e37559b2 | 265 | static void |
8ded351a | 266 | dt3155_stop_streaming(struct vb2_queue *q) |
d42bffb8 | 267 | { |
8ded351a MM |
268 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
269 | struct vb2_buffer *vb; | |
270 | ||
271 | spin_lock_irq(&pd->lock); | |
272 | while (!list_empty(&pd->dmaq)) { | |
273 | vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry); | |
274 | list_del(&vb->done_entry); | |
275 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); | |
276 | } | |
277 | spin_unlock_irq(&pd->lock); | |
278 | msleep(45); /* irq hendler will stop the hardware */ | |
d42bffb8 MM |
279 | } |
280 | ||
d42bffb8 | 281 | static void |
8ded351a | 282 | dt3155_buf_queue(struct vb2_buffer *vb) |
d42bffb8 | 283 | { |
8ded351a MM |
284 | struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); |
285 | ||
286 | /* pd->q->streaming = 1 when dt3155_buf_queue() is invoked */ | |
287 | spin_lock_irq(&pd->lock); | |
288 | if (pd->curr_buf) | |
289 | list_add_tail(&vb->done_entry, &pd->dmaq); | |
290 | else { | |
291 | pd->curr_buf = vb; | |
292 | dt3155_start_acq(pd); | |
293 | } | |
294 | spin_unlock_irq(&pd->lock); | |
d42bffb8 | 295 | } |
8ded351a MM |
296 | /* |
297 | * end driver-specific callbacks | |
298 | */ | |
d42bffb8 | 299 | |
5ae7437e | 300 | static const struct vb2_ops q_ops = { |
8ded351a MM |
301 | .queue_setup = dt3155_queue_setup, |
302 | .wait_prepare = dt3155_wait_prepare, | |
303 | .wait_finish = dt3155_wait_finish, | |
d42bffb8 | 304 | .buf_prepare = dt3155_buf_prepare, |
8ded351a | 305 | .stop_streaming = dt3155_stop_streaming, |
d42bffb8 | 306 | .buf_queue = dt3155_buf_queue, |
d42bffb8 MM |
307 | }; |
308 | ||
309 | static irqreturn_t | |
310 | dt3155_irq_handler_even(int irq, void *dev_id) | |
311 | { | |
312 | struct dt3155_priv *ipd = dev_id; | |
8ded351a | 313 | struct vb2_buffer *ivb; |
d42bffb8 MM |
314 | dma_addr_t dma_addr; |
315 | u32 tmp; | |
316 | ||
317 | tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD); | |
318 | if (!tmp) | |
319 | return IRQ_NONE; /* not our irq */ | |
320 | if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) { | |
321 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START, | |
322 | ipd->regs + INT_CSR); | |
323 | ipd->field_count++; | |
324 | return IRQ_HANDLED; /* start of field irq */ | |
325 | } | |
c94a2e47 | 326 | if ((tmp & FLD_START) && (tmp & FLD_END_ODD)) |
5ba321cf | 327 | ipd->stats.start_before_end++; |
d42bffb8 MM |
328 | /* check for corrupted fields */ |
329 | /* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */ | |
330 | /* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */ | |
331 | tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD); | |
332 | if (tmp) { | |
c94a2e47 | 333 | ipd->stats.corrupted_fields++; |
d42bffb8 MM |
334 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
335 | FLD_DN_ODD | FLD_DN_EVEN | | |
336 | CAP_CONT_EVEN | CAP_CONT_ODD, | |
337 | ipd->regs + CSR1); | |
338 | mmiowb(); | |
339 | } | |
340 | ||
341 | spin_lock(&ipd->lock); | |
8ded351a | 342 | if (ipd->curr_buf) { |
0dcb953a | 343 | v4l2_get_timestamp(&ipd->curr_buf->v4l2_buf.timestamp); |
8ded351a MM |
344 | ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1; |
345 | vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE); | |
346 | } | |
347 | ||
348 | if (!ipd->q->streaming || list_empty(&ipd->dmaq)) | |
d42bffb8 | 349 | goto stop_dma; |
8ded351a MM |
350 | ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry); |
351 | list_del(&ivb->done_entry); | |
352 | ipd->curr_buf = ivb; | |
1f28291c | 353 | dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0); |
d42bffb8 | 354 | iowrite32(dma_addr, ipd->regs + EVEN_DMA_START); |
8ded351a MM |
355 | iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START); |
356 | iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE); | |
357 | iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE); | |
d42bffb8 MM |
358 | mmiowb(); |
359 | /* enable interrupts, clear all irq flags */ | |
360 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | | |
361 | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); | |
362 | spin_unlock(&ipd->lock); | |
363 | return IRQ_HANDLED; | |
364 | ||
365 | stop_dma: | |
366 | ipd->curr_buf = NULL; | |
367 | /* stop the board */ | |
368 | write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2); | |
8ded351a MM |
369 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
370 | FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1); | |
d42bffb8 MM |
371 | /* disable interrupts, clear all irq flags */ |
372 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); | |
373 | spin_unlock(&ipd->lock); | |
374 | return IRQ_HANDLED; | |
375 | } | |
376 | ||
d42bffb8 MM |
377 | static int |
378 | dt3155_open(struct file *filp) | |
379 | { | |
380 | int ret = 0; | |
381 | struct dt3155_priv *pd = video_drvdata(filp); | |
382 | ||
0d0c1596 HV |
383 | if (mutex_lock_interruptible(&pd->mux)) |
384 | return -ERESTARTSYS; | |
d42bffb8 | 385 | if (!pd->users) { |
8ded351a MM |
386 | pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL); |
387 | if (!pd->q) { | |
d42bffb8 MM |
388 | ret = -ENOMEM; |
389 | goto err_alloc_queue; | |
390 | } | |
8ded351a | 391 | pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
ade48681 | 392 | pd->q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; |
8ded351a MM |
393 | pd->q->io_modes = VB2_READ | VB2_MMAP; |
394 | pd->q->ops = &q_ops; | |
395 | pd->q->mem_ops = &vb2_dma_contig_memops; | |
396 | pd->q->drv_priv = pd; | |
397 | pd->curr_buf = NULL; | |
398 | pd->field_count = 0; | |
067d8513 MCC |
399 | ret = vb2_queue_init(pd->q); |
400 | if (ret < 0) | |
228b791b | 401 | goto err_request_irq; |
8ded351a MM |
402 | INIT_LIST_HEAD(&pd->dmaq); |
403 | spin_lock_init(&pd->lock); | |
d42bffb8 MM |
404 | /* disable all irqs, clear all irq flags */ |
405 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, | |
406 | pd->regs + INT_CSR); | |
17078647 | 407 | ret = request_irq(pd->pdev->irq, dt3155_irq_handler_even, |
d42bffb8 | 408 | IRQF_SHARED, DT3155_NAME, pd); |
c94a2e47 | 409 | if (ret) |
d42bffb8 | 410 | goto err_request_irq; |
d42bffb8 MM |
411 | } |
412 | pd->users++; | |
228b791b | 413 | mutex_unlock(&pd->mux); |
8ded351a | 414 | return 0; /* success */ |
d42bffb8 | 415 | err_request_irq: |
8ded351a MM |
416 | kfree(pd->q); |
417 | pd->q = NULL; | |
d42bffb8 | 418 | err_alloc_queue: |
0d0c1596 | 419 | mutex_unlock(&pd->mux); |
d42bffb8 MM |
420 | return ret; |
421 | } | |
422 | ||
423 | static int | |
424 | dt3155_release(struct file *filp) | |
425 | { | |
426 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 427 | |
0d0c1596 | 428 | mutex_lock(&pd->mux); |
d42bffb8 MM |
429 | pd->users--; |
430 | BUG_ON(pd->users < 0); | |
d42bffb8 | 431 | if (!pd->users) { |
8ded351a | 432 | vb2_queue_release(pd->q); |
d42bffb8 | 433 | free_irq(pd->pdev->irq, pd); |
8ded351a MM |
434 | if (pd->q->alloc_ctx[0]) |
435 | vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]); | |
436 | kfree(pd->q); | |
437 | pd->q = NULL; | |
d42bffb8 | 438 | } |
0d0c1596 | 439 | mutex_unlock(&pd->mux); |
8ded351a | 440 | return 0; |
d42bffb8 MM |
441 | } |
442 | ||
443 | static ssize_t | |
444 | dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff) | |
445 | { | |
446 | struct dt3155_priv *pd = video_drvdata(filp); | |
0d0c1596 | 447 | ssize_t res; |
8ded351a | 448 | |
0d0c1596 HV |
449 | if (mutex_lock_interruptible(&pd->mux)) |
450 | return -ERESTARTSYS; | |
451 | res = vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK); | |
452 | mutex_unlock(&pd->mux); | |
453 | return res; | |
d42bffb8 MM |
454 | } |
455 | ||
456 | static unsigned int | |
457 | dt3155_poll(struct file *filp, struct poll_table_struct *polltbl) | |
458 | { | |
459 | struct dt3155_priv *pd = video_drvdata(filp); | |
0d0c1596 | 460 | unsigned int res; |
d42bffb8 | 461 | |
0d0c1596 HV |
462 | mutex_lock(&pd->mux); |
463 | res = vb2_poll(pd->q, filp, polltbl); | |
464 | mutex_unlock(&pd->mux); | |
465 | return res; | |
d42bffb8 MM |
466 | } |
467 | ||
468 | static int | |
469 | dt3155_mmap(struct file *filp, struct vm_area_struct *vma) | |
470 | { | |
471 | struct dt3155_priv *pd = video_drvdata(filp); | |
0d0c1596 | 472 | int res; |
d42bffb8 | 473 | |
0d0c1596 HV |
474 | if (mutex_lock_interruptible(&pd->mux)) |
475 | return -ERESTARTSYS; | |
476 | res = vb2_mmap(pd->q, vma); | |
477 | mutex_unlock(&pd->mux); | |
478 | return res; | |
d42bffb8 MM |
479 | } |
480 | ||
481 | static const struct v4l2_file_operations dt3155_fops = { | |
482 | .owner = THIS_MODULE, | |
483 | .open = dt3155_open, | |
484 | .release = dt3155_release, | |
485 | .read = dt3155_read, | |
486 | .poll = dt3155_poll, | |
487 | .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ | |
488 | .mmap = dt3155_mmap, | |
489 | }; | |
490 | ||
491 | static int | |
492 | dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type) | |
493 | { | |
494 | struct dt3155_priv *pd = video_drvdata(filp); | |
8ded351a MM |
495 | |
496 | return vb2_streamon(pd->q, type); | |
d42bffb8 MM |
497 | } |
498 | ||
499 | static int | |
500 | dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type) | |
501 | { | |
502 | struct dt3155_priv *pd = video_drvdata(filp); | |
8ded351a MM |
503 | |
504 | return vb2_streamoff(pd->q, type); | |
d42bffb8 MM |
505 | } |
506 | ||
507 | static int | |
508 | dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap) | |
509 | { | |
510 | struct dt3155_priv *pd = video_drvdata(filp); | |
511 | ||
512 | strcpy(cap->driver, DT3155_NAME); | |
513 | strcpy(cap->card, DT3155_NAME " frame grabber"); | |
514 | sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev)); | |
515 | cap->version = | |
516 | KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT); | |
517 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | | |
8ded351a | 518 | DT3155_CAPTURE_METHOD; |
d42bffb8 MM |
519 | return 0; |
520 | } | |
521 | ||
522 | static int | |
523 | dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f) | |
524 | { | |
525 | if (f->index >= NUM_OF_FORMATS) | |
526 | return -EINVAL; | |
527 | *f = frame_std[f->index]; | |
528 | return 0; | |
529 | } | |
530 | ||
531 | static int | |
532 | dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) | |
533 | { | |
534 | if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
535 | return -EINVAL; | |
536 | f->fmt.pix.width = img_width; | |
537 | f->fmt.pix.height = img_height; | |
538 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY; | |
539 | f->fmt.pix.field = V4L2_FIELD_NONE; | |
540 | f->fmt.pix.bytesperline = f->fmt.pix.width; | |
541 | f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height; | |
542 | f->fmt.pix.colorspace = 0; | |
543 | f->fmt.pix.priv = 0; | |
544 | return 0; | |
545 | } | |
546 | ||
547 | static int | |
548 | dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) | |
549 | { | |
550 | if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
551 | return -EINVAL; | |
552 | if (f->fmt.pix.width == img_width && | |
553 | f->fmt.pix.height == img_height && | |
554 | f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY && | |
555 | f->fmt.pix.field == V4L2_FIELD_NONE && | |
556 | f->fmt.pix.bytesperline == f->fmt.pix.width && | |
557 | f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height) | |
558 | return 0; | |
559 | else | |
560 | return -EINVAL; | |
561 | } | |
562 | ||
563 | static int | |
564 | dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) | |
565 | { | |
8ded351a | 566 | return dt3155_ioc_g_fmt_vid_cap(filp, p, f); |
d42bffb8 MM |
567 | } |
568 | ||
569 | static int | |
570 | dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b) | |
571 | { | |
572 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 573 | |
8ded351a | 574 | return vb2_reqbufs(pd->q, b); |
d42bffb8 MM |
575 | } |
576 | ||
577 | static int | |
578 | dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b) | |
579 | { | |
580 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 581 | |
8ded351a | 582 | return vb2_querybuf(pd->q, b); |
d42bffb8 MM |
583 | } |
584 | ||
585 | static int | |
586 | dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b) | |
587 | { | |
588 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 589 | |
8ded351a | 590 | return vb2_qbuf(pd->q, b); |
d42bffb8 MM |
591 | } |
592 | ||
593 | static int | |
594 | dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b) | |
595 | { | |
596 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 597 | |
8ded351a | 598 | return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK); |
d42bffb8 MM |
599 | } |
600 | ||
601 | static int | |
602 | dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm) | |
603 | { | |
604 | *norm = DT3155_CURRENT_NORM; | |
605 | return 0; | |
606 | } | |
607 | ||
608 | static int | |
609 | dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm) | |
610 | { | |
611 | *norm = DT3155_CURRENT_NORM; | |
612 | return 0; | |
613 | } | |
614 | ||
615 | static int | |
314527ac | 616 | dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id norm) |
d42bffb8 | 617 | { |
314527ac | 618 | if (norm & DT3155_CURRENT_NORM) |
d42bffb8 MM |
619 | return 0; |
620 | return -EINVAL; | |
621 | } | |
622 | ||
623 | static int | |
624 | dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input) | |
625 | { | |
626 | if (input->index) | |
627 | return -EINVAL; | |
628 | strcpy(input->name, "Coax in"); | |
629 | input->type = V4L2_INPUT_TYPE_CAMERA; | |
fdd2d934 MM |
630 | /* |
631 | * FIXME: input->std = 0 according to v4l2 API | |
632 | * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD | |
633 | * should return -EINVAL | |
634 | */ | |
635 | input->std = DT3155_CURRENT_NORM; | |
d42bffb8 MM |
636 | input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */ |
637 | return 0; | |
638 | } | |
639 | ||
640 | static int | |
641 | dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i) | |
642 | { | |
643 | *i = 0; | |
644 | return 0; | |
645 | } | |
646 | ||
647 | static int | |
648 | dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i) | |
649 | { | |
650 | if (i) | |
651 | return -EINVAL; | |
652 | return 0; | |
653 | } | |
654 | ||
655 | static int | |
656 | dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms) | |
657 | { | |
658 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
659 | return -EINVAL; | |
660 | parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; | |
661 | parms->parm.capture.capturemode = 0; | |
662 | parms->parm.capture.timeperframe.numerator = 1001; | |
663 | parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000; | |
664 | parms->parm.capture.extendedmode = 0; | |
fdd2d934 | 665 | parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */ |
d42bffb8 MM |
666 | return 0; |
667 | } | |
668 | ||
669 | static int | |
670 | dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms) | |
671 | { | |
672 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
673 | return -EINVAL; | |
674 | parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; | |
675 | parms->parm.capture.capturemode = 0; | |
676 | parms->parm.capture.timeperframe.numerator = 1001; | |
677 | parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000; | |
678 | parms->parm.capture.extendedmode = 0; | |
fdd2d934 | 679 | parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */ |
d42bffb8 MM |
680 | return 0; |
681 | } | |
682 | ||
683 | static const struct v4l2_ioctl_ops dt3155_ioctl_ops = { | |
684 | .vidioc_streamon = dt3155_ioc_streamon, | |
685 | .vidioc_streamoff = dt3155_ioc_streamoff, | |
686 | .vidioc_querycap = dt3155_ioc_querycap, | |
687 | /* | |
688 | .vidioc_g_priority = dt3155_ioc_g_priority, | |
689 | .vidioc_s_priority = dt3155_ioc_s_priority, | |
690 | */ | |
691 | .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap, | |
692 | .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap, | |
693 | .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap, | |
694 | .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap, | |
695 | .vidioc_reqbufs = dt3155_ioc_reqbufs, | |
696 | .vidioc_querybuf = dt3155_ioc_querybuf, | |
697 | .vidioc_qbuf = dt3155_ioc_qbuf, | |
698 | .vidioc_dqbuf = dt3155_ioc_dqbuf, | |
699 | .vidioc_querystd = dt3155_ioc_querystd, | |
700 | .vidioc_g_std = dt3155_ioc_g_std, | |
701 | .vidioc_s_std = dt3155_ioc_s_std, | |
702 | .vidioc_enum_input = dt3155_ioc_enum_input, | |
703 | .vidioc_g_input = dt3155_ioc_g_input, | |
704 | .vidioc_s_input = dt3155_ioc_s_input, | |
705 | /* | |
706 | .vidioc_queryctrl = dt3155_ioc_queryctrl, | |
707 | .vidioc_g_ctrl = dt3155_ioc_g_ctrl, | |
708 | .vidioc_s_ctrl = dt3155_ioc_s_ctrl, | |
709 | .vidioc_querymenu = dt3155_ioc_querymenu, | |
710 | .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls, | |
711 | .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls, | |
712 | */ | |
713 | .vidioc_g_parm = dt3155_ioc_g_parm, | |
714 | .vidioc_s_parm = dt3155_ioc_s_parm, | |
715 | /* | |
716 | .vidioc_cropcap = dt3155_ioc_cropcap, | |
717 | .vidioc_g_crop = dt3155_ioc_g_crop, | |
718 | .vidioc_s_crop = dt3155_ioc_s_crop, | |
719 | .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes, | |
720 | .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals, | |
d42bffb8 MM |
721 | */ |
722 | }; | |
723 | ||
2a91a6d1 | 724 | static int |
8ded351a | 725 | dt3155_init_board(struct pci_dev *pdev) |
d42bffb8 | 726 | { |
8ded351a | 727 | struct dt3155_priv *pd = pci_get_drvdata(pdev); |
a57941c2 MM |
728 | void *buf_cpu; |
729 | dma_addr_t buf_dma; | |
d42bffb8 MM |
730 | int i; |
731 | u8 tmp; | |
a57941c2 | 732 | |
8ded351a | 733 | pci_set_master(pdev); /* dt3155 needs it */ |
d42bffb8 MM |
734 | |
735 | /* resetting the adapter */ | |
736 | iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN, | |
737 | pd->regs + CSR1); | |
738 | mmiowb(); | |
8ded351a | 739 | msleep(20); |
d42bffb8 MM |
740 | |
741 | /* initializing adaper registers */ | |
742 | iowrite32(FIFO_EN | SRST, pd->regs + CSR1); | |
743 | mmiowb(); | |
744 | iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT); | |
745 | iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT); | |
746 | iowrite32(0x00000020, pd->regs + FIFO_TRIGER); | |
747 | iowrite32(0x00000103, pd->regs + XFER_MODE); | |
748 | iowrite32(0, pd->regs + RETRY_WAIT_CNT); | |
749 | iowrite32(0, pd->regs + INT_CSR); | |
750 | iowrite32(1, pd->regs + EVEN_FLD_MASK); | |
751 | iowrite32(1, pd->regs + ODD_FLD_MASK); | |
752 | iowrite32(0, pd->regs + MASK_LENGTH); | |
753 | iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT); | |
754 | iowrite32(0x01010101, pd->regs + IIC_CLK_DUR); | |
755 | mmiowb(); | |
756 | ||
757 | /* verifying that we have a DT3155 board (not just a SAA7116 chip) */ | |
758 | read_i2c_reg(pd->regs, DT_ID, &tmp); | |
759 | if (tmp != DT3155_ID) | |
760 | return -ENODEV; | |
761 | ||
762 | /* initialize AD LUT */ | |
763 | write_i2c_reg(pd->regs, AD_ADDR, 0); | |
764 | for (i = 0; i < 256; i++) | |
765 | write_i2c_reg(pd->regs, AD_LUT, i); | |
766 | ||
767 | /* initialize ADC references */ | |
768 | /* FIXME: pos_ref & neg_ref depend on VT_50HZ */ | |
769 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); | |
770 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); | |
771 | write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF); | |
772 | write_i2c_reg(pd->regs, AD_CMD, 34); | |
773 | write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF); | |
774 | write_i2c_reg(pd->regs, AD_CMD, 0); | |
775 | ||
776 | /* initialize PM LUT */ | |
777 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM); | |
778 | for (i = 0; i < 256; i++) { | |
779 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); | |
780 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); | |
781 | } | |
782 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL); | |
783 | for (i = 0; i < 256; i++) { | |
784 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); | |
785 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); | |
786 | } | |
787 | write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */ | |
788 | ||
6dc8f382 | 789 | /* select channel 1 for input and set sync level */ |
d42bffb8 MM |
790 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); |
791 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); | |
792 | ||
a57941c2 | 793 | /* allocate memory, and initialize the DMA machine */ |
8ded351a | 794 | buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma, |
a57941c2 | 795 | GFP_KERNEL); |
c94a2e47 | 796 | if (!buf_cpu) |
d42bffb8 | 797 | return -ENOMEM; |
a57941c2 MM |
798 | iowrite32(buf_dma, pd->regs + EVEN_DMA_START); |
799 | iowrite32(buf_dma, pd->regs + ODD_DMA_START); | |
d42bffb8 MM |
800 | iowrite32(0, pd->regs + EVEN_DMA_STRIDE); |
801 | iowrite32(0, pd->regs + ODD_DMA_STRIDE); | |
802 | ||
803 | /* Perform a pseudo even field acquire */ | |
804 | iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1); | |
805 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL); | |
806 | write_i2c_reg(pd->regs, CONFIG, pd->config); | |
807 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL); | |
808 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL); | |
809 | msleep(100); | |
810 | read_i2c_reg(pd->regs, CSR2, &tmp); | |
811 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE); | |
812 | write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE); | |
813 | write_i2c_reg(pd->regs, CSR2, pd->csr2); | |
814 | iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1); | |
815 | ||
a57941c2 | 816 | /* deallocate memory */ |
8ded351a | 817 | dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma); |
c94a2e47 | 818 | if (tmp & BUSY_EVEN) |
d42bffb8 | 819 | return -EIO; |
d42bffb8 MM |
820 | return 0; |
821 | } | |
822 | ||
823 | static struct video_device dt3155_vdev = { | |
824 | .name = DT3155_NAME, | |
825 | .fops = &dt3155_fops, | |
826 | .ioctl_ops = &dt3155_ioctl_ops, | |
827 | .minor = -1, | |
828 | .release = video_device_release, | |
fdd2d934 | 829 | .tvnorms = DT3155_CURRENT_NORM, |
d42bffb8 MM |
830 | }; |
831 | ||
a57941c2 MM |
832 | /* same as in drivers/base/dma-coherent.c */ |
833 | struct dma_coherent_mem { | |
834 | void *virt_base; | |
8ded351a | 835 | dma_addr_t device_base; |
a57941c2 MM |
836 | int size; |
837 | int flags; | |
838 | unsigned long *bitmap; | |
839 | }; | |
840 | ||
2a91a6d1 | 841 | static int |
a57941c2 MM |
842 | dt3155_alloc_coherent(struct device *dev, size_t size, int flags) |
843 | { | |
f932e3a3 MM |
844 | struct dma_coherent_mem *mem; |
845 | dma_addr_t dev_base; | |
a57941c2 MM |
846 | int pages = size >> PAGE_SHIFT; |
847 | int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); | |
848 | ||
849 | if ((flags & DMA_MEMORY_MAP) == 0) | |
850 | goto out; | |
851 | if (!size) | |
852 | goto out; | |
853 | if (dev->dma_mem) | |
854 | goto out; | |
855 | ||
f932e3a3 MM |
856 | mem = kzalloc(sizeof(*mem), GFP_KERNEL); |
857 | if (!mem) | |
a57941c2 | 858 | goto out; |
f932e3a3 MM |
859 | mem->virt_base = dma_alloc_coherent(dev, size, &dev_base, |
860 | DT3155_COH_FLAGS); | |
861 | if (!mem->virt_base) | |
862 | goto err_alloc_coherent; | |
863 | mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); | |
864 | if (!mem->bitmap) | |
a57941c2 MM |
865 | goto err_bitmap; |
866 | ||
f932e3a3 MM |
867 | /* coherent_dma_mask is already set to 32 bits */ |
868 | mem->device_base = dev_base; | |
869 | mem->size = pages; | |
870 | mem->flags = flags; | |
871 | dev->dma_mem = mem; | |
a57941c2 MM |
872 | return DMA_MEMORY_MAP; |
873 | ||
a57941c2 | 874 | err_bitmap: |
f932e3a3 MM |
875 | dma_free_coherent(dev, size, mem->virt_base, dev_base); |
876 | err_alloc_coherent: | |
877 | kfree(mem); | |
a57941c2 MM |
878 | out: |
879 | return 0; | |
880 | } | |
881 | ||
4ce7986d | 882 | static void |
a57941c2 MM |
883 | dt3155_free_coherent(struct device *dev) |
884 | { | |
885 | struct dma_coherent_mem *mem = dev->dma_mem; | |
886 | ||
887 | if (!mem) | |
888 | return; | |
889 | dev->dma_mem = NULL; | |
890 | dma_free_coherent(dev, mem->size << PAGE_SHIFT, | |
891 | mem->virt_base, mem->device_base); | |
892 | kfree(mem->bitmap); | |
893 | kfree(mem); | |
894 | } | |
895 | ||
2a91a6d1 | 896 | static int |
8ded351a | 897 | dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
d42bffb8 | 898 | { |
a57941c2 | 899 | int err; |
d42bffb8 MM |
900 | struct dt3155_priv *pd; |
901 | ||
68788979 | 902 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
c94a2e47 | 903 | if (err) |
a57941c2 | 904 | return -ENODEV; |
d42bffb8 | 905 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); |
c94a2e47 | 906 | if (!pd) |
d42bffb8 | 907 | return -ENOMEM; |
d42bffb8 | 908 | pd->vdev = video_device_alloc(); |
5b340ea0 DC |
909 | if (!pd->vdev) { |
910 | err = -ENOMEM; | |
d42bffb8 | 911 | goto err_video_device_alloc; |
5b340ea0 | 912 | } |
d42bffb8 | 913 | *pd->vdev = dt3155_vdev; |
8ded351a | 914 | pci_set_drvdata(pdev, pd); /* for use in dt3155_remove() */ |
a57941c2 | 915 | video_set_drvdata(pd->vdev, pd); /* for use in video_fops */ |
d42bffb8 | 916 | pd->users = 0; |
8ded351a | 917 | pd->pdev = pdev; |
d42bffb8 | 918 | INIT_LIST_HEAD(&pd->dmaq); |
d42bffb8 | 919 | mutex_init(&pd->mux); |
8ded351a MM |
920 | pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */ |
921 | spin_lock_init(&pd->lock); | |
d42bffb8 MM |
922 | pd->csr2 = csr2_init; |
923 | pd->config = config_init; | |
8ded351a | 924 | err = pci_enable_device(pdev); |
c94a2e47 | 925 | if (err) |
d42bffb8 | 926 | goto err_enable_dev; |
8ded351a | 927 | err = pci_request_region(pdev, 0, pci_name(pdev)); |
d42bffb8 MM |
928 | if (err) |
929 | goto err_req_region; | |
8ded351a | 930 | pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0)); |
aecf33db | 931 | if (!pd->regs) { |
d42bffb8 | 932 | err = -ENOMEM; |
d42bffb8 | 933 | goto err_pci_iomap; |
aecf33db | 934 | } |
8ded351a | 935 | err = dt3155_init_board(pdev); |
c94a2e47 | 936 | if (err) |
d42bffb8 | 937 | goto err_init_board; |
d42bffb8 | 938 | err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1); |
a57941c2 | 939 | if (err) |
c94a2e47 HS |
940 | goto err_init_board; |
941 | if (dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE, | |
942 | DMA_MEMORY_MAP)) | |
943 | dev_info(&pdev->dev, "preallocated 8 buffers\n"); | |
944 | dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev->minor); | |
d42bffb8 MM |
945 | return 0; /* success */ |
946 | ||
947 | err_init_board: | |
8ded351a | 948 | pci_iounmap(pdev, pd->regs); |
d42bffb8 | 949 | err_pci_iomap: |
8ded351a | 950 | pci_release_region(pdev, 0); |
d42bffb8 | 951 | err_req_region: |
8ded351a | 952 | pci_disable_device(pdev); |
d42bffb8 MM |
953 | err_enable_dev: |
954 | video_device_release(pd->vdev); | |
955 | err_video_device_alloc: | |
956 | kfree(pd); | |
957 | return err; | |
958 | } | |
959 | ||
4ce7986d | 960 | static void |
8ded351a | 961 | dt3155_remove(struct pci_dev *pdev) |
d42bffb8 | 962 | { |
8ded351a | 963 | struct dt3155_priv *pd = pci_get_drvdata(pdev); |
d42bffb8 | 964 | |
8ded351a | 965 | dt3155_free_coherent(&pdev->dev); |
d42bffb8 | 966 | video_unregister_device(pd->vdev); |
8ded351a MM |
967 | pci_iounmap(pdev, pd->regs); |
968 | pci_release_region(pdev, 0); | |
969 | pci_disable_device(pdev); | |
d42bffb8 MM |
970 | /* |
971 | * video_device_release() is invoked automatically | |
972 | * see: struct video_device dt3155_vdev | |
973 | */ | |
974 | kfree(pd); | |
975 | } | |
976 | ||
41e043fc | 977 | static const struct pci_device_id pci_ids[] = { |
6fb0e403 | 978 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) }, |
d42bffb8 MM |
979 | { 0, /* zero marks the end */ }, |
980 | }; | |
981 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
982 | ||
983 | static struct pci_driver pci_driver = { | |
984 | .name = DT3155_NAME, | |
985 | .id_table = pci_ids, | |
986 | .probe = dt3155_probe, | |
79fc8d89 | 987 | .remove = dt3155_remove, |
d42bffb8 MM |
988 | }; |
989 | ||
1a3acd3d | 990 | module_pci_driver(pci_driver); |
d42bffb8 MM |
991 | |
992 | MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber"); | |
993 | MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>"); | |
994 | MODULE_VERSION(DT3155_VERSION); | |
995 | MODULE_LICENSE("GPL"); |