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Commit | Line | Data |
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404f3e95 JW |
1 | /* |
2 | * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk> | |
3 | * | |
4 | * lirc_sir - Device driver for use with SIR (serial infra red) | |
5 | * mode of IrDA on many notebooks. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | * | |
21 | * | |
22 | * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> : | |
23 | * added timeout and relaxed pulse detection, removed gap bug | |
24 | * | |
25 | * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> : | |
26 | * added support for Tekram Irmate 210 (sending does not work yet, | |
27 | * kind of disappointing that nobody was able to implement that | |
28 | * before), | |
29 | * major clean-up | |
30 | * | |
31 | * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> : | |
32 | * added support for StrongARM SA1100 embedded microprocessor | |
33 | * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King | |
34 | */ | |
35 | ||
014f0066 YT |
36 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
37 | ||
404f3e95 JW |
38 | #include <linux/module.h> |
39 | #include <linux/sched.h> | |
40 | #include <linux/errno.h> | |
41 | #include <linux/signal.h> | |
42 | #include <linux/fs.h> | |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/ioport.h> | |
45 | #include <linux/kernel.h> | |
46 | #include <linux/serial_reg.h> | |
34668350 | 47 | #include <linux/ktime.h> |
404f3e95 JW |
48 | #include <linux/string.h> |
49 | #include <linux/types.h> | |
50 | #include <linux/wait.h> | |
51 | #include <linux/mm.h> | |
52 | #include <linux/delay.h> | |
53 | #include <linux/poll.h> | |
404f3e95 JW |
54 | #include <linux/io.h> |
55 | #include <asm/irq.h> | |
56 | #include <linux/fcntl.h> | |
4b71ca6b | 57 | #include <linux/platform_device.h> |
404f3e95 JW |
58 | |
59 | #include <linux/timer.h> | |
60 | ||
61 | #include <media/lirc.h> | |
62 | #include <media/lirc_dev.h> | |
63 | ||
64 | /* SECTION: Definitions */ | |
65 | ||
66 | /*** Tekram dongle ***/ | |
67 | #ifdef LIRC_SIR_TEKRAM | |
68 | /* stolen from kernel source */ | |
69 | /* definitions for Tekram dongle */ | |
70 | #define TEKRAM_115200 0x00 | |
71 | #define TEKRAM_57600 0x01 | |
72 | #define TEKRAM_38400 0x02 | |
73 | #define TEKRAM_19200 0x03 | |
74 | #define TEKRAM_9600 0x04 | |
75 | #define TEKRAM_2400 0x08 | |
76 | ||
77 | #define TEKRAM_PW 0x10 /* Pulse select bit */ | |
78 | ||
79 | /* 10bit * 1s/115200bit in milliseconds = 87ms*/ | |
80 | #define TIME_CONST (10000000ul/115200ul) | |
81 | ||
82 | #endif | |
83 | ||
84 | #ifdef LIRC_SIR_ACTISYS_ACT200L | |
85 | static void init_act200(void); | |
86 | #elif defined(LIRC_SIR_ACTISYS_ACT220L) | |
87 | static void init_act220(void); | |
88 | #endif | |
89 | ||
404f3e95 JW |
90 | #define RBUF_LEN 1024 |
91 | #define WBUF_LEN 1024 | |
92 | ||
93 | #define LIRC_DRIVER_NAME "lirc_sir" | |
94 | ||
95 | #define PULSE '[' | |
96 | ||
97 | #ifndef LIRC_SIR_TEKRAM | |
98 | /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/ | |
99 | #define TIME_CONST (9000000ul/115200ul) | |
100 | #endif | |
101 | ||
102 | ||
103 | /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */ | |
104 | #define SIR_TIMEOUT (HZ*5/100) | |
105 | ||
106 | #ifndef LIRC_ON_SA1100 | |
107 | #ifndef LIRC_IRQ | |
108 | #define LIRC_IRQ 4 | |
109 | #endif | |
110 | #ifndef LIRC_PORT | |
111 | /* for external dongles, default to com1 */ | |
d713680f GD |
112 | #if defined(LIRC_SIR_ACTISYS_ACT200L) || \ |
113 | defined(LIRC_SIR_ACTISYS_ACT220L) || \ | |
114 | defined(LIRC_SIR_TEKRAM) | |
404f3e95 JW |
115 | #define LIRC_PORT 0x3f8 |
116 | #else | |
117 | /* onboard sir ports are typically com3 */ | |
118 | #define LIRC_PORT 0x3e8 | |
119 | #endif | |
120 | #endif | |
121 | ||
122 | static int io = LIRC_PORT; | |
123 | static int irq = LIRC_IRQ; | |
124 | static int threshold = 3; | |
125 | #endif | |
126 | ||
127 | static DEFINE_SPINLOCK(timer_lock); | |
128 | static struct timer_list timerlist; | |
129 | /* time of last signal change detected */ | |
34668350 | 130 | static ktime_t last; |
404f3e95 | 131 | /* time of last UART data ready interrupt */ |
34668350 | 132 | static ktime_t last_intr_time; |
404f3e95 JW |
133 | static int last_value; |
134 | ||
135 | static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue); | |
136 | ||
137 | static DEFINE_SPINLOCK(hardware_lock); | |
138 | ||
139 | static int rx_buf[RBUF_LEN]; | |
140 | static unsigned int rx_tail, rx_head; | |
141 | ||
90ab5ee9 | 142 | static bool debug; |
404f3e95 JW |
143 | |
144 | /* SECTION: Prototypes */ | |
145 | ||
146 | /* Communication with user-space */ | |
147 | static unsigned int lirc_poll(struct file *file, poll_table *wait); | |
12a72083 TT |
148 | static ssize_t lirc_read(struct file *file, char __user *buf, size_t count, |
149 | loff_t *ppos); | |
150 | static ssize_t lirc_write(struct file *file, const char __user *buf, size_t n, | |
151 | loff_t *pos); | |
404f3e95 JW |
152 | static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); |
153 | static void add_read_queue(int flag, unsigned long val); | |
154 | static int init_chrdev(void); | |
155 | static void drop_chrdev(void); | |
156 | /* Hardware */ | |
157 | static irqreturn_t sir_interrupt(int irq, void *dev_id); | |
158 | static void send_space(unsigned long len); | |
159 | static void send_pulse(unsigned long len); | |
160 | static int init_hardware(void); | |
161 | static void drop_hardware(void); | |
162 | /* Initialisation */ | |
163 | static int init_port(void); | |
164 | static void drop_port(void); | |
165 | ||
404f3e95 JW |
166 | static inline unsigned int sinp(int offset) |
167 | { | |
168 | return inb(io + offset); | |
169 | } | |
170 | ||
171 | static inline void soutp(int offset, int value) | |
172 | { | |
173 | outb(value, io + offset); | |
174 | } | |
404f3e95 JW |
175 | |
176 | #ifndef MAX_UDELAY_MS | |
177 | #define MAX_UDELAY_US 5000 | |
178 | #else | |
179 | #define MAX_UDELAY_US (MAX_UDELAY_MS*1000) | |
180 | #endif | |
181 | ||
182 | static void safe_udelay(unsigned long usecs) | |
183 | { | |
184 | while (usecs > MAX_UDELAY_US) { | |
185 | udelay(MAX_UDELAY_US); | |
186 | usecs -= MAX_UDELAY_US; | |
187 | } | |
188 | udelay(usecs); | |
189 | } | |
190 | ||
191 | /* SECTION: Communication with user-space */ | |
192 | ||
193 | static unsigned int lirc_poll(struct file *file, poll_table *wait) | |
194 | { | |
195 | poll_wait(file, &lirc_read_queue, wait); | |
196 | if (rx_head != rx_tail) | |
197 | return POLLIN | POLLRDNORM; | |
198 | return 0; | |
199 | } | |
200 | ||
12a72083 TT |
201 | static ssize_t lirc_read(struct file *file, char __user *buf, size_t count, |
202 | loff_t *ppos) | |
404f3e95 JW |
203 | { |
204 | int n = 0; | |
205 | int retval = 0; | |
206 | DECLARE_WAITQUEUE(wait, current); | |
207 | ||
208 | if (count % sizeof(int)) | |
209 | return -EINVAL; | |
210 | ||
211 | add_wait_queue(&lirc_read_queue, &wait); | |
212 | set_current_state(TASK_INTERRUPTIBLE); | |
213 | while (n < count) { | |
214 | if (rx_head != rx_tail) { | |
12a72083 TT |
215 | if (copy_to_user(buf + n, |
216 | rx_buf + rx_head, | |
217 | sizeof(int))) { | |
404f3e95 JW |
218 | retval = -EFAULT; |
219 | break; | |
220 | } | |
221 | rx_head = (rx_head + 1) & (RBUF_LEN - 1); | |
222 | n += sizeof(int); | |
223 | } else { | |
224 | if (file->f_flags & O_NONBLOCK) { | |
225 | retval = -EAGAIN; | |
226 | break; | |
227 | } | |
228 | if (signal_pending(current)) { | |
229 | retval = -ERESTARTSYS; | |
230 | break; | |
231 | } | |
232 | schedule(); | |
233 | set_current_state(TASK_INTERRUPTIBLE); | |
234 | } | |
235 | } | |
236 | remove_wait_queue(&lirc_read_queue, &wait); | |
237 | set_current_state(TASK_RUNNING); | |
238 | return n ? n : retval; | |
239 | } | |
12a72083 TT |
240 | static ssize_t lirc_write(struct file *file, const char __user *buf, size_t n, |
241 | loff_t *pos) | |
404f3e95 JW |
242 | { |
243 | unsigned long flags; | |
244 | int i, count; | |
245 | int *tx_buf; | |
246 | ||
247 | count = n / sizeof(int); | |
248 | if (n % sizeof(int) || count % 2 == 0) | |
249 | return -EINVAL; | |
250 | tx_buf = memdup_user(buf, n); | |
251 | if (IS_ERR(tx_buf)) | |
252 | return PTR_ERR(tx_buf); | |
253 | i = 0; | |
404f3e95 JW |
254 | local_irq_save(flags); |
255 | while (1) { | |
256 | if (i >= count) | |
257 | break; | |
258 | if (tx_buf[i]) | |
259 | send_pulse(tx_buf[i]); | |
260 | i++; | |
261 | if (i >= count) | |
262 | break; | |
263 | if (tx_buf[i]) | |
264 | send_space(tx_buf[i]); | |
265 | i++; | |
266 | } | |
267 | local_irq_restore(flags); | |
88914bdf | 268 | kfree(tx_buf); |
404f3e95 JW |
269 | return count; |
270 | } | |
271 | ||
272 | static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) | |
273 | { | |
12a72083 | 274 | u32 __user *uptr = (u32 __user *)arg; |
404f3e95 | 275 | int retval = 0; |
12a72083 | 276 | u32 value = 0; |
dbc5a5b6 | 277 | |
404f3e95 JW |
278 | if (cmd == LIRC_GET_FEATURES) |
279 | value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2; | |
280 | else if (cmd == LIRC_GET_SEND_MODE) | |
281 | value = LIRC_MODE_PULSE; | |
282 | else if (cmd == LIRC_GET_REC_MODE) | |
283 | value = LIRC_MODE_MODE2; | |
404f3e95 JW |
284 | |
285 | switch (cmd) { | |
286 | case LIRC_GET_FEATURES: | |
287 | case LIRC_GET_SEND_MODE: | |
288 | case LIRC_GET_REC_MODE: | |
12a72083 | 289 | retval = put_user(value, uptr); |
404f3e95 JW |
290 | break; |
291 | ||
292 | case LIRC_SET_SEND_MODE: | |
293 | case LIRC_SET_REC_MODE: | |
12a72083 | 294 | retval = get_user(value, uptr); |
404f3e95 | 295 | break; |
404f3e95 JW |
296 | default: |
297 | retval = -ENOIOCTLCMD; | |
298 | ||
299 | } | |
300 | ||
301 | if (retval) | |
302 | return retval; | |
303 | if (cmd == LIRC_SET_REC_MODE) { | |
304 | if (value != LIRC_MODE_MODE2) | |
305 | retval = -ENOSYS; | |
306 | } else if (cmd == LIRC_SET_SEND_MODE) { | |
307 | if (value != LIRC_MODE_PULSE) | |
308 | retval = -ENOSYS; | |
309 | } | |
310 | ||
311 | return retval; | |
312 | } | |
313 | ||
314 | static void add_read_queue(int flag, unsigned long val) | |
315 | { | |
316 | unsigned int new_rx_tail; | |
317 | int newval; | |
318 | ||
c96bf1d6 | 319 | pr_debug("add flag %d with val %lu\n", flag, val); |
404f3e95 JW |
320 | |
321 | newval = val & PULSE_MASK; | |
322 | ||
323 | /* | |
324 | * statistically, pulses are ~TIME_CONST/2 too long. we could | |
325 | * maybe make this more exact, but this is good enough | |
326 | */ | |
327 | if (flag) { | |
328 | /* pulse */ | |
329 | if (newval > TIME_CONST/2) | |
330 | newval -= TIME_CONST/2; | |
331 | else /* should not ever happen */ | |
332 | newval = 1; | |
333 | newval |= PULSE_BIT; | |
334 | } else { | |
335 | newval += TIME_CONST/2; | |
336 | } | |
337 | new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1); | |
338 | if (new_rx_tail == rx_head) { | |
c96bf1d6 | 339 | pr_debug("Buffer overrun.\n"); |
404f3e95 JW |
340 | return; |
341 | } | |
342 | rx_buf[rx_tail] = newval; | |
343 | rx_tail = new_rx_tail; | |
344 | wake_up_interruptible(&lirc_read_queue); | |
345 | } | |
346 | ||
0f9313ad | 347 | static const struct file_operations lirc_fops = { |
404f3e95 JW |
348 | .owner = THIS_MODULE, |
349 | .read = lirc_read, | |
350 | .write = lirc_write, | |
351 | .poll = lirc_poll, | |
352 | .unlocked_ioctl = lirc_ioctl, | |
8be292cc JW |
353 | #ifdef CONFIG_COMPAT |
354 | .compat_ioctl = lirc_ioctl, | |
355 | #endif | |
404f3e95 JW |
356 | .open = lirc_dev_fop_open, |
357 | .release = lirc_dev_fop_close, | |
d9d2e9d5 | 358 | .llseek = no_llseek, |
404f3e95 JW |
359 | }; |
360 | ||
361 | static int set_use_inc(void *data) | |
362 | { | |
d713680f | 363 | return 0; |
404f3e95 JW |
364 | } |
365 | ||
366 | static void set_use_dec(void *data) | |
367 | { | |
368 | } | |
369 | ||
370 | static struct lirc_driver driver = { | |
d713680f GD |
371 | .name = LIRC_DRIVER_NAME, |
372 | .minor = -1, | |
373 | .code_length = 1, | |
374 | .sample_rate = 0, | |
375 | .data = NULL, | |
376 | .add_to_buf = NULL, | |
377 | .set_use_inc = set_use_inc, | |
378 | .set_use_dec = set_use_dec, | |
379 | .fops = &lirc_fops, | |
380 | .dev = NULL, | |
381 | .owner = THIS_MODULE, | |
404f3e95 JW |
382 | }; |
383 | ||
4b71ca6b | 384 | static struct platform_device *lirc_sir_dev; |
404f3e95 JW |
385 | |
386 | static int init_chrdev(void) | |
387 | { | |
4b71ca6b | 388 | driver.dev = &lirc_sir_dev->dev; |
404f3e95 JW |
389 | driver.minor = lirc_register_driver(&driver); |
390 | if (driver.minor < 0) { | |
014f0066 | 391 | pr_err("init_chrdev() failed.\n"); |
404f3e95 JW |
392 | return -EIO; |
393 | } | |
394 | return 0; | |
395 | } | |
396 | ||
397 | static void drop_chrdev(void) | |
398 | { | |
399 | lirc_unregister_driver(driver.minor); | |
400 | } | |
401 | ||
402 | /* SECTION: Hardware */ | |
404f3e95 JW |
403 | static void sir_timeout(unsigned long data) |
404 | { | |
405 | /* | |
406 | * if last received signal was a pulse, but receiving stopped | |
407 | * within the 9 bit frame, we need to finish this pulse and | |
408 | * simulate a signal change to from pulse to space. Otherwise | |
409 | * upper layers will receive two sequences next time. | |
410 | */ | |
411 | ||
412 | unsigned long flags; | |
413 | unsigned long pulse_end; | |
414 | ||
415 | /* avoid interference with interrupt */ | |
416 | spin_lock_irqsave(&timer_lock, flags); | |
417 | if (last_value) { | |
404f3e95 JW |
418 | /* clear unread bits in UART and restart */ |
419 | outb(UART_FCR_CLEAR_RCVR, io + UART_FCR); | |
404f3e95 | 420 | /* determine 'virtual' pulse end: */ |
34668350 KS |
421 | pulse_end = min_t(unsigned long, |
422 | ktime_us_delta(last, last_intr_time), | |
423 | PULSE_MASK); | |
c96bf1d6 AM |
424 | dev_dbg(driver.dev, "timeout add %d for %lu usec\n", |
425 | last_value, pulse_end); | |
404f3e95 JW |
426 | add_read_queue(last_value, pulse_end); |
427 | last_value = 0; | |
34668350 | 428 | last = last_intr_time; |
404f3e95 JW |
429 | } |
430 | spin_unlock_irqrestore(&timer_lock, flags); | |
431 | } | |
432 | ||
433 | static irqreturn_t sir_interrupt(int irq, void *dev_id) | |
434 | { | |
435 | unsigned char data; | |
34668350 KS |
436 | ktime_t curr_time; |
437 | static unsigned long delt; | |
438 | unsigned long deltintr; | |
404f3e95 JW |
439 | unsigned long flags; |
440 | int iir, lsr; | |
441 | ||
442 | while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) { | |
443 | switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */ | |
444 | case UART_IIR_MSI: | |
445 | (void) inb(io + UART_MSR); | |
446 | break; | |
447 | case UART_IIR_RLSI: | |
448 | (void) inb(io + UART_LSR); | |
449 | break; | |
450 | case UART_IIR_THRI: | |
451 | #if 0 | |
452 | if (lsr & UART_LSR_THRE) /* FIFO is empty */ | |
453 | outb(data, io + UART_TX) | |
454 | #endif | |
455 | break; | |
456 | case UART_IIR_RDI: | |
457 | /* avoid interference with timer */ | |
458 | spin_lock_irqsave(&timer_lock, flags); | |
459 | do { | |
460 | del_timer(&timerlist); | |
461 | data = inb(io + UART_RX); | |
34668350 KS |
462 | curr_time = ktime_get(); |
463 | delt = min_t(unsigned long, | |
464 | ktime_us_delta(last, curr_time), | |
465 | PULSE_MASK); | |
466 | deltintr = min_t(unsigned long, | |
467 | ktime_us_delta(last_intr_time, | |
468 | curr_time), | |
469 | PULSE_MASK); | |
c96bf1d6 | 470 | dev_dbg(driver.dev, "t %lu, d %d\n", |
34668350 | 471 | deltintr, (int)data); |
404f3e95 JW |
472 | /* |
473 | * if nothing came in last X cycles, | |
474 | * it was gap | |
475 | */ | |
34668350 | 476 | if (deltintr > TIME_CONST * threshold) { |
404f3e95 | 477 | if (last_value) { |
c96bf1d6 | 478 | dev_dbg(driver.dev, "GAP\n"); |
404f3e95 JW |
479 | /* simulate signal change */ |
480 | add_read_queue(last_value, | |
34668350 KS |
481 | delt - |
482 | deltintr); | |
404f3e95 | 483 | last_value = 0; |
34668350 KS |
484 | last = last_intr_time; |
485 | delt = deltintr; | |
404f3e95 JW |
486 | } |
487 | } | |
488 | data = 1; | |
489 | if (data ^ last_value) { | |
490 | /* | |
34668350 | 491 | * deltintr > 2*TIME_CONST, remember? |
404f3e95 JW |
492 | * the other case is timeout |
493 | */ | |
494 | add_read_queue(last_value, | |
34668350 | 495 | delt-TIME_CONST); |
404f3e95 | 496 | last_value = data; |
34668350 KS |
497 | last = curr_time; |
498 | last = ktime_sub_us(last, | |
499 | TIME_CONST); | |
404f3e95 | 500 | } |
34668350 | 501 | last_intr_time = curr_time; |
404f3e95 JW |
502 | if (data) { |
503 | /* | |
504 | * start timer for end of | |
505 | * sequence detection | |
506 | */ | |
507 | timerlist.expires = jiffies + | |
508 | SIR_TIMEOUT; | |
509 | add_timer(&timerlist); | |
510 | } | |
511 | ||
512 | lsr = inb(io + UART_LSR); | |
513 | } while (lsr & UART_LSR_DR); /* data ready */ | |
514 | spin_unlock_irqrestore(&timer_lock, flags); | |
515 | break; | |
516 | default: | |
517 | break; | |
518 | } | |
519 | } | |
404f3e95 JW |
520 | return IRQ_RETVAL(IRQ_HANDLED); |
521 | } | |
522 | ||
404f3e95 JW |
523 | static void send_space(unsigned long len) |
524 | { | |
525 | safe_udelay(len); | |
526 | } | |
527 | ||
528 | static void send_pulse(unsigned long len) | |
529 | { | |
530 | long bytes_out = len / TIME_CONST; | |
404f3e95 | 531 | |
04f561ff | 532 | if (bytes_out == 0) |
404f3e95 | 533 | bytes_out++; |
04f561ff | 534 | |
404f3e95 JW |
535 | while (bytes_out--) { |
536 | outb(PULSE, io + UART_TX); | |
537 | /* FIXME treba seriozne cakanie z char/serial.c */ | |
538 | while (!(inb(io + UART_LSR) & UART_LSR_THRE)) | |
539 | ; | |
540 | } | |
404f3e95 | 541 | } |
404f3e95 JW |
542 | |
543 | static int init_hardware(void) | |
544 | { | |
545 | unsigned long flags; | |
546 | ||
547 | spin_lock_irqsave(&hardware_lock, flags); | |
548 | /* reset UART */ | |
c72374ff | 549 | #if defined(LIRC_SIR_TEKRAM) |
404f3e95 JW |
550 | /* disable FIFO */ |
551 | soutp(UART_FCR, | |
552 | UART_FCR_CLEAR_RCVR| | |
553 | UART_FCR_CLEAR_XMIT| | |
554 | UART_FCR_TRIGGER_1); | |
555 | ||
556 | /* Set DLAB 0. */ | |
557 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
558 | ||
559 | /* First of all, disable all interrupts */ | |
560 | soutp(UART_IER, sinp(UART_IER) & | |
561 | (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI))); | |
562 | ||
563 | /* Set DLAB 1. */ | |
564 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); | |
565 | ||
566 | /* Set divisor to 12 => 9600 Baud */ | |
567 | soutp(UART_DLM, 0); | |
568 | soutp(UART_DLL, 12); | |
569 | ||
570 | /* Set DLAB 0. */ | |
571 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
572 | ||
573 | /* power supply */ | |
574 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | |
575 | safe_udelay(50*1000); | |
576 | ||
577 | /* -DTR low -> reset PIC */ | |
578 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); | |
579 | udelay(1*1000); | |
580 | ||
581 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | |
582 | udelay(100); | |
583 | ||
584 | ||
585 | /* -RTS low -> send control byte */ | |
586 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); | |
587 | udelay(7); | |
588 | soutp(UART_TX, TEKRAM_115200|TEKRAM_PW); | |
589 | ||
590 | /* one byte takes ~1042 usec to transmit at 9600,8N1 */ | |
591 | udelay(1500); | |
592 | ||
593 | /* back to normal operation */ | |
594 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | |
595 | udelay(50); | |
596 | ||
597 | udelay(1500); | |
598 | ||
599 | /* read previous control byte */ | |
014f0066 | 600 | pr_info("0x%02x\n", sinp(UART_RX)); |
404f3e95 JW |
601 | |
602 | /* Set DLAB 1. */ | |
603 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); | |
604 | ||
605 | /* Set divisor to 1 => 115200 Baud */ | |
606 | soutp(UART_DLM, 0); | |
607 | soutp(UART_DLL, 1); | |
608 | ||
609 | /* Set DLAB 0, 8 Bit */ | |
610 | soutp(UART_LCR, UART_LCR_WLEN8); | |
611 | /* enable interrupts */ | |
612 | soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); | |
613 | #else | |
614 | outb(0, io + UART_MCR); | |
615 | outb(0, io + UART_IER); | |
616 | /* init UART */ | |
617 | /* set DLAB, speed = 115200 */ | |
618 | outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR); | |
619 | outb(1, io + UART_DLL); outb(0, io + UART_DLM); | |
620 | /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */ | |
621 | outb(UART_LCR_WLEN7, io + UART_LCR); | |
622 | /* FIFO operation */ | |
623 | outb(UART_FCR_ENABLE_FIFO, io + UART_FCR); | |
624 | /* interrupts */ | |
625 | /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */ | |
626 | outb(UART_IER_RDI, io + UART_IER); | |
627 | /* turn on UART */ | |
628 | outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR); | |
629 | #ifdef LIRC_SIR_ACTISYS_ACT200L | |
630 | init_act200(); | |
631 | #elif defined(LIRC_SIR_ACTISYS_ACT220L) | |
632 | init_act220(); | |
633 | #endif | |
634 | #endif | |
635 | spin_unlock_irqrestore(&hardware_lock, flags); | |
636 | return 0; | |
637 | } | |
638 | ||
639 | static void drop_hardware(void) | |
640 | { | |
641 | unsigned long flags; | |
642 | ||
643 | spin_lock_irqsave(&hardware_lock, flags); | |
644 | ||
404f3e95 JW |
645 | /* turn off interrupts */ |
646 | outb(0, io + UART_IER); | |
c72374ff | 647 | |
404f3e95 JW |
648 | spin_unlock_irqrestore(&hardware_lock, flags); |
649 | } | |
650 | ||
651 | /* SECTION: Initialisation */ | |
652 | ||
653 | static int init_port(void) | |
654 | { | |
655 | int retval; | |
656 | ||
657 | /* get I/O port access and IRQ line */ | |
404f3e95 | 658 | if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) { |
014f0066 | 659 | pr_err("i/o port 0x%.4x already in use.\n", io); |
404f3e95 JW |
660 | return -EBUSY; |
661 | } | |
18e9351e | 662 | retval = request_irq(irq, sir_interrupt, 0, |
404f3e95 JW |
663 | LIRC_DRIVER_NAME, NULL); |
664 | if (retval < 0) { | |
404f3e95 | 665 | release_region(io, 8); |
014f0066 | 666 | pr_err("IRQ %d already in use.\n", irq); |
404f3e95 JW |
667 | return retval; |
668 | } | |
014f0066 | 669 | pr_info("I/O port 0x%.4x, IRQ %d.\n", io, irq); |
404f3e95 | 670 | |
b856e0f7 | 671 | setup_timer(&timerlist, sir_timeout, 0); |
404f3e95 JW |
672 | |
673 | return 0; | |
674 | } | |
675 | ||
676 | static void drop_port(void) | |
677 | { | |
678 | free_irq(irq, NULL); | |
679 | del_timer_sync(&timerlist); | |
404f3e95 | 680 | release_region(io, 8); |
404f3e95 JW |
681 | } |
682 | ||
683 | #ifdef LIRC_SIR_ACTISYS_ACT200L | |
684 | /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */ | |
685 | /* some code borrowed from Linux IRDA driver */ | |
686 | ||
687 | /* Register 0: Control register #1 */ | |
688 | #define ACT200L_REG0 0x00 | |
689 | #define ACT200L_TXEN 0x01 /* Enable transmitter */ | |
690 | #define ACT200L_RXEN 0x02 /* Enable receiver */ | |
691 | #define ACT200L_ECHO 0x08 /* Echo control chars */ | |
692 | ||
693 | /* Register 1: Control register #2 */ | |
694 | #define ACT200L_REG1 0x10 | |
695 | #define ACT200L_LODB 0x01 /* Load new baud rate count value */ | |
696 | #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */ | |
697 | ||
698 | /* Register 3: Transmit mode register #2 */ | |
699 | #define ACT200L_REG3 0x30 | |
700 | #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ | |
701 | #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ | |
702 | #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */ | |
703 | ||
704 | /* Register 4: Output Power register */ | |
705 | #define ACT200L_REG4 0x40 | |
706 | #define ACT200L_OP0 0x01 /* Enable LED1C output */ | |
707 | #define ACT200L_OP1 0x02 /* Enable LED2C output */ | |
708 | #define ACT200L_BLKR 0x04 | |
709 | ||
710 | /* Register 5: Receive Mode register */ | |
711 | #define ACT200L_REG5 0x50 | |
712 | #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */ | |
713 | /*.. other various IRDA bit modes, and TV remote modes..*/ | |
714 | ||
715 | /* Register 6: Receive Sensitivity register #1 */ | |
716 | #define ACT200L_REG6 0x60 | |
717 | #define ACT200L_RS0 0x01 /* receive threshold bit 0 */ | |
718 | #define ACT200L_RS1 0x02 /* receive threshold bit 1 */ | |
719 | ||
720 | /* Register 7: Receive Sensitivity register #2 */ | |
721 | #define ACT200L_REG7 0x70 | |
722 | #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */ | |
723 | ||
724 | /* Register 8,9: Baud Rate Divider register #1,#2 */ | |
725 | #define ACT200L_REG8 0x80 | |
726 | #define ACT200L_REG9 0x90 | |
727 | ||
728 | #define ACT200L_2400 0x5f | |
729 | #define ACT200L_9600 0x17 | |
730 | #define ACT200L_19200 0x0b | |
731 | #define ACT200L_38400 0x05 | |
732 | #define ACT200L_57600 0x03 | |
733 | #define ACT200L_115200 0x01 | |
734 | ||
735 | /* Register 13: Control register #3 */ | |
736 | #define ACT200L_REG13 0xd0 | |
737 | #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */ | |
738 | ||
739 | /* Register 15: Status register */ | |
740 | #define ACT200L_REG15 0xf0 | |
741 | ||
742 | /* Register 21: Control register #4 */ | |
743 | #define ACT200L_REG21 0x50 | |
744 | #define ACT200L_EXCK 0x02 /* Disable clock output driver */ | |
745 | #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */ | |
746 | ||
747 | static void init_act200(void) | |
748 | { | |
749 | int i; | |
750 | __u8 control[] = { | |
751 | ACT200L_REG15, | |
752 | ACT200L_REG13 | ACT200L_SHDW, | |
753 | ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL, | |
754 | ACT200L_REG13, | |
755 | ACT200L_REG7 | ACT200L_ENPOS, | |
756 | ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1, | |
757 | ACT200L_REG5 | ACT200L_RWIDL, | |
758 | ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR, | |
759 | ACT200L_REG3 | ACT200L_B0, | |
760 | ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN, | |
761 | ACT200L_REG8 | (ACT200L_115200 & 0x0f), | |
762 | ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f), | |
763 | ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE | |
764 | }; | |
765 | ||
766 | /* Set DLAB 1. */ | |
767 | soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8); | |
768 | ||
769 | /* Set divisor to 12 => 9600 Baud */ | |
770 | soutp(UART_DLM, 0); | |
771 | soutp(UART_DLL, 12); | |
772 | ||
773 | /* Set DLAB 0. */ | |
774 | soutp(UART_LCR, UART_LCR_WLEN8); | |
775 | /* Set divisor to 12 => 9600 Baud */ | |
776 | ||
777 | /* power supply */ | |
778 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | |
779 | for (i = 0; i < 50; i++) | |
780 | safe_udelay(1000); | |
781 | ||
782 | /* Reset the dongle : set RTS low for 25 ms */ | |
783 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); | |
784 | for (i = 0; i < 25; i++) | |
785 | udelay(1000); | |
786 | ||
787 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | |
788 | udelay(100); | |
789 | ||
790 | /* Clear DTR and set RTS to enter command mode */ | |
791 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); | |
792 | udelay(7); | |
793 | ||
794 | /* send out the control register settings for 115K 7N1 SIR operation */ | |
795 | for (i = 0; i < sizeof(control); i++) { | |
796 | soutp(UART_TX, control[i]); | |
797 | /* one byte takes ~1042 usec to transmit at 9600,8N1 */ | |
798 | udelay(1500); | |
799 | } | |
800 | ||
801 | /* back to normal operation */ | |
802 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | |
803 | udelay(50); | |
804 | ||
805 | udelay(1500); | |
806 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); | |
807 | ||
808 | /* Set DLAB 1. */ | |
809 | soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); | |
810 | ||
811 | /* Set divisor to 1 => 115200 Baud */ | |
812 | soutp(UART_DLM, 0); | |
813 | soutp(UART_DLL, 1); | |
814 | ||
815 | /* Set DLAB 0. */ | |
816 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
817 | ||
818 | /* Set DLAB 0, 7 Bit */ | |
819 | soutp(UART_LCR, UART_LCR_WLEN7); | |
820 | ||
821 | /* enable interrupts */ | |
822 | soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); | |
823 | } | |
824 | #endif | |
825 | ||
826 | #ifdef LIRC_SIR_ACTISYS_ACT220L | |
827 | /* | |
828 | * Derived from linux IrDA driver (net/irda/actisys.c) | |
829 | * Drop me a mail for any kind of comment: maxx@spaceboyz.net | |
830 | */ | |
831 | ||
832 | void init_act220(void) | |
833 | { | |
834 | int i; | |
835 | ||
836 | /* DLAB 1 */ | |
837 | soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7); | |
838 | ||
839 | /* 9600 baud */ | |
840 | soutp(UART_DLM, 0); | |
841 | soutp(UART_DLL, 12); | |
842 | ||
843 | /* DLAB 0 */ | |
844 | soutp(UART_LCR, UART_LCR_WLEN7); | |
845 | ||
846 | /* reset the dongle, set DTR low for 10us */ | |
847 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); | |
848 | udelay(10); | |
849 | ||
850 | /* back to normal (still 9600) */ | |
851 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2); | |
852 | ||
853 | /* | |
854 | * send RTS pulses until we reach 115200 | |
855 | * i hope this is really the same for act220l/act220l+ | |
856 | */ | |
857 | for (i = 0; i < 3; i++) { | |
858 | udelay(10); | |
859 | /* set RTS low for 10 us */ | |
860 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); | |
861 | udelay(10); | |
862 | /* set RTS high for 10 us */ | |
863 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | |
864 | } | |
865 | ||
866 | /* back to normal operation */ | |
867 | udelay(1500); /* better safe than sorry ;) */ | |
868 | ||
869 | /* Set DLAB 1. */ | |
870 | soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); | |
871 | ||
872 | /* Set divisor to 1 => 115200 Baud */ | |
873 | soutp(UART_DLM, 0); | |
874 | soutp(UART_DLL, 1); | |
875 | ||
876 | /* Set DLAB 0, 7 Bit */ | |
877 | /* The dongle doesn't seem to have any problems with operation at 7N1 */ | |
878 | soutp(UART_LCR, UART_LCR_WLEN7); | |
879 | ||
880 | /* enable interrupts */ | |
881 | soutp(UART_IER, UART_IER_RDI); | |
882 | } | |
883 | #endif | |
884 | ||
885 | static int init_lirc_sir(void) | |
886 | { | |
887 | int retval; | |
888 | ||
889 | init_waitqueue_head(&lirc_read_queue); | |
890 | retval = init_port(); | |
891 | if (retval < 0) | |
892 | return retval; | |
893 | init_hardware(); | |
014f0066 | 894 | pr_info("Installed.\n"); |
404f3e95 JW |
895 | return 0; |
896 | } | |
897 | ||
fd8413a2 | 898 | static int lirc_sir_probe(struct platform_device *dev) |
4b71ca6b JW |
899 | { |
900 | return 0; | |
901 | } | |
902 | ||
6dd11195 | 903 | static int lirc_sir_remove(struct platform_device *dev) |
4b71ca6b JW |
904 | { |
905 | return 0; | |
906 | } | |
907 | ||
908 | static struct platform_driver lirc_sir_driver = { | |
909 | .probe = lirc_sir_probe, | |
01f6f49b | 910 | .remove = lirc_sir_remove, |
4b71ca6b JW |
911 | .driver = { |
912 | .name = "lirc_sir", | |
4b71ca6b JW |
913 | }, |
914 | }; | |
404f3e95 JW |
915 | |
916 | static int __init lirc_sir_init(void) | |
917 | { | |
918 | int retval; | |
919 | ||
4b71ca6b JW |
920 | retval = platform_driver_register(&lirc_sir_driver); |
921 | if (retval) { | |
014f0066 | 922 | pr_err("Platform driver register failed!\n"); |
4b71ca6b JW |
923 | return -ENODEV; |
924 | } | |
925 | ||
926 | lirc_sir_dev = platform_device_alloc("lirc_dev", 0); | |
927 | if (!lirc_sir_dev) { | |
014f0066 | 928 | pr_err("Platform device alloc failed!\n"); |
4b71ca6b JW |
929 | retval = -ENOMEM; |
930 | goto pdev_alloc_fail; | |
931 | } | |
932 | ||
933 | retval = platform_device_add(lirc_sir_dev); | |
934 | if (retval) { | |
014f0066 | 935 | pr_err("Platform device add failed!\n"); |
4b71ca6b JW |
936 | retval = -ENODEV; |
937 | goto pdev_add_fail; | |
938 | } | |
939 | ||
404f3e95 JW |
940 | retval = init_chrdev(); |
941 | if (retval < 0) | |
4b71ca6b JW |
942 | goto fail; |
943 | ||
404f3e95 JW |
944 | retval = init_lirc_sir(); |
945 | if (retval) { | |
946 | drop_chrdev(); | |
4b71ca6b | 947 | goto fail; |
404f3e95 | 948 | } |
4b71ca6b | 949 | |
404f3e95 | 950 | return 0; |
4b71ca6b JW |
951 | |
952 | fail: | |
953 | platform_device_del(lirc_sir_dev); | |
954 | pdev_add_fail: | |
955 | platform_device_put(lirc_sir_dev); | |
956 | pdev_alloc_fail: | |
957 | platform_driver_unregister(&lirc_sir_driver); | |
958 | return retval; | |
404f3e95 JW |
959 | } |
960 | ||
961 | static void __exit lirc_sir_exit(void) | |
962 | { | |
963 | drop_hardware(); | |
964 | drop_chrdev(); | |
965 | drop_port(); | |
4b71ca6b JW |
966 | platform_device_unregister(lirc_sir_dev); |
967 | platform_driver_unregister(&lirc_sir_driver); | |
014f0066 | 968 | pr_info("Uninstalled.\n"); |
404f3e95 JW |
969 | } |
970 | ||
971 | module_init(lirc_sir_init); | |
972 | module_exit(lirc_sir_exit); | |
973 | ||
974 | #ifdef LIRC_SIR_TEKRAM | |
975 | MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210"); | |
976 | MODULE_AUTHOR("Christoph Bartelmus"); | |
404f3e95 JW |
977 | #elif defined(LIRC_SIR_ACTISYS_ACT200L) |
978 | MODULE_DESCRIPTION("LIRC driver for Actisys Act200L"); | |
979 | MODULE_AUTHOR("Karl Bongers"); | |
980 | #elif defined(LIRC_SIR_ACTISYS_ACT220L) | |
981 | MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)"); | |
982 | MODULE_AUTHOR("Jan Roemisch"); | |
983 | #else | |
984 | MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports"); | |
985 | MODULE_AUTHOR("Milan Pikula"); | |
986 | #endif | |
987 | MODULE_LICENSE("GPL"); | |
988 | ||
404f3e95 JW |
989 | module_param(io, int, S_IRUGO); |
990 | MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)"); | |
991 | ||
992 | module_param(irq, int, S_IRUGO); | |
993 | MODULE_PARM_DESC(irq, "Interrupt (4 or 3)"); | |
994 | ||
995 | module_param(threshold, int, S_IRUGO); | |
996 | MODULE_PARM_DESC(threshold, "space detection threshold (3)"); | |
404f3e95 JW |
997 | |
998 | module_param(debug, bool, S_IRUGO | S_IWUSR); | |
999 | MODULE_PARM_DESC(debug, "Enable debugging messages"); |