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staging: media: lirc: lirc_zilog.c: replace custom print macros with dev_* and pr_*
[mirror_ubuntu-artful-kernel.git] / drivers / staging / media / lirc / lirc_sir.c
CommitLineData
404f3e95
JW		 1/*
2 * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
3 *
4 * lirc_sir - Device driver for use with SIR (serial infra red)
5 * mode of IrDA on many notebooks.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 *
22 * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
23 * added timeout and relaxed pulse detection, removed gap bug
24 *
25 * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
26 * added support for Tekram Irmate 210 (sending does not work yet,
27 * kind of disappointing that nobody was able to implement that
28 * before),
29 * major clean-up
30 *
31 * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
32 * added support for StrongARM SA1100 embedded microprocessor
33 * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
34 */
35
014f0066
YT		 36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
404f3e95
JW		 38#include <linux/module.h>
39#include <linux/sched.h>
40#include <linux/errno.h>
41#include <linux/signal.h>
42#include <linux/fs.h>
43#include <linux/interrupt.h>
44#include <linux/ioport.h>
45#include <linux/kernel.h>
46#include <linux/serial_reg.h>
47#include <linux/time.h>
48#include <linux/string.h>
49#include <linux/types.h>
50#include <linux/wait.h>
51#include <linux/mm.h>
52#include <linux/delay.h>
53#include <linux/poll.h>
404f3e95
JW		 54#include <linux/io.h>
55#include <asm/irq.h>
56#include <linux/fcntl.h>
4b71ca6b 57#include <linux/platform_device.h>
404f3e95
JW		 58
59#include <linux/timer.h>
60
61#include <media/lirc.h>
62#include <media/lirc_dev.h>
63
64/* SECTION: Definitions */
65
66/*** Tekram dongle ***/
67#ifdef LIRC_SIR_TEKRAM
68/* stolen from kernel source */
69/* definitions for Tekram dongle */
70#define TEKRAM_115200 0x00
71#define TEKRAM_57600 0x01
72#define TEKRAM_38400 0x02
73#define TEKRAM_19200 0x03
74#define TEKRAM_9600 0x04
75#define TEKRAM_2400 0x08
76
77#define TEKRAM_PW 0x10 /* Pulse select bit */
78
79/* 10bit * 1s/115200bit in milliseconds = 87ms*/
80#define TIME_CONST (10000000ul/115200ul)
81
82#endif
83
84#ifdef LIRC_SIR_ACTISYS_ACT200L
85static void init_act200(void);
86#elif defined(LIRC_SIR_ACTISYS_ACT220L)
87static void init_act220(void);
88#endif
89
404f3e95
JW		 90#define RBUF_LEN 1024
91#define WBUF_LEN 1024
92
93#define LIRC_DRIVER_NAME "lirc_sir"
94
95#define PULSE '['
96
97#ifndef LIRC_SIR_TEKRAM
98/* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
99#define TIME_CONST (9000000ul/115200ul)
100#endif
101
102
103/* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
104#define SIR_TIMEOUT (HZ*5/100)
105
106#ifndef LIRC_ON_SA1100
107#ifndef LIRC_IRQ
108#define LIRC_IRQ 4
109#endif
110#ifndef LIRC_PORT
111/* for external dongles, default to com1 */
d713680f
GD		 112#if defined(LIRC_SIR_ACTISYS_ACT200L) || \
113 defined(LIRC_SIR_ACTISYS_ACT220L) || \
114 defined(LIRC_SIR_TEKRAM)
404f3e95
JW		 115#define LIRC_PORT 0x3f8
116#else
117/* onboard sir ports are typically com3 */
118#define LIRC_PORT 0x3e8
119#endif
120#endif
121
122static int io = LIRC_PORT;
123static int irq = LIRC_IRQ;
124static int threshold = 3;
125#endif
126
127static DEFINE_SPINLOCK(timer_lock);
128static struct timer_list timerlist;
129/* time of last signal change detected */
130static struct timeval last_tv = {0, 0};
131/* time of last UART data ready interrupt */
132static struct timeval last_intr_tv = {0, 0};
133static int last_value;
134
135static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue);
136
137static DEFINE_SPINLOCK(hardware_lock);
138
139static int rx_buf[RBUF_LEN];
140static unsigned int rx_tail, rx_head;
141
90ab5ee9 142static bool debug;
404f3e95
JW		 143#define dprintk(fmt, args...) \
144 do { \
145 if (debug) \
146 printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \
147 fmt, ## args); \
148 } while (0)
149
150/* SECTION: Prototypes */
151
152/* Communication with user-space */
153static unsigned int lirc_poll(struct file *file, poll_table *wait);
12a72083
TT		 154static ssize_t lirc_read(struct file *file, char __user *buf, size_t count,
155 loff_t *ppos);
156static ssize_t lirc_write(struct file *file, const char __user *buf, size_t n,
157 loff_t *pos);
404f3e95
JW		 158static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
159static void add_read_queue(int flag, unsigned long val);
160static int init_chrdev(void);
161static void drop_chrdev(void);
162/* Hardware */
163static irqreturn_t sir_interrupt(int irq, void *dev_id);
164static void send_space(unsigned long len);
165static void send_pulse(unsigned long len);
166static int init_hardware(void);
167static void drop_hardware(void);
168/* Initialisation */
169static int init_port(void);
170static void drop_port(void);
171
404f3e95
JW		 172static inline unsigned int sinp(int offset)
173{
174 return inb(io + offset);
175}
176
177static inline void soutp(int offset, int value)
178{
179 outb(value, io + offset);
180}
404f3e95
JW		 181
182#ifndef MAX_UDELAY_MS
183#define MAX_UDELAY_US 5000
184#else
185#define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
186#endif
187
188static void safe_udelay(unsigned long usecs)
189{
190 while (usecs > MAX_UDELAY_US) {
191 udelay(MAX_UDELAY_US);
192 usecs -= MAX_UDELAY_US;
193 }
194 udelay(usecs);
195}
196
197/* SECTION: Communication with user-space */
198
199static unsigned int lirc_poll(struct file *file, poll_table *wait)
200{
201 poll_wait(file, &lirc_read_queue, wait);
202 if (rx_head != rx_tail)
203 return POLLIN | POLLRDNORM;
204 return 0;
205}
206
12a72083
TT		 207static ssize_t lirc_read(struct file *file, char __user *buf, size_t count,
208 loff_t *ppos)
404f3e95
JW		 209{
210 int n = 0;
211 int retval = 0;
212 DECLARE_WAITQUEUE(wait, current);
213
214 if (count % sizeof(int))
215 return -EINVAL;
216
217 add_wait_queue(&lirc_read_queue, &wait);
218 set_current_state(TASK_INTERRUPTIBLE);
219 while (n < count) {
220 if (rx_head != rx_tail) {
12a72083
TT		 221 if (copy_to_user(buf + n,
222 rx_buf + rx_head,
223 sizeof(int))) {
404f3e95
JW		 224 retval = -EFAULT;
225 break;
226 }
227 rx_head = (rx_head + 1) & (RBUF_LEN - 1);
228 n += sizeof(int);
229 } else {
230 if (file->f_flags & O_NONBLOCK) {
231 retval = -EAGAIN;
232 break;
233 }
234 if (signal_pending(current)) {
235 retval = -ERESTARTSYS;
236 break;
237 }
238 schedule();
239 set_current_state(TASK_INTERRUPTIBLE);
240 }
241 }
242 remove_wait_queue(&lirc_read_queue, &wait);
243 set_current_state(TASK_RUNNING);
244 return n ? n : retval;
245}
12a72083
TT		 246static ssize_t lirc_write(struct file *file, const char __user *buf, size_t n,
247 loff_t *pos)
404f3e95
JW		 248{
249 unsigned long flags;
250 int i, count;
251 int *tx_buf;
252
253 count = n / sizeof(int);
254 if (n % sizeof(int) || count % 2 == 0)
255 return -EINVAL;
256 tx_buf = memdup_user(buf, n);
257 if (IS_ERR(tx_buf))
258 return PTR_ERR(tx_buf);
259 i = 0;
404f3e95
JW		 260 local_irq_save(flags);
261 while (1) {
262 if (i >= count)
263 break;
264 if (tx_buf[i])
265 send_pulse(tx_buf[i]);
266 i++;
267 if (i >= count)
268 break;
269 if (tx_buf[i])
270 send_space(tx_buf[i]);
271 i++;
272 }
273 local_irq_restore(flags);
88914bdf 274 kfree(tx_buf);
404f3e95
JW		 275 return count;
276}
277
278static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
279{
12a72083 280 u32 __user *uptr = (u32 __user *)arg;
404f3e95 281 int retval = 0;
12a72083 282 u32 value = 0;
dbc5a5b6 283
404f3e95
JW		 284 if (cmd == LIRC_GET_FEATURES)
285 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2;
286 else if (cmd == LIRC_GET_SEND_MODE)
287 value = LIRC_MODE_PULSE;
288 else if (cmd == LIRC_GET_REC_MODE)
289 value = LIRC_MODE_MODE2;
404f3e95
JW		 290
291 switch (cmd) {
292 case LIRC_GET_FEATURES:
293 case LIRC_GET_SEND_MODE:
294 case LIRC_GET_REC_MODE:
12a72083 295 retval = put_user(value, uptr);
404f3e95
JW		 296 break;
297
298 case LIRC_SET_SEND_MODE:
299 case LIRC_SET_REC_MODE:
12a72083 300 retval = get_user(value, uptr);
404f3e95 301 break;
404f3e95
JW		 302 default:
303 retval = -ENOIOCTLCMD;
304
305 }
306
307 if (retval)
308 return retval;
309 if (cmd == LIRC_SET_REC_MODE) {
310 if (value != LIRC_MODE_MODE2)
311 retval = -ENOSYS;
312 } else if (cmd == LIRC_SET_SEND_MODE) {
313 if (value != LIRC_MODE_PULSE)
314 retval = -ENOSYS;
315 }
316
317 return retval;
318}
319
320static void add_read_queue(int flag, unsigned long val)
321{
322 unsigned int new_rx_tail;
323 int newval;
324
325 dprintk("add flag %d with val %lu\n", flag, val);
326
327 newval = val & PULSE_MASK;
328
329 /*
330 * statistically, pulses are ~TIME_CONST/2 too long. we could
331 * maybe make this more exact, but this is good enough
332 */
333 if (flag) {
334 /* pulse */
335 if (newval > TIME_CONST/2)
336 newval -= TIME_CONST/2;
337 else /* should not ever happen */
338 newval = 1;
339 newval |= PULSE_BIT;
340 } else {
341 newval += TIME_CONST/2;
342 }
343 new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1);
344 if (new_rx_tail == rx_head) {
345 dprintk("Buffer overrun.\n");
346 return;
347 }
348 rx_buf[rx_tail] = newval;
349 rx_tail = new_rx_tail;
350 wake_up_interruptible(&lirc_read_queue);
351}
352
0f9313ad 353static const struct file_operations lirc_fops = {
404f3e95
JW		 354 .owner = THIS_MODULE,
355 .read = lirc_read,
356 .write = lirc_write,
357 .poll = lirc_poll,
358 .unlocked_ioctl = lirc_ioctl,
8be292cc
JW		 359#ifdef CONFIG_COMPAT
360 .compat_ioctl = lirc_ioctl,
361#endif
404f3e95
JW		 362 .open = lirc_dev_fop_open,
363 .release = lirc_dev_fop_close,
d9d2e9d5 364 .llseek = no_llseek,
404f3e95
JW		 365};
366
367static int set_use_inc(void *data)
368{
d713680f 369 return 0;
404f3e95
JW		 370}
371
372static void set_use_dec(void *data)
373{
374}
375
376static struct lirc_driver driver = {
d713680f
GD		 377 .name = LIRC_DRIVER_NAME,
378 .minor = -1,
379 .code_length = 1,
380 .sample_rate = 0,
381 .data = NULL,
382 .add_to_buf = NULL,
383 .set_use_inc = set_use_inc,
384 .set_use_dec = set_use_dec,
385 .fops = &lirc_fops,
386 .dev = NULL,
387 .owner = THIS_MODULE,
404f3e95
JW		 388};
389
4b71ca6b 390static struct platform_device *lirc_sir_dev;
404f3e95
JW		 391
392static int init_chrdev(void)
393{
4b71ca6b 394 driver.dev = &lirc_sir_dev->dev;
404f3e95
JW		 395 driver.minor = lirc_register_driver(&driver);
396 if (driver.minor < 0) {
014f0066 397 pr_err("init_chrdev() failed.\n");
404f3e95
JW		 398 return -EIO;
399 }
400 return 0;
401}
402
403static void drop_chrdev(void)
404{
405 lirc_unregister_driver(driver.minor);
406}
407
408/* SECTION: Hardware */
409static long delta(struct timeval *tv1, struct timeval *tv2)
410{
411 unsigned long deltv;
412
413 deltv = tv2->tv_sec - tv1->tv_sec;
414 if (deltv > 15)
415 deltv = 0xFFFFFF;
416 else
417 deltv = deltv*1000000 +
418 tv2->tv_usec -
419 tv1->tv_usec;
420 return deltv;
421}
422
423static void sir_timeout(unsigned long data)
424{
425 /*
426 * if last received signal was a pulse, but receiving stopped
427 * within the 9 bit frame, we need to finish this pulse and
428 * simulate a signal change to from pulse to space. Otherwise
429 * upper layers will receive two sequences next time.
430 */
431
432 unsigned long flags;
433 unsigned long pulse_end;
434
435 /* avoid interference with interrupt */
436 spin_lock_irqsave(&timer_lock, flags);
437 if (last_value) {
404f3e95
JW		 438 /* clear unread bits in UART and restart */
439 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
404f3e95
JW		 440 /* determine 'virtual' pulse end: */
441 pulse_end = delta(&last_tv, &last_intr_tv);
442 dprintk("timeout add %d for %lu usec\n", last_value, pulse_end);
443 add_read_queue(last_value, pulse_end);
444 last_value = 0;
445 last_tv = last_intr_tv;
446 }
447 spin_unlock_irqrestore(&timer_lock, flags);
448}
449
450static irqreturn_t sir_interrupt(int irq, void *dev_id)
451{
452 unsigned char data;
453 struct timeval curr_tv;
454 static unsigned long deltv;
404f3e95
JW		 455 unsigned long deltintrtv;
456 unsigned long flags;
457 int iir, lsr;
458
459 while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
460 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
461 case UART_IIR_MSI:
462 (void) inb(io + UART_MSR);
463 break;
464 case UART_IIR_RLSI:
465 (void) inb(io + UART_LSR);
466 break;
467 case UART_IIR_THRI:
468#if 0
469 if (lsr & UART_LSR_THRE) /* FIFO is empty */
470 outb(data, io + UART_TX)
471#endif
472 break;
473 case UART_IIR_RDI:
474 /* avoid interference with timer */
475 spin_lock_irqsave(&timer_lock, flags);
476 do {
477 del_timer(&timerlist);
478 data = inb(io + UART_RX);
479 do_gettimeofday(&curr_tv);
480 deltv = delta(&last_tv, &curr_tv);
481 deltintrtv = delta(&last_intr_tv, &curr_tv);
482 dprintk("t %lu, d %d\n", deltintrtv, (int)data);
483 /*
484 * if nothing came in last X cycles,
485 * it was gap
486 */
487 if (deltintrtv > TIME_CONST * threshold) {
488 if (last_value) {
489 dprintk("GAP\n");
490 /* simulate signal change */
491 add_read_queue(last_value,
492 deltv -
493 deltintrtv);
494 last_value = 0;
495 last_tv.tv_sec =
496 last_intr_tv.tv_sec;
497 last_tv.tv_usec =
498 last_intr_tv.tv_usec;
499 deltv = deltintrtv;
500 }
501 }
502 data = 1;
503 if (data ^ last_value) {
504 /*
505 * deltintrtv > 2*TIME_CONST, remember?
506 * the other case is timeout
507 */
508 add_read_queue(last_value,
509 deltv-TIME_CONST);
510 last_value = data;
511 last_tv = curr_tv;
512 if (last_tv.tv_usec >= TIME_CONST) {
513 last_tv.tv_usec -= TIME_CONST;
514 } else {
515 last_tv.tv_sec--;
516 last_tv.tv_usec += 1000000 -
517 TIME_CONST;
518 }
519 }
520 last_intr_tv = curr_tv;
521 if (data) {
522 /*
523 * start timer for end of
524 * sequence detection
525 */
526 timerlist.expires = jiffies +
527 SIR_TIMEOUT;
528 add_timer(&timerlist);
529 }
530
531 lsr = inb(io + UART_LSR);
532 } while (lsr & UART_LSR_DR); /* data ready */
533 spin_unlock_irqrestore(&timer_lock, flags);
534 break;
535 default:
536 break;
537 }
538 }
404f3e95
JW		 539 return IRQ_RETVAL(IRQ_HANDLED);
540}
541
404f3e95
JW		 542static void send_space(unsigned long len)
543{
544 safe_udelay(len);
545}
546
547static void send_pulse(unsigned long len)
548{
549 long bytes_out = len / TIME_CONST;
404f3e95 550
04f561ff 551 if (bytes_out == 0)
404f3e95 552 bytes_out++;
04f561ff 553
404f3e95
JW		 554 while (bytes_out--) {
555 outb(PULSE, io + UART_TX);
556 /* FIXME treba seriozne cakanie z char/serial.c */
557 while (!(inb(io + UART_LSR) & UART_LSR_THRE))
558 ;
559 }
404f3e95 560}
404f3e95
JW		 561
562static int init_hardware(void)
563{
564 unsigned long flags;
565
566 spin_lock_irqsave(&hardware_lock, flags);
567 /* reset UART */
c72374ff 568#if defined(LIRC_SIR_TEKRAM)
404f3e95
JW		 569 /* disable FIFO */
570 soutp(UART_FCR,
571 UART_FCR_CLEAR_RCVR|
572 UART_FCR_CLEAR_XMIT|
573 UART_FCR_TRIGGER_1);
574
575 /* Set DLAB 0. */
576 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
577
578 /* First of all, disable all interrupts */
579 soutp(UART_IER, sinp(UART_IER) &
580 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
581
582 /* Set DLAB 1. */
583 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
584
585 /* Set divisor to 12 => 9600 Baud */
586 soutp(UART_DLM, 0);
587 soutp(UART_DLL, 12);
588
589 /* Set DLAB 0. */
590 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
591
592 /* power supply */
593 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
594 safe_udelay(50*1000);
595
596 /* -DTR low -> reset PIC */
597 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
598 udelay(1*1000);
599
600 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
601 udelay(100);
602
603
604 /* -RTS low -> send control byte */
605 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
606 udelay(7);
607 soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
608
609 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
610 udelay(1500);
611
612 /* back to normal operation */
613 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
614 udelay(50);
615
616 udelay(1500);
617
618 /* read previous control byte */
014f0066 619 pr_info("0x%02x\n", sinp(UART_RX));
404f3e95
JW		 620
621 /* Set DLAB 1. */
622 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
623
624 /* Set divisor to 1 => 115200 Baud */
625 soutp(UART_DLM, 0);
626 soutp(UART_DLL, 1);
627
628 /* Set DLAB 0, 8 Bit */
629 soutp(UART_LCR, UART_LCR_WLEN8);
630 /* enable interrupts */
631 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
632#else
633 outb(0, io + UART_MCR);
634 outb(0, io + UART_IER);
635 /* init UART */
636 /* set DLAB, speed = 115200 */
637 outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
638 outb(1, io + UART_DLL); outb(0, io + UART_DLM);
639 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
640 outb(UART_LCR_WLEN7, io + UART_LCR);
641 /* FIFO operation */
642 outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
643 /* interrupts */
644 /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
645 outb(UART_IER_RDI, io + UART_IER);
646 /* turn on UART */
647 outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
648#ifdef LIRC_SIR_ACTISYS_ACT200L
649 init_act200();
650#elif defined(LIRC_SIR_ACTISYS_ACT220L)
651 init_act220();
652#endif
653#endif
654 spin_unlock_irqrestore(&hardware_lock, flags);
655 return 0;
656}
657
658static void drop_hardware(void)
659{
660 unsigned long flags;
661
662 spin_lock_irqsave(&hardware_lock, flags);
663
404f3e95
JW		 664 /* turn off interrupts */
665 outb(0, io + UART_IER);
c72374ff 666
404f3e95
JW		 667 spin_unlock_irqrestore(&hardware_lock, flags);
668}
669
670/* SECTION: Initialisation */
671
672static int init_port(void)
673{
674 int retval;
675
676 /* get I/O port access and IRQ line */
404f3e95 677 if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) {
014f0066 678 pr_err("i/o port 0x%.4x already in use.\n", io);
404f3e95
JW		 679 return -EBUSY;
680 }
18e9351e 681 retval = request_irq(irq, sir_interrupt, 0,
404f3e95
JW		 682 LIRC_DRIVER_NAME, NULL);
683 if (retval < 0) {
404f3e95 684 release_region(io, 8);
014f0066 685 pr_err("IRQ %d already in use.\n", irq);
404f3e95
JW		 686 return retval;
687 }
014f0066 688 pr_info("I/O port 0x%.4x, IRQ %d.\n", io, irq);
404f3e95
JW		 689
690 init_timer(&timerlist);
691 timerlist.function = sir_timeout;
692 timerlist.data = 0xabadcafe;
693
694 return 0;
695}
696
697static void drop_port(void)
698{
699 free_irq(irq, NULL);
700 del_timer_sync(&timerlist);
404f3e95 701 release_region(io, 8);
404f3e95
JW		 702}
703
704#ifdef LIRC_SIR_ACTISYS_ACT200L
705/* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
706/* some code borrowed from Linux IRDA driver */
707
708/* Register 0: Control register #1 */
709#define ACT200L_REG0 0x00
710#define ACT200L_TXEN 0x01 /* Enable transmitter */
711#define ACT200L_RXEN 0x02 /* Enable receiver */
712#define ACT200L_ECHO 0x08 /* Echo control chars */
713
714/* Register 1: Control register #2 */
715#define ACT200L_REG1 0x10
716#define ACT200L_LODB 0x01 /* Load new baud rate count value */
717#define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */
718
719/* Register 3: Transmit mode register #2 */
720#define ACT200L_REG3 0x30
721#define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
722#define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
723#define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */
724
725/* Register 4: Output Power register */
726#define ACT200L_REG4 0x40
727#define ACT200L_OP0 0x01 /* Enable LED1C output */
728#define ACT200L_OP1 0x02 /* Enable LED2C output */
729#define ACT200L_BLKR 0x04
730
731/* Register 5: Receive Mode register */
732#define ACT200L_REG5 0x50
733#define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */
734 /*.. other various IRDA bit modes, and TV remote modes..*/
735
736/* Register 6: Receive Sensitivity register #1 */
737#define ACT200L_REG6 0x60
738#define ACT200L_RS0 0x01 /* receive threshold bit 0 */
739#define ACT200L_RS1 0x02 /* receive threshold bit 1 */
740
741/* Register 7: Receive Sensitivity register #2 */
742#define ACT200L_REG7 0x70
743#define ACT200L_ENPOS 0x04 /* Ignore the falling edge */
744
745/* Register 8,9: Baud Rate Divider register #1,#2 */
746#define ACT200L_REG8 0x80
747#define ACT200L_REG9 0x90
748
749#define ACT200L_2400 0x5f
750#define ACT200L_9600 0x17
751#define ACT200L_19200 0x0b
752#define ACT200L_38400 0x05
753#define ACT200L_57600 0x03
754#define ACT200L_115200 0x01
755
756/* Register 13: Control register #3 */
757#define ACT200L_REG13 0xd0
758#define ACT200L_SHDW 0x01 /* Enable access to shadow registers */
759
760/* Register 15: Status register */
761#define ACT200L_REG15 0xf0
762
763/* Register 21: Control register #4 */
764#define ACT200L_REG21 0x50
765#define ACT200L_EXCK 0x02 /* Disable clock output driver */
766#define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */
767
768static void init_act200(void)
769{
770 int i;
771 __u8 control[] = {
772 ACT200L_REG15,
773 ACT200L_REG13 | ACT200L_SHDW,
774 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
775 ACT200L_REG13,
776 ACT200L_REG7 | ACT200L_ENPOS,
777 ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1,
778 ACT200L_REG5 | ACT200L_RWIDL,
779 ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR,
780 ACT200L_REG3 | ACT200L_B0,
781 ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN,
782 ACT200L_REG8 | (ACT200L_115200 & 0x0f),
783 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
784 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
785 };
786
787 /* Set DLAB 1. */
788 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
789
790 /* Set divisor to 12 => 9600 Baud */
791 soutp(UART_DLM, 0);
792 soutp(UART_DLL, 12);
793
794 /* Set DLAB 0. */
795 soutp(UART_LCR, UART_LCR_WLEN8);
796 /* Set divisor to 12 => 9600 Baud */
797
798 /* power supply */
799 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
800 for (i = 0; i < 50; i++)
801 safe_udelay(1000);
802
803 /* Reset the dongle : set RTS low for 25 ms */
804 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
805 for (i = 0; i < 25; i++)
806 udelay(1000);
807
808 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
809 udelay(100);
810
811 /* Clear DTR and set RTS to enter command mode */
812 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
813 udelay(7);
814
815 /* send out the control register settings for 115K 7N1 SIR operation */
816 for (i = 0; i < sizeof(control); i++) {
817 soutp(UART_TX, control[i]);
818 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
819 udelay(1500);
820 }
821
822 /* back to normal operation */
823 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
824 udelay(50);
825
826 udelay(1500);
827 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
828
829 /* Set DLAB 1. */
830 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
831
832 /* Set divisor to 1 => 115200 Baud */
833 soutp(UART_DLM, 0);
834 soutp(UART_DLL, 1);
835
836 /* Set DLAB 0. */
837 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
838
839 /* Set DLAB 0, 7 Bit */
840 soutp(UART_LCR, UART_LCR_WLEN7);
841
842 /* enable interrupts */
843 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
844}
845#endif
846
847#ifdef LIRC_SIR_ACTISYS_ACT220L
848/*
849 * Derived from linux IrDA driver (net/irda/actisys.c)
850 * Drop me a mail for any kind of comment: maxx@spaceboyz.net
851 */
852
853void init_act220(void)
854{
855 int i;
856
857 /* DLAB 1 */
858 soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
859
860 /* 9600 baud */
861 soutp(UART_DLM, 0);
862 soutp(UART_DLL, 12);
863
864 /* DLAB 0 */
865 soutp(UART_LCR, UART_LCR_WLEN7);
866
867 /* reset the dongle, set DTR low for 10us */
868 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
869 udelay(10);
870
871 /* back to normal (still 9600) */
872 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
873
874 /*
875 * send RTS pulses until we reach 115200
876 * i hope this is really the same for act220l/act220l+
877 */
878 for (i = 0; i < 3; i++) {
879 udelay(10);
880 /* set RTS low for 10 us */
881 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
882 udelay(10);
883 /* set RTS high for 10 us */
884 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
885 }
886
887 /* back to normal operation */
888 udelay(1500); /* better safe than sorry ;) */
889
890 /* Set DLAB 1. */
891 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
892
893 /* Set divisor to 1 => 115200 Baud */
894 soutp(UART_DLM, 0);
895 soutp(UART_DLL, 1);
896
897 /* Set DLAB 0, 7 Bit */
898 /* The dongle doesn't seem to have any problems with operation at 7N1 */
899 soutp(UART_LCR, UART_LCR_WLEN7);
900
901 /* enable interrupts */
902 soutp(UART_IER, UART_IER_RDI);
903}
904#endif
905
906static int init_lirc_sir(void)
907{
908 int retval;
909
910 init_waitqueue_head(&lirc_read_queue);
911 retval = init_port();
912 if (retval < 0)
913 return retval;
914 init_hardware();
014f0066 915 pr_info("Installed.\n");
404f3e95
JW		 916 return 0;
917}
918
fd8413a2 919static int lirc_sir_probe(struct platform_device *dev)
4b71ca6b
JW		 920{
921 return 0;
922}
923
6dd11195 924static int lirc_sir_remove(struct platform_device *dev)
4b71ca6b
JW		 925{
926 return 0;
927}
928
929static struct platform_driver lirc_sir_driver = {
930 .probe = lirc_sir_probe,
01f6f49b 931 .remove = lirc_sir_remove,
4b71ca6b
JW		 932 .driver = {
933 .name = "lirc_sir",
934 .owner = THIS_MODULE,
935 },
936};
404f3e95
JW		 937
938static int __init lirc_sir_init(void)
939{
940 int retval;
941
4b71ca6b
JW		 942 retval = platform_driver_register(&lirc_sir_driver);
943 if (retval) {
014f0066 944 pr_err("Platform driver register failed!\n");
4b71ca6b
JW		 945 return -ENODEV;
946 }
947
948 lirc_sir_dev = platform_device_alloc("lirc_dev", 0);
949 if (!lirc_sir_dev) {
014f0066 950 pr_err("Platform device alloc failed!\n");
4b71ca6b
JW		 951 retval = -ENOMEM;
952 goto pdev_alloc_fail;
953 }
954
955 retval = platform_device_add(lirc_sir_dev);
956 if (retval) {
014f0066 957 pr_err("Platform device add failed!\n");
4b71ca6b
JW		 958 retval = -ENODEV;
959 goto pdev_add_fail;
960 }
961
404f3e95
JW		 962 retval = init_chrdev();
963 if (retval < 0)
4b71ca6b
JW		 964 goto fail;
965
404f3e95
JW		 966 retval = init_lirc_sir();
967 if (retval) {
968 drop_chrdev();
4b71ca6b 969 goto fail;
404f3e95 970 }
4b71ca6b 971
404f3e95 972 return 0;
4b71ca6b
JW		 973
974fail:
975 platform_device_del(lirc_sir_dev);
976pdev_add_fail:
977 platform_device_put(lirc_sir_dev);
978pdev_alloc_fail:
979 platform_driver_unregister(&lirc_sir_driver);
980 return retval;
404f3e95
JW		 981}
982
983static void __exit lirc_sir_exit(void)
984{
985 drop_hardware();
986 drop_chrdev();
987 drop_port();
4b71ca6b
JW		 988 platform_device_unregister(lirc_sir_dev);
989 platform_driver_unregister(&lirc_sir_driver);
014f0066 990 pr_info("Uninstalled.\n");
404f3e95
JW		 991}
992
993module_init(lirc_sir_init);
994module_exit(lirc_sir_exit);
995
996#ifdef LIRC_SIR_TEKRAM
997MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
998MODULE_AUTHOR("Christoph Bartelmus");
404f3e95
JW		 999#elif defined(LIRC_SIR_ACTISYS_ACT200L)
1000MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
1001MODULE_AUTHOR("Karl Bongers");
1002#elif defined(LIRC_SIR_ACTISYS_ACT220L)
1003MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
1004MODULE_AUTHOR("Jan Roemisch");
1005#else
1006MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
1007MODULE_AUTHOR("Milan Pikula");
1008#endif
1009MODULE_LICENSE("GPL");
1010
404f3e95
JW		 1011module_param(io, int, S_IRUGO);
1012MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
1013
1014module_param(irq, int, S_IRUGO);
1015MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
1016
1017module_param(threshold, int, S_IRUGO);
1018MODULE_PARM_DESC(threshold, "space detection threshold (3)");
404f3e95
JW		 1019
1020module_param(debug, bool, S_IRUGO | S_IWUSR);
1021MODULE_PARM_DESC(debug, "Enable debugging messages");
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