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[media] staging/media: Use dev_ or pr_ printks in lirc/lirc_sasem.c
[mirror_ubuntu-artful-kernel.git] / drivers / staging / media / lirc / lirc_sir.c
CommitLineData
404f3e95
JW		 1/*
2 * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
3 *
4 * lirc_sir - Device driver for use with SIR (serial infra red)
5 * mode of IrDA on many notebooks.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 *
22 * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
23 * added timeout and relaxed pulse detection, removed gap bug
24 *
25 * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
26 * added support for Tekram Irmate 210 (sending does not work yet,
27 * kind of disappointing that nobody was able to implement that
28 * before),
29 * major clean-up
30 *
31 * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
32 * added support for StrongARM SA1100 embedded microprocessor
33 * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
34 */
35
36#include <linux/module.h>
37#include <linux/sched.h>
38#include <linux/errno.h>
39#include <linux/signal.h>
40#include <linux/fs.h>
41#include <linux/interrupt.h>
42#include <linux/ioport.h>
43#include <linux/kernel.h>
44#include <linux/serial_reg.h>
45#include <linux/time.h>
46#include <linux/string.h>
47#include <linux/types.h>
48#include <linux/wait.h>
49#include <linux/mm.h>
50#include <linux/delay.h>
51#include <linux/poll.h>
404f3e95
JW		 52#include <linux/io.h>
53#include <asm/irq.h>
54#include <linux/fcntl.h>
4b71ca6b 55#include <linux/platform_device.h>
404f3e95
JW		 56#ifdef LIRC_ON_SA1100
57#include <asm/hardware.h>
58#ifdef CONFIG_SA1100_COLLIE
59#include <asm/arch/tc35143.h>
60#include <asm/ucb1200.h>
61#endif
62#endif
63
64#include <linux/timer.h>
65
66#include <media/lirc.h>
67#include <media/lirc_dev.h>
68
69/* SECTION: Definitions */
70
71/*** Tekram dongle ***/
72#ifdef LIRC_SIR_TEKRAM
73/* stolen from kernel source */
74/* definitions for Tekram dongle */
75#define TEKRAM_115200 0x00
76#define TEKRAM_57600 0x01
77#define TEKRAM_38400 0x02
78#define TEKRAM_19200 0x03
79#define TEKRAM_9600 0x04
80#define TEKRAM_2400 0x08
81
82#define TEKRAM_PW 0x10 /* Pulse select bit */
83
84/* 10bit * 1s/115200bit in milliseconds = 87ms*/
85#define TIME_CONST (10000000ul/115200ul)
86
87#endif
88
89#ifdef LIRC_SIR_ACTISYS_ACT200L
90static void init_act200(void);
91#elif defined(LIRC_SIR_ACTISYS_ACT220L)
92static void init_act220(void);
93#endif
94
95/*** SA1100 ***/
96#ifdef LIRC_ON_SA1100
97struct sa1100_ser2_registers {
98 /* HSSP control register */
99 unsigned char hscr0;
100 /* UART registers */
101 unsigned char utcr0;
102 unsigned char utcr1;
103 unsigned char utcr2;
104 unsigned char utcr3;
105 unsigned char utcr4;
106 unsigned char utdr;
107 unsigned char utsr0;
108 unsigned char utsr1;
109} sr;
110
111static int irq = IRQ_Ser2ICP;
112
113#define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0
114
115/* pulse/space ratio of 50/50 */
116static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
117/* 1000000/freq-pulse_width */
118static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
119static unsigned int freq = 38000; /* modulation frequency */
120static unsigned int duty_cycle = 50; /* duty cycle of 50% */
121
122#endif
123
124#define RBUF_LEN 1024
125#define WBUF_LEN 1024
126
127#define LIRC_DRIVER_NAME "lirc_sir"
128
129#define PULSE '['
130
131#ifndef LIRC_SIR_TEKRAM
132/* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
133#define TIME_CONST (9000000ul/115200ul)
134#endif
135
136
137/* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
138#define SIR_TIMEOUT (HZ*5/100)
139
140#ifndef LIRC_ON_SA1100
141#ifndef LIRC_IRQ
142#define LIRC_IRQ 4
143#endif
144#ifndef LIRC_PORT
145/* for external dongles, default to com1 */
d713680f
GD		 146#if defined(LIRC_SIR_ACTISYS_ACT200L) || \
147 defined(LIRC_SIR_ACTISYS_ACT220L) || \
148 defined(LIRC_SIR_TEKRAM)
404f3e95
JW		 149#define LIRC_PORT 0x3f8
150#else
151/* onboard sir ports are typically com3 */
152#define LIRC_PORT 0x3e8
153#endif
154#endif
155
156static int io = LIRC_PORT;
157static int irq = LIRC_IRQ;
158static int threshold = 3;
159#endif
160
161static DEFINE_SPINLOCK(timer_lock);
162static struct timer_list timerlist;
163/* time of last signal change detected */
164static struct timeval last_tv = {0, 0};
165/* time of last UART data ready interrupt */
166static struct timeval last_intr_tv = {0, 0};
167static int last_value;
168
169static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue);
170
171static DEFINE_SPINLOCK(hardware_lock);
172
173static int rx_buf[RBUF_LEN];
174static unsigned int rx_tail, rx_head;
175
90ab5ee9 176static bool debug;
404f3e95
JW		 177#define dprintk(fmt, args...) \
178 do { \
179 if (debug) \
180 printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \
181 fmt, ## args); \
182 } while (0)
183
184/* SECTION: Prototypes */
185
186/* Communication with user-space */
187static unsigned int lirc_poll(struct file *file, poll_table *wait);
188static ssize_t lirc_read(struct file *file, char *buf, size_t count,
189 loff_t *ppos);
190static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
191 loff_t *pos);
192static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
193static void add_read_queue(int flag, unsigned long val);
194static int init_chrdev(void);
195static void drop_chrdev(void);
196/* Hardware */
197static irqreturn_t sir_interrupt(int irq, void *dev_id);
198static void send_space(unsigned long len);
199static void send_pulse(unsigned long len);
200static int init_hardware(void);
201static void drop_hardware(void);
202/* Initialisation */
203static int init_port(void);
204static void drop_port(void);
205
206#ifdef LIRC_ON_SA1100
207static void on(void)
208{
209 PPSR |= PPC_TXD2;
210}
211
212static void off(void)
213{
214 PPSR &= ~PPC_TXD2;
215}
216#else
217static inline unsigned int sinp(int offset)
218{
219 return inb(io + offset);
220}
221
222static inline void soutp(int offset, int value)
223{
224 outb(value, io + offset);
225}
226#endif
227
228#ifndef MAX_UDELAY_MS
229#define MAX_UDELAY_US 5000
230#else
231#define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
232#endif
233
234static void safe_udelay(unsigned long usecs)
235{
236 while (usecs > MAX_UDELAY_US) {
237 udelay(MAX_UDELAY_US);
238 usecs -= MAX_UDELAY_US;
239 }
240 udelay(usecs);
241}
242
243/* SECTION: Communication with user-space */
244
245static unsigned int lirc_poll(struct file *file, poll_table *wait)
246{
247 poll_wait(file, &lirc_read_queue, wait);
248 if (rx_head != rx_tail)
249 return POLLIN | POLLRDNORM;
250 return 0;
251}
252
253static ssize_t lirc_read(struct file *file, char *buf, size_t count,
254 loff_t *ppos)
255{
256 int n = 0;
257 int retval = 0;
258 DECLARE_WAITQUEUE(wait, current);
259
260 if (count % sizeof(int))
261 return -EINVAL;
262
263 add_wait_queue(&lirc_read_queue, &wait);
264 set_current_state(TASK_INTERRUPTIBLE);
265 while (n < count) {
266 if (rx_head != rx_tail) {
267 if (copy_to_user((void *) buf + n,
268 (void *) (rx_buf + rx_head),
269 sizeof(int))) {
270 retval = -EFAULT;
271 break;
272 }
273 rx_head = (rx_head + 1) & (RBUF_LEN - 1);
274 n += sizeof(int);
275 } else {
276 if (file->f_flags & O_NONBLOCK) {
277 retval = -EAGAIN;
278 break;
279 }
280 if (signal_pending(current)) {
281 retval = -ERESTARTSYS;
282 break;
283 }
284 schedule();
285 set_current_state(TASK_INTERRUPTIBLE);
286 }
287 }
288 remove_wait_queue(&lirc_read_queue, &wait);
289 set_current_state(TASK_RUNNING);
290 return n ? n : retval;
291}
292static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
293 loff_t *pos)
294{
295 unsigned long flags;
296 int i, count;
297 int *tx_buf;
298
299 count = n / sizeof(int);
300 if (n % sizeof(int) || count % 2 == 0)
301 return -EINVAL;
302 tx_buf = memdup_user(buf, n);
303 if (IS_ERR(tx_buf))
304 return PTR_ERR(tx_buf);
305 i = 0;
306#ifdef LIRC_ON_SA1100
307 /* disable receiver */
308 Ser2UTCR3 = 0;
309#endif
310 local_irq_save(flags);
311 while (1) {
312 if (i >= count)
313 break;
314 if (tx_buf[i])
315 send_pulse(tx_buf[i]);
316 i++;
317 if (i >= count)
318 break;
319 if (tx_buf[i])
320 send_space(tx_buf[i]);
321 i++;
322 }
323 local_irq_restore(flags);
324#ifdef LIRC_ON_SA1100
325 off();
326 udelay(1000); /* wait 1ms for IR diode to recover */
327 Ser2UTCR3 = 0;
328 /* clear status register to prevent unwanted interrupts */
329 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
330 /* enable receiver */
331 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
332#endif
88914bdf 333 kfree(tx_buf);
404f3e95
JW		 334 return count;
335}
336
337static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
338{
339 int retval = 0;
a1266818 340 __u32 value = 0;
404f3e95 341#ifdef LIRC_ON_SA1100
404f3e95
JW		 342
343 if (cmd == LIRC_GET_FEATURES)
344 value = LIRC_CAN_SEND_PULSE |
345 LIRC_CAN_SET_SEND_DUTY_CYCLE |
346 LIRC_CAN_SET_SEND_CARRIER |
347 LIRC_CAN_REC_MODE2;
348 else if (cmd == LIRC_GET_SEND_MODE)
349 value = LIRC_MODE_PULSE;
350 else if (cmd == LIRC_GET_REC_MODE)
351 value = LIRC_MODE_MODE2;
352#else
353 if (cmd == LIRC_GET_FEATURES)
354 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2;
355 else if (cmd == LIRC_GET_SEND_MODE)
356 value = LIRC_MODE_PULSE;
357 else if (cmd == LIRC_GET_REC_MODE)
358 value = LIRC_MODE_MODE2;
359#endif
360
361 switch (cmd) {
362 case LIRC_GET_FEATURES:
363 case LIRC_GET_SEND_MODE:
364 case LIRC_GET_REC_MODE:
a1266818 365 retval = put_user(value, (__u32 *) arg);
404f3e95
JW		 366 break;
367
368 case LIRC_SET_SEND_MODE:
369 case LIRC_SET_REC_MODE:
a1266818 370 retval = get_user(value, (__u32 *) arg);
404f3e95
JW		 371 break;
372#ifdef LIRC_ON_SA1100
373 case LIRC_SET_SEND_DUTY_CYCLE:
a1266818 374 retval = get_user(value, (__u32 *) arg);
404f3e95
JW		 375 if (retval)
376 return retval;
a1266818 377 if (value <= 0 || value > 100)
404f3e95 378 return -EINVAL;
a1266818
JW		 379 /* (value/100)*(1000000/freq) */
380 duty_cycle = value;
404f3e95
JW		 381 pulse_width = (unsigned long) duty_cycle*10000/freq;
382 space_width = (unsigned long) 1000000L/freq-pulse_width;
383 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
384 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
385 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
386 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
387 break;
388 case LIRC_SET_SEND_CARRIER:
a1266818 389 retval = get_user(value, (__u32 *) arg);
404f3e95
JW		 390 if (retval)
391 return retval;
a1266818 392 if (value > 500000 || value < 20000)
404f3e95 393 return -EINVAL;
a1266818 394 freq = value;
404f3e95
JW		 395 pulse_width = (unsigned long) duty_cycle*10000/freq;
396 space_width = (unsigned long) 1000000L/freq-pulse_width;
397 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
398 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
399 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
400 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
401 break;
402#endif
403 default:
404 retval = -ENOIOCTLCMD;
405
406 }
407
408 if (retval)
409 return retval;
410 if (cmd == LIRC_SET_REC_MODE) {
411 if (value != LIRC_MODE_MODE2)
412 retval = -ENOSYS;
413 } else if (cmd == LIRC_SET_SEND_MODE) {
414 if (value != LIRC_MODE_PULSE)
415 retval = -ENOSYS;
416 }
417
418 return retval;
419}
420
421static void add_read_queue(int flag, unsigned long val)
422{
423 unsigned int new_rx_tail;
424 int newval;
425
426 dprintk("add flag %d with val %lu\n", flag, val);
427
428 newval = val & PULSE_MASK;
429
430 /*
431 * statistically, pulses are ~TIME_CONST/2 too long. we could
432 * maybe make this more exact, but this is good enough
433 */
434 if (flag) {
435 /* pulse */
436 if (newval > TIME_CONST/2)
437 newval -= TIME_CONST/2;
438 else /* should not ever happen */
439 newval = 1;
440 newval |= PULSE_BIT;
441 } else {
442 newval += TIME_CONST/2;
443 }
444 new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1);
445 if (new_rx_tail == rx_head) {
446 dprintk("Buffer overrun.\n");
447 return;
448 }
449 rx_buf[rx_tail] = newval;
450 rx_tail = new_rx_tail;
451 wake_up_interruptible(&lirc_read_queue);
452}
453
0f9313ad 454static const struct file_operations lirc_fops = {
404f3e95
JW		 455 .owner = THIS_MODULE,
456 .read = lirc_read,
457 .write = lirc_write,
458 .poll = lirc_poll,
459 .unlocked_ioctl = lirc_ioctl,
8be292cc
JW		 460#ifdef CONFIG_COMPAT
461 .compat_ioctl = lirc_ioctl,
462#endif
404f3e95
JW		 463 .open = lirc_dev_fop_open,
464 .release = lirc_dev_fop_close,
d9d2e9d5 465 .llseek = no_llseek,
404f3e95
JW		 466};
467
468static int set_use_inc(void *data)
469{
d713680f 470 return 0;
404f3e95
JW		 471}
472
473static void set_use_dec(void *data)
474{
475}
476
477static struct lirc_driver driver = {
d713680f
GD		 478 .name = LIRC_DRIVER_NAME,
479 .minor = -1,
480 .code_length = 1,
481 .sample_rate = 0,
482 .data = NULL,
483 .add_to_buf = NULL,
484 .set_use_inc = set_use_inc,
485 .set_use_dec = set_use_dec,
486 .fops = &lirc_fops,
487 .dev = NULL,
488 .owner = THIS_MODULE,
404f3e95
JW		 489};
490
4b71ca6b 491static struct platform_device *lirc_sir_dev;
404f3e95
JW		 492
493static int init_chrdev(void)
494{
4b71ca6b 495 driver.dev = &lirc_sir_dev->dev;
404f3e95
JW		 496 driver.minor = lirc_register_driver(&driver);
497 if (driver.minor < 0) {
498 printk(KERN_ERR LIRC_DRIVER_NAME ": init_chrdev() failed.\n");
499 return -EIO;
500 }
501 return 0;
502}
503
504static void drop_chrdev(void)
505{
506 lirc_unregister_driver(driver.minor);
507}
508
509/* SECTION: Hardware */
510static long delta(struct timeval *tv1, struct timeval *tv2)
511{
512 unsigned long deltv;
513
514 deltv = tv2->tv_sec - tv1->tv_sec;
515 if (deltv > 15)
516 deltv = 0xFFFFFF;
517 else
518 deltv = deltv*1000000 +
519 tv2->tv_usec -
520 tv1->tv_usec;
521 return deltv;
522}
523
524static void sir_timeout(unsigned long data)
525{
526 /*
527 * if last received signal was a pulse, but receiving stopped
528 * within the 9 bit frame, we need to finish this pulse and
529 * simulate a signal change to from pulse to space. Otherwise
530 * upper layers will receive two sequences next time.
531 */
532
533 unsigned long flags;
534 unsigned long pulse_end;
535
536 /* avoid interference with interrupt */
537 spin_lock_irqsave(&timer_lock, flags);
538 if (last_value) {
539#ifndef LIRC_ON_SA1100
540 /* clear unread bits in UART and restart */
541 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
542#endif
543 /* determine 'virtual' pulse end: */
544 pulse_end = delta(&last_tv, &last_intr_tv);
545 dprintk("timeout add %d for %lu usec\n", last_value, pulse_end);
546 add_read_queue(last_value, pulse_end);
547 last_value = 0;
548 last_tv = last_intr_tv;
549 }
550 spin_unlock_irqrestore(&timer_lock, flags);
551}
552
553static irqreturn_t sir_interrupt(int irq, void *dev_id)
554{
555 unsigned char data;
556 struct timeval curr_tv;
557 static unsigned long deltv;
558#ifdef LIRC_ON_SA1100
559 int status;
560 static int n;
561
562 status = Ser2UTSR0;
563 /*
564 * Deal with any receive errors first. The bytes in error may be
565 * the only bytes in the receive FIFO, so we do this first.
566 */
567 while (status & UTSR0_EIF) {
568 int bstat;
569
570 if (debug) {
571 dprintk("EIF\n");
572 bstat = Ser2UTSR1;
573
574 if (bstat & UTSR1_FRE)
575 dprintk("frame error\n");
576 if (bstat & UTSR1_ROR)
577 dprintk("receive fifo overrun\n");
578 if (bstat & UTSR1_PRE)
579 dprintk("parity error\n");
580 }
581
582 bstat = Ser2UTDR;
583 n++;
584 status = Ser2UTSR0;
585 }
586
587 if (status & (UTSR0_RFS | UTSR0_RID)) {
588 do_gettimeofday(&curr_tv);
589 deltv = delta(&last_tv, &curr_tv);
590 do {
591 data = Ser2UTDR;
592 dprintk("%d data: %u\n", n, (unsigned int) data);
593 n++;
594 } while (status & UTSR0_RID && /* do not empty fifo in order to
595 * get UTSR0_RID in any case */
596 Ser2UTSR1 & UTSR1_RNE); /* data ready */
597
598 if (status&UTSR0_RID) {
599 add_read_queue(0 , deltv - n * TIME_CONST); /*space*/
600 add_read_queue(1, n * TIME_CONST); /*pulse*/
601 n = 0;
602 last_tv = curr_tv;
603 }
604 }
605
606 if (status & UTSR0_TFS)
607 printk(KERN_ERR "transmit fifo not full, shouldn't happen\n");
608
609 /* We must clear certain bits. */
610 status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
611 if (status)
612 Ser2UTSR0 = status;
613#else
614 unsigned long deltintrtv;
615 unsigned long flags;
616 int iir, lsr;
617
618 while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
619 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
620 case UART_IIR_MSI:
621 (void) inb(io + UART_MSR);
622 break;
623 case UART_IIR_RLSI:
624 (void) inb(io + UART_LSR);
625 break;
626 case UART_IIR_THRI:
627#if 0
628 if (lsr & UART_LSR_THRE) /* FIFO is empty */
629 outb(data, io + UART_TX)
630#endif
631 break;
632 case UART_IIR_RDI:
633 /* avoid interference with timer */
634 spin_lock_irqsave(&timer_lock, flags);
635 do {
636 del_timer(&timerlist);
637 data = inb(io + UART_RX);
638 do_gettimeofday(&curr_tv);
639 deltv = delta(&last_tv, &curr_tv);
640 deltintrtv = delta(&last_intr_tv, &curr_tv);
641 dprintk("t %lu, d %d\n", deltintrtv, (int)data);
642 /*
643 * if nothing came in last X cycles,
644 * it was gap
645 */
646 if (deltintrtv > TIME_CONST * threshold) {
647 if (last_value) {
648 dprintk("GAP\n");
649 /* simulate signal change */
650 add_read_queue(last_value,
651 deltv -
652 deltintrtv);
653 last_value = 0;
654 last_tv.tv_sec =
655 last_intr_tv.tv_sec;
656 last_tv.tv_usec =
657 last_intr_tv.tv_usec;
658 deltv = deltintrtv;
659 }
660 }
661 data = 1;
662 if (data ^ last_value) {
663 /*
664 * deltintrtv > 2*TIME_CONST, remember?
665 * the other case is timeout
666 */
667 add_read_queue(last_value,
668 deltv-TIME_CONST);
669 last_value = data;
670 last_tv = curr_tv;
671 if (last_tv.tv_usec >= TIME_CONST) {
672 last_tv.tv_usec -= TIME_CONST;
673 } else {
674 last_tv.tv_sec--;
675 last_tv.tv_usec += 1000000 -
676 TIME_CONST;
677 }
678 }
679 last_intr_tv = curr_tv;
680 if (data) {
681 /*
682 * start timer for end of
683 * sequence detection
684 */
685 timerlist.expires = jiffies +
686 SIR_TIMEOUT;
687 add_timer(&timerlist);
688 }
689
690 lsr = inb(io + UART_LSR);
691 } while (lsr & UART_LSR_DR); /* data ready */
692 spin_unlock_irqrestore(&timer_lock, flags);
693 break;
694 default:
695 break;
696 }
697 }
698#endif
699 return IRQ_RETVAL(IRQ_HANDLED);
700}
701
702#ifdef LIRC_ON_SA1100
703static void send_pulse(unsigned long length)
704{
705 unsigned long k, delay;
706 int flag;
707
708 if (length == 0)
709 return;
710 /*
711 * this won't give us the carrier frequency we really want
712 * due to integer arithmetic, but we can accept this inaccuracy
713 */
714
715 for (k = flag = 0; k < length; k += delay, flag = !flag) {
716 if (flag) {
717 off();
718 delay = space_width;
719 } else {
720 on();
721 delay = pulse_width;
722 }
723 safe_udelay(delay);
724 }
725 off();
726}
727
728static void send_space(unsigned long length)
729{
730 if (length == 0)
731 return;
732 off();
733 safe_udelay(length);
734}
735#else
736static void send_space(unsigned long len)
737{
738 safe_udelay(len);
739}
740
741static void send_pulse(unsigned long len)
742{
743 long bytes_out = len / TIME_CONST;
404f3e95 744
04f561ff 745 if (bytes_out == 0)
404f3e95 746 bytes_out++;
04f561ff 747
404f3e95
JW		 748 while (bytes_out--) {
749 outb(PULSE, io + UART_TX);
750 /* FIXME treba seriozne cakanie z char/serial.c */
751 while (!(inb(io + UART_LSR) & UART_LSR_THRE))
752 ;
753 }
404f3e95
JW		 754}
755#endif
756
757#ifdef CONFIG_SA1100_COLLIE
758static int sa1100_irda_set_power_collie(int state)
759{
760 if (state) {
761 /*
762 * 0 - off
763 * 1 - short range, lowest power
764 * 2 - medium range, medium power
765 * 3 - maximum range, high power
766 */
767 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
768 TC35143_IODIR_OUTPUT);
769 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW);
770 udelay(100);
771 } else {
772 /* OFF */
773 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
774 TC35143_IODIR_OUTPUT);
775 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH);
776 }
777 return 0;
778}
779#endif
780
781static int init_hardware(void)
782{
783 unsigned long flags;
784
785 spin_lock_irqsave(&hardware_lock, flags);
786 /* reset UART */
787#ifdef LIRC_ON_SA1100
788#ifdef CONFIG_SA1100_BITSY
789 if (machine_is_bitsy()) {
790 printk(KERN_INFO "Power on IR module\n");
791 set_bitsy_egpio(EGPIO_BITSY_IR_ON);
792 }
793#endif
794#ifdef CONFIG_SA1100_COLLIE
795 sa1100_irda_set_power_collie(3); /* power on */
796#endif
797 sr.hscr0 = Ser2HSCR0;
798
799 sr.utcr0 = Ser2UTCR0;
800 sr.utcr1 = Ser2UTCR1;
801 sr.utcr2 = Ser2UTCR2;
802 sr.utcr3 = Ser2UTCR3;
803 sr.utcr4 = Ser2UTCR4;
804
805 sr.utdr = Ser2UTDR;
806 sr.utsr0 = Ser2UTSR0;
807 sr.utsr1 = Ser2UTSR1;
808
809 /* configure GPIO */
810 /* output */
811 PPDR |= PPC_TXD2;
812 PSDR |= PPC_TXD2;
813 /* set output to 0 */
814 off();
815
816 /* Enable HP-SIR modulation, and ensure that the port is disabled. */
817 Ser2UTCR3 = 0;
818 Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP);
819
820 /* clear status register to prevent unwanted interrupts */
821 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
822
823 /* 7N1 */
824 Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData;
825 /* 115200 */
826 Ser2UTCR1 = 0;
827 Ser2UTCR2 = 1;
828 /* use HPSIR, 1.6 usec pulses */
829 Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us;
830
831 /* enable receiver, receive fifo interrupt */
832 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
833
834 /* clear status register to prevent unwanted interrupts */
835 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
836
837#elif defined(LIRC_SIR_TEKRAM)
838 /* disable FIFO */
839 soutp(UART_FCR,
840 UART_FCR_CLEAR_RCVR|
841 UART_FCR_CLEAR_XMIT|
842 UART_FCR_TRIGGER_1);
843
844 /* Set DLAB 0. */
845 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
846
847 /* First of all, disable all interrupts */
848 soutp(UART_IER, sinp(UART_IER) &
849 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
850
851 /* Set DLAB 1. */
852 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
853
854 /* Set divisor to 12 => 9600 Baud */
855 soutp(UART_DLM, 0);
856 soutp(UART_DLL, 12);
857
858 /* Set DLAB 0. */
859 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
860
861 /* power supply */
862 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
863 safe_udelay(50*1000);
864
865 /* -DTR low -> reset PIC */
866 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
867 udelay(1*1000);
868
869 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
870 udelay(100);
871
872
873 /* -RTS low -> send control byte */
874 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
875 udelay(7);
876 soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
877
878 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
879 udelay(1500);
880
881 /* back to normal operation */
882 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
883 udelay(50);
884
885 udelay(1500);
886
887 /* read previous control byte */
888 printk(KERN_INFO LIRC_DRIVER_NAME
889 ": 0x%02x\n", sinp(UART_RX));
890
891 /* Set DLAB 1. */
892 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
893
894 /* Set divisor to 1 => 115200 Baud */
895 soutp(UART_DLM, 0);
896 soutp(UART_DLL, 1);
897
898 /* Set DLAB 0, 8 Bit */
899 soutp(UART_LCR, UART_LCR_WLEN8);
900 /* enable interrupts */
901 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
902#else
903 outb(0, io + UART_MCR);
904 outb(0, io + UART_IER);
905 /* init UART */
906 /* set DLAB, speed = 115200 */
907 outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
908 outb(1, io + UART_DLL); outb(0, io + UART_DLM);
909 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
910 outb(UART_LCR_WLEN7, io + UART_LCR);
911 /* FIFO operation */
912 outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
913 /* interrupts */
914 /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
915 outb(UART_IER_RDI, io + UART_IER);
916 /* turn on UART */
917 outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
918#ifdef LIRC_SIR_ACTISYS_ACT200L
919 init_act200();
920#elif defined(LIRC_SIR_ACTISYS_ACT220L)
921 init_act220();
922#endif
923#endif
924 spin_unlock_irqrestore(&hardware_lock, flags);
925 return 0;
926}
927
928static void drop_hardware(void)
929{
930 unsigned long flags;
931
932 spin_lock_irqsave(&hardware_lock, flags);
933
934#ifdef LIRC_ON_SA1100
935 Ser2UTCR3 = 0;
936
937 Ser2UTCR0 = sr.utcr0;
938 Ser2UTCR1 = sr.utcr1;
939 Ser2UTCR2 = sr.utcr2;
940 Ser2UTCR4 = sr.utcr4;
941 Ser2UTCR3 = sr.utcr3;
942
943 Ser2HSCR0 = sr.hscr0;
944#ifdef CONFIG_SA1100_BITSY
945 if (machine_is_bitsy())
946 clr_bitsy_egpio(EGPIO_BITSY_IR_ON);
947#endif
948#ifdef CONFIG_SA1100_COLLIE
949 sa1100_irda_set_power_collie(0); /* power off */
950#endif
951#else
952 /* turn off interrupts */
953 outb(0, io + UART_IER);
954#endif
955 spin_unlock_irqrestore(&hardware_lock, flags);
956}
957
958/* SECTION: Initialisation */
959
960static int init_port(void)
961{
962 int retval;
963
964 /* get I/O port access and IRQ line */
965#ifndef LIRC_ON_SA1100
966 if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) {
967 printk(KERN_ERR LIRC_DRIVER_NAME
968 ": i/o port 0x%.4x already in use.\n", io);
969 return -EBUSY;
970 }
971#endif
18e9351e 972 retval = request_irq(irq, sir_interrupt, 0,
404f3e95
JW		 973 LIRC_DRIVER_NAME, NULL);
974 if (retval < 0) {
975# ifndef LIRC_ON_SA1100
976 release_region(io, 8);
977# endif
978 printk(KERN_ERR LIRC_DRIVER_NAME
979 ": IRQ %d already in use.\n",
980 irq);
981 return retval;
982 }
983#ifndef LIRC_ON_SA1100
984 printk(KERN_INFO LIRC_DRIVER_NAME
985 ": I/O port 0x%.4x, IRQ %d.\n",
986 io, irq);
987#endif
988
989 init_timer(&timerlist);
990 timerlist.function = sir_timeout;
991 timerlist.data = 0xabadcafe;
992
993 return 0;
994}
995
996static void drop_port(void)
997{
998 free_irq(irq, NULL);
999 del_timer_sync(&timerlist);
1000#ifndef LIRC_ON_SA1100
1001 release_region(io, 8);
1002#endif
1003}
1004
1005#ifdef LIRC_SIR_ACTISYS_ACT200L
1006/* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
1007/* some code borrowed from Linux IRDA driver */
1008
1009/* Register 0: Control register #1 */
1010#define ACT200L_REG0 0x00
1011#define ACT200L_TXEN 0x01 /* Enable transmitter */
1012#define ACT200L_RXEN 0x02 /* Enable receiver */
1013#define ACT200L_ECHO 0x08 /* Echo control chars */
1014
1015/* Register 1: Control register #2 */
1016#define ACT200L_REG1 0x10
1017#define ACT200L_LODB 0x01 /* Load new baud rate count value */
1018#define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */
1019
1020/* Register 3: Transmit mode register #2 */
1021#define ACT200L_REG3 0x30
1022#define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
1023#define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
1024#define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */
1025
1026/* Register 4: Output Power register */
1027#define ACT200L_REG4 0x40
1028#define ACT200L_OP0 0x01 /* Enable LED1C output */
1029#define ACT200L_OP1 0x02 /* Enable LED2C output */
1030#define ACT200L_BLKR 0x04
1031
1032/* Register 5: Receive Mode register */
1033#define ACT200L_REG5 0x50
1034#define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */
1035 /*.. other various IRDA bit modes, and TV remote modes..*/
1036
1037/* Register 6: Receive Sensitivity register #1 */
1038#define ACT200L_REG6 0x60
1039#define ACT200L_RS0 0x01 /* receive threshold bit 0 */
1040#define ACT200L_RS1 0x02 /* receive threshold bit 1 */
1041
1042/* Register 7: Receive Sensitivity register #2 */
1043#define ACT200L_REG7 0x70
1044#define ACT200L_ENPOS 0x04 /* Ignore the falling edge */
1045
1046/* Register 8,9: Baud Rate Divider register #1,#2 */
1047#define ACT200L_REG8 0x80
1048#define ACT200L_REG9 0x90
1049
1050#define ACT200L_2400 0x5f
1051#define ACT200L_9600 0x17
1052#define ACT200L_19200 0x0b
1053#define ACT200L_38400 0x05
1054#define ACT200L_57600 0x03
1055#define ACT200L_115200 0x01
1056
1057/* Register 13: Control register #3 */
1058#define ACT200L_REG13 0xd0
1059#define ACT200L_SHDW 0x01 /* Enable access to shadow registers */
1060
1061/* Register 15: Status register */
1062#define ACT200L_REG15 0xf0
1063
1064/* Register 21: Control register #4 */
1065#define ACT200L_REG21 0x50
1066#define ACT200L_EXCK 0x02 /* Disable clock output driver */
1067#define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */
1068
1069static void init_act200(void)
1070{
1071 int i;
1072 __u8 control[] = {
1073 ACT200L_REG15,
1074 ACT200L_REG13 | ACT200L_SHDW,
1075 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
1076 ACT200L_REG13,
1077 ACT200L_REG7 | ACT200L_ENPOS,
1078 ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1,
1079 ACT200L_REG5 | ACT200L_RWIDL,
1080 ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR,
1081 ACT200L_REG3 | ACT200L_B0,
1082 ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN,
1083 ACT200L_REG8 | (ACT200L_115200 & 0x0f),
1084 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
1085 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
1086 };
1087
1088 /* Set DLAB 1. */
1089 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
1090
1091 /* Set divisor to 12 => 9600 Baud */
1092 soutp(UART_DLM, 0);
1093 soutp(UART_DLL, 12);
1094
1095 /* Set DLAB 0. */
1096 soutp(UART_LCR, UART_LCR_WLEN8);
1097 /* Set divisor to 12 => 9600 Baud */
1098
1099 /* power supply */
1100 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1101 for (i = 0; i < 50; i++)
1102 safe_udelay(1000);
1103
1104 /* Reset the dongle : set RTS low for 25 ms */
1105 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1106 for (i = 0; i < 25; i++)
1107 udelay(1000);
1108
1109 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1110 udelay(100);
1111
1112 /* Clear DTR and set RTS to enter command mode */
1113 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1114 udelay(7);
1115
1116 /* send out the control register settings for 115K 7N1 SIR operation */
1117 for (i = 0; i < sizeof(control); i++) {
1118 soutp(UART_TX, control[i]);
1119 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
1120 udelay(1500);
1121 }
1122
1123 /* back to normal operation */
1124 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1125 udelay(50);
1126
1127 udelay(1500);
1128 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
1129
1130 /* Set DLAB 1. */
1131 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1132
1133 /* Set divisor to 1 => 115200 Baud */
1134 soutp(UART_DLM, 0);
1135 soutp(UART_DLL, 1);
1136
1137 /* Set DLAB 0. */
1138 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
1139
1140 /* Set DLAB 0, 7 Bit */
1141 soutp(UART_LCR, UART_LCR_WLEN7);
1142
1143 /* enable interrupts */
1144 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
1145}
1146#endif
1147
1148#ifdef LIRC_SIR_ACTISYS_ACT220L
1149/*
1150 * Derived from linux IrDA driver (net/irda/actisys.c)
1151 * Drop me a mail for any kind of comment: maxx@spaceboyz.net
1152 */
1153
1154void init_act220(void)
1155{
1156 int i;
1157
1158 /* DLAB 1 */
1159 soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
1160
1161 /* 9600 baud */
1162 soutp(UART_DLM, 0);
1163 soutp(UART_DLL, 12);
1164
1165 /* DLAB 0 */
1166 soutp(UART_LCR, UART_LCR_WLEN7);
1167
1168 /* reset the dongle, set DTR low for 10us */
1169 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1170 udelay(10);
1171
1172 /* back to normal (still 9600) */
1173 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
1174
1175 /*
1176 * send RTS pulses until we reach 115200
1177 * i hope this is really the same for act220l/act220l+
1178 */
1179 for (i = 0; i < 3; i++) {
1180 udelay(10);
1181 /* set RTS low for 10 us */
1182 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1183 udelay(10);
1184 /* set RTS high for 10 us */
1185 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1186 }
1187
1188 /* back to normal operation */
1189 udelay(1500); /* better safe than sorry ;) */
1190
1191 /* Set DLAB 1. */
1192 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1193
1194 /* Set divisor to 1 => 115200 Baud */
1195 soutp(UART_DLM, 0);
1196 soutp(UART_DLL, 1);
1197
1198 /* Set DLAB 0, 7 Bit */
1199 /* The dongle doesn't seem to have any problems with operation at 7N1 */
1200 soutp(UART_LCR, UART_LCR_WLEN7);
1201
1202 /* enable interrupts */
1203 soutp(UART_IER, UART_IER_RDI);
1204}
1205#endif
1206
1207static int init_lirc_sir(void)
1208{
1209 int retval;
1210
1211 init_waitqueue_head(&lirc_read_queue);
1212 retval = init_port();
1213 if (retval < 0)
1214 return retval;
1215 init_hardware();
1216 printk(KERN_INFO LIRC_DRIVER_NAME
1217 ": Installed.\n");
1218 return 0;
1219}
1220
4b71ca6b
JW		 1221static int __devinit lirc_sir_probe(struct platform_device *dev)
1222{
1223 return 0;
1224}
1225
1226static int __devexit lirc_sir_remove(struct platform_device *dev)
1227{
1228 return 0;
1229}
1230
1231static struct platform_driver lirc_sir_driver = {
1232 .probe = lirc_sir_probe,
1233 .remove = __devexit_p(lirc_sir_remove),
1234 .driver = {
1235 .name = "lirc_sir",
1236 .owner = THIS_MODULE,
1237 },
1238};
404f3e95
JW		 1239
1240static int __init lirc_sir_init(void)
1241{
1242 int retval;
1243
4b71ca6b
JW		 1244 retval = platform_driver_register(&lirc_sir_driver);
1245 if (retval) {
1246 printk(KERN_ERR LIRC_DRIVER_NAME ": Platform driver register "
1247 "failed!\n");
1248 return -ENODEV;
1249 }
1250
1251 lirc_sir_dev = platform_device_alloc("lirc_dev", 0);
1252 if (!lirc_sir_dev) {
1253 printk(KERN_ERR LIRC_DRIVER_NAME ": Platform device alloc "
1254 "failed!\n");
1255 retval = -ENOMEM;
1256 goto pdev_alloc_fail;
1257 }
1258
1259 retval = platform_device_add(lirc_sir_dev);
1260 if (retval) {
1261 printk(KERN_ERR LIRC_DRIVER_NAME ": Platform device add "
1262 "failed!\n");
1263 retval = -ENODEV;
1264 goto pdev_add_fail;
1265 }
1266
404f3e95
JW		 1267 retval = init_chrdev();
1268 if (retval < 0)
4b71ca6b
JW		 1269 goto fail;
1270
404f3e95
JW		 1271 retval = init_lirc_sir();
1272 if (retval) {
1273 drop_chrdev();
4b71ca6b 1274 goto fail;
404f3e95 1275 }
4b71ca6b 1276
404f3e95 1277 return 0;
4b71ca6b
JW		 1278
1279fail:
1280 platform_device_del(lirc_sir_dev);
1281pdev_add_fail:
1282 platform_device_put(lirc_sir_dev);
1283pdev_alloc_fail:
1284 platform_driver_unregister(&lirc_sir_driver);
1285 return retval;
404f3e95
JW		 1286}
1287
1288static void __exit lirc_sir_exit(void)
1289{
1290 drop_hardware();
1291 drop_chrdev();
1292 drop_port();
4b71ca6b
JW		 1293 platform_device_unregister(lirc_sir_dev);
1294 platform_driver_unregister(&lirc_sir_driver);
404f3e95
JW		 1295 printk(KERN_INFO LIRC_DRIVER_NAME ": Uninstalled.\n");
1296}
1297
1298module_init(lirc_sir_init);
1299module_exit(lirc_sir_exit);
1300
1301#ifdef LIRC_SIR_TEKRAM
1302MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
1303MODULE_AUTHOR("Christoph Bartelmus");
1304#elif defined(LIRC_ON_SA1100)
1305MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor");
1306MODULE_AUTHOR("Christoph Bartelmus");
1307#elif defined(LIRC_SIR_ACTISYS_ACT200L)
1308MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
1309MODULE_AUTHOR("Karl Bongers");
1310#elif defined(LIRC_SIR_ACTISYS_ACT220L)
1311MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
1312MODULE_AUTHOR("Jan Roemisch");
1313#else
1314MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
1315MODULE_AUTHOR("Milan Pikula");
1316#endif
1317MODULE_LICENSE("GPL");
1318
1319#ifdef LIRC_ON_SA1100
1320module_param(irq, int, S_IRUGO);
1321MODULE_PARM_DESC(irq, "Interrupt (16)");
1322#else
1323module_param(io, int, S_IRUGO);
1324MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
1325
1326module_param(irq, int, S_IRUGO);
1327MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
1328
1329module_param(threshold, int, S_IRUGO);
1330MODULE_PARM_DESC(threshold, "space detection threshold (3)");
1331#endif
1332
1333module_param(debug, bool, S_IRUGO | S_IWUSR);
1334MODULE_PARM_DESC(debug, "Enable debugging messages");
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