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1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Cedrus VPU driver | |
4 | * | |
5 | * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com> | |
6 | * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com> | |
7 | * Copyright (C) 2018 Bootlin | |
8 | * | |
9 | * Based on the vim2m driver, that is: | |
10 | * | |
11 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | |
12 | * Pawel Osciak, <pawel@osciak.com> | |
13 | * Marek Szyprowski, <m.szyprowski@samsung.com> | |
14 | */ | |
15 | ||
16 | #ifndef _CEDRUS_H_ | |
17 | #define _CEDRUS_H_ | |
18 | ||
19 | #include <media/v4l2-ctrls.h> | |
20 | #include <media/v4l2-device.h> | |
21 | #include <media/v4l2-mem2mem.h> | |
22 | #include <media/videobuf2-v4l2.h> | |
23 | #include <media/videobuf2-dma-contig.h> | |
24 | ||
25 | #include <linux/platform_device.h> | |
26 | ||
27 | #define CEDRUS_NAME "cedrus" | |
28 | ||
29 | #define CEDRUS_CAPABILITY_UNTILED BIT(0) | |
30 | ||
31 | enum cedrus_codec { | |
32 | CEDRUS_CODEC_MPEG2, | |
33 | ||
34 | CEDRUS_CODEC_LAST, | |
35 | }; | |
36 | ||
37 | enum cedrus_irq_status { | |
38 | CEDRUS_IRQ_NONE, | |
39 | CEDRUS_IRQ_ERROR, | |
40 | CEDRUS_IRQ_OK, | |
41 | }; | |
42 | ||
43 | struct cedrus_control { | |
44 | u32 id; | |
45 | u32 elem_size; | |
46 | enum cedrus_codec codec; | |
47 | unsigned char required:1; | |
48 | }; | |
49 | ||
50 | struct cedrus_mpeg2_run { | |
51 | const struct v4l2_ctrl_mpeg2_slice_params *slice_params; | |
52 | const struct v4l2_ctrl_mpeg2_quantization *quantization; | |
53 | }; | |
54 | ||
55 | struct cedrus_run { | |
56 | struct vb2_v4l2_buffer *src; | |
57 | struct vb2_v4l2_buffer *dst; | |
58 | ||
59 | union { | |
60 | struct cedrus_mpeg2_run mpeg2; | |
61 | }; | |
62 | }; | |
63 | ||
64 | struct cedrus_buffer { | |
65 | struct v4l2_m2m_buffer m2m_buf; | |
66 | }; | |
67 | ||
68 | struct cedrus_ctx { | |
69 | struct v4l2_fh fh; | |
70 | struct cedrus_dev *dev; | |
71 | ||
72 | struct v4l2_pix_format src_fmt; | |
73 | struct v4l2_pix_format dst_fmt; | |
74 | enum cedrus_codec current_codec; | |
75 | ||
76 | struct v4l2_ctrl_handler hdl; | |
77 | struct v4l2_ctrl **ctrls; | |
78 | ||
79 | struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME]; | |
80 | }; | |
81 | ||
82 | struct cedrus_dec_ops { | |
83 | void (*irq_clear)(struct cedrus_ctx *ctx); | |
84 | void (*irq_disable)(struct cedrus_ctx *ctx); | |
85 | enum cedrus_irq_status (*irq_status)(struct cedrus_ctx *ctx); | |
86 | void (*setup)(struct cedrus_ctx *ctx, struct cedrus_run *run); | |
87 | int (*start)(struct cedrus_ctx *ctx); | |
88 | void (*stop)(struct cedrus_ctx *ctx); | |
89 | void (*trigger)(struct cedrus_ctx *ctx); | |
90 | }; | |
91 | ||
92 | struct cedrus_variant { | |
93 | unsigned int capabilities; | |
94 | }; | |
95 | ||
96 | struct cedrus_dev { | |
97 | struct v4l2_device v4l2_dev; | |
98 | struct video_device vfd; | |
99 | struct media_device mdev; | |
100 | struct media_pad pad[2]; | |
101 | struct platform_device *pdev; | |
102 | struct device *dev; | |
103 | struct v4l2_m2m_dev *m2m_dev; | |
104 | struct cedrus_dec_ops *dec_ops[CEDRUS_CODEC_LAST]; | |
105 | ||
106 | /* Device file mutex */ | |
107 | struct mutex dev_mutex; | |
50e76151 PK |
108 | |
109 | void __iomem *base; | |
110 | ||
111 | struct clk *mod_clk; | |
112 | struct clk *ahb_clk; | |
113 | struct clk *ram_clk; | |
114 | ||
115 | struct reset_control *rstc; | |
116 | ||
117 | unsigned int capabilities; | |
118 | }; | |
119 | ||
120 | extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; | |
121 | ||
122 | static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) | |
123 | { | |
124 | writel(val, dev->base + reg); | |
125 | } | |
126 | ||
127 | static inline u32 cedrus_read(struct cedrus_dev *dev, u32 reg) | |
128 | { | |
129 | return readl(dev->base + reg); | |
130 | } | |
131 | ||
132 | static inline dma_addr_t cedrus_buf_addr(struct vb2_buffer *buf, | |
133 | struct v4l2_pix_format *pix_fmt, | |
134 | unsigned int plane) | |
135 | { | |
136 | dma_addr_t addr = vb2_dma_contig_plane_dma_addr(buf, 0); | |
137 | ||
138 | return addr + (pix_fmt ? (dma_addr_t)pix_fmt->bytesperline * | |
139 | pix_fmt->height * plane : 0); | |
140 | } | |
141 | ||
142 | static inline dma_addr_t cedrus_dst_buf_addr(struct cedrus_ctx *ctx, | |
d998e03e | 143 | int index, unsigned int plane) |
50e76151 | 144 | { |
d998e03e | 145 | struct vb2_buffer *buf; |
50e76151 | 146 | |
d998e03e HV |
147 | if (index < 0) |
148 | return 0; | |
149 | ||
150 | buf = ctx->dst_bufs[index]; | |
50e76151 PK |
151 | return buf ? cedrus_buf_addr(buf, &ctx->dst_fmt, plane) : 0; |
152 | } | |
153 | ||
154 | static inline struct cedrus_buffer * | |
155 | vb2_v4l2_to_cedrus_buffer(const struct vb2_v4l2_buffer *p) | |
156 | { | |
157 | return container_of(p, struct cedrus_buffer, m2m_buf.vb); | |
158 | } | |
159 | ||
160 | static inline struct cedrus_buffer * | |
161 | vb2_to_cedrus_buffer(const struct vb2_buffer *p) | |
162 | { | |
163 | return vb2_v4l2_to_cedrus_buffer(to_vb2_v4l2_buffer(p)); | |
164 | } | |
165 | ||
166 | void *cedrus_find_control_data(struct cedrus_ctx *ctx, u32 id); | |
167 | ||
168 | #endif |