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1 | /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
15 | * 02110-1301, USA. | |
16 | */ | |
17 | ||
18 | #include "msm_fb.h" | |
19 | ||
20 | #include <linux/memory.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/time.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include "linux/proc_fs.h" | |
27 | ||
28 | #include <linux/delay.h> | |
29 | ||
30 | #include <mach/hardware.h> | |
31 | #include <linux/io.h> | |
32 | ||
33 | #include <asm/system.h> | |
34 | #include <asm/mach-types.h> | |
35 | ||
36 | /* #define TMD20QVGA_LCD_18BPP */ | |
37 | #define QVGA_WIDTH 240 | |
38 | #define QVGA_HEIGHT 320 | |
39 | ||
40 | #ifdef TMD20QVGA_LCD_18BPP | |
41 | #define DISP_QVGA_18BPP(x) ((((x)<<2) & 0x3FC00)|(( (x)<<1)& 0x1FE)) | |
42 | #define DISP_REG(name) uint32 register_##name; | |
43 | #define OUTPORT(x, y) outpdw(x, y) | |
44 | #define INPORT(x) inpdw(x) | |
45 | #else | |
46 | #define DISP_QVGA_18BPP(x) (x) | |
47 | #define DISP_REG(name) uint16 register_##name; | |
48 | #define OUTPORT(x, y) outpw(x, y) | |
49 | #define INPORT(x) intpw(x) | |
50 | #endif | |
51 | ||
52 | static void *DISP_CMD_PORT; | |
53 | static void *DISP_DATA_PORT; | |
54 | ||
55 | #define DISP_RNTI 0x10 | |
56 | ||
57 | #define DISP_CMD_OUT(cmd) OUTPORT(DISP_CMD_PORT, DISP_QVGA_18BPP(cmd)) | |
58 | #define DISP_DATA_OUT(data) OUTPORT(DISP_DATA_PORT, data) | |
59 | #define DISP_DATA_IN() INPORT(DISP_DATA_PORT) | |
60 | ||
61 | #if (defined(TMD20QVGA_LCD_18BPP)) | |
62 | #define DISP_DATA_OUT_16TO18BPP(x) \ | |
63 | DISP_DATA_OUT((((x)&0xf800)<<2|((x)&0x80000)>>3) \ | |
64 | | (((x)&0x7e0)<<1) \ | |
65 | | (((x)&0x1F)<<1|((x)&0x10)>>4)) | |
66 | #else | |
67 | #define DISP_DATA_OUT_16TO18BPP(x) \ | |
68 | DISP_DATA_OUT(x) | |
69 | #endif | |
70 | ||
71 | #define DISP_WRITE_OUT(addr, data) \ | |
72 | register_##addr = DISP_QVGA_18BPP(data); \ | |
73 | DISP_CMD_OUT(addr); \ | |
74 | DISP_DATA_OUT(register_##addr); | |
75 | ||
76 | #define DISP_UPDATE_VALUE(addr, bitmask, data) \ | |
77 | DISP_WRITE_OUT(##addr, (register_##addr & ~(bitmask)) | (data)); | |
78 | ||
79 | #define DISP_VAL_IF(bitvalue, bitmask) \ | |
80 | ((bitvalue) ? (bitmask) : 0) | |
81 | ||
82 | /* QVGA = 256 x 320 */ | |
83 | /* actual display is 240 x 320...offset by 0x10 */ | |
84 | #define DISP_ROW_COL_TO_ADDR(row, col) ((row) * 0x100 + col) | |
85 | #define DISP_SET_RECT(ulhc_row, lrhc_row, ulhc_col, lrhc_col) \ | |
86 | { \ | |
87 | DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_1_ADDR, (ulhc_col) + tmd20qvga_panel_offset); \ | |
88 | DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_2_ADDR, (lrhc_col) + tmd20qvga_panel_offset); \ | |
89 | DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_1_ADDR, (ulhc_row)); \ | |
90 | DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_2_ADDR, (lrhc_row)); \ | |
91 | DISP_WRITE_OUT(DISP_RAM_ADDR_SET_1_ADDR, (ulhc_col) + tmd20qvga_panel_offset); \ | |
92 | DISP_WRITE_OUT(DISP_RAM_ADDR_SET_2_ADDR, (ulhc_row)); \ | |
93 | } | |
94 | ||
95 | #define WAIT_MSEC(msec) mdelay(msec) | |
96 | ||
97 | /* | |
98 | * TMD QVGA Address | |
99 | */ | |
100 | /* Display Control */ | |
101 | #define DISP_START_OSCILLATION_ADDR 0x000 | |
102 | DISP_REG(DISP_START_OSCILLATION_ADDR) | |
103 | #define DISP_DRIVER_OUTPUT_CTL_ADDR 0x001 | |
104 | DISP_REG(DISP_DRIVER_OUTPUT_CTL_ADDR) | |
105 | #define DISP_LCD_DRIVING_SIG_ADDR 0x002 | |
106 | DISP_REG(DISP_LCD_DRIVING_SIG_ADDR) | |
107 | #define DISP_ENTRY_MODE_ADDR 0x003 | |
108 | DISP_REG(DISP_ENTRY_MODE_ADDR) | |
109 | #define DISP_DISPLAY_CTL_1_ADDR 0x007 | |
110 | DISP_REG(DISP_DISPLAY_CTL_1_ADDR) | |
111 | #define DISP_DISPLAY_CTL_2_ADDR 0x008 | |
112 | DISP_REG(DISP_DISPLAY_CTL_2_ADDR) | |
113 | ||
114 | /* DISPLAY MODE 0x009 partial display not supported */ | |
115 | #define DISP_POWER_SUPPLY_INTF_ADDR 0x00A | |
116 | DISP_REG(DISP_POWER_SUPPLY_INTF_ADDR) | |
117 | ||
118 | /* DISPLAY MODE 0x00B xZoom feature is not supported */ | |
119 | #define DISP_EXT_DISPLAY_CTL_1_ADDR 0x00C | |
120 | DISP_REG(DISP_EXT_DISPLAY_CTL_1_ADDR) | |
121 | ||
122 | #define DISP_FRAME_CYCLE_CTL_ADDR 0x00D | |
123 | DISP_REG(DISP_FRAME_CYCLE_CTL_ADDR) | |
124 | ||
125 | #define DISP_EXT_DISPLAY_CTL_2_ADDR 0x00E | |
126 | DISP_REG(DISP_EXT_DISPLAY_CTL_2_ADDR) | |
127 | ||
128 | #define DISP_EXT_DISPLAY_CTL_3_ADDR 0x00F | |
129 | DISP_REG(DISP_EXT_DISPLAY_CTL_3_ADDR) | |
130 | ||
131 | #define DISP_LTPS_CTL_1_ADDR 0x012 | |
132 | DISP_REG(DISP_LTPS_CTL_1_ADDR) | |
133 | #define DISP_LTPS_CTL_2_ADDR 0x013 | |
134 | DISP_REG(DISP_LTPS_CTL_2_ADDR) | |
135 | #define DISP_LTPS_CTL_3_ADDR 0x014 | |
136 | DISP_REG(DISP_LTPS_CTL_3_ADDR) | |
137 | #define DISP_LTPS_CTL_4_ADDR 0x018 | |
138 | DISP_REG(DISP_LTPS_CTL_4_ADDR) | |
139 | #define DISP_LTPS_CTL_5_ADDR 0x019 | |
140 | DISP_REG(DISP_LTPS_CTL_5_ADDR) | |
141 | #define DISP_LTPS_CTL_6_ADDR 0x01A | |
142 | DISP_REG(DISP_LTPS_CTL_6_ADDR) | |
143 | #define DISP_AMP_SETTING_ADDR 0x01C | |
144 | DISP_REG(DISP_AMP_SETTING_ADDR) | |
145 | #define DISP_MODE_SETTING_ADDR 0x01D | |
146 | DISP_REG(DISP_MODE_SETTING_ADDR) | |
147 | #define DISP_POFF_LN_SETTING_ADDR 0x01E | |
148 | DISP_REG(DISP_POFF_LN_SETTING_ADDR) | |
149 | /* Power Contol */ | |
150 | #define DISP_POWER_CTL_1_ADDR 0x100 | |
151 | DISP_REG(DISP_POWER_CTL_1_ADDR) | |
152 | #define DISP_POWER_CTL_2_ADDR 0x101 | |
153 | DISP_REG(DISP_POWER_CTL_2_ADDR) | |
154 | #define DISP_POWER_CTL_3_ADDR 0x102 | |
155 | DISP_REG(DISP_POWER_CTL_3_ADDR) | |
156 | #define DISP_POWER_CTL_4_ADDR 0x103 | |
157 | DISP_REG(DISP_POWER_CTL_4_ADDR) | |
158 | #define DISP_POWER_CTL_5_ADDR 0x104 | |
159 | DISP_REG(DISP_POWER_CTL_5_ADDR) | |
160 | #define DISP_POWER_CTL_6_ADDR 0x105 | |
161 | DISP_REG(DISP_POWER_CTL_6_ADDR) | |
162 | #define DISP_POWER_CTL_7_ADDR 0x106 | |
163 | DISP_REG(DISP_POWER_CTL_7_ADDR) | |
164 | /* RAM Access */ | |
165 | #define DISP_RAM_ADDR_SET_1_ADDR 0x200 | |
166 | DISP_REG(DISP_RAM_ADDR_SET_1_ADDR) | |
167 | #define DISP_RAM_ADDR_SET_2_ADDR 0x201 | |
168 | DISP_REG(DISP_RAM_ADDR_SET_2_ADDR) | |
169 | #define DISP_CMD_RAMRD DISP_CMD_RAMWR | |
170 | #define DISP_CMD_RAMWR 0x202 | |
171 | DISP_REG(DISP_CMD_RAMWR) | |
172 | #define DISP_RAM_DATA_MASK_1_ADDR 0x203 | |
173 | DISP_REG(DISP_RAM_DATA_MASK_1_ADDR) | |
174 | #define DISP_RAM_DATA_MASK_2_ADDR 0x204 | |
175 | DISP_REG(DISP_RAM_DATA_MASK_2_ADDR) | |
176 | /* Gamma Control, Contrast, Gray Scale Setting */ | |
177 | #define DISP_GAMMA_CONTROL_1_ADDR 0x300 | |
178 | DISP_REG(DISP_GAMMA_CONTROL_1_ADDR) | |
179 | #define DISP_GAMMA_CONTROL_2_ADDR 0x301 | |
180 | DISP_REG(DISP_GAMMA_CONTROL_2_ADDR) | |
181 | #define DISP_GAMMA_CONTROL_3_ADDR 0x302 | |
182 | DISP_REG(DISP_GAMMA_CONTROL_3_ADDR) | |
183 | #define DISP_GAMMA_CONTROL_4_ADDR 0x303 | |
184 | DISP_REG(DISP_GAMMA_CONTROL_4_ADDR) | |
185 | #define DISP_GAMMA_CONTROL_5_ADDR 0x304 | |
186 | DISP_REG(DISP_GAMMA_CONTROL_5_ADDR) | |
187 | /* Coordinate Control */ | |
188 | #define DISP_VERT_SCROLL_CTL_1_ADDR 0x400 | |
189 | DISP_REG(DISP_VERT_SCROLL_CTL_1_ADDR) | |
190 | #define DISP_VERT_SCROLL_CTL_2_ADDR 0x401 | |
191 | DISP_REG(DISP_VERT_SCROLL_CTL_2_ADDR) | |
192 | #define DISP_SCREEN_1_DRV_POS_1_ADDR 0x402 | |
193 | DISP_REG(DISP_SCREEN_1_DRV_POS_1_ADDR) | |
194 | #define DISP_SCREEN_1_DRV_POS_2_ADDR 0x403 | |
195 | DISP_REG(DISP_SCREEN_1_DRV_POS_2_ADDR) | |
196 | #define DISP_SCREEN_2_DRV_POS_1_ADDR 0x404 | |
197 | DISP_REG(DISP_SCREEN_2_DRV_POS_1_ADDR) | |
198 | #define DISP_SCREEN_2_DRV_POS_2_ADDR 0x405 | |
199 | DISP_REG(DISP_SCREEN_2_DRV_POS_2_ADDR) | |
200 | #define DISP_HORZ_RAM_ADDR_POS_1_ADDR 0x406 | |
201 | DISP_REG(DISP_HORZ_RAM_ADDR_POS_1_ADDR) | |
202 | #define DISP_HORZ_RAM_ADDR_POS_2_ADDR 0x407 | |
203 | DISP_REG(DISP_HORZ_RAM_ADDR_POS_2_ADDR) | |
204 | #define DISP_VERT_RAM_ADDR_POS_1_ADDR 0x408 | |
205 | DISP_REG(DISP_VERT_RAM_ADDR_POS_1_ADDR) | |
206 | #define DISP_VERT_RAM_ADDR_POS_2_ADDR 0x409 | |
207 | DISP_REG(DISP_VERT_RAM_ADDR_POS_2_ADDR) | |
208 | #define DISP_TMD_700_ADDR 0x700 /* 0x700 */ | |
209 | DISP_REG(DISP_TMD_700_ADDR) | |
210 | #define DISP_TMD_015_ADDR 0x015 /* 0x700 */ | |
211 | DISP_REG(DISP_TMD_015_ADDR) | |
212 | #define DISP_TMD_305_ADDR 0x305 /* 0x700 */ | |
213 | DISP_REG(DISP_TMD_305_ADDR) | |
214 | ||
215 | /* | |
216 | * TMD QVGA Bit Definations | |
217 | */ | |
218 | ||
219 | #define DISP_BIT_IB15 0x8000 | |
220 | #define DISP_BIT_IB14 0x4000 | |
221 | #define DISP_BIT_IB13 0x2000 | |
222 | #define DISP_BIT_IB12 0x1000 | |
223 | #define DISP_BIT_IB11 0x0800 | |
224 | #define DISP_BIT_IB10 0x0400 | |
225 | #define DISP_BIT_IB09 0x0200 | |
226 | #define DISP_BIT_IB08 0x0100 | |
227 | #define DISP_BIT_IB07 0x0080 | |
228 | #define DISP_BIT_IB06 0x0040 | |
229 | #define DISP_BIT_IB05 0x0020 | |
230 | #define DISP_BIT_IB04 0x0010 | |
231 | #define DISP_BIT_IB03 0x0008 | |
232 | #define DISP_BIT_IB02 0x0004 | |
233 | #define DISP_BIT_IB01 0x0002 | |
234 | #define DISP_BIT_IB00 0x0001 | |
235 | /* | |
236 | * Display Control | |
237 | * DISP_START_OSCILLATION_ADDR Start Oscillation | |
238 | * DISP_DRIVER_OUTPUT_CTL_ADDR Driver Output Control | |
239 | */ | |
240 | #define DISP_BITMASK_SS DISP_BIT_IB08 | |
241 | #define DISP_BITMASK_NL5 DISP_BIT_IB05 | |
242 | #define DISP_BITMASK_NL4 DISP_BIT_IB04 | |
243 | #define DISP_BITMASK_NL3 DISP_BIT_IB03 | |
244 | #define DISP_BITMASK_NL2 DISP_BIT_IB02 | |
245 | #define DISP_BITMASK_NL1 DISP_BIT_IB01 | |
246 | #define DISP_BITMASK_NL0 DISP_BIT_IB00 | |
247 | /* DISP_LCD_DRIVING_SIG_ADDR LCD Driving Signal Setting */ | |
248 | #define DISP_BITMASK_BC DISP_BIT_IB09 | |
249 | /* DISP_ENTRY_MODE_ADDR Entry Mode */ | |
250 | #define DISP_BITMASK_TRI DISP_BIT_IB15 | |
251 | #define DISP_BITMASK_DFM1 DISP_BIT_IB14 | |
252 | #define DISP_BITMASK_DFM0 DISP_BIT_IB13 | |
253 | #define DISP_BITMASK_BGR DISP_BIT_IB12 | |
254 | #define DISP_BITMASK_HWM0 DISP_BIT_IB08 | |
255 | #define DISP_BITMASK_ID1 DISP_BIT_IB05 | |
256 | #define DISP_BITMASK_ID0 DISP_BIT_IB04 | |
257 | #define DISP_BITMASK_AM DISP_BIT_IB03 | |
258 | /* DISP_DISPLAY_CTL_1_ADDR Display Control (1) */ | |
259 | #define DISP_BITMASK_COL1 DISP_BIT_IB15 | |
260 | #define DISP_BITMASK_COL0 DISP_BIT_IB14 | |
261 | #define DISP_BITMASK_VLE2 DISP_BIT_IB10 | |
262 | #define DISP_BITMASK_VLE1 DISP_BIT_IB09 | |
263 | #define DISP_BITMASK_SPT DISP_BIT_IB08 | |
264 | #define DISP_BITMASK_PT1 DISP_BIT_IB07 | |
265 | #define DISP_BITMASK_PT0 DISP_BIT_IB06 | |
266 | #define DISP_BITMASK_REV DISP_BIT_IB02 | |
267 | /* DISP_DISPLAY_CTL_2_ADDR Display Control (2) */ | |
268 | #define DISP_BITMASK_FP3 DISP_BIT_IB11 | |
269 | #define DISP_BITMASK_FP2 DISP_BIT_IB10 | |
270 | #define DISP_BITMASK_FP1 DISP_BIT_IB09 | |
271 | #define DISP_BITMASK_FP0 DISP_BIT_IB08 | |
272 | #define DISP_BITMASK_BP3 DISP_BIT_IB03 | |
273 | #define DISP_BITMASK_BP2 DISP_BIT_IB02 | |
274 | #define DISP_BITMASK_BP1 DISP_BIT_IB01 | |
275 | #define DISP_BITMASK_BP0 DISP_BIT_IB00 | |
276 | /* DISP_POWER_SUPPLY_INTF_ADDR Power Supply IC Interface Control */ | |
277 | #define DISP_BITMASK_CSE DISP_BIT_IB12 | |
278 | #define DISP_BITMASK_TE DISP_BIT_IB08 | |
279 | #define DISP_BITMASK_IX3 DISP_BIT_IB03 | |
280 | #define DISP_BITMASK_IX2 DISP_BIT_IB02 | |
281 | #define DISP_BITMASK_IX1 DISP_BIT_IB01 | |
282 | #define DISP_BITMASK_IX0 DISP_BIT_IB00 | |
283 | /* DISP_EXT_DISPLAY_CTL_1_ADDR External Display Interface Control (1) */ | |
284 | #define DISP_BITMASK_RM DISP_BIT_IB08 | |
285 | #define DISP_BITMASK_DM1 DISP_BIT_IB05 | |
286 | #define DISP_BITMASK_DM0 DISP_BIT_IB04 | |
287 | #define DISP_BITMASK_RIM1 DISP_BIT_IB01 | |
288 | #define DISP_BITMASK_RIM0 DISP_BIT_IB00 | |
289 | /* DISP_FRAME_CYCLE_CTL_ADDR Frame Frequency Adjustment Control */ | |
290 | #define DISP_BITMASK_DIVI1 DISP_BIT_IB09 | |
291 | #define DISP_BITMASK_DIVI0 DISP_BIT_IB08 | |
292 | #define DISP_BITMASK_RTNI4 DISP_BIT_IB04 | |
293 | #define DISP_BITMASK_RTNI3 DISP_BIT_IB03 | |
294 | #define DISP_BITMASK_RTNI2 DISP_BIT_IB02 | |
295 | #define DISP_BITMASK_RTNI1 DISP_BIT_IB01 | |
296 | #define DISP_BITMASK_RTNI0 DISP_BIT_IB00 | |
297 | /* DISP_EXT_DISPLAY_CTL_2_ADDR External Display Interface Control (2) */ | |
298 | #define DISP_BITMASK_DIVE1 DISP_BIT_IB09 | |
299 | #define DISP_BITMASK_DIVE0 DISP_BIT_IB08 | |
300 | #define DISP_BITMASK_RTNE7 DISP_BIT_IB07 | |
301 | #define DISP_BITMASK_RTNE6 DISP_BIT_IB06 | |
302 | #define DISP_BITMASK_RTNE5 DISP_BIT_IB05 | |
303 | #define DISP_BITMASK_RTNE4 DISP_BIT_IB04 | |
304 | #define DISP_BITMASK_RTNE3 DISP_BIT_IB03 | |
305 | #define DISP_BITMASK_RTNE2 DISP_BIT_IB02 | |
306 | #define DISP_BITMASK_RTNE1 DISP_BIT_IB01 | |
307 | #define DISP_BITMASK_RTNE0 DISP_BIT_IB00 | |
308 | /* DISP_EXT_DISPLAY_CTL_3_ADDR External Display Interface Control (3) */ | |
309 | #define DISP_BITMASK_VSPL DISP_BIT_IB04 | |
310 | #define DISP_BITMASK_HSPL DISP_BIT_IB03 | |
311 | #define DISP_BITMASK_VPL DISP_BIT_IB02 | |
312 | #define DISP_BITMASK_EPL DISP_BIT_IB01 | |
313 | #define DISP_BITMASK_DPL DISP_BIT_IB00 | |
314 | /* DISP_LTPS_CTL_1_ADDR LTPS Interface Control (1) */ | |
315 | #define DISP_BITMASK_CLWI3 DISP_BIT_IB11 | |
316 | #define DISP_BITMASK_CLWI2 DISP_BIT_IB10 | |
317 | #define DISP_BITMASK_CLWI1 DISP_BIT_IB09 | |
318 | #define DISP_BITMASK_CLWI0 DISP_BIT_IB08 | |
319 | #define DISP_BITMASK_CLTI1 DISP_BIT_IB01 | |
320 | #define DISP_BITMASK_CLTI0 DISP_BIT_IB00 | |
321 | /* DISP_LTPS_CTL_2_ADDR LTPS Interface Control (2) */ | |
322 | #define DISP_BITMASK_OEVBI1 DISP_BIT_IB09 | |
323 | #define DISP_BITMASK_OEVBI0 DISP_BIT_IB08 | |
324 | #define DISP_BITMASK_OEVFI1 DISP_BIT_IB01 | |
325 | #define DISP_BITMASK_OEVFI0 DISP_BIT_IB00 | |
326 | /* DISP_LTPS_CTL_3_ADDR LTPS Interface Control (3) */ | |
327 | #define DISP_BITMASK_SHI1 DISP_BIT_IB01 | |
328 | #define DISP_BITMASK_SHI0 DISP_BIT_IB00 | |
329 | /* DISP_LTPS_CTL_4_ADDR LTPS Interface Control (4) */ | |
330 | #define DISP_BITMASK_CLWE5 DISP_BIT_IB13 | |
331 | #define DISP_BITMASK_CLWE4 DISP_BIT_IB12 | |
332 | #define DISP_BITMASK_CLWE3 DISP_BIT_IB11 | |
333 | #define DISP_BITMASK_CLWE2 DISP_BIT_IB10 | |
334 | #define DISP_BITMASK_CLWE1 DISP_BIT_IB09 | |
335 | #define DISP_BITMASK_CLWE0 DISP_BIT_IB08 | |
336 | #define DISP_BITMASK_CLTE3 DISP_BIT_IB03 | |
337 | #define DISP_BITMASK_CLTE2 DISP_BIT_IB02 | |
338 | #define DISP_BITMASK_CLTE1 DISP_BIT_IB01 | |
339 | #define DISP_BITMASK_CLTE0 DISP_BIT_IB00 | |
340 | /* DISP_LTPS_CTL_5_ADDR LTPS Interface Control (5) */ | |
341 | #define DISP_BITMASK_OEVBE3 DISP_BIT_IB11 | |
342 | #define DISP_BITMASK_OEVBE2 DISP_BIT_IB10 | |
343 | #define DISP_BITMASK_OEVBE1 DISP_BIT_IB09 | |
344 | #define DISP_BITMASK_OEVBE0 DISP_BIT_IB08 | |
345 | #define DISP_BITMASK_OEVFE3 DISP_BIT_IB03 | |
346 | #define DISP_BITMASK_OEVFE2 DISP_BIT_IB02 | |
347 | #define DISP_BITMASK_OEVFE1 DISP_BIT_IB01 | |
348 | #define DISP_BITMASK_OEVFE0 DISP_BIT_IB00 | |
349 | /* DISP_LTPS_CTL_6_ADDR LTPS Interface Control (6) */ | |
350 | #define DISP_BITMASK_SHE3 DISP_BIT_IB03 | |
351 | #define DISP_BITMASK_SHE2 DISP_BIT_IB02 | |
352 | #define DISP_BITMASK_SHE1 DISP_BIT_IB01 | |
353 | #define DISP_BITMASK_SHE0 DISP_BIT_IB00 | |
354 | /* DISP_AMP_SETTING_ADDR Amplify Setting */ | |
355 | #define DISP_BITMASK_ABSW1 DISP_BIT_IB01 | |
356 | #define DISP_BITMASK_ABSW0 DISP_BIT_IB00 | |
357 | /* DISP_MODE_SETTING_ADDR Mode Setting */ | |
358 | #define DISP_BITMASK_DSTB DISP_BIT_IB02 | |
359 | #define DISP_BITMASK_STB DISP_BIT_IB00 | |
360 | /* DISP_POFF_LN_SETTING_ADDR Power Off Line Setting */ | |
361 | #define DISP_BITMASK_POFH3 DISP_BIT_IB03 | |
362 | #define DISP_BITMASK_POFH2 DISP_BIT_IB02 | |
363 | #define DISP_BITMASK_POFH1 DISP_BIT_IB01 | |
364 | #define DISP_BITMASK_POFH0 DISP_BIT_IB00 | |
365 | ||
366 | /* Power Contol */ | |
367 | /* DISP_POWER_CTL_1_ADDR Power Control (1) */ | |
368 | #define DISP_BITMASK_PO DISP_BIT_IB11 | |
369 | #define DISP_BITMASK_VCD DISP_BIT_IB09 | |
370 | #define DISP_BITMASK_VSC DISP_BIT_IB08 | |
371 | #define DISP_BITMASK_CON DISP_BIT_IB07 | |
372 | #define DISP_BITMASK_ASW1 DISP_BIT_IB06 | |
373 | #define DISP_BITMASK_ASW0 DISP_BIT_IB05 | |
374 | #define DISP_BITMASK_OEV DISP_BIT_IB04 | |
375 | #define DISP_BITMASK_OEVE DISP_BIT_IB03 | |
376 | #define DISP_BITMASK_FR DISP_BIT_IB02 | |
377 | #define DISP_BITMASK_D1 DISP_BIT_IB01 | |
378 | #define DISP_BITMASK_D0 DISP_BIT_IB00 | |
379 | /* DISP_POWER_CTL_2_ADDR Power Control (2) */ | |
380 | #define DISP_BITMASK_DC4 DISP_BIT_IB15 | |
381 | #define DISP_BITMASK_DC3 DISP_BIT_IB14 | |
382 | #define DISP_BITMASK_SAP2 DISP_BIT_IB13 | |
383 | #define DISP_BITMASK_SAP1 DISP_BIT_IB12 | |
384 | #define DISP_BITMASK_SAP0 DISP_BIT_IB11 | |
385 | #define DISP_BITMASK_BT2 DISP_BIT_IB10 | |
386 | #define DISP_BITMASK_BT1 DISP_BIT_IB09 | |
387 | #define DISP_BITMASK_BT0 DISP_BIT_IB08 | |
388 | #define DISP_BITMASK_DC2 DISP_BIT_IB07 | |
389 | #define DISP_BITMASK_DC1 DISP_BIT_IB06 | |
390 | #define DISP_BITMASK_DC0 DISP_BIT_IB05 | |
391 | #define DISP_BITMASK_AP2 DISP_BIT_IB04 | |
392 | #define DISP_BITMASK_AP1 DISP_BIT_IB03 | |
393 | #define DISP_BITMASK_AP0 DISP_BIT_IB02 | |
394 | /* DISP_POWER_CTL_3_ADDR Power Control (3) */ | |
395 | #define DISP_BITMASK_VGL4 DISP_BIT_IB10 | |
396 | #define DISP_BITMASK_VGL3 DISP_BIT_IB09 | |
397 | #define DISP_BITMASK_VGL2 DISP_BIT_IB08 | |
398 | #define DISP_BITMASK_VGL1 DISP_BIT_IB07 | |
399 | #define DISP_BITMASK_VGL0 DISP_BIT_IB06 | |
400 | #define DISP_BITMASK_VGH4 DISP_BIT_IB04 | |
401 | #define DISP_BITMASK_VGH3 DISP_BIT_IB03 | |
402 | #define DISP_BITMASK_VGH2 DISP_BIT_IB02 | |
403 | #define DISP_BITMASK_VGH1 DISP_BIT_IB01 | |
404 | #define DISP_BITMASK_VGH0 DISP_BIT_IB00 | |
405 | /* DISP_POWER_CTL_4_ADDR Power Control (4) */ | |
406 | #define DISP_BITMASK_VC2 DISP_BIT_IB02 | |
407 | #define DISP_BITMASK_VC1 DISP_BIT_IB01 | |
408 | #define DISP_BITMASK_VC0 DISP_BIT_IB00 | |
409 | /* DISP_POWER_CTL_5_ADDR Power Control (5) */ | |
410 | #define DISP_BITMASK_VRL3 DISP_BIT_IB11 | |
411 | #define DISP_BITMASK_VRL2 DISP_BIT_IB10 | |
412 | #define DISP_BITMASK_VRL1 DISP_BIT_IB09 | |
413 | #define DISP_BITMASK_VRL0 DISP_BIT_IB08 | |
414 | #define DISP_BITMASK_PON DISP_BIT_IB04 | |
415 | #define DISP_BITMASK_VRH3 DISP_BIT_IB03 | |
416 | #define DISP_BITMASK_VRH2 DISP_BIT_IB02 | |
417 | #define DISP_BITMASK_VRH1 DISP_BIT_IB01 | |
418 | #define DISP_BITMASK_VRH0 DISP_BIT_IB00 | |
419 | /* DISP_POWER_CTL_6_ADDR Power Control (6) */ | |
420 | #define DISP_BITMASK_VCOMG DISP_BIT_IB13 | |
421 | #define DISP_BITMASK_VDV4 DISP_BIT_IB12 | |
422 | #define DISP_BITMASK_VDV3 DISP_BIT_IB11 | |
423 | #define DISP_BITMASK_VDV2 DISP_BIT_IB10 | |
424 | #define DISP_BITMASK_VDV1 DISP_BIT_IB09 | |
425 | #define DISP_BITMASK_VDV0 DISP_BIT_IB08 | |
426 | #define DISP_BITMASK_VCM4 DISP_BIT_IB04 | |
427 | #define DISP_BITMASK_VCM3 DISP_BIT_IB03 | |
428 | #define DISP_BITMASK_VCM2 DISP_BIT_IB02 | |
429 | #define DISP_BITMASK_VCM1 DISP_BIT_IB01 | |
430 | #define DISP_BITMASK_VCM0 DISP_BIT_IB00 | |
431 | /* RAM Access */ | |
432 | /* DISP_RAM_ADDR_SET_1_ADDR RAM Address Set (1) */ | |
433 | #define DISP_BITMASK_AD7 DISP_BIT_IB07 | |
434 | #define DISP_BITMASK_AD6 DISP_BIT_IB06 | |
435 | #define DISP_BITMASK_AD5 DISP_BIT_IB05 | |
436 | #define DISP_BITMASK_AD4 DISP_BIT_IB04 | |
437 | #define DISP_BITMASK_AD3 DISP_BIT_IB03 | |
438 | #define DISP_BITMASK_AD2 DISP_BIT_IB02 | |
439 | #define DISP_BITMASK_AD1 DISP_BIT_IB01 | |
440 | #define DISP_BITMASK_AD0 DISP_BIT_IB00 | |
441 | /* DISP_RAM_ADDR_SET_2_ADDR RAM Address Set (2) */ | |
442 | #define DISP_BITMASK_AD16 DISP_BIT_IB08 | |
443 | #define DISP_BITMASK_AD15 DISP_BIT_IB07 | |
444 | #define DISP_BITMASK_AD14 DISP_BIT_IB06 | |
445 | #define DISP_BITMASK_AD13 DISP_BIT_IB05 | |
446 | #define DISP_BITMASK_AD12 DISP_BIT_IB04 | |
447 | #define DISP_BITMASK_AD11 DISP_BIT_IB03 | |
448 | #define DISP_BITMASK_AD10 DISP_BIT_IB02 | |
449 | #define DISP_BITMASK_AD9 DISP_BIT_IB01 | |
450 | #define DISP_BITMASK_AD8 DISP_BIT_IB00 | |
451 | /* | |
452 | * DISP_CMD_RAMWR RAM Data Read/Write | |
453 | * Use Data Bit Configuration | |
454 | */ | |
455 | /* DISP_RAM_DATA_MASK_1_ADDR RAM Write Data Mask (1) */ | |
456 | #define DISP_BITMASK_WM11 DISP_BIT_IB13 | |
457 | #define DISP_BITMASK_WM10 DISP_BIT_IB12 | |
458 | #define DISP_BITMASK_WM9 DISP_BIT_IB11 | |
459 | #define DISP_BITMASK_WM8 DISP_BIT_IB10 | |
460 | #define DISP_BITMASK_WM7 DISP_BIT_IB09 | |
461 | #define DISP_BITMASK_WM6 DISP_BIT_IB08 | |
462 | #define DISP_BITMASK_WM5 DISP_BIT_IB05 | |
463 | #define DISP_BITMASK_WM4 DISP_BIT_IB04 | |
464 | #define DISP_BITMASK_WM3 DISP_BIT_IB03 | |
465 | #define DISP_BITMASK_WM2 DISP_BIT_IB02 | |
466 | #define DISP_BITMASK_WM1 DISP_BIT_IB01 | |
467 | #define DISP_BITMASK_WM0 DISP_BIT_IB00 | |
468 | /* DISP_RAM_DATA_MASK_2_ADDR RAM Write Data Mask (2) */ | |
469 | #define DISP_BITMASK_WM17 DISP_BIT_IB05 | |
470 | #define DISP_BITMASK_WM16 DISP_BIT_IB04 | |
471 | #define DISP_BITMASK_WM15 DISP_BIT_IB03 | |
472 | #define DISP_BITMASK_WM14 DISP_BIT_IB02 | |
473 | #define DISP_BITMASK_WM13 DISP_BIT_IB01 | |
474 | #define DISP_BITMASK_WM12 DISP_BIT_IB00 | |
475 | /*Gamma Control */ | |
476 | /* DISP_GAMMA_CONTROL_1_ADDR Gamma Control (1) */ | |
477 | #define DISP_BITMASK_PKP12 DISP_BIT_IB10 | |
478 | #define DISP_BITMASK_PKP11 DISP_BIT_IB08 | |
479 | #define DISP_BITMASK_PKP10 DISP_BIT_IB09 | |
480 | #define DISP_BITMASK_PKP02 DISP_BIT_IB02 | |
481 | #define DISP_BITMASK_PKP01 DISP_BIT_IB01 | |
482 | #define DISP_BITMASK_PKP00 DISP_BIT_IB00 | |
483 | /* DISP_GAMMA_CONTROL_2_ADDR Gamma Control (2) */ | |
484 | #define DISP_BITMASK_PKP32 DISP_BIT_IB10 | |
485 | #define DISP_BITMASK_PKP31 DISP_BIT_IB09 | |
486 | #define DISP_BITMASK_PKP30 DISP_BIT_IB08 | |
487 | #define DISP_BITMASK_PKP22 DISP_BIT_IB02 | |
488 | #define DISP_BITMASK_PKP21 DISP_BIT_IB01 | |
489 | #define DISP_BITMASK_PKP20 DISP_BIT_IB00 | |
490 | /* DISP_GAMMA_CONTROL_3_ADDR Gamma Control (3) */ | |
491 | #define DISP_BITMASK_PKP52 DISP_BIT_IB10 | |
492 | #define DISP_BITMASK_PKP51 DISP_BIT_IB09 | |
493 | #define DISP_BITMASK_PKP50 DISP_BIT_IB08 | |
494 | #define DISP_BITMASK_PKP42 DISP_BIT_IB02 | |
495 | #define DISP_BITMASK_PKP41 DISP_BIT_IB01 | |
496 | #define DISP_BITMASK_PKP40 DISP_BIT_IB00 | |
497 | /* DISP_GAMMA_CONTROL_4_ADDR Gamma Control (4) */ | |
498 | #define DISP_BITMASK_PRP12 DISP_BIT_IB10 | |
499 | #define DISP_BITMASK_PRP11 DISP_BIT_IB08 | |
500 | #define DISP_BITMASK_PRP10 DISP_BIT_IB09 | |
501 | #define DISP_BITMASK_PRP02 DISP_BIT_IB02 | |
502 | #define DISP_BITMASK_PRP01 DISP_BIT_IB01 | |
503 | #define DISP_BITMASK_PRP00 DISP_BIT_IB00 | |
504 | /* DISP_GAMMA_CONTROL_5_ADDR Gamma Control (5) */ | |
505 | #define DISP_BITMASK_VRP14 DISP_BIT_IB12 | |
506 | #define DISP_BITMASK_VRP13 DISP_BIT_IB11 | |
507 | #define DISP_BITMASK_VRP12 DISP_BIT_IB10 | |
508 | #define DISP_BITMASK_VRP11 DISP_BIT_IB08 | |
509 | #define DISP_BITMASK_VRP10 DISP_BIT_IB09 | |
510 | #define DISP_BITMASK_VRP03 DISP_BIT_IB03 | |
511 | #define DISP_BITMASK_VRP02 DISP_BIT_IB02 | |
512 | #define DISP_BITMASK_VRP01 DISP_BIT_IB01 | |
513 | #define DISP_BITMASK_VRP00 DISP_BIT_IB00 | |
514 | /* DISP_GAMMA_CONTROL_6_ADDR Gamma Control (6) */ | |
515 | #define DISP_BITMASK_PKN12 DISP_BIT_IB10 | |
516 | #define DISP_BITMASK_PKN11 DISP_BIT_IB08 | |
517 | #define DISP_BITMASK_PKN10 DISP_BIT_IB09 | |
518 | #define DISP_BITMASK_PKN02 DISP_BIT_IB02 | |
519 | #define DISP_BITMASK_PKN01 DISP_BIT_IB01 | |
520 | #define DISP_BITMASK_PKN00 DISP_BIT_IB00 | |
521 | /* DISP_GAMMA_CONTROL_7_ADDR Gamma Control (7) */ | |
522 | #define DISP_BITMASK_PKN32 DISP_BIT_IB10 | |
523 | #define DISP_BITMASK_PKN31 DISP_BIT_IB08 | |
524 | #define DISP_BITMASK_PKN30 DISP_BIT_IB09 | |
525 | #define DISP_BITMASK_PKN22 DISP_BIT_IB02 | |
526 | #define DISP_BITMASK_PKN21 DISP_BIT_IB01 | |
527 | #define DISP_BITMASK_PKN20 DISP_BIT_IB00 | |
528 | /* DISP_GAMMA_CONTROL_8_ADDR Gamma Control (8) */ | |
529 | #define DISP_BITMASK_PKN52 DISP_BIT_IB10 | |
530 | #define DISP_BITMASK_PKN51 DISP_BIT_IB08 | |
531 | #define DISP_BITMASK_PKN50 DISP_BIT_IB09 | |
532 | #define DISP_BITMASK_PKN42 DISP_BIT_IB02 | |
533 | #define DISP_BITMASK_PKN41 DISP_BIT_IB01 | |
534 | #define DISP_BITMASK_PKN40 DISP_BIT_IB00 | |
535 | /* DISP_GAMMA_CONTROL_9_ADDR Gamma Control (9) */ | |
536 | #define DISP_BITMASK_PRN12 DISP_BIT_IB10 | |
537 | #define DISP_BITMASK_PRN11 DISP_BIT_IB08 | |
538 | #define DISP_BITMASK_PRN10 DISP_BIT_IB09 | |
539 | #define DISP_BITMASK_PRN02 DISP_BIT_IB02 | |
540 | #define DISP_BITMASK_PRN01 DISP_BIT_IB01 | |
541 | #define DISP_BITMASK_PRN00 DISP_BIT_IB00 | |
542 | /* DISP_GAMMA_CONTROL_10_ADDR Gamma Control (10) */ | |
543 | #define DISP_BITMASK_VRN14 DISP_BIT_IB12 | |
544 | #define DISP_BITMASK_VRN13 DISP_BIT_IB11 | |
545 | #define DISP_BITMASK_VRN12 DISP_BIT_IB10 | |
546 | #define DISP_BITMASK_VRN11 DISP_BIT_IB08 | |
547 | #define DISP_BITMASK_VRN10 DISP_BIT_IB09 | |
548 | #define DISP_BITMASK_VRN03 DISP_BIT_IB03 | |
549 | #define DISP_BITMASK_VRN02 DISP_BIT_IB02 | |
550 | #define DISP_BITMASK_VRN01 DISP_BIT_IB01 | |
551 | #define DISP_BITMASK_VRN00 DISP_BIT_IB00 | |
552 | /* Coordinate Control */ | |
553 | /* DISP_VERT_SCROLL_CTL_1_ADDR Vertical Scroll Control (1) */ | |
554 | #define DISP_BITMASK_VL18 DISP_BIT_IB08 | |
555 | #define DISP_BITMASK_VL17 DISP_BIT_IB07 | |
556 | #define DISP_BITMASK_VL16 DISP_BIT_IB06 | |
557 | #define DISP_BITMASK_VL15 DISP_BIT_IB05 | |
558 | #define DISP_BITMASK_VL14 DISP_BIT_IB04 | |
559 | #define DISP_BITMASK_VL13 DISP_BIT_IB03 | |
560 | #define DISP_BITMASK_VL12 DISP_BIT_IB02 | |
561 | #define DISP_BITMASK_VL11 DISP_BIT_IB01 | |
562 | #define DISP_BITMASK_VL10 DISP_BIT_IB00 | |
563 | /* DISP_VERT_SCROLL_CTL_2_ADDR Vertical Scroll Control (2) */ | |
564 | #define DISP_BITMASK_VL28 DISP_BIT_IB08 | |
565 | #define DISP_BITMASK_VL27 DISP_BIT_IB07 | |
566 | #define DISP_BITMASK_VL26 DISP_BIT_IB06 | |
567 | #define DISP_BITMASK_VL25 DISP_BIT_IB05 | |
568 | #define DISP_BITMASK_VL24 DISP_BIT_IB04 | |
569 | #define DISP_BITMASK_VL23 DISP_BIT_IB03 | |
570 | #define DISP_BITMASK_VL22 DISP_BIT_IB02 | |
571 | #define DISP_BITMASK_VL21 DISP_BIT_IB01 | |
572 | #define DISP_BITMASK_VL20 DISP_BIT_IB00 | |
573 | /* DISP_SCREEN_1_DRV_POS_1_ADDR First Screen Driving Position (1) */ | |
574 | #define DISP_BITMASK_SS18 DISP_BIT_IB08 | |
575 | #define DISP_BITMASK_SS17 DISP_BIT_IB07 | |
576 | #define DISP_BITMASK_SS16 DISP_BIT_IB06 | |
577 | #define DISP_BITMASK_SS15 DISP_BIT_IB05 | |
578 | #define DISP_BITMASK_SS14 DISP_BIT_IB04 | |
579 | #define DISP_BITMASK_SS13 DISP_BIT_IB03 | |
580 | #define DISP_BITMASK_SS12 DISP_BIT_IB02 | |
581 | #define DISP_BITMASK_SS11 DISP_BIT_IB01 | |
582 | #define DISP_BITMASK_SS10 DISP_BIT_IB00 | |
583 | /* DISP_SCREEN_1_DRV_POS_2_ADDR First Screen Driving Position (2) */ | |
584 | #define DISP_BITMASK_SE18 DISP_BIT_IB08 | |
585 | #define DISP_BITMASK_SE17 DISP_BIT_IB07 | |
586 | #define DISP_BITMASK_SE16 DISP_BIT_IB06 | |
587 | #define DISP_BITMASK_SE15 DISP_BIT_IB05 | |
588 | #define DISP_BITMASK_SE14 DISP_BIT_IB04 | |
589 | #define DISP_BITMASK_SE13 DISP_BIT_IB03 | |
590 | #define DISP_BITMASK_SE12 DISP_BIT_IB02 | |
591 | #define DISP_BITMASK_SE11 DISP_BIT_IB01 | |
592 | #define DISP_BITMASK_SE10 DISP_BIT_IB00 | |
593 | /* DISP_SCREEN_2_DRV_POS_1_ADDR Second Screen Driving Position (1) */ | |
594 | #define DISP_BITMASK_SS28 DISP_BIT_IB08 | |
595 | #define DISP_BITMASK_SS27 DISP_BIT_IB07 | |
596 | #define DISP_BITMASK_SS26 DISP_BIT_IB06 | |
597 | #define DISP_BITMASK_SS25 DISP_BIT_IB05 | |
598 | #define DISP_BITMASK_SS24 DISP_BIT_IB04 | |
599 | #define DISP_BITMASK_SS23 DISP_BIT_IB03 | |
600 | #define DISP_BITMASK_SS22 DISP_BIT_IB02 | |
601 | #define DISP_BITMASK_SS21 DISP_BIT_IB01 | |
602 | #define DISP_BITMASK_SS20 DISP_BIT_IB00 | |
603 | /* DISP_SCREEN_3_DRV_POS_2_ADDR Second Screen Driving Position (2) */ | |
604 | #define DISP_BITMASK_SE28 DISP_BIT_IB08 | |
605 | #define DISP_BITMASK_SE27 DISP_BIT_IB07 | |
606 | #define DISP_BITMASK_SE26 DISP_BIT_IB06 | |
607 | #define DISP_BITMASK_SE25 DISP_BIT_IB05 | |
608 | #define DISP_BITMASK_SE24 DISP_BIT_IB04 | |
609 | #define DISP_BITMASK_SE23 DISP_BIT_IB03 | |
610 | #define DISP_BITMASK_SE22 DISP_BIT_IB02 | |
611 | #define DISP_BITMASK_SE21 DISP_BIT_IB01 | |
612 | #define DISP_BITMASK_SE20 DISP_BIT_IB00 | |
613 | /* DISP_HORZ_RAM_ADDR_POS_1_ADDR Horizontal RAM Address Position (1) */ | |
614 | #define DISP_BITMASK_HSA7 DISP_BIT_IB07 | |
615 | #define DISP_BITMASK_HSA6 DISP_BIT_IB06 | |
616 | #define DISP_BITMASK_HSA5 DISP_BIT_IB05 | |
617 | #define DISP_BITMASK_HSA4 DISP_BIT_IB04 | |
618 | #define DISP_BITMASK_HSA3 DISP_BIT_IB03 | |
619 | #define DISP_BITMASK_HSA2 DISP_BIT_IB02 | |
620 | #define DISP_BITMASK_HSA1 DISP_BIT_IB01 | |
621 | #define DISP_BITMASK_HSA0 DISP_BIT_IB00 | |
622 | /* DISP_HORZ_RAM_ADDR_POS_2_ADDR Horizontal RAM Address Position (2) */ | |
623 | #define DISP_BITMASK_HEA7 DISP_BIT_IB07 | |
624 | #define DISP_BITMASK_HEA6 DISP_BIT_IB06 | |
625 | #define DISP_BITMASK_HEA5 DISP_BIT_IB05 | |
626 | #define DISP_BITMASK_HEA4 DISP_BIT_IB04 | |
627 | #define DISP_BITMASK_HEA3 DISP_BIT_IB03 | |
628 | #define DISP_BITMASK_HEA2 DISP_BIT_IB02 | |
629 | #define DISP_BITMASK_HEA1 DISP_BIT_IB01 | |
630 | #define DISP_BITMASK_HEA0 DISP_BIT_IB00 | |
631 | /* DISP_VERT_RAM_ADDR_POS_1_ADDR Vertical RAM Address Position (1) */ | |
632 | #define DISP_BITMASK_VSA8 DISP_BIT_IB08 | |
633 | #define DISP_BITMASK_VSA7 DISP_BIT_IB07 | |
634 | #define DISP_BITMASK_VSA6 DISP_BIT_IB06 | |
635 | #define DISP_BITMASK_VSA5 DISP_BIT_IB05 | |
636 | #define DISP_BITMASK_VSA4 DISP_BIT_IB04 | |
637 | #define DISP_BITMASK_VSA3 DISP_BIT_IB03 | |
638 | #define DISP_BITMASK_VSA2 DISP_BIT_IB02 | |
639 | #define DISP_BITMASK_VSA1 DISP_BIT_IB01 | |
640 | #define DISP_BITMASK_VSA0 DISP_BIT_IB00 | |
641 | /* DISP_VERT_RAM_ADDR_POS_2_ADDR Vertical RAM Address Position (2) */ | |
642 | #define DISP_BITMASK_VEA8 DISP_BIT_IB08 | |
643 | #define DISP_BITMASK_VEA7 DISP_BIT_IB07 | |
644 | #define DISP_BITMASK_VEA6 DISP_BIT_IB06 | |
645 | #define DISP_BITMASK_VEA5 DISP_BIT_IB05 | |
646 | #define DISP_BITMASK_VEA4 DISP_BIT_IB04 | |
647 | #define DISP_BITMASK_VEA3 DISP_BIT_IB03 | |
648 | #define DISP_BITMASK_VEA2 DISP_BIT_IB02 | |
649 | #define DISP_BITMASK_VEA1 DISP_BIT_IB01 | |
650 | #define DISP_BITMASK_VEA0 DISP_BIT_IB00 | |
651 | static word disp_area_start_row; | |
652 | static word disp_area_end_row; | |
653 | static boolean disp_initialized = FALSE; | |
654 | /* For some reason the contrast set at init time is not good. Need to do | |
655 | * it again | |
656 | */ | |
657 | static boolean display_on = FALSE; | |
658 | ||
659 | static uint32 tmd20qvga_lcd_rev; | |
660 | uint16 tmd20qvga_panel_offset; | |
661 | ||
662 | #ifdef DISP_DEVICE_8BPP | |
663 | static word convert_8_to_16_tbl[256] = { | |
664 | 0x0000, 0x2000, 0x4000, 0x6000, 0x8000, 0xA000, 0xC000, 0xE000, | |
665 | 0x0100, 0x2100, 0x4100, 0x6100, 0x8100, 0xA100, 0xC100, 0xE100, | |
666 | 0x0200, 0x2200, 0x4200, 0x6200, 0x8200, 0xA200, 0xC200, 0xE200, | |
667 | 0x0300, 0x2300, 0x4300, 0x6300, 0x8300, 0xA300, 0xC300, 0xE300, | |
668 | 0x0400, 0x2400, 0x4400, 0x6400, 0x8400, 0xA400, 0xC400, 0xE400, | |
669 | 0x0500, 0x2500, 0x4500, 0x6500, 0x8500, 0xA500, 0xC500, 0xE500, | |
670 | 0x0600, 0x2600, 0x4600, 0x6600, 0x8600, 0xA600, 0xC600, 0xE600, | |
671 | 0x0700, 0x2700, 0x4700, 0x6700, 0x8700, 0xA700, 0xC700, 0xE700, | |
672 | 0x0008, 0x2008, 0x4008, 0x6008, 0x8008, 0xA008, 0xC008, 0xE008, | |
673 | 0x0108, 0x2108, 0x4108, 0x6108, 0x8108, 0xA108, 0xC108, 0xE108, | |
674 | 0x0208, 0x2208, 0x4208, 0x6208, 0x8208, 0xA208, 0xC208, 0xE208, | |
675 | 0x0308, 0x2308, 0x4308, 0x6308, 0x8308, 0xA308, 0xC308, 0xE308, | |
676 | 0x0408, 0x2408, 0x4408, 0x6408, 0x8408, 0xA408, 0xC408, 0xE408, | |
677 | 0x0508, 0x2508, 0x4508, 0x6508, 0x8508, 0xA508, 0xC508, 0xE508, | |
678 | 0x0608, 0x2608, 0x4608, 0x6608, 0x8608, 0xA608, 0xC608, 0xE608, | |
679 | 0x0708, 0x2708, 0x4708, 0x6708, 0x8708, 0xA708, 0xC708, 0xE708, | |
680 | 0x0010, 0x2010, 0x4010, 0x6010, 0x8010, 0xA010, 0xC010, 0xE010, | |
681 | 0x0110, 0x2110, 0x4110, 0x6110, 0x8110, 0xA110, 0xC110, 0xE110, | |
682 | 0x0210, 0x2210, 0x4210, 0x6210, 0x8210, 0xA210, 0xC210, 0xE210, | |
683 | 0x0310, 0x2310, 0x4310, 0x6310, 0x8310, 0xA310, 0xC310, 0xE310, | |
684 | 0x0410, 0x2410, 0x4410, 0x6410, 0x8410, 0xA410, 0xC410, 0xE410, | |
685 | 0x0510, 0x2510, 0x4510, 0x6510, 0x8510, 0xA510, 0xC510, 0xE510, | |
686 | 0x0610, 0x2610, 0x4610, 0x6610, 0x8610, 0xA610, 0xC610, 0xE610, | |
687 | 0x0710, 0x2710, 0x4710, 0x6710, 0x8710, 0xA710, 0xC710, 0xE710, | |
688 | 0x0018, 0x2018, 0x4018, 0x6018, 0x8018, 0xA018, 0xC018, 0xE018, | |
689 | 0x0118, 0x2118, 0x4118, 0x6118, 0x8118, 0xA118, 0xC118, 0xE118, | |
690 | 0x0218, 0x2218, 0x4218, 0x6218, 0x8218, 0xA218, 0xC218, 0xE218, | |
691 | 0x0318, 0x2318, 0x4318, 0x6318, 0x8318, 0xA318, 0xC318, 0xE318, | |
692 | 0x0418, 0x2418, 0x4418, 0x6418, 0x8418, 0xA418, 0xC418, 0xE418, | |
693 | 0x0518, 0x2518, 0x4518, 0x6518, 0x8518, 0xA518, 0xC518, 0xE518, | |
694 | 0x0618, 0x2618, 0x4618, 0x6618, 0x8618, 0xA618, 0xC618, 0xE618, | |
695 | 0x0718, 0x2718, 0x4718, 0x6718, 0x8718, 0xA718, 0xC718, 0xE718 | |
696 | }; | |
697 | #endif /* DISP_DEVICE_8BPP */ | |
698 | ||
699 | static void tmd20qvga_disp_set_rect(int x, int y, int xres, int yres); | |
700 | static void tmd20qvga_disp_init(struct platform_device *pdev); | |
701 | static void tmd20qvga_disp_set_contrast(void); | |
702 | static void tmd20qvga_disp_set_display_area(word start_row, word end_row); | |
703 | static int tmd20qvga_disp_off(struct platform_device *pdev); | |
704 | static int tmd20qvga_disp_on(struct platform_device *pdev); | |
705 | static void tmd20qvga_set_revId(int); | |
706 | ||
707 | /* future use */ | |
708 | void tmd20qvga_disp_clear_screen_area(word start_row, word end_row, | |
709 | word start_column, word end_column); | |
710 | ||
711 | static void tmd20qvga_set_revId(int id) | |
712 | { | |
713 | ||
714 | tmd20qvga_lcd_rev = id; | |
715 | ||
716 | if (tmd20qvga_lcd_rev == 1) | |
717 | tmd20qvga_panel_offset = 0x10; | |
718 | else | |
719 | tmd20qvga_panel_offset = 0; | |
720 | } | |
721 | ||
722 | static void tmd20qvga_disp_init(struct platform_device *pdev) | |
723 | { | |
724 | struct msm_fb_data_type *mfd; | |
725 | ||
726 | if (disp_initialized) | |
727 | return; | |
728 | ||
729 | mfd = platform_get_drvdata(pdev); | |
730 | ||
731 | DISP_CMD_PORT = mfd->cmd_port; | |
732 | DISP_DATA_PORT = mfd->data_port; | |
733 | ||
734 | #ifdef TMD20QVGA_LCD_18BPP | |
735 | tmd20qvga_set_revId(2); | |
736 | #else | |
737 | tmd20qvga_set_revId(1); | |
738 | #endif | |
739 | ||
740 | disp_initialized = TRUE; | |
741 | tmd20qvga_disp_set_contrast(); | |
742 | tmd20qvga_disp_set_display_area(0, QVGA_HEIGHT - 1); | |
743 | } | |
744 | ||
745 | static void tmd20qvga_disp_set_rect(int x, int y, int xres, int yres) | |
746 | { | |
747 | if (!disp_initialized) | |
748 | return; | |
749 | ||
750 | DISP_SET_RECT(y, y + yres - 1, x, x + xres - 1); | |
751 | ||
752 | DISP_CMD_OUT(DISP_CMD_RAMWR); | |
753 | } | |
754 | ||
755 | static void tmd20qvga_disp_set_display_area(word start_row, word end_row) | |
756 | { | |
757 | word start_driving = start_row; | |
758 | word end_driving = end_row; | |
759 | ||
760 | if (!disp_initialized) | |
761 | return; | |
762 | ||
763 | /* Range checking | |
764 | */ | |
765 | if (end_driving >= QVGA_HEIGHT) | |
766 | end_driving = QVGA_HEIGHT - 1; | |
767 | if (start_driving > end_driving) { | |
768 | /* Probably Backwards Switch */ | |
769 | start_driving = end_driving; | |
770 | end_driving = start_row; /* Has not changed */ | |
771 | if (end_driving >= QVGA_HEIGHT) | |
772 | end_driving = QVGA_HEIGHT - 1; | |
773 | } | |
774 | ||
775 | if ((start_driving == disp_area_start_row) | |
776 | && (end_driving == disp_area_end_row)) | |
777 | return; | |
778 | ||
779 | disp_area_start_row = start_driving; | |
780 | disp_area_end_row = end_driving; | |
781 | ||
782 | DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, | |
783 | DISP_VAL_IF(start_driving & 0x100, | |
784 | DISP_BITMASK_SS18) | | |
785 | DISP_VAL_IF(start_driving & 0x080, | |
786 | DISP_BITMASK_SS17) | | |
787 | DISP_VAL_IF(start_driving & 0x040, | |
788 | DISP_BITMASK_SS16) | | |
789 | DISP_VAL_IF(start_driving & 0x020, | |
790 | DISP_BITMASK_SS15) | | |
791 | DISP_VAL_IF(start_driving & 0x010, | |
792 | DISP_BITMASK_SS14) | | |
793 | DISP_VAL_IF(start_driving & 0x008, | |
794 | DISP_BITMASK_SS13) | | |
795 | DISP_VAL_IF(start_driving & 0x004, | |
796 | DISP_BITMASK_SS12) | | |
797 | DISP_VAL_IF(start_driving & 0x002, | |
798 | DISP_BITMASK_SS11) | | |
799 | DISP_VAL_IF(start_driving & 0x001, DISP_BITMASK_SS10)); | |
800 | ||
801 | DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, | |
802 | DISP_VAL_IF(end_driving & 0x100, DISP_BITMASK_SE18) | | |
803 | DISP_VAL_IF(end_driving & 0x080, DISP_BITMASK_SE17) | | |
804 | DISP_VAL_IF(end_driving & 0x040, DISP_BITMASK_SE16) | | |
805 | DISP_VAL_IF(end_driving & 0x020, DISP_BITMASK_SE15) | | |
806 | DISP_VAL_IF(end_driving & 0x010, DISP_BITMASK_SE14) | | |
807 | DISP_VAL_IF(end_driving & 0x008, DISP_BITMASK_SE13) | | |
808 | DISP_VAL_IF(end_driving & 0x004, DISP_BITMASK_SE12) | | |
809 | DISP_VAL_IF(end_driving & 0x002, DISP_BITMASK_SE11) | | |
810 | DISP_VAL_IF(end_driving & 0x001, DISP_BITMASK_SE10)); | |
811 | } | |
812 | ||
813 | static int tmd20qvga_disp_off(struct platform_device *pdev) | |
814 | { | |
815 | if (!disp_initialized) | |
816 | tmd20qvga_disp_init(pdev); | |
817 | ||
818 | if (display_on) { | |
819 | if (tmd20qvga_lcd_rev == 2) { | |
820 | DISP_WRITE_OUT(DISP_POFF_LN_SETTING_ADDR, 0x000A); | |
821 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFEE); | |
822 | WAIT_MSEC(40); | |
823 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xF812); | |
824 | WAIT_MSEC(40); | |
825 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xE811); | |
826 | WAIT_MSEC(40); | |
827 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC011); | |
828 | WAIT_MSEC(40); | |
829 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x4011); | |
830 | WAIT_MSEC(20); | |
831 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0010); | |
832 | ||
833 | } else { | |
834 | DISP_WRITE_OUT(DISP_POFF_LN_SETTING_ADDR, 0x000F); | |
835 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFE); | |
836 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); | |
837 | WAIT_MSEC(40); | |
838 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BED); | |
839 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); | |
840 | WAIT_MSEC(40); | |
841 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x00CD); | |
842 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); | |
843 | WAIT_MSEC(20); | |
844 | DISP_WRITE_OUT(DISP_START_OSCILLATION_ADDR, 0x0); | |
845 | } | |
846 | ||
847 | DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0004); | |
848 | DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0000); | |
849 | ||
850 | display_on = FALSE; | |
851 | } | |
852 | ||
853 | return 0; | |
854 | } | |
855 | ||
856 | static int tmd20qvga_disp_on(struct platform_device *pdev) | |
857 | { | |
858 | if (!disp_initialized) | |
859 | tmd20qvga_disp_init(pdev); | |
860 | ||
861 | if (!display_on) { | |
862 | /* Deep Stand-by -> Stand-by */ | |
863 | DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR); | |
864 | WAIT_MSEC(1); | |
865 | DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR); | |
866 | WAIT_MSEC(1); | |
867 | DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR); | |
868 | WAIT_MSEC(1); | |
869 | ||
870 | /* OFF -> Deep Stan-By -> Stand-by */ | |
871 | /* let's change the state from "Stand-by" to "Sleep" */ | |
872 | DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0005); | |
873 | WAIT_MSEC(1); | |
874 | ||
875 | /* Sleep -> Displaying */ | |
876 | DISP_WRITE_OUT(DISP_START_OSCILLATION_ADDR, 0x0001); | |
877 | DISP_WRITE_OUT(DISP_DRIVER_OUTPUT_CTL_ADDR, 0x0127); | |
878 | DISP_WRITE_OUT(DISP_LCD_DRIVING_SIG_ADDR, 0x200); | |
879 | /* fast write mode */ | |
880 | DISP_WRITE_OUT(DISP_ENTRY_MODE_ADDR, 0x0130); | |
881 | if (tmd20qvga_lcd_rev == 2) | |
882 | DISP_WRITE_OUT(DISP_TMD_700_ADDR, 0x0003); | |
883 | /* back porch = 14 + front porch = 2 --> 16 lines */ | |
884 | if (tmd20qvga_lcd_rev == 2) { | |
885 | #ifdef TMD20QVGA_LCD_18BPP | |
886 | /* 256k color */ | |
887 | DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x0000); | |
888 | #else | |
889 | /* 65k color */ | |
890 | DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x4000); | |
891 | #endif | |
892 | DISP_WRITE_OUT(DISP_DISPLAY_CTL_2_ADDR, 0x0302); | |
893 | } else { | |
894 | #ifdef TMD20QVGA_LCD_18BPP | |
895 | /* 256k color */ | |
896 | DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x0004); | |
897 | #else | |
898 | /* 65k color */ | |
899 | DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x4004); | |
900 | #endif | |
901 | DISP_WRITE_OUT(DISP_DISPLAY_CTL_2_ADDR, 0x020E); | |
902 | } | |
903 | /* 16 bit one transfer */ | |
904 | if (tmd20qvga_lcd_rev == 2) { | |
905 | DISP_WRITE_OUT(DISP_EXT_DISPLAY_CTL_1_ADDR, 0x0000); | |
906 | DISP_WRITE_OUT(DISP_FRAME_CYCLE_CTL_ADDR, 0x0010); | |
907 | DISP_WRITE_OUT(DISP_LTPS_CTL_1_ADDR, 0x0302); | |
908 | DISP_WRITE_OUT(DISP_LTPS_CTL_2_ADDR, 0x0102); | |
909 | DISP_WRITE_OUT(DISP_LTPS_CTL_3_ADDR, 0x0000); | |
910 | DISP_WRITE_OUT(DISP_TMD_015_ADDR, 0x2000); | |
911 | ||
912 | DISP_WRITE_OUT(DISP_AMP_SETTING_ADDR, 0x0000); | |
913 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403); | |
914 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0304); | |
915 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0403); | |
916 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303); | |
917 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0101); | |
918 | DISP_WRITE_OUT(DISP_TMD_305_ADDR, 0); | |
919 | ||
920 | DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, 0x0000); | |
921 | DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, 0x013F); | |
922 | ||
923 | DISP_WRITE_OUT(DISP_POWER_CTL_3_ADDR, 0x077D); | |
924 | ||
925 | DISP_WRITE_OUT(DISP_POWER_CTL_4_ADDR, 0x0005); | |
926 | DISP_WRITE_OUT(DISP_POWER_CTL_5_ADDR, 0x0000); | |
927 | DISP_WRITE_OUT(DISP_POWER_CTL_6_ADDR, 0x0015); | |
928 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC010); | |
929 | WAIT_MSEC(1); | |
930 | ||
931 | DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x0001); | |
932 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFFE); | |
933 | WAIT_MSEC(60); | |
934 | } else { | |
935 | DISP_WRITE_OUT(DISP_EXT_DISPLAY_CTL_1_ADDR, 0x0001); | |
936 | DISP_WRITE_OUT(DISP_FRAME_CYCLE_CTL_ADDR, 0x0010); | |
937 | DISP_WRITE_OUT(DISP_LTPS_CTL_1_ADDR, 0x0301); | |
938 | DISP_WRITE_OUT(DISP_LTPS_CTL_2_ADDR, 0x0001); | |
939 | DISP_WRITE_OUT(DISP_LTPS_CTL_3_ADDR, 0x0000); | |
940 | DISP_WRITE_OUT(DISP_AMP_SETTING_ADDR, 0x0000); | |
941 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0507); | |
942 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0405); | |
943 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0607); | |
944 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0502); | |
945 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0301); | |
946 | DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, 0x0000); | |
947 | DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, 0x013F); | |
948 | DISP_WRITE_OUT(DISP_POWER_CTL_3_ADDR, 0x0795); | |
949 | ||
950 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0102); | |
951 | WAIT_MSEC(1); | |
952 | ||
953 | DISP_WRITE_OUT(DISP_POWER_CTL_4_ADDR, 0x0450); | |
954 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0103); | |
955 | WAIT_MSEC(1); | |
956 | ||
957 | DISP_WRITE_OUT(DISP_POWER_CTL_5_ADDR, 0x0008); | |
958 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0104); | |
959 | WAIT_MSEC(1); | |
960 | ||
961 | DISP_WRITE_OUT(DISP_POWER_CTL_6_ADDR, 0x0C00); | |
962 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0105); | |
963 | WAIT_MSEC(1); | |
964 | ||
965 | DISP_WRITE_OUT(DISP_POWER_CTL_7_ADDR, 0x0000); | |
966 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0106); | |
967 | WAIT_MSEC(1); | |
968 | ||
969 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0801); | |
970 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); | |
971 | WAIT_MSEC(1); | |
972 | ||
973 | DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x001F); | |
974 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0101); | |
975 | WAIT_MSEC(60); | |
976 | ||
977 | DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x009F); | |
978 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0101); | |
979 | WAIT_MSEC(10); | |
980 | ||
981 | DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_1_ADDR, 0x0010); | |
982 | DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_2_ADDR, 0x00FF); | |
983 | DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_1_ADDR, 0x0000); | |
984 | DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_2_ADDR, 0x013F); | |
985 | /* RAM starts at address 0x10 */ | |
986 | DISP_WRITE_OUT(DISP_RAM_ADDR_SET_1_ADDR, 0x0010); | |
987 | DISP_WRITE_OUT(DISP_RAM_ADDR_SET_2_ADDR, 0x0000); | |
988 | ||
989 | /* lcd controller uses internal clock, not ext. vsync */ | |
990 | DISP_CMD_OUT(DISP_CMD_RAMWR); | |
991 | ||
992 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0881); | |
993 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); | |
994 | WAIT_MSEC(40); | |
995 | ||
996 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BE1); | |
997 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); | |
998 | WAIT_MSEC(40); | |
999 | ||
1000 | DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFF); | |
1001 | DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); | |
1002 | } | |
1003 | display_on = TRUE; | |
1004 | } | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static void tmd20qvga_disp_set_contrast(void) | |
1010 | { | |
1011 | #if (defined(TMD20QVGA_LCD_18BPP)) | |
1012 | ||
1013 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403); | |
1014 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0302); | |
1015 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0403); | |
1016 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303); | |
1017 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0F07); | |
1018 | ||
1019 | #else | |
1020 | int newcontrast = 0x46; | |
1021 | ||
1022 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403); | |
1023 | ||
1024 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, | |
1025 | DISP_VAL_IF(newcontrast & 0x0001, DISP_BITMASK_PKP20) | | |
1026 | DISP_VAL_IF(newcontrast & 0x0002, DISP_BITMASK_PKP21) | | |
1027 | DISP_VAL_IF(newcontrast & 0x0004, DISP_BITMASK_PKP22) | | |
1028 | DISP_VAL_IF(newcontrast & 0x0010, DISP_BITMASK_PKP30) | | |
1029 | DISP_VAL_IF(newcontrast & 0x0020, DISP_BITMASK_PKP31) | | |
1030 | DISP_VAL_IF(newcontrast & 0x0040, DISP_BITMASK_PKP32)); | |
1031 | ||
1032 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, | |
1033 | DISP_VAL_IF(newcontrast & 0x0010, DISP_BITMASK_PKP40) | | |
1034 | DISP_VAL_IF(newcontrast & 0x0020, DISP_BITMASK_PKP41) | | |
1035 | DISP_VAL_IF(newcontrast & 0x0040, DISP_BITMASK_PKP42) | | |
1036 | DISP_VAL_IF(newcontrast & 0x0001, DISP_BITMASK_PKP50) | | |
1037 | DISP_VAL_IF(newcontrast & 0x0002, DISP_BITMASK_PKP51) | | |
1038 | DISP_VAL_IF(newcontrast & 0x0004, DISP_BITMASK_PKP52)); | |
1039 | ||
1040 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303); | |
1041 | DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0F07); | |
1042 | ||
1043 | #endif /* defined(TMD20QVGA_LCD_18BPP) */ | |
1044 | ||
1045 | } /* End disp_set_contrast */ | |
1046 | ||
1047 | void tmd20qvga_disp_clear_screen_area | |
1048 | (word start_row, word end_row, word start_column, word end_column) { | |
1049 | int32 i; | |
1050 | ||
1051 | /* Clear the display screen */ | |
1052 | DISP_SET_RECT(start_row, end_row, start_column, end_column); | |
1053 | DISP_CMD_OUT(DISP_CMD_RAMWR); | |
1054 | i = (end_row - start_row + 1) * (end_column - start_column + 1); | |
1055 | for (; i > 0; i--) | |
1056 | DISP_DATA_OUT_16TO18BPP(0x0); | |
1057 | } | |
1058 | ||
1059 | static int __init tmd20qvga_probe(struct platform_device *pdev) | |
1060 | { | |
1061 | msm_fb_add_device(pdev); | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | static struct platform_driver this_driver = { | |
1067 | .probe = tmd20qvga_probe, | |
1068 | .driver = { | |
1069 | .name = "ebi2_tmd_qvga", | |
1070 | }, | |
1071 | }; | |
1072 | ||
1073 | static struct msm_fb_panel_data tmd20qvga_panel_data = { | |
1074 | .on = tmd20qvga_disp_on, | |
1075 | .off = tmd20qvga_disp_off, | |
1076 | .set_rect = tmd20qvga_disp_set_rect, | |
1077 | }; | |
1078 | ||
1079 | static struct platform_device this_device = { | |
1080 | .name = "ebi2_tmd_qvga", | |
1081 | .id = 0, | |
1082 | .dev = { | |
1083 | .platform_data = &tmd20qvga_panel_data, | |
1084 | } | |
1085 | }; | |
1086 | ||
1087 | static int __init tmd20qvga_init(void) | |
1088 | { | |
1089 | int ret; | |
1090 | struct msm_panel_info *pinfo; | |
1091 | ||
1092 | ret = platform_driver_register(&this_driver); | |
1093 | if (!ret) { | |
1094 | pinfo = &tmd20qvga_panel_data.panel_info; | |
1095 | pinfo->xres = 240; | |
1096 | pinfo->yres = 320; | |
1097 | pinfo->type = EBI2_PANEL; | |
1098 | pinfo->pdest = DISPLAY_1; | |
1099 | pinfo->wait_cycle = 0x808000; | |
1100 | #ifdef TMD20QVGA_LCD_18BPP | |
1101 | pinfo->bpp = 18; | |
1102 | #else | |
1103 | pinfo->bpp = 16; | |
1104 | #endif | |
1105 | pinfo->fb_num = 2; | |
1106 | pinfo->lcd.vsync_enable = TRUE; | |
1107 | pinfo->lcd.refx100 = 6000; | |
1108 | pinfo->lcd.v_back_porch = 16; | |
1109 | pinfo->lcd.v_front_porch = 4; | |
1110 | pinfo->lcd.v_pulse_width = 0; | |
1111 | pinfo->lcd.hw_vsync_mode = FALSE; | |
1112 | pinfo->lcd.vsync_notifier_period = 0; | |
1113 | ||
1114 | ret = platform_device_register(&this_device); | |
1115 | if (ret) | |
1116 | platform_driver_unregister(&this_driver); | |
1117 | } | |
1118 | ||
1119 | return ret; | |
1120 | } | |
1121 | ||
1122 | module_init(tmd20qvga_init); |