[mirror_ubuntu-artful-kernel.git] / drivers / staging / msm / mddihosti.h

/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Code Aurora nor
 *       the names of its contributors may be used to endorse or promote
 *       products derived from this software without specific prior written
 *       permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef MDDIHOSTI_H
#define MDDIHOSTI_H

#include "msm_fb.h"
#include "mddihost.h"
#include <linux/clk.h>

/* Register offsets in MDDI, applies to both msm_pmdh_base and
 * (u32)msm_emdh_base. */
#define MDDI_CMD   		0x0000
#define MDDI_VERSION   		0x0004
#define MDDI_PRI_PTR		0x0008
#define MDDI_BPS		0x0010
#define MDDI_SPM		0x0014
#define MDDI_INT		0x0018
#define MDDI_INTEN		0x001c
#define MDDI_REV_PTR		0x0020
#define MDDI_REV_SIZE		0x0024
#define MDDI_STAT		0x0028
#define MDDI_REV_RATE_DIV	0x002c
#define MDDI_REV_CRC_ERR	0x0030
#define MDDI_TA1_LEN		0x0034
#define MDDI_TA2_LEN		0x0038
#define MDDI_TEST		0x0040
#define MDDI_REV_PKT_CNT	0x0044
#define MDDI_DRIVE_HI		0x0048
#define MDDI_DRIVE_LO		0x004c
#define MDDI_DISP_WAKE		0x0050
#define MDDI_REV_ENCAP_SZ	0x0054
#define MDDI_RTD_VAL		0x0058
#define MDDI_PAD_CTL		0x0068
#define MDDI_DRIVER_START_CNT	0x006c
#define MDDI_CORE_VER		0x008c
#define MDDI_FIFO_ALLOC         0x0090
#define MDDI_PAD_IO_CTL         0x00a0
#define MDDI_PAD_CAL            0x00a4

extern u32 mddi_msg_level;

/* No longer need to write to clear these registers */
#define xxxx_mddi_host_reg_outm(reg, mask, val)  \
do { \
	if (host_idx == MDDI_HOST_PRIM) \
		mddi_host_reg_outm_pmdh(reg, mask, val); \
	else \
		mddi_host_reg_outm_emdh(reg, mask, val); \
} while (0)

#define mddi_host_reg_outm(reg, mask, val) \
do { \
	unsigned long __addr; \
	if (host_idx == MDDI_HOST_PRIM) \
		__addr = (u32)msm_pmdh_base + MDDI_##reg; \
	else \
		__addr = (u32)msm_emdh_base + MDDI_##reg; \
	writel((readl(__addr) & ~(mask)) | ((val) & (mask)), __addr); \
} while (0)

#define xxxx_mddi_host_reg_out(reg, val) \
do { \
	if (host_idx == MDDI_HOST_PRIM)  \
		mddi_host_reg_out_pmdh(reg, val); \
	else \
		mddi_host_reg_out_emdh(reg, val); \
	} while (0)

#define mddi_host_reg_out(reg, val) \
do { \
	if (host_idx == MDDI_HOST_PRIM) \
		writel(val, (u32)msm_pmdh_base + MDDI_##reg); \
	else \
		writel(val, (u32)msm_emdh_base + MDDI_##reg); \
} while (0)

#define xxxx_mddi_host_reg_in(reg)  \
  ((host_idx) ? \
     mddi_host_reg_in_emdh(reg) : mddi_host_reg_in_pmdh(reg));

#define mddi_host_reg_in(reg) \
((host_idx) ? \
	readl((u32)msm_emdh_base + MDDI_##reg) : \
	readl((u32)msm_pmdh_base + MDDI_##reg)) \

#define xxxx_mddi_host_reg_inm(reg, mask)  \
  ((host_idx) ? \
    mddi_host_reg_inm_emdh(reg, mask) : \
    mddi_host_reg_inm_pmdh(reg, mask);)

#define mddi_host_reg_inm(reg, mask) \
((host_idx) ? \
	readl((u32)msm_emdh_base + MDDI_##reg) & (mask) : \
	readl((u32)msm_pmdh_base + MDDI_##reg) & (mask)) \

/* Using non-cacheable pmem, so do nothing */
#define mddi_invalidate_cache_lines(addr_start, num_bytes)
/*
 * Using non-cacheable pmem, so do nothing with cache
 * but, ensure write goes out to memory
 */
#define mddi_flush_cache_lines(addr_start, num_bytes)  \
    (void) addr_start; \
    (void) num_bytes;  \
    memory_barrier()

/* Since this translates to Remote Procedure Calls to check on clock status
* just use a local variable to keep track of io_clock */
#define MDDI_HOST_IS_IO_CLOCK_ON mddi_host_io_clock_on
#define MDDI_HOST_ENABLE_IO_CLOCK
#define MDDI_HOST_DISABLE_IO_CLOCK
#define MDDI_HOST_IS_HCLK_ON mddi_host_hclk_on
#define MDDI_HOST_ENABLE_HCLK
#define MDDI_HOST_DISABLE_HCLK
#define FEATURE_MDDI_HOST_IO_CLOCK_CONTROL_DISABLE
#define FEATURE_MDDI_HOST_HCLK_CONTROL_DISABLE

#define TRAMP_MDDI_HOST_ISR TRAMP_MDDI_PRI_ISR
#define TRAMP_MDDI_HOST_EXT_ISR TRAMP_MDDI_EXT_ISR
#define MDP_LINE_COUNT_BMSK  0x3ff
#define MDP_SYNC_STATUS  0x000c
#define MDP_LINE_COUNT      \
(readl(msm_mdp_base + MDP_SYNC_STATUS) & MDP_LINE_COUNT_BMSK)

/* MDP sends 256 pixel packets, so lower value hibernates more without
* significantly increasing latency of waiting for next subframe */
#define MDDI_HOST_BYTES_PER_SUBFRAME  0x3C00

#if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
#define MDDI_HOST_TA2_LEN       0x001a
#define MDDI_HOST_REV_RATE_DIV  0x0004
#else
#define MDDI_HOST_TA2_LEN       0x000c
#define MDDI_HOST_REV_RATE_DIV  0x0002
#endif

#define MDDI_MSG_EMERG(msg, ...)    \
	if (mddi_msg_level > 0)  \
		printk(KERN_EMERG msg, ## __VA_ARGS__);
#define MDDI_MSG_ALERT(msg, ...)    \
	if (mddi_msg_level > 1)  \
		printk(KERN_ALERT msg, ## __VA_ARGS__);
#define MDDI_MSG_CRIT(msg, ...)    \
	if (mddi_msg_level > 2)  \
		printk(KERN_CRIT msg, ## __VA_ARGS__);
#define MDDI_MSG_ERR(msg, ...)    \
	if (mddi_msg_level > 3)  \
		printk(KERN_ERR msg, ## __VA_ARGS__);
#define MDDI_MSG_WARNING(msg, ...)    \
	if (mddi_msg_level > 4)  \
		printk(KERN_WARNING msg, ## __VA_ARGS__);
#define MDDI_MSG_NOTICE(msg, ...)    \
	if (mddi_msg_level > 5)  \
		printk(KERN_NOTICE msg, ## __VA_ARGS__);
#define MDDI_MSG_INFO(msg, ...)    \
	if (mddi_msg_level > 6)  \
		printk(KERN_INFO msg, ## __VA_ARGS__);
#define MDDI_MSG_DEBUG(msg, ...)    \
	if (mddi_msg_level > 7)  \
		printk(KERN_DEBUG msg, ## __VA_ARGS__);

#define GCC_PACKED __attribute__((packed))
typedef struct GCC_PACKED {
	uint16 packet_length;
	/* total # of bytes in the packet not including
		the packet_length field. */

	uint16 packet_type;
	/* A Packet Type of 70 identifies the packet as
		a Client status Packet. */

	uint16 bClient_ID;
	/* This field is reserved for future use and shall
		be set to zero. */

} mddi_rev_packet_type;

typedef struct GCC_PACKED {
	uint16 packet_length;
	/* total # of bytes in the packet not including
		the packet_length field. */

	uint16 packet_type;
	/* A Packet Type of 70 identifies the packet as
		a Client status Packet. */

	uint16 bClient_ID;
	/* This field is reserved for future use and shall
		be set to zero. */

	uint16 reverse_link_request;
	/* 16 bit unsigned integer with number of bytes client
		needs in the * reverse encapsulation message
		to transmit data. */

	uint8 crc_error_count;
	uint8 capability_change;
	uint16 graphics_busy_flags;

	uint16 parameter_CRC;
	/* 16-bit CRC of all the bytes in the packet
		including Packet Length. */

} mddi_client_status_type;

typedef struct GCC_PACKED {
	uint16 packet_length;
	/* total # of bytes in the packet not including
		the packet_length field. */

	uint16 packet_type;
	/* A Packet Type of 66 identifies the packet as
		a Client Capability Packet. */

	uint16 bClient_ID;
	/* This field is reserved for future use and
		shall be set to zero. */

	uint16 Protocol_Version;
	uint16 Minimum_Protocol_Version;
	uint16 Data_Rate_Capability;
	uint8 Interface_Type_Capability;
	uint8 Number_of_Alt_Displays;
	uint16 PostCal_Data_Rate;
	uint16 Bitmap_Width;
	uint16 Bitmap_Height;
	uint16 Display_Window_Width;
	uint16 Display_Window_Height;
	uint32 Color_Map_Size;
	uint16 Color_Map_RGB_Width;
	uint16 RGB_Capability;
	uint8 Monochrome_Capability;
	uint8 Reserved_1;
	uint16 Y_Cb_Cr_Capability;
	uint16 Bayer_Capability;
	uint16 Alpha_Cursor_Image_Planes;
	uint32 Client_Feature_Capability_Indicators;
	uint8 Maximum_Video_Frame_Rate_Capability;
	uint8 Minimum_Video_Frame_Rate_Capability;
	uint16 Minimum_Sub_frame_Rate;
	uint16 Audio_Buffer_Depth;
	uint16 Audio_Channel_Capability;
	uint16 Audio_Sample_Rate_Capability;
	uint8 Audio_Sample_Resolution;
	uint8 Mic_Audio_Sample_Resolution;
	uint16 Mic_Sample_Rate_Capability;
	uint8 Keyboard_Data_Format;
	uint8 pointing_device_data_format;
	uint16 content_protection_type;
	uint16 Mfr_Name;
	uint16 Product_Code;
	uint16 Reserved_3;
	uint32 Serial_Number;
	uint8 Week_of_Manufacture;
	uint8 Year_of_Manufacture;

	uint16 parameter_CRC;
	/* 16-bit CRC of all the bytes in the packet including Packet Length. */

} mddi_client_capability_type;

typedef struct GCC_PACKED {
	uint16 packet_length;
	/* total # of bytes in the packet not including the packet_length field. */

	uint16 packet_type;
	/* A Packet Type of 16 identifies the packet as a Video Stream Packet. */

	uint16 bClient_ID;
	/* This field is reserved for future use and shall be set to zero. */

	uint16 video_data_format_descriptor;
	/* format of each pixel in the Pixel Data in the present stream in the
	 * present packet.
	 * If bits [15:13] = 000 monochrome
	 * If bits [15:13] = 001 color pixels (palette).
	 * If bits [15:13] = 010 color pixels in raw RGB
	 * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
	 * If bits [15:13] = 100 Bayer pixels
	 */

	uint16 pixel_data_attributes;
	/* interpreted as follows:
	 * Bits [1:0] = 11  pixel data is displayed to both eyes
	 * Bits [1:0] = 10  pixel data is routed to the left eye only.
	 * Bits [1:0] = 01  pixel data is routed to the right eye only.
	 * Bits [1:0] = 00  pixel data is routed to the alternate display.
	 * Bit 2 is 0  Pixel Data is in the standard progressive format.
	 * Bit 2 is 1  Pixel Data is in interlace format.
	 * Bit 3 is 0  Pixel Data is in the standard progressive format.
	 * Bit 3 is 1  Pixel Data is in alternate pixel format.
	 * Bit 4 is 0  Pixel Data is to or from the display frame buffer.
	 * Bit 4 is 1  Pixel Data is to or from the camera.
	 * Bit 5 is 0  pixel data contains the next consecutive row of pixels.
	 * Bit 5 is 1  X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
	 *             X Start, and Y Start parameters are not defined and
	 *             shall be ignored by the client.
	 * Bits [7:6] = 01  Pixel data is written to the offline image buffer.
	 * Bits [7:6] = 00  Pixel data is written to the buffer to refresh display.
	 * Bits [7:6] = 11  Pixel data is written to all image buffers.
	 * Bits [7:6] = 10  Invalid. Reserved for future use.
	 * Bits 8 through 11 alternate display number.
	 * Bits 12 through 14 are reserved for future use and shall be set to zero.
	 * Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
	 */

	uint16 x_left_edge;
	uint16 y_top_edge;
	/* X,Y coordinate of the top left edge of the screen window */

	uint16 x_right_edge;
	uint16 y_bottom_edge;
	/*  X,Y coordinate of the bottom right edge of the window being updated. */

	uint16 x_start;
	uint16 y_start;
	/*  (X Start, Y Start) is the first pixel in the Pixel Data field below. */

	uint16 pixel_count;
	/*  number of pixels in the Pixel Data field below. */

	uint16 parameter_CRC;
	/*  16-bit CRC of all bytes from the Packet Length to the Pixel Count. */

	uint16 reserved;
	/* 16-bit variable to make structure align on 4 byte boundary */

} mddi_video_stream_packet_type;

typedef struct GCC_PACKED {
	uint16 packet_length;
	/* total # of bytes in the packet not including the packet_length field. */

	uint16 packet_type;
	/* A Packet Type of 146 identifies the packet as a Register Access Packet. */

	uint16 bClient_ID;
	/* This field is reserved for future use and shall be set to zero. */

	uint16 read_write_info;
	/* Bits 13:0  a 14-bit unsigned integer that specifies the number of
	 *            32-bit Register Data List items to be transferred in the
	 *            Register Data List field.
	 * Bits[15:14] = 00  Write to register(s);
	 * Bits[15:14] = 10  Read from register(s);
	 * Bits[15:14] = 11  Response to a Read.
	 * Bits[15:14] = 01  this value is reserved for future use. */

	uint32 register_address;
	/* the register address that is to be written to or read from. */

	uint16 parameter_CRC;
	/* 16-bit CRC of all bytes from the Packet Length to the Register Address. */

	uint32 register_data_list;
	/* list of 4-byte register data values for/from client registers */

} mddi_register_access_packet_type;

typedef union GCC_PACKED {
	mddi_video_stream_packet_type video_pkt;
	mddi_register_access_packet_type register_pkt;
	/* add 48 byte pad to ensure 64 byte llist struct, that can be
	 * manipulated easily with cache */
	uint32 alignment_pad[12];	/* 48 bytes */
} mddi_packet_header_type;

typedef struct GCC_PACKED mddi_host_llist_struct {
	uint16 link_controller_flags;
	uint16 packet_header_count;
	uint16 packet_data_count;
	void *packet_data_pointer;
	struct mddi_host_llist_struct *next_packet_pointer;
	uint16 reserved;
	mddi_packet_header_type packet_header;
} mddi_linked_list_type;

typedef struct {
	struct completion done_comp;
	mddi_llist_done_cb_type done_cb;
	uint16 next_idx;
	boolean waiting;
	boolean in_use;
} mddi_linked_list_notify_type;

#define MDDI_LLIST_POOL_SIZE 0x1000
#define MDDI_MAX_NUM_LLIST_ITEMS (MDDI_LLIST_POOL_SIZE / \
		 sizeof(mddi_linked_list_type))
#define UNASSIGNED_INDEX MDDI_MAX_NUM_LLIST_ITEMS
#define MDDI_FIRST_DYNAMIC_LLIST_IDX 0

/* Static llist items can be used for applications that frequently send
 * the same set of packets using the linked list interface. */
/* Here we configure for 6 static linked list items:
 *  The 1st is used for a the adaptive backlight setting.
 *  and the remaining 5 are used for sending window adjustments for
 *  MDDI clients that need windowing info sent separate from video
 *  packets. */
#define MDDI_NUM_STATIC_ABL_ITEMS 1
#define MDDI_NUM_STATIC_WINDOW_ITEMS 5
#define MDDI_NUM_STATIC_LLIST_ITEMS (MDDI_NUM_STATIC_ABL_ITEMS + \
				MDDI_NUM_STATIC_WINDOW_ITEMS)
#define MDDI_NUM_DYNAMIC_LLIST_ITEMS (MDDI_MAX_NUM_LLIST_ITEMS - \
				MDDI_NUM_STATIC_LLIST_ITEMS)

#define MDDI_FIRST_STATIC_LLIST_IDX  MDDI_NUM_DYNAMIC_LLIST_ITEMS
#define MDDI_FIRST_STATIC_ABL_IDX  MDDI_FIRST_STATIC_LLIST_IDX
#define MDDI_FIRST_STATIC_WINDOW_IDX  (MDDI_FIRST_STATIC_LLIST_IDX + \
				MDDI_NUM_STATIC_ABL_ITEMS)

/* GPIO registers */
#define VSYNC_WAKEUP_REG          0x80
#define GPIO_REG                  0x81
#define GPIO_OUTPUT_REG           0x82
#define GPIO_INTERRUPT_REG        0x83
#define GPIO_INTERRUPT_ENABLE_REG 0x84
#define GPIO_POLARITY_REG         0x85

/* Interrupt Bits */
#define MDDI_INT_PRI_PTR_READ       0x0001
#define MDDI_INT_SEC_PTR_READ       0x0002
#define MDDI_INT_REV_DATA_AVAIL     0x0004
#define MDDI_INT_DISP_REQ           0x0008
#define MDDI_INT_PRI_UNDERFLOW      0x0010
#define MDDI_INT_SEC_UNDERFLOW      0x0020
#define MDDI_INT_REV_OVERFLOW       0x0040
#define MDDI_INT_CRC_ERROR          0x0080
#define MDDI_INT_MDDI_IN            0x0100
#define MDDI_INT_PRI_OVERWRITE      0x0200
#define MDDI_INT_SEC_OVERWRITE      0x0400
#define MDDI_INT_REV_OVERWRITE      0x0800
#define MDDI_INT_DMA_FAILURE        0x1000
#define MDDI_INT_LINK_ACTIVE        0x2000
#define MDDI_INT_IN_HIBERNATION     0x4000
#define MDDI_INT_PRI_LINK_LIST_DONE 0x8000
#define MDDI_INT_SEC_LINK_LIST_DONE 0x10000
#define MDDI_INT_NO_CMD_PKTS_PEND   0x20000
#define MDDI_INT_RTD_FAILURE        0x40000

#define MDDI_INT_ERROR_CONDITIONS ( \
	MDDI_INT_PRI_UNDERFLOW | MDDI_INT_SEC_UNDERFLOW | \
	MDDI_INT_REV_OVERFLOW | MDDI_INT_CRC_ERROR | \
	MDDI_INT_PRI_OVERWRITE | MDDI_INT_SEC_OVERWRITE | \
	MDDI_INT_RTD_FAILURE | \
	MDDI_INT_REV_OVERWRITE | MDDI_INT_DMA_FAILURE)

#define MDDI_INT_LINK_STATE_CHANGES ( \
	MDDI_INT_LINK_ACTIVE | MDDI_INT_IN_HIBERNATION)

/* Status Bits */
#define MDDI_STAT_LINK_ACTIVE        0x0001
#define MDDI_STAT_NEW_REV_PTR        0x0002
#define MDDI_STAT_NEW_PRI_PTR        0x0004
#define MDDI_STAT_NEW_SEC_PTR        0x0008
#define MDDI_STAT_IN_HIBERNATION     0x0010
#define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020
#define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040
#define MDDI_STAT_PENDING_TIMING_PKT 0x0080
#define MDDI_STAT_PENDING_REV_ENCAP  0x0100
#define MDDI_STAT_PENDING_POWERDOWN  0x0200
#define MDDI_STAT_RTD_MEAS_FAIL      0x0800
#define MDDI_STAT_CLIENT_WAKEUP_REQ  0x1000

/* Command Bits */
#define MDDI_CMD_POWERDOWN           0x0100
#define MDDI_CMD_POWERUP             0x0200
#define MDDI_CMD_HIBERNATE           0x0300
#define MDDI_CMD_RESET               0x0400
#define MDDI_CMD_DISP_IGNORE         0x0501
#define MDDI_CMD_DISP_LISTEN         0x0500
#define MDDI_CMD_SEND_REV_ENCAP      0x0600
#define MDDI_CMD_GET_CLIENT_CAP      0x0601
#define MDDI_CMD_GET_CLIENT_STATUS   0x0602
#define MDDI_CMD_SEND_RTD            0x0700
#define MDDI_CMD_LINK_ACTIVE         0x0900
#define MDDI_CMD_PERIODIC_REV_ENCAP  0x0A00

extern void mddi_host_init(mddi_host_type host);
extern void mddi_host_powerdown(mddi_host_type host);
extern uint16 mddi_get_next_free_llist_item(mddi_host_type host, boolean wait);
extern uint16 mddi_get_reg_read_llist_item(mddi_host_type host, boolean wait);
extern void mddi_queue_forward_packets(uint16 first_llist_idx,
				       uint16 last_llist_idx,
				       boolean wait,
				       mddi_llist_done_cb_type llist_done_cb,
				       mddi_host_type host);

extern void mddi_host_write_pix_attr_reg(uint32 value);
extern void mddi_client_lcd_gpio_poll(uint32 poll_reg_val);
extern void mddi_client_lcd_vsync_detected(boolean detected);
extern void mddi_host_disable_hibernation(boolean disable);

extern mddi_linked_list_type *llist_extern[];
extern mddi_linked_list_type *llist_dma_extern[];
extern mddi_linked_list_notify_type *llist_extern_notify[];
extern struct timer_list mddi_host_timer;

typedef struct {
	uint16 transmitting_start_idx;
	uint16 transmitting_end_idx;
	uint16 waiting_start_idx;
	uint16 waiting_end_idx;
	uint16 reg_read_idx;
	uint16 next_free_idx;
	boolean reg_read_waiting;
} mddi_llist_info_type;

extern mddi_llist_info_type mddi_llist;

#define MDDI_GPIO_DEFAULT_POLLING_INTERVAL 200
typedef struct {
	uint32 polling_reg;
	uint32 polling_val;
	uint32 polling_interval;
	boolean polling_enabled;
} mddi_gpio_info_type;

uint32 mddi_get_client_id(void);
void mddi_mhctl_remove(mddi_host_type host_idx);
void mddi_host_timer_service(unsigned long data);
#endif /* MDDIHOSTI_H */
Commit	Line	Data
9d200153 SM	1	/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
	2	*
	3	* Redistribution and use in source and binary forms, with or without
	4	* modification, are permitted provided that the following conditions are met:
	5	* * Redistributions of source code must retain the above copyright
	6	* notice, this list of conditions and the following disclaimer.
	7	* * Redistributions in binary form must reproduce the above copyright
	8	* notice, this list of conditions and the following disclaimer in the
	9	* documentation and/or other materials provided with the distribution.
	10	* * Neither the name of Code Aurora nor
	11	* the names of its contributors may be used to endorse or promote
	12	* products derived from this software without specific prior written
	13	* permission.
	14	*
	15	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	16	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	17	* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	18	* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	19	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	20	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	21	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
	22	* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	23	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
	24	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
	25	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*
	27	*/
	28
	29	#ifndef MDDIHOSTI_H
	30	#define MDDIHOSTI_H
	31
	32	#include "msm_fb.h"
	33	#include "mddihost.h"
	34	#include <linux/clk.h>
	35
	36	/* Register offsets in MDDI, applies to both msm_pmdh_base and
	37	* (u32)msm_emdh_base. */
	38	#define MDDI_CMD 0x0000
	39	#define MDDI_VERSION 0x0004
	40	#define MDDI_PRI_PTR 0x0008
	41	#define MDDI_BPS 0x0010
	42	#define MDDI_SPM 0x0014
	43	#define MDDI_INT 0x0018
	44	#define MDDI_INTEN 0x001c
	45	#define MDDI_REV_PTR 0x0020
	46	#define MDDI_REV_SIZE 0x0024
	47	#define MDDI_STAT 0x0028
	48	#define MDDI_REV_RATE_DIV 0x002c
	49	#define MDDI_REV_CRC_ERR 0x0030
	50	#define MDDI_TA1_LEN 0x0034
	51	#define MDDI_TA2_LEN 0x0038
	52	#define MDDI_TEST 0x0040
	53	#define MDDI_REV_PKT_CNT 0x0044
	54	#define MDDI_DRIVE_HI 0x0048
	55	#define MDDI_DRIVE_LO 0x004c
	56	#define MDDI_DISP_WAKE 0x0050
	57	#define MDDI_REV_ENCAP_SZ 0x0054
	58	#define MDDI_RTD_VAL 0x0058
	59	#define MDDI_PAD_CTL 0x0068
	60	#define MDDI_DRIVER_START_CNT 0x006c
	61	#define MDDI_CORE_VER 0x008c
	62	#define MDDI_FIFO_ALLOC 0x0090
	63	#define MDDI_PAD_IO_CTL 0x00a0
	64	#define MDDI_PAD_CAL 0x00a4
65
66	extern u32 mddi_msg_level;
67
68	/* No longer need to write to clear these registers */
69	#define xxxx_mddi_host_reg_outm(reg, mask, val) \
70	do { \
71	if (host_idx == MDDI_HOST_PRIM) \
72	mddi_host_reg_outm_pmdh(reg, mask, val); \
73	else \
74	mddi_host_reg_outm_emdh(reg, mask, val); \
75	} while (0)
76
77	#define mddi_host_reg_outm(reg, mask, val) \
78	do { \
79	unsigned long __addr; \
80	if (host_idx == MDDI_HOST_PRIM) \
81	__addr = (u32)msm_pmdh_base + MDDI_##reg; \
82	else \
83	__addr = (u32)msm_emdh_base + MDDI_##reg; \
84	writel((readl(__addr) & ~(mask)) \| ((val) & (mask)), __addr); \
85	} while (0)
86
87	#define xxxx_mddi_host_reg_out(reg, val) \
88	do { \
89	if (host_idx == MDDI_HOST_PRIM) \
90	mddi_host_reg_out_pmdh(reg, val); \
91	else \
92	mddi_host_reg_out_emdh(reg, val); \
93	} while (0)
94
95	#define mddi_host_reg_out(reg, val) \
96	do { \
97	if (host_idx == MDDI_HOST_PRIM) \
98	writel(val, (u32)msm_pmdh_base + MDDI_##reg); \
99	else \
100	writel(val, (u32)msm_emdh_base + MDDI_##reg); \
101	} while (0)
102
103	#define xxxx_mddi_host_reg_in(reg) \
104	((host_idx) ? \
105	mddi_host_reg_in_emdh(reg) : mddi_host_reg_in_pmdh(reg));
106
107	#define mddi_host_reg_in(reg) \
108	((host_idx) ? \
109	readl((u32)msm_emdh_base + MDDI_##reg) : \
110	readl((u32)msm_pmdh_base + MDDI_##reg)) \
111
112	#define xxxx_mddi_host_reg_inm(reg, mask) \
113	((host_idx) ? \
114	mddi_host_reg_inm_emdh(reg, mask) : \
115	mddi_host_reg_inm_pmdh(reg, mask);)
116
117	#define mddi_host_reg_inm(reg, mask) \
118	((host_idx) ? \
119	readl((u32)msm_emdh_base + MDDI_##reg) & (mask) : \
120	readl((u32)msm_pmdh_base + MDDI_##reg) & (mask)) \
121
122	/* Using non-cacheable pmem, so do nothing */
123	#define mddi_invalidate_cache_lines(addr_start, num_bytes)
124	/*
125	* Using non-cacheable pmem, so do nothing with cache
126	* but, ensure write goes out to memory
127	*/
128	#define mddi_flush_cache_lines(addr_start, num_bytes) \
129	(void) addr_start; \
130	(void) num_bytes; \
131	memory_barrier()
132
133	/* Since this translates to Remote Procedure Calls to check on clock status
134	* just use a local variable to keep track of io_clock */
135	#define MDDI_HOST_IS_IO_CLOCK_ON mddi_host_io_clock_on
136	#define MDDI_HOST_ENABLE_IO_CLOCK
137	#define MDDI_HOST_DISABLE_IO_CLOCK
138	#define MDDI_HOST_IS_HCLK_ON mddi_host_hclk_on
139	#define MDDI_HOST_ENABLE_HCLK
140	#define MDDI_HOST_DISABLE_HCLK
141	#define FEATURE_MDDI_HOST_IO_CLOCK_CONTROL_DISABLE
142	#define FEATURE_MDDI_HOST_HCLK_CONTROL_DISABLE
143
144	#define TRAMP_MDDI_HOST_ISR TRAMP_MDDI_PRI_ISR
145	#define TRAMP_MDDI_HOST_EXT_ISR TRAMP_MDDI_EXT_ISR
146	#define MDP_LINE_COUNT_BMSK 0x3ff
147	#define MDP_SYNC_STATUS 0x000c
148	#define MDP_LINE_COUNT \
149	(readl(msm_mdp_base + MDP_SYNC_STATUS) & MDP_LINE_COUNT_BMSK)
150
151	/* MDP sends 256 pixel packets, so lower value hibernates more without
152	* significantly increasing latency of waiting for next subframe */
153	#define MDDI_HOST_BYTES_PER_SUBFRAME 0x3C00
154
155	#if defined(CONFIG_FB_MSM_MDP31) \|\| defined(CONFIG_FB_MSM_MDP40)
156	#define MDDI_HOST_TA2_LEN 0x001a
157	#define MDDI_HOST_REV_RATE_DIV 0x0004
158	#else
159	#define MDDI_HOST_TA2_LEN 0x000c
160	#define MDDI_HOST_REV_RATE_DIV 0x0002
161	#endif
162
163	#define MDDI_MSG_EMERG(msg, ...) \
164	if (mddi_msg_level > 0) \
165	printk(KERN_EMERG msg, ## __VA_ARGS__);
166	#define MDDI_MSG_ALERT(msg, ...) \
167	if (mddi_msg_level > 1) \
168	printk(KERN_ALERT msg, ## __VA_ARGS__);
169	#define MDDI_MSG_CRIT(msg, ...) \
170	if (mddi_msg_level > 2) \
171	printk(KERN_CRIT msg, ## __VA_ARGS__);
172	#define MDDI_MSG_ERR(msg, ...) \
173	if (mddi_msg_level > 3) \
174	printk(KERN_ERR msg, ## __VA_ARGS__);
175	#define MDDI_MSG_WARNING(msg, ...) \
176	if (mddi_msg_level > 4) \
177	printk(KERN_WARNING msg, ## __VA_ARGS__);
178	#define MDDI_MSG_NOTICE(msg, ...) \
179	if (mddi_msg_level > 5) \
180	printk(KERN_NOTICE msg, ## __VA_ARGS__);
181	#define MDDI_MSG_INFO(msg, ...) \
182	if (mddi_msg_level > 6) \
183	printk(KERN_INFO msg, ## __VA_ARGS__);
184	#define MDDI_MSG_DEBUG(msg, ...) \
185	if (mddi_msg_level > 7) \
186	printk(KERN_DEBUG msg, ## __VA_ARGS__);
187
188	#define GCC_PACKED __attribute__((packed))
189	typedef struct GCC_PACKED {
190	uint16 packet_length;
191	/* total # of bytes in the packet not including
192	the packet_length field. */
193
194	uint16 packet_type;
195	/* A Packet Type of 70 identifies the packet as
196	a Client status Packet. */
197
198	uint16 bClient_ID;
199	/* This field is reserved for future use and shall
200	be set to zero. */
201
202	} mddi_rev_packet_type;
203
204	typedef struct GCC_PACKED {
205	uint16 packet_length;
206	/* total # of bytes in the packet not including
207	the packet_length field. */
208
209	uint16 packet_type;
210	/* A Packet Type of 70 identifies the packet as
211	a Client status Packet. */
212
213	uint16 bClient_ID;
214	/* This field is reserved for future use and shall
215	be set to zero. */
216
217	uint16 reverse_link_request;
218	/* 16 bit unsigned integer with number of bytes client
219	needs in the * reverse encapsulation message
220	to transmit data. */
221
222	uint8 crc_error_count;
223	uint8 capability_change;
224	uint16 graphics_busy_flags;
225
226	uint16 parameter_CRC;
227	/* 16-bit CRC of all the bytes in the packet
228	including Packet Length. */
229
230	} mddi_client_status_type;
231
232	typedef struct GCC_PACKED {
233	uint16 packet_length;
234	/* total # of bytes in the packet not including
235	the packet_length field. */
236
237	uint16 packet_type;
238	/* A Packet Type of 66 identifies the packet as
239	a Client Capability Packet. */
240
241	uint16 bClient_ID;
242	/* This field is reserved for future use and
243	shall be set to zero. */
244
245	uint16 Protocol_Version;
246	uint16 Minimum_Protocol_Version;
247	uint16 Data_Rate_Capability;
248	uint8 Interface_Type_Capability;
249	uint8 Number_of_Alt_Displays;
250	uint16 PostCal_Data_Rate;
251	uint16 Bitmap_Width;
252	uint16 Bitmap_Height;
253	uint16 Display_Window_Width;
254	uint16 Display_Window_Height;
255	uint32 Color_Map_Size;
256	uint16 Color_Map_RGB_Width;
257	uint16 RGB_Capability;
258	uint8 Monochrome_Capability;
259	uint8 Reserved_1;
260	uint16 Y_Cb_Cr_Capability;
261	uint16 Bayer_Capability;
262	uint16 Alpha_Cursor_Image_Planes;
263	uint32 Client_Feature_Capability_Indicators;
264	uint8 Maximum_Video_Frame_Rate_Capability;
265	uint8 Minimum_Video_Frame_Rate_Capability;
266	uint16 Minimum_Sub_frame_Rate;
267	uint16 Audio_Buffer_Depth;
268	uint16 Audio_Channel_Capability;
269	uint16 Audio_Sample_Rate_Capability;
270	uint8 Audio_Sample_Resolution;
271	uint8 Mic_Audio_Sample_Resolution;
272	uint16 Mic_Sample_Rate_Capability;
273	uint8 Keyboard_Data_Format;
274	uint8 pointing_device_data_format;
275	uint16 content_protection_type;
276	uint16 Mfr_Name;
277	uint16 Product_Code;
278	uint16 Reserved_3;
279	uint32 Serial_Number;
280	uint8 Week_of_Manufacture;
281	uint8 Year_of_Manufacture;
282
283	uint16 parameter_CRC;
284	/* 16-bit CRC of all the bytes in the packet including Packet Length. */
285
286	} mddi_client_capability_type;
287
288	typedef struct GCC_PACKED {
289	uint16 packet_length;
290	/* total # of bytes in the packet not including the packet_length field. */
291
292	uint16 packet_type;
293	/* A Packet Type of 16 identifies the packet as a Video Stream Packet. */
294
295	uint16 bClient_ID;
296	/* This field is reserved for future use and shall be set to zero. */
297
298	uint16 video_data_format_descriptor;
299	/* format of each pixel in the Pixel Data in the present stream in the
300	* present packet.
301	* If bits [15:13] = 000 monochrome
302	* If bits [15:13] = 001 color pixels (palette).
303	* If bits [15:13] = 010 color pixels in raw RGB
304	* If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
305	* If bits [15:13] = 100 Bayer pixels
306	*/
307
308	uint16 pixel_data_attributes;
309	/* interpreted as follows:
310	* Bits [1:0] = 11 pixel data is displayed to both eyes
311	* Bits [1:0] = 10 pixel data is routed to the left eye only.
312	* Bits [1:0] = 01 pixel data is routed to the right eye only.
313	* Bits [1:0] = 00 pixel data is routed to the alternate display.
314	* Bit 2 is 0 Pixel Data is in the standard progressive format.
315	* Bit 2 is 1 Pixel Data is in interlace format.
316	* Bit 3 is 0 Pixel Data is in the standard progressive format.
317	* Bit 3 is 1 Pixel Data is in alternate pixel format.
318	* Bit 4 is 0 Pixel Data is to or from the display frame buffer.
319	* Bit 4 is 1 Pixel Data is to or from the camera.
320	* Bit 5 is 0 pixel data contains the next consecutive row of pixels.
321	* Bit 5 is 1 X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
322	* X Start, and Y Start parameters are not defined and
323	* shall be ignored by the client.
324	* Bits [7:6] = 01 Pixel data is written to the offline image buffer.
325	* Bits [7:6] = 00 Pixel data is written to the buffer to refresh display.
326	* Bits [7:6] = 11 Pixel data is written to all image buffers.
327	* Bits [7:6] = 10 Invalid. Reserved for future use.
328	* Bits 8 through 11 alternate display number.
329	* Bits 12 through 14 are reserved for future use and shall be set to zero.
330	* Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
331	*/
332
333	uint16 x_left_edge;
334	uint16 y_top_edge;
335	/* X,Y coordinate of the top left edge of the screen window */
336
337	uint16 x_right_edge;
338	uint16 y_bottom_edge;
339	/* X,Y coordinate of the bottom right edge of the window being updated. */
340
341	uint16 x_start;
342	uint16 y_start;
343	/* (X Start, Y Start) is the first pixel in the Pixel Data field below. */
344
345	uint16 pixel_count;
346	/* number of pixels in the Pixel Data field below. */
347
348	uint16 parameter_CRC;
349	/* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
350
351	uint16 reserved;
352	/* 16-bit variable to make structure align on 4 byte boundary */
353
354	} mddi_video_stream_packet_type;
355
356	typedef struct GCC_PACKED {
357	uint16 packet_length;
358	/* total # of bytes in the packet not including the packet_length field. */
359
360	uint16 packet_type;
361	/* A Packet Type of 146 identifies the packet as a Register Access Packet. */
362
363	uint16 bClient_ID;
364	/* This field is reserved for future use and shall be set to zero. */
365
366	uint16 read_write_info;
367	/* Bits 13:0 a 14-bit unsigned integer that specifies the number of
368	* 32-bit Register Data List items to be transferred in the
369	* Register Data List field.
370	* Bits[15:14] = 00 Write to register(s);
371	* Bits[15:14] = 10 Read from register(s);
372	* Bits[15:14] = 11 Response to a Read.
373	* Bits[15:14] = 01 this value is reserved for future use. */
374
375	uint32 register_address;
376	/* the register address that is to be written to or read from. */
377
378	uint16 parameter_CRC;
379	/* 16-bit CRC of all bytes from the Packet Length to the Register Address. */
380
381	uint32 register_data_list;
382	/* list of 4-byte register data values for/from client registers */
383
384	} mddi_register_access_packet_type;
385
386	typedef union GCC_PACKED {
387	mddi_video_stream_packet_type video_pkt;
388	mddi_register_access_packet_type register_pkt;
389	/* add 48 byte pad to ensure 64 byte llist struct, that can be
390	* manipulated easily with cache */
391	uint32 alignment_pad[12]; /* 48 bytes */
392	} mddi_packet_header_type;
393
394	typedef struct GCC_PACKED mddi_host_llist_struct {
395	uint16 link_controller_flags;
396	uint16 packet_header_count;
397	uint16 packet_data_count;
398	void *packet_data_pointer;
399	struct mddi_host_llist_struct *next_packet_pointer;
400	uint16 reserved;
401	mddi_packet_header_type packet_header;
402	} mddi_linked_list_type;
403
404	typedef struct {
405	struct completion done_comp;
406	mddi_llist_done_cb_type done_cb;
407	uint16 next_idx;
408	boolean waiting;
409	boolean in_use;
410	} mddi_linked_list_notify_type;
411
412	#define MDDI_LLIST_POOL_SIZE 0x1000
413	#define MDDI_MAX_NUM_LLIST_ITEMS (MDDI_LLIST_POOL_SIZE / \
414	sizeof(mddi_linked_list_type))
415	#define UNASSIGNED_INDEX MDDI_MAX_NUM_LLIST_ITEMS
416	#define MDDI_FIRST_DYNAMIC_LLIST_IDX 0
417
418	/* Static llist items can be used for applications that frequently send
419	* the same set of packets using the linked list interface. */
420	/* Here we configure for 6 static linked list items:
421	* The 1st is used for a the adaptive backlight setting.
422	* and the remaining 5 are used for sending window adjustments for
423	* MDDI clients that need windowing info sent separate from video
424	* packets. */
425	#define MDDI_NUM_STATIC_ABL_ITEMS 1
426	#define MDDI_NUM_STATIC_WINDOW_ITEMS 5
427	#define MDDI_NUM_STATIC_LLIST_ITEMS (MDDI_NUM_STATIC_ABL_ITEMS + \
428	MDDI_NUM_STATIC_WINDOW_ITEMS)
429	#define MDDI_NUM_DYNAMIC_LLIST_ITEMS (MDDI_MAX_NUM_LLIST_ITEMS - \
430	MDDI_NUM_STATIC_LLIST_ITEMS)
431
432	#define MDDI_FIRST_STATIC_LLIST_IDX MDDI_NUM_DYNAMIC_LLIST_ITEMS
433	#define MDDI_FIRST_STATIC_ABL_IDX MDDI_FIRST_STATIC_LLIST_IDX
434	#define MDDI_FIRST_STATIC_WINDOW_IDX (MDDI_FIRST_STATIC_LLIST_IDX + \
435	MDDI_NUM_STATIC_ABL_ITEMS)
436
437	/* GPIO registers */
438	#define VSYNC_WAKEUP_REG 0x80
439	#define GPIO_REG 0x81
440	#define GPIO_OUTPUT_REG 0x82
441	#define GPIO_INTERRUPT_REG 0x83
442	#define GPIO_INTERRUPT_ENABLE_REG 0x84
443	#define GPIO_POLARITY_REG 0x85
444
445	/* Interrupt Bits */
446	#define MDDI_INT_PRI_PTR_READ 0x0001
447	#define MDDI_INT_SEC_PTR_READ 0x0002
448	#define MDDI_INT_REV_DATA_AVAIL 0x0004
449	#define MDDI_INT_DISP_REQ 0x0008
450	#define MDDI_INT_PRI_UNDERFLOW 0x0010
451	#define MDDI_INT_SEC_UNDERFLOW 0x0020
452	#define MDDI_INT_REV_OVERFLOW 0x0040
453	#define MDDI_INT_CRC_ERROR 0x0080
454	#define MDDI_INT_MDDI_IN 0x0100
455	#define MDDI_INT_PRI_OVERWRITE 0x0200
456	#define MDDI_INT_SEC_OVERWRITE 0x0400
457	#define MDDI_INT_REV_OVERWRITE 0x0800
458	#define MDDI_INT_DMA_FAILURE 0x1000
459	#define MDDI_INT_LINK_ACTIVE 0x2000
460	#define MDDI_INT_IN_HIBERNATION 0x4000
461	#define MDDI_INT_PRI_LINK_LIST_DONE 0x8000
462	#define MDDI_INT_SEC_LINK_LIST_DONE 0x10000
463	#define MDDI_INT_NO_CMD_PKTS_PEND 0x20000
464	#define MDDI_INT_RTD_FAILURE 0x40000
465
466	#define MDDI_INT_ERROR_CONDITIONS ( \
467	MDDI_INT_PRI_UNDERFLOW \| MDDI_INT_SEC_UNDERFLOW \| \
468	MDDI_INT_REV_OVERFLOW \| MDDI_INT_CRC_ERROR \| \
469	MDDI_INT_PRI_OVERWRITE \| MDDI_INT_SEC_OVERWRITE \| \
470	MDDI_INT_RTD_FAILURE \| \
471	MDDI_INT_REV_OVERWRITE \| MDDI_INT_DMA_FAILURE)
472
473	#define MDDI_INT_LINK_STATE_CHANGES ( \
474	MDDI_INT_LINK_ACTIVE \| MDDI_INT_IN_HIBERNATION)
475
476	/* Status Bits */
477	#define MDDI_STAT_LINK_ACTIVE 0x0001
478	#define MDDI_STAT_NEW_REV_PTR 0x0002
479	#define MDDI_STAT_NEW_PRI_PTR 0x0004
480	#define MDDI_STAT_NEW_SEC_PTR 0x0008
481	#define MDDI_STAT_IN_HIBERNATION 0x0010
482	#define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020
483	#define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040
484	#define MDDI_STAT_PENDING_TIMING_PKT 0x0080
485	#define MDDI_STAT_PENDING_REV_ENCAP 0x0100
486	#define MDDI_STAT_PENDING_POWERDOWN 0x0200
487	#define MDDI_STAT_RTD_MEAS_FAIL 0x0800
488	#define MDDI_STAT_CLIENT_WAKEUP_REQ 0x1000
489
490	/* Command Bits */
491	#define MDDI_CMD_POWERDOWN 0x0100
492	#define MDDI_CMD_POWERUP 0x0200
493	#define MDDI_CMD_HIBERNATE 0x0300
494	#define MDDI_CMD_RESET 0x0400
495	#define MDDI_CMD_DISP_IGNORE 0x0501
496	#define MDDI_CMD_DISP_LISTEN 0x0500
497	#define MDDI_CMD_SEND_REV_ENCAP 0x0600
498	#define MDDI_CMD_GET_CLIENT_CAP 0x0601
499	#define MDDI_CMD_GET_CLIENT_STATUS 0x0602
500	#define MDDI_CMD_SEND_RTD 0x0700
501	#define MDDI_CMD_LINK_ACTIVE 0x0900
502	#define MDDI_CMD_PERIODIC_REV_ENCAP 0x0A00
503
504	extern void mddi_host_init(mddi_host_type host);
505	extern void mddi_host_powerdown(mddi_host_type host);
506	extern uint16 mddi_get_next_free_llist_item(mddi_host_type host, boolean wait);
507	extern uint16 mddi_get_reg_read_llist_item(mddi_host_type host, boolean wait);
508	extern void mddi_queue_forward_packets(uint16 first_llist_idx,
509	uint16 last_llist_idx,
510	boolean wait,
511	mddi_llist_done_cb_type llist_done_cb,
512	mddi_host_type host);
513
514	extern void mddi_host_write_pix_attr_reg(uint32 value);
515	extern void mddi_client_lcd_gpio_poll(uint32 poll_reg_val);
516	extern void mddi_client_lcd_vsync_detected(boolean detected);
517	extern void mddi_host_disable_hibernation(boolean disable);
518
519	extern mddi_linked_list_type *llist_extern[];
520	extern mddi_linked_list_type *llist_dma_extern[];
521	extern mddi_linked_list_notify_type *llist_extern_notify[];
522	extern struct timer_list mddi_host_timer;
523
524	typedef struct {
525	uint16 transmitting_start_idx;
526	uint16 transmitting_end_idx;
527	uint16 waiting_start_idx;
528	uint16 waiting_end_idx;
529	uint16 reg_read_idx;
530	uint16 next_free_idx;
531	boolean reg_read_waiting;
532	} mddi_llist_info_type;
533
534	extern mddi_llist_info_type mddi_llist;
535
536	#define MDDI_GPIO_DEFAULT_POLLING_INTERVAL 200
537	typedef struct {
538	uint32 polling_reg;
539	uint32 polling_val;
540	uint32 polling_interval;
541	boolean polling_enabled;
542	} mddi_gpio_info_type;
543
544	uint32 mddi_get_client_id(void);
545	void mddi_mhctl_remove(mddi_host_type host_idx);
546	void mddi_host_timer_service(unsigned long data);
547	#endif /* MDDIHOSTI_H */