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[mirror_ubuntu-jammy-kernel.git] / drivers / staging / netlogic / xlr_net.c
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6f98b1a2
GR		 1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#include <linux/phy.h>
35#include <linux/delay.h>
36#include <linux/netdevice.h>
37#include <linux/smp.h>
38#include <linux/ethtool.h>
39#include <linux/module.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/jiffies.h>
43#include <linux/interrupt.h>
44#include <linux/platform_device.h>
45
46#include <asm/mipsregs.h>
2db0083d
A		 47/*
48 * fmn.h - For FMN credit configuration and registering fmn_handler.
6f98b1a2
GR		 49 * FMN is communication mechanism that allows processing agents within
50 * XLR/XLS to communicate each other.
51 */
52#include <asm/netlogic/xlr/fmn.h>
53
54#include "platform_net.h"
55#include "xlr_net.h"
56
57/*
58 * The readl/writel implementation byteswaps on XLR/XLS, so
59 * we need to use __raw_ IO to read the NAE registers
60 * because they are in the big-endian MMIO area on the SoC.
61 */
62static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
63{
64 __raw_writel(val, base + reg);
65}
66
67static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
68{
69 return __raw_readl(base + reg);
70}
71
72static inline void xlr_reg_update(u32 *base_addr,
73 u32 off, u32 val, u32 mask)
74{
75 u32 tmp;
76
77 tmp = xlr_nae_rdreg(base_addr, off);
78 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
79}
80
81/*
82 * Table of net_device pointers indexed by port, this will be used to
83 * lookup the net_device corresponding to a port by the message ring handler.
84 *
85 * Maximum ports in XLR/XLS is 8(8 GMAC on XLS, 4 GMAC + 2 XGMAC on XLR)
86 */
87static struct net_device *mac_to_ndev[8];
88
89static inline struct sk_buff *mac_get_skb_back_ptr(void *addr)
90{
91 struct sk_buff **back_ptr;
92
2db0083d
A		 93 /*
94 * this function should be used only for newly allocated packets.
6f98b1a2
GR		 95 * It assumes the first cacheline is for the back pointer related
96 * book keeping info.
97 */
98 back_ptr = (struct sk_buff **)(addr - MAC_SKB_BACK_PTR_SIZE);
99 return *back_ptr;
100}
101
102static inline void mac_put_skb_back_ptr(struct sk_buff *skb)
103{
104 struct sk_buff **back_ptr = (struct sk_buff **)skb->data;
105
2db0083d
A		 106 /*
107 * this function should be used only for newly allocated packets.
6f98b1a2
GR		 108 * It assumes the first cacheline is for the back pointer related
109 * book keeping info.
110 */
111 skb_reserve(skb, MAC_SKB_BACK_PTR_SIZE);
112 *back_ptr = skb;
113}
114
115static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
116{
117 struct nlm_fmn_msg msg;
118 int ret = 0, num_try = 0, stnid;
119 unsigned long paddr, mflags;
120
121 paddr = virt_to_bus(addr);
122 msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
123 msg.msg1 = 0;
124 msg.msg2 = 0;
125 msg.msg3 = 0;
126 stnid = priv->nd->rfr_station;
127 do {
128 mflags = nlm_cop2_enable();
129 ret = nlm_fmn_send(1, 0, stnid, &msg);
130 nlm_cop2_restore(mflags);
131 if (ret == 0)
132 return 0;
133 } while (++num_try < 10000);
134
135 pr_err("Send to RFR failed in RX path\n");
136 return ret;
137}
138
139static inline struct sk_buff *xlr_alloc_skb(void)
140{
141 struct sk_buff *skb;
142
143 /* skb->data is cache aligned */
144 skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
145 if (!skb) {
146 pr_err("SKB allocation failed\n");
147 return NULL;
148 }
149 mac_put_skb_back_ptr(skb);
150 return skb;
151}
152
153static void xlr_net_fmn_handler(int bkt, int src_stnid, int size,
154 int code, struct nlm_fmn_msg *msg, void *arg)
155{
156 struct sk_buff *skb, *skb_new = NULL;
157 struct net_device *ndev;
158 struct xlr_net_priv *priv;
159 u64 length, port;
160 void *addr;
161
162 length = (msg->msg0 >> 40) & 0x3fff;
163 if (length == 0) {
164 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
165 dev_kfree_skb_any(addr);
166 } else if (length) {
167 addr = bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
168 length = length - BYTE_OFFSET - MAC_CRC_LEN;
169 port = msg->msg0 & 0x0f;
170 if (src_stnid == FMN_STNID_GMAC1)
171 port = port + 4;
172 skb = mac_get_skb_back_ptr(addr);
173 skb->dev = mac_to_ndev[port];
174 ndev = skb->dev;
175 priv = netdev_priv(ndev);
176
177 /* 16 byte IP header align */
178 skb_reserve(skb, BYTE_OFFSET);
179 skb_put(skb, length);
180 skb->protocol = eth_type_trans(skb, skb->dev);
181 skb->dev->last_rx = jiffies;
182 netif_rx(skb);
183 /* Fill rx ring */
184 skb_new = xlr_alloc_skb();
185 if (skb_new)
186 send_to_rfr_fifo(priv, skb_new->data);
187 }
188 return;
189}
190
191/* Ethtool operation */
192static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
193{
194 struct xlr_net_priv *priv = netdev_priv(ndev);
195 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
196
197 if (!phydev)
198 return -ENODEV;
199 return phy_ethtool_gset(phydev, ecmd);
200}
201
202static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
203{
204 struct xlr_net_priv *priv = netdev_priv(ndev);
205 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
206
207 if (!phydev)
208 return -ENODEV;
209 return phy_ethtool_sset(phydev, ecmd);
210}
211
212static struct ethtool_ops xlr_ethtool_ops = {
213 .get_settings = xlr_get_settings,
214 .set_settings = xlr_set_settings,
215};
216
217/* Net operations */
218static int xlr_net_fill_rx_ring(struct net_device *ndev)
219{
220 struct sk_buff *skb;
221 struct xlr_net_priv *priv = netdev_priv(ndev);
222 int i;
223
224 for (i = 0; i < MAX_FRIN_SPILL/2; i++) {
225 skb = xlr_alloc_skb();
226 if (!skb)
227 return -ENOMEM;
228 send_to_rfr_fifo(priv, skb->data);
229 }
230 pr_info("Rx ring setup done\n");
231 return 0;
232}
233
234static int xlr_net_open(struct net_device *ndev)
235{
236 u32 err;
237 struct xlr_net_priv *priv = netdev_priv(ndev);
238 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
239
240 /* schedule a link state check */
241 phy_start(phydev);
242
243 err = phy_start_aneg(phydev);
244 if (err) {
245 pr_err("Autoneg failed\n");
246 return err;
247 }
248
249 /* Setup the speed from PHY to internal reg*/
250 xlr_set_gmac_speed(priv);
251 netif_tx_start_all_queues(ndev);
252 return 0;
253}
254
255static int xlr_net_stop(struct net_device *ndev)
256{
257 struct xlr_net_priv *priv = netdev_priv(ndev);
258 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
259
260 phy_stop(phydev);
261 netif_tx_stop_all_queues(ndev);
262 return 0;
263}
264
265static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
266 struct sk_buff *skb)
267{
268 unsigned long physkb = virt_to_phys(skb);
269 int cpu_core = nlm_core_id();
270 int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */
271 msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */
272 ((u64)127 << 54) | /* No Free back */
273 (u64)skb->len << 40 | /* Length of data */
274 ((u64)addr));
275 msg->msg1 = (((u64)1 << 63) |
276 ((u64)fr_stn_id << 54) | /* Free back id */
277 (u64)0 << 40 | /* Set len to 0 */
278 ((u64)physkb & 0xffffffff)); /* 32bit address */
279 msg->msg2 = msg->msg3 = 0;
280}
281
282static void __maybe_unused xlr_wakeup_queue(unsigned long dev)
283{
284 struct net_device *ndev = (struct net_device *) dev;
285 struct xlr_net_priv *priv = netdev_priv(ndev);
286 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
287
288 if (phydev->link)
289 netif_tx_wake_queue(netdev_get_tx_queue(ndev, priv->wakeup_q));
290}
291
292static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
293 struct net_device *ndev)
294{
295 struct nlm_fmn_msg msg;
296 struct xlr_net_priv *priv = netdev_priv(ndev);
297 int ret;
6f98b1a2
GR		 298 u32 flags;
299
6f98b1a2
GR		 300 xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
301 flags = nlm_cop2_enable();
302 ret = nlm_fmn_send(2, 0, priv->nd->tx_stnid, &msg);
303 nlm_cop2_restore(flags);
304 if (ret)
305 dev_kfree_skb_any(skb);
306 return NETDEV_TX_OK;
307}
308
f663dd9a 309static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb,
f234e187
HS		 310 void *accel_priv,
311 select_queue_fallback_t fallback)
6f98b1a2
GR		 312{
313 return (u16)smp_processor_id();
314}
315
316static void xlr_hw_set_mac_addr(struct net_device *ndev)
317{
318 struct xlr_net_priv *priv = netdev_priv(ndev);
319
320 /* set mac station address */
321 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
322 ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
323 (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
324 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
325 ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
326
327 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
328 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
329 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
330 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
331
332 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
333 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
334 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
335 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
336
337 if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
338 priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
339 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
340}
341
342static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
343{
344 int err;
345
346 err = eth_mac_addr(ndev, data);
347 if (err)
348 return err;
349 xlr_hw_set_mac_addr(ndev);
350 return 0;
351}
352
353static void xlr_set_rx_mode(struct net_device *ndev)
354{
355 struct xlr_net_priv *priv = netdev_priv(ndev);
356 u32 regval;
357
358 regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
359
360 if (ndev->flags & IFF_PROMISC) {
361 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
362 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
363 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
364 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
365 } else {
366 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
367 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
368 }
369
370 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
371}
372
373static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
374{
375 struct xlr_net_priv *priv = netdev_priv(ndev);
376
377 stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
378 stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
379 stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
380 stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
381 stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
382 stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
383 RX_DROP_PACKET_COUNTER);
384 stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
385 TX_DROP_FRAME_COUNTER);
386
387 stats->multicast = xlr_nae_rdreg(priv->base_addr,
388 RX_MULTICAST_PACKET_COUNTER);
389 stats->collisions = xlr_nae_rdreg(priv->base_addr,
390 TX_TOTAL_COLLISION_COUNTER);
391
392 stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
393 RX_FRAME_LENGTH_ERROR_COUNTER);
394 stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
395 RX_DROP_PACKET_COUNTER);
396 stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
397 RX_FCS_ERROR_COUNTER);
398 stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
399 RX_ALIGNMENT_ERROR_COUNTER);
400
401 stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
402 RX_DROP_PACKET_COUNTER);
403 stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
404 RX_CARRIER_SENSE_ERROR_COUNTER);
405
406 stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
407 stats->rx_frame_errors + stats->rx_fifo_errors +
408 stats->rx_missed_errors);
409
410 stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
411 TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
412 stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
413 TX_DROP_FRAME_COUNTER);
414 stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
415 TX_DROP_FRAME_COUNTER);
416}
417
418static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev,
419 struct rtnl_link_stats64 *stats)
420{
421 xlr_stats(ndev, stats);
422 return stats;
423}
424
425static struct net_device_ops xlr_netdev_ops = {
426 .ndo_open = xlr_net_open,
427 .ndo_stop = xlr_net_stop,
428 .ndo_start_xmit = xlr_net_start_xmit,
429 .ndo_select_queue = xlr_net_select_queue,
430 .ndo_set_mac_address = xlr_net_set_mac_addr,
431 .ndo_set_rx_mode = xlr_set_rx_mode,
432 .ndo_get_stats64 = xlr_get_stats64,
433};
434
435/* Gmac init */
436static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
437 int reg_start_1, int reg_size, int size)
438{
439 void *spill;
440 u32 *base;
441 unsigned long phys_addr;
442 u32 spill_size;
443
444 base = priv->base_addr;
445 spill_size = size;
446 spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
447 if (!spill)
448 pr_err("Unable to allocate memory for spill area!\n");
449
450 spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
451 phys_addr = virt_to_phys(spill);
452 dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
453 size, phys_addr);
454 xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
455 xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
456 xlr_nae_wreg(base, reg_size, spill_size);
457
458 return spill;
459}
460
461/*
462 * Configure the 6 FIFO's that are used by the network accelarator to
463 * communicate with the rest of the XLx device. 4 of the FIFO's are for
464 * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
465 * the NA with free descriptors.
466 */
467static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
468{
469 priv->frin_spill = xlr_config_spill(priv,
470 R_REG_FRIN_SPILL_MEM_START_0,
471 R_REG_FRIN_SPILL_MEM_START_1,
472 R_REG_FRIN_SPILL_MEM_SIZE,
473 MAX_FRIN_SPILL *
474 sizeof(u64));
475 priv->frout_spill = xlr_config_spill(priv,
476 R_FROUT_SPILL_MEM_START_0,
477 R_FROUT_SPILL_MEM_START_1,
478 R_FROUT_SPILL_MEM_SIZE,
479 MAX_FROUT_SPILL *
480 sizeof(u64));
481 priv->class_0_spill = xlr_config_spill(priv,
482 R_CLASS0_SPILL_MEM_START_0,
483 R_CLASS0_SPILL_MEM_START_1,
484 R_CLASS0_SPILL_MEM_SIZE,
485 MAX_CLASS_0_SPILL *
486 sizeof(u64));
487 priv->class_1_spill = xlr_config_spill(priv,
488 R_CLASS1_SPILL_MEM_START_0,
489 R_CLASS1_SPILL_MEM_START_1,
490 R_CLASS1_SPILL_MEM_SIZE,
491 MAX_CLASS_1_SPILL *
492 sizeof(u64));
493 priv->class_2_spill = xlr_config_spill(priv,
494 R_CLASS2_SPILL_MEM_START_0,
495 R_CLASS2_SPILL_MEM_START_1,
496 R_CLASS2_SPILL_MEM_SIZE,
497 MAX_CLASS_2_SPILL *
498 sizeof(u64));
499 priv->class_3_spill = xlr_config_spill(priv,
500 R_CLASS3_SPILL_MEM_START_0,
501 R_CLASS3_SPILL_MEM_START_1,
502 R_CLASS3_SPILL_MEM_SIZE,
503 MAX_CLASS_3_SPILL *
504 sizeof(u64));
505}
506
2db0083d
A		 507/*
508 * Configure PDE to Round-Robin distribution of packets to the
509 * available cpu
510 */
6f98b1a2
GR		 511static void xlr_config_pde(struct xlr_net_priv *priv)
512{
513 int i = 0;
514 u64 bkt_map = 0;
515
516 /* Each core has 8 buckets(station) */
517 for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
518 bkt_map |= (0xff << (i * 8));
519
520 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
521 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
522 ((bkt_map >> 32) & 0xffffffff));
523
524 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
525 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
526 ((bkt_map >> 32) & 0xffffffff));
527
528 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
529 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
530 ((bkt_map >> 32) & 0xffffffff));
531
532 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
533 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
534 ((bkt_map >> 32) & 0xffffffff));
535}
536
2db0083d
A		 537/*
538 * Setup the Message ring credits, bucket size and other
539 * common configuration
540 */
6f98b1a2
GR		 541static void xlr_config_common(struct xlr_net_priv *priv)
542{
543 struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
544 int start_stn_id = gmac->start_stn_id;
545 int end_stn_id = gmac->end_stn_id;
546 int *bucket_size = priv->nd->bucket_size;
547 int i, j;
548
549 /* Setting non-core MsgBktSize(0x321 - 0x325) */
550 for (i = start_stn_id; i <= end_stn_id; i++) {
551 xlr_nae_wreg(priv->base_addr,
552 R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
553 bucket_size[i]);
554 }
555
2db0083d
A		 556 /*
557 * Setting non-core Credit counter register
558 * Distributing Gmac's credit to CPU's
559 */
6f98b1a2
GR		 560 for (i = 0; i < 8; i++) {
561 for (j = 0; j < 8; j++)
562 xlr_nae_wreg(priv->base_addr,
563 (R_CC_CPU0_0 + (i * 8)) + j,
564 gmac->credit_config[(i * 8) + j]);
565 }
566
567 xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
568 xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
569 xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
570 xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
571 xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
572 xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
573
574 xlr_net_fill_rx_ring(priv->ndev);
575 nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
576 NULL);
577}
578
579static void xlr_config_translate_table(struct xlr_net_priv *priv)
580{
581 u32 cpu_mask;
582 u32 val;
583 int bkts[32]; /* one bucket is assumed for each cpu */
584 int b1, b2, c1, c2, i, j, k;
585 int use_bkt;
586
587 use_bkt = 0;
588 cpu_mask = priv->nd->cpu_mask;
589
590 pr_info("Using %s-based distribution\n",
591 (use_bkt) ? "bucket" : "class");
592 j = 0;
593 for (i = 0; i < 32; i++) {
594 if ((1 << i) & cpu_mask) {
595 /* for each cpu, mark the 4+threadid bucket */
596 bkts[j] = ((i / 4) * 8) + (i % 4);
597 j++;
598 }
599 }
600
601 /*configure the 128 * 9 Translation table to send to available buckets*/
602 k = 0;
603 c1 = 3;
604 c2 = 0;
605 for (i = 0; i < 64; i++) {
2db0083d
A		 606 /*
607 * On use_bkt set the b0, b1 are used, else
6f98b1a2
GR		 608 * the 4 classes are used, here implemented
609 * a logic to distribute the packets to the
610 * buckets equally or based on the class
611 */
612 c1 = (c1 + 1) & 3;
613 c2 = (c1 + 1) & 3;
614 b1 = bkts[k];
615 k = (k + 1) % j;
616 b2 = bkts[k];
617 k = (k + 1) % j;
6f98b1a2
GR		 618
619 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
620 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
621 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
622 i, b1, b2, c1, c2);
623 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
624 c1 = c2;
625 }
626}
627
628static void xlr_config_parser(struct xlr_net_priv *priv)
629{
630 u32 val;
631
632 /* Mark it as ETHERNET type */
633 xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
634
635 /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
636 xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
637 ((0x7f << 8) | (1 << 1)));
638
639 /* configure the parser : L2 Type is configured in the bootloader */
640 /* extract IP: src, dest protocol */
641 xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
642 (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
643 (0x0800 << 0));
644 xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
645 (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
646 (16 << 4) | 4);
647
648 /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
649 xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
650 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
651 val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
652 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
653 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
654
655 xlr_config_translate_table(priv);
656}
657
658static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
659{
660 unsigned long timeout, stoptime, checktime;
661 int timedout;
662
663 /* 100ms timeout*/
664 timeout = msecs_to_jiffies(100);
665 stoptime = jiffies + timeout;
666 timedout = 0;
667
668 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
669
670 /* Write the data which starts the write cycle */
671 xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32) val);
672
673 /* poll for the read cycle to complete */
674 while (!timedout) {
675 checktime = jiffies;
676 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
677 break;
678 timedout = time_after(checktime, stoptime);
679 }
680 if (timedout) {
681 pr_info("Phy device write err: device busy");
682 return -EBUSY;
683 }
684
685 return 0;
686}
687
688static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
689{
690 unsigned long timeout, stoptime, checktime;
691 int timedout;
692
693 /* 100ms timeout*/
694 timeout = msecs_to_jiffies(100);
695 stoptime = jiffies + timeout;
696 timedout = 0;
697
698 /* setup the phy reg to be used */
699 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
700 (phy_addr << 8) | (regnum << 0));
701
702 /* Issue the read command */
703 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
704 (1 << O_MII_MGMT_COMMAND__rstat));
705
706
707 /* poll for the read cycle to complete */
708 while (!timedout) {
709 checktime = jiffies;
710 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
711 break;
712 timedout = time_after(checktime, stoptime);
713 }
714 if (timedout) {
715 pr_info("Phy device read err: device busy");
716 return -EBUSY;
717 }
718
719 /* clear the read cycle */
720 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
721
722 /* Read the data */
723 return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
724}
725
726static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
727{
728 struct xlr_net_priv *priv = bus->priv;
729 int ret;
730
731 ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
732 dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
733 phy_addr, regnum, val, ret);
734 return ret;
735}
736
737static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
738{
739 struct xlr_net_priv *priv = bus->priv;
740 int ret;
741
742 ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum);
743 dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
744 phy_addr, regnum, ret);
745 return ret;
746}
747
2db0083d
A		 748/*
749 * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
6f98b1a2
GR		 750 * which can be configured either SGMII or RGMII, considered SGMII
751 * by default, if board setup to RGMII the port_type need to set
752 * accordingly.Serdes and PCS layer need to configured for SGMII
753 */
754static void xlr_sgmii_init(struct xlr_net_priv *priv)
755{
756 int phy;
757
758 xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
759 xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
760 xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
761 xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
762 xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
763 xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
764 xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
765 xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
766 xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
767 xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
768 xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
769
770 /* program GPIO values for serdes init parameters */
771 xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
772 xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
773
774 xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
775 xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
776
777 /* enable autoneg - more magic */
778 phy = priv->port_id % 4 + 27;
779 xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
780 xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
781}
782
783void xlr_set_gmac_speed(struct xlr_net_priv *priv)
784{
785 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
786 int speed;
787
788 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
789 xlr_sgmii_init(priv);
790
791 if (phydev->speed != priv->phy_speed) {
792 pr_info("change %d to %d\n", priv->phy_speed, phydev->speed);
793 speed = phydev->speed;
794 if (speed == SPEED_1000) {
795 /* Set interface to Byte mode */
796 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
797 priv->phy_speed = speed;
798 } else if (speed == SPEED_100 || speed == SPEED_10) {
799 /* Set interface to Nibble mode */
800 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
801 priv->phy_speed = speed;
802 }
803 /* Set SGMII speed in Interface controll reg */
804 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
805 if (speed == SPEED_10)
806 xlr_nae_wreg(priv->base_addr,
807 R_INTERFACE_CONTROL, SGMII_SPEED_10);
808 if (speed == SPEED_100)
809 xlr_nae_wreg(priv->base_addr,
810 R_INTERFACE_CONTROL, SGMII_SPEED_100);
811 if (speed == SPEED_1000)
812 xlr_nae_wreg(priv->base_addr,
813 R_INTERFACE_CONTROL, SGMII_SPEED_1000);
814 }
815 if (speed == SPEED_10)
816 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
817 if (speed == SPEED_100)
818 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
819 if (speed == SPEED_1000)
820 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
821 }
822 pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
823}
824
825static void xlr_gmac_link_adjust(struct net_device *ndev)
826{
827 struct xlr_net_priv *priv = netdev_priv(ndev);
828 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
829 u32 intreg;
830
831 intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
832 if (phydev->link) {
833 if (phydev->speed != priv->phy_speed) {
834 pr_info("gmac%d : Link up\n", priv->port_id);
835 xlr_set_gmac_speed(priv);
836 }
837 } else {
838 pr_info("gmac%d : Link down\n", priv->port_id);
839 xlr_set_gmac_speed(priv);
840 }
841}
842
843static int xlr_mii_probe(struct xlr_net_priv *priv)
844{
845 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
846
847 if (!phydev) {
848 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
849 return -ENODEV;
850 }
851
852 /* Attach MAC to PHY */
853 phydev = phy_connect(priv->ndev, dev_name(&phydev->dev),
854 &xlr_gmac_link_adjust, priv->nd->phy_interface);
855
856 if (IS_ERR(phydev)) {
857 pr_err("could not attach PHY\n");
858 return PTR_ERR(phydev);
859 }
860 phydev->supported &= (ADVERTISED_10baseT_Full
861 | ADVERTISED_10baseT_Half
862 | ADVERTISED_100baseT_Full
863 | ADVERTISED_100baseT_Half
864 | ADVERTISED_1000baseT_Full
865 | ADVERTISED_Autoneg
866 | ADVERTISED_MII);
867
868 phydev->advertising = phydev->supported;
869 pr_info("attached PHY driver [%s] (mii_bus:phy_addr=%s\n",
870 phydev->drv->name, dev_name(&phydev->dev));
871 return 0;
872}
873
874static int xlr_setup_mdio(struct xlr_net_priv *priv,
875 struct platform_device *pdev)
876{
877 int err;
878
879 priv->phy_addr = priv->nd->phy_addr;
880 priv->mii_bus = mdiobus_alloc();
881 if (!priv->mii_bus) {
882 pr_err("mdiobus alloc failed\n");
883 return -ENOMEM;
884 }
885
886 priv->mii_bus->priv = priv;
887 priv->mii_bus->name = "xlr-mdio";
888 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
889 priv->mii_bus->name, priv->port_id);
890 priv->mii_bus->read = xlr_mii_read;
891 priv->mii_bus->write = xlr_mii_write;
892 priv->mii_bus->parent = &pdev->dev;
893 priv->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
ad3815a5
AC		 894 if (priv->mii_bus->irq == NULL) {
895 pr_err("irq alloc failed\n");
896 mdiobus_free(priv->mii_bus);
897 return -ENOMEM;
898 }
6f98b1a2
GR		 899 priv->mii_bus->irq[priv->phy_addr] = priv->ndev->irq;
900
901 /* Scan only the enabled address */
902 priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
903
904 /* setting clock divisor to 54 */
905 xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
906
907 err = mdiobus_register(priv->mii_bus);
908 if (err) {
909 mdiobus_free(priv->mii_bus);
910 pr_err("mdio bus registration failed\n");
911 return err;
912 }
913
9d2ea4de 914 pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
6f98b1a2
GR		 915 err = xlr_mii_probe(priv);
916 if (err) {
917 mdiobus_free(priv->mii_bus);
918 return err;
919 }
920 return 0;
921}
922
923static void xlr_port_enable(struct xlr_net_priv *priv)
924{
925 u32 prid = (read_c0_prid() & 0xf000);
926
927 /* Setup MAC_CONFIG reg if (xls & rgmii) */
928 if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
929 priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
930 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
931 (1 << O_RX_CONTROL__RGMII), (1 << O_RX_CONTROL__RGMII));
932
933 /* Rx Tx enable */
934 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
935 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
936 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
937 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
938 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)));
939
940 /* Setup tx control reg */
941 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
942 ((1 << O_TX_CONTROL__TxEnable) |
943 (512 << O_TX_CONTROL__TxThreshold)), 0x3fff);
944
945 /* Setup rx control reg */
946 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
947 1 << O_RX_CONTROL__RxEnable, 1 << O_RX_CONTROL__RxEnable);
948}
949
950static void xlr_port_disable(struct xlr_net_priv *priv)
951{
952 /* Setup MAC_CONFIG reg */
953 /* Rx Tx disable*/
954 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
955 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
956 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
957 0x0);
958
959 /* Setup tx control reg */
960 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
961 ((1 << O_TX_CONTROL__TxEnable) |
962 (512 << O_TX_CONTROL__TxThreshold)), 0);
963
964 /* Setup rx control reg */
965 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
966 1 << O_RX_CONTROL__RxEnable, 0);
967}
968
969/* Initialization of gmac */
970static int xlr_gmac_init(struct xlr_net_priv *priv,
971 struct platform_device *pdev)
972{
973 int ret;
974
975 pr_info("Initializing the gmac%d\n", priv->port_id);
976
977 xlr_port_disable(priv);
978 xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
979 (1 << O_DESC_PACK_CTRL__MaxEntry)
980 | (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset)
981 | (1600 << O_DESC_PACK_CTRL__RegularSize));
982
983 ret = xlr_setup_mdio(priv, pdev);
984 if (ret)
985 return ret;
986 xlr_port_enable(priv);
987
988 /* Enable Full-duplex/1000Mbps/CRC */
989 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
990 /* speed 2.5Mhz */
991 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
992 /* Setup Interrupt mask reg */
993 xlr_nae_wreg(priv->base_addr, R_INTMASK,
994 (1 << O_INTMASK__TxIllegal) |
995 (1 << O_INTMASK__MDInt) |
996 (1 << O_INTMASK__TxFetchError) |
997 (1 << O_INTMASK__P2PSpillEcc) |
998 (1 << O_INTMASK__TagFull) |
999 (1 << O_INTMASK__Underrun) |
1000 (1 << O_INTMASK__Abort)
1001 );
1002
1003 /* Clear all stats */
1004 xlr_reg_update(priv->base_addr, R_STATCTRL,
1005 0, 1 << O_STATCTRL__ClrCnt);
1006 xlr_reg_update(priv->base_addr, R_STATCTRL,
1007 1 << O_STATCTRL__ClrCnt, 1 << O_STATCTRL__ClrCnt);
1008 return 0;
1009}
1010
1011static int xlr_net_probe(struct platform_device *pdev)
1012{
1013 struct xlr_net_priv *priv = NULL;
1014 struct net_device *ndev;
1015 struct resource *res;
1016 int mac, err;
1017
1018 mac = pdev->id;
1019 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1020 if (!ndev) {
1021 pr_err("Allocation of Ethernet device failed\n");
1022 return -ENOMEM;
1023 }
1024
1025 priv = netdev_priv(ndev);
1026 priv->pdev = pdev;
1027 priv->ndev = ndev;
1028 priv->port_id = mac;
1029 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1030
1031 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1032 if (res == NULL) {
1033 pr_err("No memory resource for MAC %d\n", mac);
1034 err = -ENODEV;
1035 goto err_gmac;
1036 }
1037
803c83fc 1038 ndev->base_addr = (unsigned long) devm_ioremap_resource
6f98b1a2 1039 (&pdev->dev, res);
803c83fc 1040 if (IS_ERR_VALUE(ndev->base_addr)) {
c639b9fb
WY		 1041 err = ndev->base_addr;
1042 goto err_gmac;
6f98b1a2
GR		 1043 }
1044
1045 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1046 if (res == NULL) {
1047 pr_err("No irq resource for MAC %d\n", mac);
1048 err = -ENODEV;
1049 goto err_gmac;
1050 }
1051 ndev->irq = res->start;
1052
1053 priv->mii_addr = priv->nd->mii_addr;
1054 priv->serdes_addr = priv->nd->serdes_addr;
1055 priv->pcs_addr = priv->nd->pcs_addr;
1056 priv->gpio_addr = priv->nd->gpio_addr;
1057 priv->base_addr = (u32 *) ndev->base_addr;
1058
1059 mac_to_ndev[mac] = ndev;
1060 ndev->netdev_ops = &xlr_netdev_ops;
1061 ndev->watchdog_timeo = HZ;
1062
1063 /* Setup Mac address and Rx mode */
1064 eth_hw_addr_random(ndev);
1065 xlr_hw_set_mac_addr(ndev);
1066 xlr_set_rx_mode(ndev);
1067
1068 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
7ad24ea4 1069 ndev->ethtool_ops = &xlr_ethtool_ops;
6f98b1a2
GR		 1070 SET_NETDEV_DEV(ndev, &pdev->dev);
1071
1072 /* Common registers, do one time initialization */
1073 if (mac == 0 || mac == 4) {
1074 xlr_config_fifo_spill_area(priv);
1075 /* Configure PDE to Round-Robin pkt distribution */
1076 xlr_config_pde(priv);
1077 xlr_config_parser(priv);
1078 }
1079 /* Call init with respect to port */
1080 if (strcmp(res->name, "gmac") == 0) {
1081 err = xlr_gmac_init(priv, pdev);
1082 if (err) {
1083 pr_err("gmac%d init failed\n", mac);
1084 goto err_gmac;
1085 }
1086 }
1087
1088 if (mac == 0 || mac == 4)
1089 xlr_config_common(priv);
1090
1091 err = register_netdev(ndev);
1092 if (err)
1093 goto err_netdev;
1094 platform_set_drvdata(pdev, priv);
1095 return 0;
1096
1097err_netdev:
1098 mdiobus_free(priv->mii_bus);
1099err_gmac:
1100 free_netdev(ndev);
1101 return err;
1102}
1103
1104static int xlr_net_remove(struct platform_device *pdev)
1105{
1106 struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1107 unregister_netdev(priv->ndev);
1108 mdiobus_unregister(priv->mii_bus);
1109 mdiobus_free(priv->mii_bus);
1110 free_netdev(priv->ndev);
1111 return 0;
1112}
1113
1114static struct platform_driver xlr_net_driver = {
1115 .probe = xlr_net_probe,
1116 .remove = xlr_net_remove,
1117 .driver = {
1118 .name = "xlr-net",
1119 .owner = THIS_MODULE,
1120 },
1121};
1122
1123module_platform_driver(xlr_net_driver);
1124
1125MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1126MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1127MODULE_LICENSE("Dual BSD/GPL");
1128MODULE_ALIAS("platform:xlr-net");
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