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162c7d8c MD |
1 | /* |
2 | * NVEC: NVIDIA compliant embedded controller interface | |
3 | * | |
4 | * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net> | |
5 | * | |
6 | * Authors: Pierre-Hugues Husson <phhusson@free.fr> | |
7 | * Ilya Petrov <ilya.muromec@gmail.com> | |
8 | * Marc Dietrich <marvin24@gmx.de> | |
791c4a64 | 9 | * Julian Andres Klode <jak@jak-linux.org> |
162c7d8c MD |
10 | * |
11 | * This file is subject to the terms and conditions of the GNU General Public | |
12 | * License. See the file "COPYING" in the main directory of this archive | |
13 | * for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | /* #define DEBUG */ | |
32890b98 | 18 | |
12b5a55d | 19 | #include <linux/kernel.h> |
3b769edd | 20 | #include <linux/module.h> |
0b1076c4 | 21 | #include <linux/atomic.h> |
12b5a55d | 22 | #include <linux/clk.h> |
32890b98 | 23 | #include <linux/completion.h> |
12b5a55d JAK |
24 | #include <linux/delay.h> |
25 | #include <linux/err.h> | |
26 | #include <linux/gpio.h> | |
32890b98 | 27 | #include <linux/interrupt.h> |
162c7d8c | 28 | #include <linux/io.h> |
32890b98 | 29 | #include <linux/irq.h> |
7990b0d7 MD |
30 | #include <linux/of.h> |
31 | #include <linux/of_gpio.h> | |
32890b98 | 32 | #include <linux/list.h> |
12b5a55d JAK |
33 | #include <linux/mfd/core.h> |
34 | #include <linux/mutex.h> | |
32890b98 | 35 | #include <linux/notifier.h> |
32890b98 | 36 | #include <linux/platform_device.h> |
12b5a55d JAK |
37 | #include <linux/slab.h> |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/workqueue.h> | |
162c7d8c | 40 | |
162c7d8c MD |
41 | #include <mach/clk.h> |
42 | ||
32890b98 MD |
43 | #include "nvec.h" |
44 | ||
391d2fa9 JAK |
45 | #define I2C_CNFG 0x00 |
46 | #define I2C_CNFG_PACKET_MODE_EN (1<<10) | |
47 | #define I2C_CNFG_NEW_MASTER_SFM (1<<11) | |
48 | #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 | |
49 | ||
50 | #define I2C_SL_CNFG 0x20 | |
d3f862ae | 51 | #define I2C_SL_NEWSL (1<<2) |
391d2fa9 JAK |
52 | #define I2C_SL_NACK (1<<1) |
53 | #define I2C_SL_RESP (1<<0) | |
54 | #define I2C_SL_IRQ (1<<3) | |
55 | #define END_TRANS (1<<4) | |
56 | #define RCVD (1<<2) | |
57 | #define RNW (1<<1) | |
58 | ||
59 | #define I2C_SL_RCVD 0x24 | |
60 | #define I2C_SL_STATUS 0x28 | |
61 | #define I2C_SL_ADDR1 0x2c | |
62 | #define I2C_SL_ADDR2 0x30 | |
63 | #define I2C_SL_DELAY_COUNT 0x3c | |
64 | ||
bb0590e2 JAK |
65 | /** |
66 | * enum nvec_msg_category - Message categories for nvec_msg_alloc() | |
67 | * @NVEC_MSG_RX: The message is an incoming message (from EC) | |
68 | * @NVEC_MSG_TX: The message is an outgoing message (to EC) | |
69 | */ | |
70 | enum nvec_msg_category { | |
71 | NVEC_MSG_RX, | |
72 | NVEC_MSG_TX, | |
73 | }; | |
74 | ||
162c7d8c MD |
75 | static const unsigned char EC_DISABLE_EVENT_REPORTING[3] = "\x04\x00\x00"; |
76 | static const unsigned char EC_ENABLE_EVENT_REPORTING[3] = "\x04\x00\x01"; | |
77 | static const unsigned char EC_GET_FIRMWARE_VERSION[2] = "\x07\x15"; | |
32890b98 MD |
78 | |
79 | static struct nvec_chip *nvec_power_handle; | |
80 | ||
f686e9af MD |
81 | static struct mfd_cell nvec_devices[] = { |
82 | { | |
162c7d8c MD |
83 | .name = "nvec-kbd", |
84 | .id = 1, | |
f686e9af MD |
85 | }, |
86 | { | |
162c7d8c MD |
87 | .name = "nvec-mouse", |
88 | .id = 1, | |
f686e9af MD |
89 | }, |
90 | { | |
162c7d8c MD |
91 | .name = "nvec-power", |
92 | .id = 1, | |
f686e9af MD |
93 | }, |
94 | { | |
162c7d8c MD |
95 | .name = "nvec-power", |
96 | .id = 2, | |
f686e9af | 97 | }, |
97cc2657 | 98 | { |
ac562680 | 99 | .name = "nvec-paz00", |
97cc2657 IP |
100 | .id = 1, |
101 | }, | |
f686e9af MD |
102 | }; |
103 | ||
bdf034d9 JAK |
104 | /** |
105 | * nvec_register_notifier - Register a notifier with nvec | |
106 | * @nvec: A &struct nvec_chip | |
107 | * @nb: The notifier block to register | |
108 | * | |
109 | * Registers a notifier with @nvec. The notifier will be added to an atomic | |
110 | * notifier chain that is called for all received messages except those that | |
111 | * correspond to a request initiated by nvec_write_sync(). | |
112 | */ | |
32890b98 | 113 | int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb, |
162c7d8c | 114 | unsigned int events) |
32890b98 MD |
115 | { |
116 | return atomic_notifier_chain_register(&nvec->notifier_list, nb); | |
117 | } | |
118 | EXPORT_SYMBOL_GPL(nvec_register_notifier); | |
119 | ||
bdf034d9 JAK |
120 | /** |
121 | * nvec_status_notifier - The final notifier | |
122 | * | |
123 | * Prints a message about control events not handled in the notifier | |
124 | * chain. | |
125 | */ | |
162c7d8c MD |
126 | static int nvec_status_notifier(struct notifier_block *nb, |
127 | unsigned long event_type, void *data) | |
32890b98 | 128 | { |
50d4656a MD |
129 | struct nvec_chip *nvec = container_of(nb, struct nvec_chip, |
130 | nvec_status_notifier); | |
32890b98 | 131 | unsigned char *msg = (unsigned char *)data; |
32890b98 | 132 | |
162c7d8c | 133 | if (event_type != NVEC_CNTL) |
32890b98 MD |
134 | return NOTIFY_DONE; |
135 | ||
50d4656a | 136 | dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type); |
a3a9aa1a MD |
137 | print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1, |
138 | msg, msg[1] + 2, true); | |
32890b98 MD |
139 | |
140 | return NOTIFY_OK; | |
141 | } | |
142 | ||
bdf034d9 JAK |
143 | /** |
144 | * nvec_msg_alloc: | |
145 | * @nvec: A &struct nvec_chip | |
bb0590e2 | 146 | * @category: Pool category, see &enum nvec_msg_category |
bdf034d9 JAK |
147 | * |
148 | * Allocate a single &struct nvec_msg object from the message pool of | |
149 | * @nvec. The result shall be passed to nvec_msg_free() if no longer | |
150 | * used. | |
bb0590e2 JAK |
151 | * |
152 | * Outgoing messages are placed in the upper 75% of the pool, keeping the | |
153 | * lower 25% available for RX buffers only. The reason is to prevent a | |
154 | * situation where all buffers are full and a message is thus endlessly | |
155 | * retried because the response could never be processed. | |
bdf034d9 | 156 | */ |
bb0590e2 JAK |
157 | static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec, |
158 | enum nvec_msg_category category) | |
0b1076c4 | 159 | { |
bb0590e2 | 160 | int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0; |
0b1076c4 | 161 | |
bb0590e2 | 162 | for (; i < NVEC_POOL_SIZE; i++) { |
0b1076c4 JAK |
163 | if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) { |
164 | dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i); | |
165 | return &nvec->msg_pool[i]; | |
166 | } | |
167 | } | |
168 | ||
bb0590e2 JAK |
169 | dev_err(nvec->dev, "could not allocate %s buffer\n", |
170 | (category == NVEC_MSG_TX) ? "TX" : "RX"); | |
0b1076c4 JAK |
171 | |
172 | return NULL; | |
173 | } | |
174 | ||
bdf034d9 JAK |
175 | /** |
176 | * nvec_msg_free: | |
177 | * @nvec: A &struct nvec_chip | |
178 | * @msg: A message (must be allocated by nvec_msg_alloc() and belong to @nvec) | |
179 | * | |
180 | * Free the given message | |
181 | */ | |
198dd267 | 182 | inline void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg) |
0b1076c4 | 183 | { |
7b770657 JAK |
184 | if (msg != &nvec->tx_scratch) |
185 | dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool); | |
0b1076c4 JAK |
186 | atomic_set(&msg->used, 0); |
187 | } | |
198dd267 | 188 | EXPORT_SYMBOL_GPL(nvec_msg_free); |
0b1076c4 | 189 | |
8517e879 JAK |
190 | /** |
191 | * nvec_msg_is_event - Return %true if @msg is an event | |
192 | * @msg: A message | |
193 | */ | |
194 | static bool nvec_msg_is_event(struct nvec_msg *msg) | |
195 | { | |
196 | return msg->data[0] >> 7; | |
197 | } | |
198 | ||
199 | /** | |
200 | * nvec_msg_size - Get the size of a message | |
201 | * @msg: The message to get the size for | |
202 | * | |
203 | * This only works for received messages, not for outgoing messages. | |
204 | */ | |
205 | static size_t nvec_msg_size(struct nvec_msg *msg) | |
206 | { | |
207 | bool is_event = nvec_msg_is_event(msg); | |
208 | int event_length = (msg->data[0] & 0x60) >> 5; | |
209 | ||
210 | /* for variable size, payload size in byte 1 + count (1) + cmd (1) */ | |
211 | if (!is_event || event_length == NVEC_VAR_SIZE) | |
212 | return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0; | |
213 | else if (event_length == NVEC_2BYTES) | |
214 | return 2; | |
215 | else if (event_length == NVEC_3BYTES) | |
216 | return 3; | |
217 | else | |
218 | return 0; | |
219 | } | |
220 | ||
bdf034d9 JAK |
221 | /** |
222 | * nvec_gpio_set_value - Set the GPIO value | |
223 | * @nvec: A &struct nvec_chip | |
224 | * @value: The value to write (0 or 1) | |
225 | * | |
226 | * Like gpio_set_value(), but generating debugging information | |
227 | */ | |
e7c40851 JAK |
228 | static void nvec_gpio_set_value(struct nvec_chip *nvec, int value) |
229 | { | |
230 | dev_dbg(nvec->dev, "GPIO changed from %u to %u\n", | |
231 | gpio_get_value(nvec->gpio), value); | |
232 | gpio_set_value(nvec->gpio, value); | |
233 | } | |
234 | ||
bdf034d9 JAK |
235 | /** |
236 | * nvec_write_async - Asynchronously write a message to NVEC | |
237 | * @nvec: An nvec_chip instance | |
238 | * @data: The message data, starting with the request type | |
239 | * @size: The size of @data | |
240 | * | |
241 | * Queue a single message to be transferred to the embedded controller | |
242 | * and return immediately. | |
243 | * | |
244 | * Returns: 0 on success, a negative error code on failure. If a failure | |
245 | * occured, the nvec driver may print an error. | |
246 | */ | |
1b9bf629 | 247 | int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data, |
162c7d8c | 248 | short size) |
32890b98 | 249 | { |
0cab4cb8 JAK |
250 | struct nvec_msg *msg; |
251 | unsigned long flags; | |
32890b98 | 252 | |
bb0590e2 JAK |
253 | msg = nvec_msg_alloc(nvec, NVEC_MSG_TX); |
254 | ||
1b9bf629 JAK |
255 | if (msg == NULL) |
256 | return -ENOMEM; | |
257 | ||
32890b98 MD |
258 | msg->data[0] = size; |
259 | memcpy(msg->data + 1, data, size); | |
260 | msg->size = size + 1; | |
32890b98 | 261 | |
0cab4cb8 | 262 | spin_lock_irqsave(&nvec->tx_lock, flags); |
32890b98 | 263 | list_add_tail(&msg->node, &nvec->tx_data); |
0cab4cb8 | 264 | spin_unlock_irqrestore(&nvec->tx_lock, flags); |
32890b98 | 265 | |
033d9959 | 266 | schedule_work(&nvec->tx_work); |
1b9bf629 JAK |
267 | |
268 | return 0; | |
32890b98 MD |
269 | } |
270 | EXPORT_SYMBOL(nvec_write_async); | |
271 | ||
bdf034d9 JAK |
272 | /** |
273 | * nvec_write_sync - Write a message to nvec and read the response | |
274 | * @nvec: An &struct nvec_chip | |
275 | * @data: The data to write | |
276 | * @size: The size of @data | |
277 | * | |
278 | * This is similar to nvec_write_async(), but waits for the | |
279 | * request to be answered before returning. This function | |
280 | * uses a mutex and can thus not be called from e.g. | |
281 | * interrupt handlers. | |
282 | * | |
283 | * Returns: A pointer to the response message on success, | |
198dd267 JAK |
284 | * %NULL on failure. Free with nvec_msg_free() once no longer |
285 | * used. | |
bdf034d9 | 286 | */ |
0cab4cb8 JAK |
287 | struct nvec_msg *nvec_write_sync(struct nvec_chip *nvec, |
288 | const unsigned char *data, short size) | |
289 | { | |
290 | struct nvec_msg *msg; | |
291 | ||
292 | mutex_lock(&nvec->sync_write_mutex); | |
293 | ||
294 | nvec->sync_write_pending = (data[1] << 8) + data[0]; | |
1b9bf629 | 295 | |
4b8bf03d MD |
296 | if (nvec_write_async(nvec, data, size) < 0) { |
297 | mutex_unlock(&nvec->sync_write_mutex); | |
1b9bf629 | 298 | return NULL; |
4b8bf03d | 299 | } |
0cab4cb8 JAK |
300 | |
301 | dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n", | |
302 | nvec->sync_write_pending); | |
303 | if (!(wait_for_completion_timeout(&nvec->sync_write, | |
304 | msecs_to_jiffies(2000)))) { | |
305 | dev_warn(nvec->dev, "timeout waiting for sync write to complete\n"); | |
306 | mutex_unlock(&nvec->sync_write_mutex); | |
307 | return NULL; | |
308 | } | |
309 | ||
310 | dev_dbg(nvec->dev, "nvec_sync_write: pong!\n"); | |
311 | ||
312 | msg = nvec->last_sync_msg; | |
313 | ||
314 | mutex_unlock(&nvec->sync_write_mutex); | |
315 | ||
316 | return msg; | |
317 | } | |
318 | EXPORT_SYMBOL(nvec_write_sync); | |
319 | ||
bdf034d9 JAK |
320 | /** |
321 | * nvec_request_master - Process outgoing messages | |
322 | * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip) | |
323 | * | |
324 | * Processes all outgoing requests by sending the request and awaiting the | |
325 | * response, then continuing with the next request. Once a request has a | |
326 | * matching response, it will be freed and removed from the list. | |
327 | */ | |
32890b98 MD |
328 | static void nvec_request_master(struct work_struct *work) |
329 | { | |
330 | struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work); | |
0cab4cb8 JAK |
331 | unsigned long flags; |
332 | long err; | |
333 | struct nvec_msg *msg; | |
334 | ||
335 | spin_lock_irqsave(&nvec->tx_lock, flags); | |
336 | while (!list_empty(&nvec->tx_data)) { | |
337 | msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node); | |
338 | spin_unlock_irqrestore(&nvec->tx_lock, flags); | |
339 | nvec_gpio_set_value(nvec, 0); | |
340 | err = wait_for_completion_interruptible_timeout( | |
341 | &nvec->ec_transfer, msecs_to_jiffies(5000)); | |
342 | ||
343 | if (err == 0) { | |
344 | dev_warn(nvec->dev, "timeout waiting for ec transfer\n"); | |
345 | nvec_gpio_set_value(nvec, 1); | |
346 | msg->pos = 0; | |
347 | } | |
32890b98 | 348 | |
0cab4cb8 JAK |
349 | spin_lock_irqsave(&nvec->tx_lock, flags); |
350 | ||
351 | if (err > 0) { | |
352 | list_del_init(&msg->node); | |
353 | nvec_msg_free(nvec, msg); | |
354 | } | |
355 | } | |
356 | spin_unlock_irqrestore(&nvec->tx_lock, flags); | |
32890b98 MD |
357 | } |
358 | ||
bdf034d9 JAK |
359 | /** |
360 | * parse_msg - Print some information and call the notifiers on an RX message | |
361 | * @nvec: A &struct nvec_chip | |
362 | * @msg: A message received by @nvec | |
363 | * | |
364 | * Paarse some pieces of the message and then call the chain of notifiers | |
365 | * registered via nvec_register_notifier. | |
366 | */ | |
32890b98 MD |
367 | static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg) |
368 | { | |
162c7d8c | 369 | if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) { |
6a371978 | 370 | dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data); |
32890b98 MD |
371 | return -EINVAL; |
372 | } | |
373 | ||
a3a9aa1a MD |
374 | if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5) |
375 | print_hex_dump(KERN_WARNING, "ec system event ", | |
376 | DUMP_PREFIX_NONE, 16, 1, msg->data, | |
377 | msg->data[1] + 2, true); | |
32890b98 | 378 | |
162c7d8c MD |
379 | atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f, |
380 | msg->data); | |
32890b98 MD |
381 | |
382 | return 0; | |
383 | } | |
384 | ||
bdf034d9 JAK |
385 | /** |
386 | * nvec_dispatch - Process messages received from the EC | |
387 | * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip) | |
388 | * | |
389 | * Process messages previously received from the EC and put into the RX | |
390 | * queue of the &struct nvec_chip instance associated with @work. | |
391 | */ | |
32890b98 MD |
392 | static void nvec_dispatch(struct work_struct *work) |
393 | { | |
394 | struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work); | |
0cab4cb8 | 395 | unsigned long flags; |
32890b98 MD |
396 | struct nvec_msg *msg; |
397 | ||
0cab4cb8 | 398 | spin_lock_irqsave(&nvec->rx_lock, flags); |
162c7d8c | 399 | while (!list_empty(&nvec->rx_data)) { |
32890b98 MD |
400 | msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node); |
401 | list_del_init(&msg->node); | |
0cab4cb8 | 402 | spin_unlock_irqrestore(&nvec->rx_lock, flags); |
32890b98 | 403 | |
162c7d8c | 404 | if (nvec->sync_write_pending == |
0cab4cb8 | 405 | (msg->data[2] << 8) + msg->data[0]) { |
32890b98 MD |
406 | dev_dbg(nvec->dev, "sync write completed!\n"); |
407 | nvec->sync_write_pending = 0; | |
408 | nvec->last_sync_msg = msg; | |
409 | complete(&nvec->sync_write); | |
410 | } else { | |
411 | parse_msg(nvec, msg); | |
0cab4cb8 | 412 | nvec_msg_free(nvec, msg); |
32890b98 | 413 | } |
0cab4cb8 | 414 | spin_lock_irqsave(&nvec->rx_lock, flags); |
32890b98 | 415 | } |
0cab4cb8 | 416 | spin_unlock_irqrestore(&nvec->rx_lock, flags); |
32890b98 MD |
417 | } |
418 | ||
bdf034d9 JAK |
419 | /** |
420 | * nvec_tx_completed - Complete the current transfer | |
421 | * @nvec: A &struct nvec_chip | |
422 | * | |
423 | * This is called when we have received an END_TRANS on a TX transfer. | |
424 | */ | |
0cab4cb8 JAK |
425 | static void nvec_tx_completed(struct nvec_chip *nvec) |
426 | { | |
427 | /* We got an END_TRANS, let's skip this, maybe there's an event */ | |
428 | if (nvec->tx->pos != nvec->tx->size) { | |
429 | dev_err(nvec->dev, "premature END_TRANS, resending\n"); | |
430 | nvec->tx->pos = 0; | |
431 | nvec_gpio_set_value(nvec, 0); | |
432 | } else { | |
433 | nvec->state = 0; | |
434 | } | |
435 | } | |
436 | ||
bdf034d9 JAK |
437 | /** |
438 | * nvec_rx_completed - Complete the current transfer | |
439 | * @nvec: A &struct nvec_chip | |
440 | * | |
441 | * This is called when we have received an END_TRANS on a RX transfer. | |
442 | */ | |
0cab4cb8 JAK |
443 | static void nvec_rx_completed(struct nvec_chip *nvec) |
444 | { | |
210ceb4f | 445 | if (nvec->rx->pos != nvec_msg_size(nvec->rx)) { |
0cab4cb8 JAK |
446 | dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n", |
447 | (uint) nvec_msg_size(nvec->rx), | |
448 | (uint) nvec->rx->pos); | |
449 | ||
210ceb4f JAK |
450 | nvec_msg_free(nvec, nvec->rx); |
451 | nvec->state = 0; | |
d6bdcf2e JAK |
452 | |
453 | /* Battery quirk - Often incomplete, and likes to crash */ | |
454 | if (nvec->rx->data[0] == NVEC_BAT) | |
455 | complete(&nvec->ec_transfer); | |
456 | ||
210ceb4f JAK |
457 | return; |
458 | } | |
459 | ||
0cab4cb8 JAK |
460 | spin_lock(&nvec->rx_lock); |
461 | ||
462 | /* add the received data to the work list | |
463 | and move the ring buffer pointer to the next entry */ | |
464 | list_add_tail(&nvec->rx->node, &nvec->rx_data); | |
465 | ||
466 | spin_unlock(&nvec->rx_lock); | |
467 | ||
468 | nvec->state = 0; | |
469 | ||
470 | if (!nvec_msg_is_event(nvec->rx)) | |
471 | complete(&nvec->ec_transfer); | |
472 | ||
033d9959 | 473 | schedule_work(&nvec->rx_work); |
0cab4cb8 JAK |
474 | } |
475 | ||
476 | /** | |
477 | * nvec_invalid_flags - Send an error message about invalid flags and jump | |
478 | * @nvec: The nvec device | |
479 | * @status: The status flags | |
480 | * @reset: Whether we shall jump to state 0. | |
481 | */ | |
482 | static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status, | |
483 | bool reset) | |
484 | { | |
485 | dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n", | |
486 | status, nvec->state); | |
487 | if (reset) | |
488 | nvec->state = 0; | |
489 | } | |
490 | ||
491 | /** | |
492 | * nvec_tx_set - Set the message to transfer (nvec->tx) | |
bdf034d9 JAK |
493 | * @nvec: A &struct nvec_chip |
494 | * | |
495 | * Gets the first entry from the tx_data list of @nvec and sets the | |
496 | * tx member to it. If the tx_data list is empty, this uses the | |
497 | * tx_scratch message to send a no operation message. | |
0cab4cb8 JAK |
498 | */ |
499 | static void nvec_tx_set(struct nvec_chip *nvec) | |
500 | { | |
501 | spin_lock(&nvec->tx_lock); | |
502 | if (list_empty(&nvec->tx_data)) { | |
503 | dev_err(nvec->dev, "empty tx - sending no-op\n"); | |
504 | memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3); | |
505 | nvec->tx_scratch.size = 3; | |
506 | nvec->tx_scratch.pos = 0; | |
507 | nvec->tx = &nvec->tx_scratch; | |
508 | list_add_tail(&nvec->tx->node, &nvec->tx_data); | |
509 | } else { | |
510 | nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg, | |
511 | node); | |
512 | nvec->tx->pos = 0; | |
513 | } | |
514 | spin_unlock(&nvec->tx_lock); | |
515 | ||
516 | dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n", | |
517 | (uint)nvec->tx->size, nvec->tx->data[1]); | |
518 | } | |
519 | ||
520 | /** | |
521 | * nvec_interrupt - Interrupt handler | |
522 | * @irq: The IRQ | |
523 | * @dev: The nvec device | |
bdf034d9 JAK |
524 | * |
525 | * Interrupt handler that fills our RX buffers and empties our TX | |
526 | * buffers. This uses a finite state machine with ridiculous amounts | |
527 | * of error checking, in order to be fairly reliable. | |
0cab4cb8 | 528 | */ |
f686e9af | 529 | static irqreturn_t nvec_interrupt(int irq, void *dev) |
32890b98 MD |
530 | { |
531 | unsigned long status; | |
0cab4cb8 JAK |
532 | unsigned int received = 0; |
533 | unsigned char to_send = 0xff; | |
534 | const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW; | |
535 | struct nvec_chip *nvec = dev; | |
536 | unsigned int state = nvec->state; | |
32890b98 | 537 | |
0cab4cb8 | 538 | status = readl(nvec->base + I2C_SL_STATUS); |
32890b98 | 539 | |
0cab4cb8 JAK |
540 | /* Filter out some errors */ |
541 | if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) { | |
542 | dev_err(nvec->dev, "unexpected irq mask %lx\n", status); | |
543 | return IRQ_HANDLED; | |
32890b98 | 544 | } |
0cab4cb8 JAK |
545 | if ((status & I2C_SL_IRQ) == 0) { |
546 | dev_err(nvec->dev, "Spurious IRQ\n"); | |
32890b98 | 547 | return IRQ_HANDLED; |
0cab4cb8 | 548 | } |
32890b98 | 549 | |
0cab4cb8 JAK |
550 | /* The EC did not request a read, so it send us something, read it */ |
551 | if ((status & RNW) == 0) { | |
552 | received = readl(nvec->base + I2C_SL_RCVD); | |
162c7d8c | 553 | if (status & RCVD) |
0cab4cb8 JAK |
554 | writel(0, nvec->base + I2C_SL_RCVD); |
555 | } | |
162c7d8c | 556 | |
0cab4cb8 JAK |
557 | if (status == (I2C_SL_IRQ | RCVD)) |
558 | nvec->state = 0; | |
559 | ||
560 | switch (nvec->state) { | |
561 | case 0: /* Verify that its a transfer start, the rest later */ | |
562 | if (status != (I2C_SL_IRQ | RCVD)) | |
563 | nvec_invalid_flags(nvec, status, false); | |
564 | break; | |
565 | case 1: /* command byte */ | |
566 | if (status != I2C_SL_IRQ) { | |
567 | nvec_invalid_flags(nvec, status, true); | |
32890b98 | 568 | } else { |
bb0590e2 | 569 | nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX); |
8da79863 JAK |
570 | /* Should not happen in a normal world */ |
571 | if (unlikely(nvec->rx == NULL)) { | |
572 | nvec->state = 0; | |
573 | break; | |
574 | } | |
0cab4cb8 JAK |
575 | nvec->rx->data[0] = received; |
576 | nvec->rx->pos = 1; | |
577 | nvec->state = 2; | |
578 | } | |
579 | break; | |
580 | case 2: /* first byte after command */ | |
581 | if (status == (I2C_SL_IRQ | RNW | RCVD)) { | |
582 | udelay(33); | |
583 | if (nvec->rx->data[0] != 0x01) { | |
584 | dev_err(nvec->dev, | |
585 | "Read without prior read command\n"); | |
586 | nvec->state = 0; | |
587 | break; | |
32890b98 | 588 | } |
0cab4cb8 JAK |
589 | nvec_msg_free(nvec, nvec->rx); |
590 | nvec->state = 3; | |
591 | nvec_tx_set(nvec); | |
592 | BUG_ON(nvec->tx->size < 1); | |
593 | to_send = nvec->tx->data[0]; | |
594 | nvec->tx->pos = 1; | |
595 | } else if (status == (I2C_SL_IRQ)) { | |
596 | BUG_ON(nvec->rx == NULL); | |
597 | nvec->rx->data[1] = received; | |
598 | nvec->rx->pos = 2; | |
599 | nvec->state = 4; | |
600 | } else { | |
601 | nvec_invalid_flags(nvec, status, true); | |
32890b98 | 602 | } |
0cab4cb8 JAK |
603 | break; |
604 | case 3: /* EC does a block read, we transmit data */ | |
605 | if (status & END_TRANS) { | |
606 | nvec_tx_completed(nvec); | |
607 | } else if ((status & RNW) == 0 || (status & RCVD)) { | |
608 | nvec_invalid_flags(nvec, status, true); | |
609 | } else if (nvec->tx && nvec->tx->pos < nvec->tx->size) { | |
610 | to_send = nvec->tx->data[nvec->tx->pos++]; | |
611 | } else { | |
612 | dev_err(nvec->dev, "tx buffer underflow on %p (%u > %u)\n", | |
613 | nvec->tx, | |
614 | (uint) (nvec->tx ? nvec->tx->pos : 0), | |
615 | (uint) (nvec->tx ? nvec->tx->size : 0)); | |
616 | nvec->state = 0; | |
32890b98 | 617 | } |
0cab4cb8 JAK |
618 | break; |
619 | case 4: /* EC does some write, we read the data */ | |
620 | if ((status & (END_TRANS | RNW)) == END_TRANS) | |
621 | nvec_rx_completed(nvec); | |
622 | else if (status & (RNW | RCVD)) | |
623 | nvec_invalid_flags(nvec, status, true); | |
624 | else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE) | |
625 | nvec->rx->data[nvec->rx->pos++] = received; | |
626 | else | |
627 | dev_err(nvec->dev, | |
628 | "RX buffer overflow on %p: " | |
629 | "Trying to write byte %u of %u\n", | |
630 | nvec->rx, nvec->rx->pos, NVEC_MSG_SIZE); | |
631 | break; | |
632 | default: | |
633 | nvec->state = 0; | |
634 | } | |
32890b98 | 635 | |
0cab4cb8 JAK |
636 | /* If we are told that a new transfer starts, verify it */ |
637 | if ((status & (RCVD | RNW)) == RCVD) { | |
638 | if (received != nvec->i2c_addr) | |
639 | dev_err(nvec->dev, | |
640 | "received address 0x%02x, expected 0x%02x\n", | |
641 | received, nvec->i2c_addr); | |
642 | nvec->state = 1; | |
32890b98 | 643 | } |
0cab4cb8 JAK |
644 | |
645 | /* Send data if requested, but not on end of transmission */ | |
646 | if ((status & (RNW | END_TRANS)) == RNW) | |
647 | writel(to_send, nvec->base + I2C_SL_RCVD); | |
648 | ||
649 | /* If we have send the first byte */ | |
650 | if (status == (I2C_SL_IRQ | RNW | RCVD)) | |
651 | nvec_gpio_set_value(nvec, 1); | |
652 | ||
653 | dev_dbg(nvec->dev, | |
654 | "Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n", | |
655 | (status & RNW) == 0 ? "received" : "R=", | |
656 | received, | |
657 | (status & (RNW | END_TRANS)) ? "sent" : "S=", | |
658 | to_send, | |
659 | state, | |
660 | status & END_TRANS ? " END_TRANS" : "", | |
661 | status & RCVD ? " RCVD" : "", | |
662 | status & RNW ? " RNW" : ""); | |
663 | ||
de839b8f JAK |
664 | |
665 | /* | |
666 | * TODO: A correct fix needs to be found for this. | |
667 | * | |
668 | * We experience less incomplete messages with this delay than without | |
669 | * it, but we don't know why. Help is appreciated. | |
670 | */ | |
671 | udelay(100); | |
672 | ||
32890b98 MD |
673 | return IRQ_HANDLED; |
674 | } | |
675 | ||
f686e9af | 676 | static void tegra_init_i2c_slave(struct nvec_chip *nvec) |
32890b98 MD |
677 | { |
678 | u32 val; | |
679 | ||
61c3b197 | 680 | clk_prepare_enable(nvec->i2c_clk); |
f686e9af MD |
681 | |
682 | tegra_periph_reset_assert(nvec->i2c_clk); | |
32890b98 | 683 | udelay(2); |
f686e9af | 684 | tegra_periph_reset_deassert(nvec->i2c_clk); |
32890b98 | 685 | |
32890b98 | 686 | val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN | |
ac810759 | 687 | (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); |
f686e9af | 688 | writel(val, nvec->base + I2C_CNFG); |
ac810759 MD |
689 | |
690 | clk_set_rate(nvec->i2c_clk, 8 * 80000); | |
691 | ||
d3f862ae | 692 | writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG); |
ac810759 MD |
693 | writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT); |
694 | ||
695 | writel(nvec->i2c_addr>>1, nvec->base + I2C_SL_ADDR1); | |
696 | writel(0, nvec->base + I2C_SL_ADDR2); | |
32890b98 | 697 | |
ac810759 MD |
698 | enable_irq(nvec->irq); |
699 | ||
61c3b197 | 700 | clk_disable_unprepare(nvec->i2c_clk); |
ac810759 MD |
701 | } |
702 | ||
ebefae28 | 703 | #ifdef CONFIG_PM_SLEEP |
ac810759 MD |
704 | static void nvec_disable_i2c_slave(struct nvec_chip *nvec) |
705 | { | |
706 | disable_irq(nvec->irq); | |
d3f862ae | 707 | writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG); |
61c3b197 | 708 | clk_disable_unprepare(nvec->i2c_clk); |
32890b98 | 709 | } |
ebefae28 | 710 | #endif |
32890b98 MD |
711 | |
712 | static void nvec_power_off(void) | |
713 | { | |
714 | nvec_write_async(nvec_power_handle, EC_DISABLE_EVENT_REPORTING, 3); | |
715 | nvec_write_async(nvec_power_handle, "\x04\x01", 2); | |
716 | } | |
717 | ||
46620803 | 718 | static int tegra_nvec_probe(struct platform_device *pdev) |
32890b98 | 719 | { |
f686e9af | 720 | int err, ret; |
32890b98 MD |
721 | struct clk *i2c_clk; |
722 | struct nvec_platform_data *pdata = pdev->dev.platform_data; | |
723 | struct nvec_chip *nvec; | |
724 | struct nvec_msg *msg; | |
f686e9af | 725 | struct resource *res; |
f686e9af | 726 | void __iomem *base; |
32890b98 | 727 | |
f5e3352e | 728 | nvec = devm_kzalloc(&pdev->dev, sizeof(struct nvec_chip), GFP_KERNEL); |
162c7d8c | 729 | if (nvec == NULL) { |
32890b98 MD |
730 | dev_err(&pdev->dev, "failed to reserve memory\n"); |
731 | return -ENOMEM; | |
732 | } | |
733 | platform_set_drvdata(pdev, nvec); | |
734 | nvec->dev = &pdev->dev; | |
7990b0d7 MD |
735 | |
736 | if (pdata) { | |
737 | nvec->gpio = pdata->gpio; | |
738 | nvec->i2c_addr = pdata->i2c_addr; | |
739 | } else if (nvec->dev->of_node) { | |
103b748e MD |
740 | nvec->gpio = of_get_named_gpio(nvec->dev->of_node, |
741 | "request-gpios", 0); | |
7990b0d7 MD |
742 | if (nvec->gpio < 0) { |
743 | dev_err(&pdev->dev, "no gpio specified"); | |
f5e3352e | 744 | return -ENODEV; |
7990b0d7 | 745 | } |
103b748e MD |
746 | if (of_property_read_u32(nvec->dev->of_node, |
747 | "slave-addr", &nvec->i2c_addr)) { | |
7990b0d7 | 748 | dev_err(&pdev->dev, "no i2c address specified"); |
f5e3352e | 749 | return -ENODEV; |
7990b0d7 MD |
750 | } |
751 | } else { | |
752 | dev_err(&pdev->dev, "no platform data\n"); | |
f5e3352e | 753 | return -ENODEV; |
7990b0d7 | 754 | } |
f686e9af MD |
755 | |
756 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
757 | if (!res) { | |
758 | dev_err(&pdev->dev, "no mem resource?\n"); | |
759 | return -ENODEV; | |
32890b98 MD |
760 | } |
761 | ||
f5e3352e | 762 | base = devm_request_and_ioremap(&pdev->dev, res); |
f686e9af MD |
763 | if (!base) { |
764 | dev_err(&pdev->dev, "Can't ioremap I2C region\n"); | |
765 | return -ENOMEM; | |
32890b98 MD |
766 | } |
767 | ||
f686e9af MD |
768 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
769 | if (!res) { | |
770 | dev_err(&pdev->dev, "no irq resource?\n"); | |
f5e3352e | 771 | return -ENODEV; |
f686e9af | 772 | } |
32890b98 | 773 | |
4344379f | 774 | i2c_clk = clk_get_sys("tegra-i2c.2", "div-clk"); |
f686e9af MD |
775 | if (IS_ERR(i2c_clk)) { |
776 | dev_err(nvec->dev, "failed to get controller clock\n"); | |
f5e3352e | 777 | return -ENODEV; |
32890b98 MD |
778 | } |
779 | ||
f686e9af MD |
780 | nvec->base = base; |
781 | nvec->irq = res->start; | |
782 | nvec->i2c_clk = i2c_clk; | |
0cab4cb8 | 783 | nvec->rx = &nvec->msg_pool[0]; |
f686e9af | 784 | |
32890b98 MD |
785 | ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list); |
786 | ||
787 | init_completion(&nvec->sync_write); | |
0cab4cb8 JAK |
788 | init_completion(&nvec->ec_transfer); |
789 | mutex_init(&nvec->sync_write_mutex); | |
790 | spin_lock_init(&nvec->tx_lock); | |
791 | spin_lock_init(&nvec->rx_lock); | |
32890b98 | 792 | INIT_LIST_HEAD(&nvec->rx_data); |
0cab4cb8 | 793 | INIT_LIST_HEAD(&nvec->tx_data); |
32890b98 MD |
794 | INIT_WORK(&nvec->rx_work, nvec_dispatch); |
795 | INIT_WORK(&nvec->tx_work, nvec_request_master); | |
796 | ||
f5e3352e MD |
797 | err = devm_gpio_request_one(&pdev->dev, nvec->gpio, GPIOF_OUT_INIT_HIGH, |
798 | "nvec gpio"); | |
aed92bbc JAK |
799 | if (err < 0) { |
800 | dev_err(nvec->dev, "couldn't request gpio\n"); | |
f5e3352e | 801 | return -ENODEV; |
aed92bbc JAK |
802 | } |
803 | ||
f5e3352e MD |
804 | err = devm_request_irq(&pdev->dev, nvec->irq, nvec_interrupt, 0, |
805 | "nvec", nvec); | |
f686e9af MD |
806 | if (err) { |
807 | dev_err(nvec->dev, "couldn't request irq\n"); | |
f5e3352e | 808 | return -ENODEV; |
f686e9af | 809 | } |
ac810759 | 810 | disable_irq(nvec->irq); |
f686e9af MD |
811 | |
812 | tegra_init_i2c_slave(nvec); | |
813 | ||
61c3b197 | 814 | clk_prepare_enable(i2c_clk); |
ac810759 | 815 | |
f686e9af | 816 | |
32890b98 MD |
817 | /* enable event reporting */ |
818 | nvec_write_async(nvec, EC_ENABLE_EVENT_REPORTING, | |
162c7d8c | 819 | sizeof(EC_ENABLE_EVENT_REPORTING)); |
32890b98 | 820 | |
32890b98 MD |
821 | nvec->nvec_status_notifier.notifier_call = nvec_status_notifier; |
822 | nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0); | |
823 | ||
824 | nvec_power_handle = nvec; | |
825 | pm_power_off = nvec_power_off; | |
826 | ||
827 | /* Get Firmware Version */ | |
828 | msg = nvec_write_sync(nvec, EC_GET_FIRMWARE_VERSION, | |
0cab4cb8 | 829 | sizeof(EC_GET_FIRMWARE_VERSION)); |
32890b98 | 830 | |
0cab4cb8 JAK |
831 | if (msg) { |
832 | dev_warn(nvec->dev, "ec firmware version %02x.%02x.%02x / %02x\n", | |
833 | msg->data[4], msg->data[5], msg->data[6], msg->data[7]); | |
32890b98 | 834 | |
0cab4cb8 JAK |
835 | nvec_msg_free(nvec, msg); |
836 | } | |
32890b98 | 837 | |
f686e9af | 838 | ret = mfd_add_devices(nvec->dev, -1, nvec_devices, |
0848c94f | 839 | ARRAY_SIZE(nvec_devices), base, 0, NULL); |
162c7d8c | 840 | if (ret) |
f686e9af MD |
841 | dev_err(nvec->dev, "error adding subdevices\n"); |
842 | ||
32890b98 | 843 | /* unmute speakers? */ |
6dca320c | 844 | nvec_write_async(nvec, "\x0d\x10\x59\x95", 4); |
32890b98 MD |
845 | |
846 | /* enable lid switch event */ | |
847 | nvec_write_async(nvec, "\x01\x01\x01\x00\x00\x02\x00", 7); | |
848 | ||
849 | /* enable power button event */ | |
850 | nvec_write_async(nvec, "\x01\x01\x01\x00\x00\x80\x00", 7); | |
851 | ||
852 | return 0; | |
32890b98 MD |
853 | } |
854 | ||
1a6a8a84 | 855 | static int tegra_nvec_remove(struct platform_device *pdev) |
32890b98 | 856 | { |
f686e9af MD |
857 | struct nvec_chip *nvec = platform_get_drvdata(pdev); |
858 | ||
859 | nvec_write_async(nvec, EC_DISABLE_EVENT_REPORTING, 3); | |
860 | mfd_remove_devices(nvec->dev); | |
eb1e40a4 TH |
861 | cancel_work_sync(&nvec->rx_work); |
862 | cancel_work_sync(&nvec->tx_work); | |
f686e9af | 863 | |
32890b98 MD |
864 | return 0; |
865 | } | |
866 | ||
ebefae28 MD |
867 | #ifdef CONFIG_PM_SLEEP |
868 | static int nvec_suspend(struct device *dev) | |
32890b98 | 869 | { |
ebefae28 | 870 | struct platform_device *pdev = to_platform_device(dev); |
32890b98 | 871 | struct nvec_chip *nvec = platform_get_drvdata(pdev); |
9feeb014 | 872 | struct nvec_msg *msg; |
32890b98 MD |
873 | |
874 | dev_dbg(nvec->dev, "suspending\n"); | |
9feeb014 MD |
875 | |
876 | /* keep these sync or you'll break suspend */ | |
877 | msg = nvec_write_sync(nvec, EC_DISABLE_EVENT_REPORTING, 3); | |
878 | nvec_msg_free(nvec, msg); | |
879 | msg = nvec_write_sync(nvec, "\x04\x02", 2); | |
880 | nvec_msg_free(nvec, msg); | |
881 | ||
ac810759 | 882 | nvec_disable_i2c_slave(nvec); |
32890b98 MD |
883 | |
884 | return 0; | |
885 | } | |
886 | ||
ebefae28 | 887 | static int nvec_resume(struct device *dev) |
162c7d8c | 888 | { |
ebefae28 | 889 | struct platform_device *pdev = to_platform_device(dev); |
32890b98 MD |
890 | struct nvec_chip *nvec = platform_get_drvdata(pdev); |
891 | ||
892 | dev_dbg(nvec->dev, "resuming\n"); | |
f686e9af | 893 | tegra_init_i2c_slave(nvec); |
32890b98 MD |
894 | nvec_write_async(nvec, EC_ENABLE_EVENT_REPORTING, 3); |
895 | ||
896 | return 0; | |
897 | } | |
32890b98 MD |
898 | #endif |
899 | ||
ebefae28 MD |
900 | static const SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume); |
901 | ||
7990b0d7 | 902 | /* Match table for of_platform binding */ |
063f9f6a | 903 | static const struct of_device_id nvidia_nvec_of_match[] = { |
7990b0d7 MD |
904 | { .compatible = "nvidia,nvec", }, |
905 | {}, | |
906 | }; | |
907 | MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match); | |
908 | ||
162c7d8c MD |
909 | static struct platform_driver nvec_device_driver = { |
910 | .probe = tegra_nvec_probe, | |
44b90a3f | 911 | .remove = tegra_nvec_remove, |
162c7d8c | 912 | .driver = { |
32890b98 MD |
913 | .name = "nvec", |
914 | .owner = THIS_MODULE, | |
ebefae28 | 915 | .pm = &nvec_pm_ops, |
7990b0d7 | 916 | .of_match_table = nvidia_nvec_of_match, |
32890b98 MD |
917 | } |
918 | }; | |
919 | ||
9891b1ce | 920 | module_platform_driver(nvec_device_driver); |
162c7d8c | 921 | |
32890b98 | 922 | MODULE_ALIAS("platform:nvec"); |
162c7d8c MD |
923 | MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface"); |
924 | MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>"); | |
925 | MODULE_LICENSE("GPL"); |