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1/*
2 * NVEC: NVIDIA compliant embedded controller interface
3 *
4 * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net>
5 *
6 * Authors: Pierre-Hugues Husson <phhusson@free.fr>
7 * Ilya Petrov <ilya.muromec@gmail.com>
8 * Marc Dietrich <marvin24@gmx.de>
791c4a64 9 * Julian Andres Klode <jak@jak-linux.org>
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10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 *
15 */
16
17/* #define DEBUG */
32890b98 18
12b5a55d 19#include <linux/kernel.h>
3b769edd 20#include <linux/module.h>
0b1076c4 21#include <linux/atomic.h>
12b5a55d 22#include <linux/clk.h>
32890b98 23#include <linux/completion.h>
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24#include <linux/delay.h>
25#include <linux/err.h>
26#include <linux/gpio.h>
32890b98 27#include <linux/interrupt.h>
162c7d8c 28#include <linux/io.h>
32890b98 29#include <linux/irq.h>
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30#include <linux/of.h>
31#include <linux/of_gpio.h>
32890b98 32#include <linux/list.h>
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33#include <linux/mfd/core.h>
34#include <linux/mutex.h>
32890b98 35#include <linux/notifier.h>
32890b98 36#include <linux/platform_device.h>
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37#include <linux/slab.h>
38#include <linux/spinlock.h>
39#include <linux/workqueue.h>
162c7d8c 40
162c7d8c 41#include <mach/clk.h>
12b5a55d 42#include <mach/iomap.h>
162c7d8c 43
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44#include "nvec.h"
45
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46#define I2C_CNFG 0x00
47#define I2C_CNFG_PACKET_MODE_EN (1<<10)
48#define I2C_CNFG_NEW_MASTER_SFM (1<<11)
49#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
50
51#define I2C_SL_CNFG 0x20
d3f862ae 52#define I2C_SL_NEWSL (1<<2)
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53#define I2C_SL_NACK (1<<1)
54#define I2C_SL_RESP (1<<0)
55#define I2C_SL_IRQ (1<<3)
56#define END_TRANS (1<<4)
57#define RCVD (1<<2)
58#define RNW (1<<1)
59
60#define I2C_SL_RCVD 0x24
61#define I2C_SL_STATUS 0x28
62#define I2C_SL_ADDR1 0x2c
63#define I2C_SL_ADDR2 0x30
64#define I2C_SL_DELAY_COUNT 0x3c
65
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66/**
67 * enum nvec_msg_category - Message categories for nvec_msg_alloc()
68 * @NVEC_MSG_RX: The message is an incoming message (from EC)
69 * @NVEC_MSG_TX: The message is an outgoing message (to EC)
70 */
71enum nvec_msg_category {
72 NVEC_MSG_RX,
73 NVEC_MSG_TX,
74};
75
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76static const unsigned char EC_DISABLE_EVENT_REPORTING[3] = "\x04\x00\x00";
77static const unsigned char EC_ENABLE_EVENT_REPORTING[3] = "\x04\x00\x01";
78static const unsigned char EC_GET_FIRMWARE_VERSION[2] = "\x07\x15";
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79
80static struct nvec_chip *nvec_power_handle;
81
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82static struct mfd_cell nvec_devices[] = {
83 {
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84 .name = "nvec-kbd",
85 .id = 1,
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86 },
87 {
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88 .name = "nvec-mouse",
89 .id = 1,
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90 },
91 {
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92 .name = "nvec-power",
93 .id = 1,
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94 },
95 {
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96 .name = "nvec-power",
97 .id = 2,
f686e9af 98 },
97cc2657 99 {
ac562680 100 .name = "nvec-paz00",
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101 .id = 1,
102 },
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103};
104
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105/**
106 * nvec_register_notifier - Register a notifier with nvec
107 * @nvec: A &struct nvec_chip
108 * @nb: The notifier block to register
109 *
110 * Registers a notifier with @nvec. The notifier will be added to an atomic
111 * notifier chain that is called for all received messages except those that
112 * correspond to a request initiated by nvec_write_sync().
113 */
32890b98 114int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb,
162c7d8c 115 unsigned int events)
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116{
117 return atomic_notifier_chain_register(&nvec->notifier_list, nb);
118}
119EXPORT_SYMBOL_GPL(nvec_register_notifier);
120
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121/**
122 * nvec_status_notifier - The final notifier
123 *
124 * Prints a message about control events not handled in the notifier
125 * chain.
126 */
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127static int nvec_status_notifier(struct notifier_block *nb,
128 unsigned long event_type, void *data)
32890b98 129{
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130 struct nvec_chip *nvec = container_of(nb, struct nvec_chip,
131 nvec_status_notifier);
32890b98 132 unsigned char *msg = (unsigned char *)data;
32890b98 133
162c7d8c 134 if (event_type != NVEC_CNTL)
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135 return NOTIFY_DONE;
136
50d4656a 137 dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type);
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138 print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1,
139 msg, msg[1] + 2, true);
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140
141 return NOTIFY_OK;
142}
143
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144/**
145 * nvec_msg_alloc:
146 * @nvec: A &struct nvec_chip
bb0590e2 147 * @category: Pool category, see &enum nvec_msg_category
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148 *
149 * Allocate a single &struct nvec_msg object from the message pool of
150 * @nvec. The result shall be passed to nvec_msg_free() if no longer
151 * used.
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152 *
153 * Outgoing messages are placed in the upper 75% of the pool, keeping the
154 * lower 25% available for RX buffers only. The reason is to prevent a
155 * situation where all buffers are full and a message is thus endlessly
156 * retried because the response could never be processed.
bdf034d9 157 */
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158static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec,
159 enum nvec_msg_category category)
0b1076c4 160{
bb0590e2 161 int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0;
0b1076c4 162
bb0590e2 163 for (; i < NVEC_POOL_SIZE; i++) {
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164 if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) {
165 dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i);
166 return &nvec->msg_pool[i];
167 }
168 }
169
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170 dev_err(nvec->dev, "could not allocate %s buffer\n",
171 (category == NVEC_MSG_TX) ? "TX" : "RX");
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172
173 return NULL;
174}
175
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176/**
177 * nvec_msg_free:
178 * @nvec: A &struct nvec_chip
179 * @msg: A message (must be allocated by nvec_msg_alloc() and belong to @nvec)
180 *
181 * Free the given message
182 */
198dd267 183inline void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg)
0b1076c4 184{
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185 if (msg != &nvec->tx_scratch)
186 dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool);
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187 atomic_set(&msg->used, 0);
188}
198dd267 189EXPORT_SYMBOL_GPL(nvec_msg_free);
0b1076c4 190
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191/**
192 * nvec_msg_is_event - Return %true if @msg is an event
193 * @msg: A message
194 */
195static bool nvec_msg_is_event(struct nvec_msg *msg)
196{
197 return msg->data[0] >> 7;
198}
199
200/**
201 * nvec_msg_size - Get the size of a message
202 * @msg: The message to get the size for
203 *
204 * This only works for received messages, not for outgoing messages.
205 */
206static size_t nvec_msg_size(struct nvec_msg *msg)
207{
208 bool is_event = nvec_msg_is_event(msg);
209 int event_length = (msg->data[0] & 0x60) >> 5;
210
211 /* for variable size, payload size in byte 1 + count (1) + cmd (1) */
212 if (!is_event || event_length == NVEC_VAR_SIZE)
213 return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0;
214 else if (event_length == NVEC_2BYTES)
215 return 2;
216 else if (event_length == NVEC_3BYTES)
217 return 3;
218 else
219 return 0;
220}
221
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222/**
223 * nvec_gpio_set_value - Set the GPIO value
224 * @nvec: A &struct nvec_chip
225 * @value: The value to write (0 or 1)
226 *
227 * Like gpio_set_value(), but generating debugging information
228 */
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229static void nvec_gpio_set_value(struct nvec_chip *nvec, int value)
230{
231 dev_dbg(nvec->dev, "GPIO changed from %u to %u\n",
232 gpio_get_value(nvec->gpio), value);
233 gpio_set_value(nvec->gpio, value);
234}
235
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236/**
237 * nvec_write_async - Asynchronously write a message to NVEC
238 * @nvec: An nvec_chip instance
239 * @data: The message data, starting with the request type
240 * @size: The size of @data
241 *
242 * Queue a single message to be transferred to the embedded controller
243 * and return immediately.
244 *
245 * Returns: 0 on success, a negative error code on failure. If a failure
246 * occured, the nvec driver may print an error.
247 */
1b9bf629 248int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data,
162c7d8c 249 short size)
32890b98 250{
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251 struct nvec_msg *msg;
252 unsigned long flags;
32890b98 253
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254 msg = nvec_msg_alloc(nvec, NVEC_MSG_TX);
255
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256 if (msg == NULL)
257 return -ENOMEM;
258
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259 msg->data[0] = size;
260 memcpy(msg->data + 1, data, size);
261 msg->size = size + 1;
32890b98 262
0cab4cb8 263 spin_lock_irqsave(&nvec->tx_lock, flags);
32890b98 264 list_add_tail(&msg->node, &nvec->tx_data);
0cab4cb8 265 spin_unlock_irqrestore(&nvec->tx_lock, flags);
32890b98 266
eb1e40a4 267 queue_work(system_nrt_wq, &nvec->tx_work);
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268
269 return 0;
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270}
271EXPORT_SYMBOL(nvec_write_async);
272
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273/**
274 * nvec_write_sync - Write a message to nvec and read the response
275 * @nvec: An &struct nvec_chip
276 * @data: The data to write
277 * @size: The size of @data
278 *
279 * This is similar to nvec_write_async(), but waits for the
280 * request to be answered before returning. This function
281 * uses a mutex and can thus not be called from e.g.
282 * interrupt handlers.
283 *
284 * Returns: A pointer to the response message on success,
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285 * %NULL on failure. Free with nvec_msg_free() once no longer
286 * used.
bdf034d9 287 */
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288struct nvec_msg *nvec_write_sync(struct nvec_chip *nvec,
289 const unsigned char *data, short size)
290{
291 struct nvec_msg *msg;
292
293 mutex_lock(&nvec->sync_write_mutex);
294
295 nvec->sync_write_pending = (data[1] << 8) + data[0];
1b9bf629 296
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297 if (nvec_write_async(nvec, data, size) < 0) {
298 mutex_unlock(&nvec->sync_write_mutex);
1b9bf629 299 return NULL;
4b8bf03d 300 }
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301
302 dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n",
303 nvec->sync_write_pending);
304 if (!(wait_for_completion_timeout(&nvec->sync_write,
305 msecs_to_jiffies(2000)))) {
306 dev_warn(nvec->dev, "timeout waiting for sync write to complete\n");
307 mutex_unlock(&nvec->sync_write_mutex);
308 return NULL;
309 }
310
311 dev_dbg(nvec->dev, "nvec_sync_write: pong!\n");
312
313 msg = nvec->last_sync_msg;
314
315 mutex_unlock(&nvec->sync_write_mutex);
316
317 return msg;
318}
319EXPORT_SYMBOL(nvec_write_sync);
320
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321/**
322 * nvec_request_master - Process outgoing messages
323 * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
324 *
325 * Processes all outgoing requests by sending the request and awaiting the
326 * response, then continuing with the next request. Once a request has a
327 * matching response, it will be freed and removed from the list.
328 */
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329static void nvec_request_master(struct work_struct *work)
330{
331 struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work);
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332 unsigned long flags;
333 long err;
334 struct nvec_msg *msg;
335
336 spin_lock_irqsave(&nvec->tx_lock, flags);
337 while (!list_empty(&nvec->tx_data)) {
338 msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node);
339 spin_unlock_irqrestore(&nvec->tx_lock, flags);
340 nvec_gpio_set_value(nvec, 0);
341 err = wait_for_completion_interruptible_timeout(
342 &nvec->ec_transfer, msecs_to_jiffies(5000));
343
344 if (err == 0) {
345 dev_warn(nvec->dev, "timeout waiting for ec transfer\n");
346 nvec_gpio_set_value(nvec, 1);
347 msg->pos = 0;
348 }
32890b98 349
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350 spin_lock_irqsave(&nvec->tx_lock, flags);
351
352 if (err > 0) {
353 list_del_init(&msg->node);
354 nvec_msg_free(nvec, msg);
355 }
356 }
357 spin_unlock_irqrestore(&nvec->tx_lock, flags);
32890b98
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358}
359
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360/**
361 * parse_msg - Print some information and call the notifiers on an RX message
362 * @nvec: A &struct nvec_chip
363 * @msg: A message received by @nvec
364 *
365 * Paarse some pieces of the message and then call the chain of notifiers
366 * registered via nvec_register_notifier.
367 */
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368static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg)
369{
162c7d8c 370 if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) {
6a371978 371 dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data);
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372 return -EINVAL;
373 }
374
a3a9aa1a
MD
375 if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5)
376 print_hex_dump(KERN_WARNING, "ec system event ",
377 DUMP_PREFIX_NONE, 16, 1, msg->data,
378 msg->data[1] + 2, true);
32890b98 379
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380 atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f,
381 msg->data);
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382
383 return 0;
384}
385
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386/**
387 * nvec_dispatch - Process messages received from the EC
388 * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
389 *
390 * Process messages previously received from the EC and put into the RX
391 * queue of the &struct nvec_chip instance associated with @work.
392 */
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393static void nvec_dispatch(struct work_struct *work)
394{
395 struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work);
0cab4cb8 396 unsigned long flags;
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397 struct nvec_msg *msg;
398
0cab4cb8 399 spin_lock_irqsave(&nvec->rx_lock, flags);
162c7d8c 400 while (!list_empty(&nvec->rx_data)) {
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401 msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node);
402 list_del_init(&msg->node);
0cab4cb8 403 spin_unlock_irqrestore(&nvec->rx_lock, flags);
32890b98 404
162c7d8c 405 if (nvec->sync_write_pending ==
0cab4cb8 406 (msg->data[2] << 8) + msg->data[0]) {
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407 dev_dbg(nvec->dev, "sync write completed!\n");
408 nvec->sync_write_pending = 0;
409 nvec->last_sync_msg = msg;
410 complete(&nvec->sync_write);
411 } else {
412 parse_msg(nvec, msg);
0cab4cb8 413 nvec_msg_free(nvec, msg);
32890b98 414 }
0cab4cb8 415 spin_lock_irqsave(&nvec->rx_lock, flags);
32890b98 416 }
0cab4cb8 417 spin_unlock_irqrestore(&nvec->rx_lock, flags);
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418}
419
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420/**
421 * nvec_tx_completed - Complete the current transfer
422 * @nvec: A &struct nvec_chip
423 *
424 * This is called when we have received an END_TRANS on a TX transfer.
425 */
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426static void nvec_tx_completed(struct nvec_chip *nvec)
427{
428 /* We got an END_TRANS, let's skip this, maybe there's an event */
429 if (nvec->tx->pos != nvec->tx->size) {
430 dev_err(nvec->dev, "premature END_TRANS, resending\n");
431 nvec->tx->pos = 0;
432 nvec_gpio_set_value(nvec, 0);
433 } else {
434 nvec->state = 0;
435 }
436}
437
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438/**
439 * nvec_rx_completed - Complete the current transfer
440 * @nvec: A &struct nvec_chip
441 *
442 * This is called when we have received an END_TRANS on a RX transfer.
443 */
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444static void nvec_rx_completed(struct nvec_chip *nvec)
445{
210ceb4f 446 if (nvec->rx->pos != nvec_msg_size(nvec->rx)) {
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447 dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n",
448 (uint) nvec_msg_size(nvec->rx),
449 (uint) nvec->rx->pos);
450
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451 nvec_msg_free(nvec, nvec->rx);
452 nvec->state = 0;
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453
454 /* Battery quirk - Often incomplete, and likes to crash */
455 if (nvec->rx->data[0] == NVEC_BAT)
456 complete(&nvec->ec_transfer);
457
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458 return;
459 }
460
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461 spin_lock(&nvec->rx_lock);
462
463 /* add the received data to the work list
464 and move the ring buffer pointer to the next entry */
465 list_add_tail(&nvec->rx->node, &nvec->rx_data);
466
467 spin_unlock(&nvec->rx_lock);
468
469 nvec->state = 0;
470
471 if (!nvec_msg_is_event(nvec->rx))
472 complete(&nvec->ec_transfer);
473
eb1e40a4 474 queue_work(system_nrt_wq, &nvec->rx_work);
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475}
476
477/**
478 * nvec_invalid_flags - Send an error message about invalid flags and jump
479 * @nvec: The nvec device
480 * @status: The status flags
481 * @reset: Whether we shall jump to state 0.
482 */
483static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status,
484 bool reset)
485{
486 dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n",
487 status, nvec->state);
488 if (reset)
489 nvec->state = 0;
490}
491
492/**
493 * nvec_tx_set - Set the message to transfer (nvec->tx)
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494 * @nvec: A &struct nvec_chip
495 *
496 * Gets the first entry from the tx_data list of @nvec and sets the
497 * tx member to it. If the tx_data list is empty, this uses the
498 * tx_scratch message to send a no operation message.
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499 */
500static void nvec_tx_set(struct nvec_chip *nvec)
501{
502 spin_lock(&nvec->tx_lock);
503 if (list_empty(&nvec->tx_data)) {
504 dev_err(nvec->dev, "empty tx - sending no-op\n");
505 memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3);
506 nvec->tx_scratch.size = 3;
507 nvec->tx_scratch.pos = 0;
508 nvec->tx = &nvec->tx_scratch;
509 list_add_tail(&nvec->tx->node, &nvec->tx_data);
510 } else {
511 nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg,
512 node);
513 nvec->tx->pos = 0;
514 }
515 spin_unlock(&nvec->tx_lock);
516
517 dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n",
518 (uint)nvec->tx->size, nvec->tx->data[1]);
519}
520
521/**
522 * nvec_interrupt - Interrupt handler
523 * @irq: The IRQ
524 * @dev: The nvec device
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525 *
526 * Interrupt handler that fills our RX buffers and empties our TX
527 * buffers. This uses a finite state machine with ridiculous amounts
528 * of error checking, in order to be fairly reliable.
0cab4cb8 529 */
f686e9af 530static irqreturn_t nvec_interrupt(int irq, void *dev)
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531{
532 unsigned long status;
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533 unsigned int received = 0;
534 unsigned char to_send = 0xff;
535 const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW;
536 struct nvec_chip *nvec = dev;
537 unsigned int state = nvec->state;
32890b98 538
0cab4cb8 539 status = readl(nvec->base + I2C_SL_STATUS);
32890b98 540
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541 /* Filter out some errors */
542 if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) {
543 dev_err(nvec->dev, "unexpected irq mask %lx\n", status);
544 return IRQ_HANDLED;
32890b98 545 }
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546 if ((status & I2C_SL_IRQ) == 0) {
547 dev_err(nvec->dev, "Spurious IRQ\n");
32890b98 548 return IRQ_HANDLED;
0cab4cb8 549 }
32890b98 550
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551 /* The EC did not request a read, so it send us something, read it */
552 if ((status & RNW) == 0) {
553 received = readl(nvec->base + I2C_SL_RCVD);
162c7d8c 554 if (status & RCVD)
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555 writel(0, nvec->base + I2C_SL_RCVD);
556 }
162c7d8c 557
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558 if (status == (I2C_SL_IRQ | RCVD))
559 nvec->state = 0;
560
561 switch (nvec->state) {
562 case 0: /* Verify that its a transfer start, the rest later */
563 if (status != (I2C_SL_IRQ | RCVD))
564 nvec_invalid_flags(nvec, status, false);
565 break;
566 case 1: /* command byte */
567 if (status != I2C_SL_IRQ) {
568 nvec_invalid_flags(nvec, status, true);
32890b98 569 } else {
bb0590e2 570 nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX);
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571 /* Should not happen in a normal world */
572 if (unlikely(nvec->rx == NULL)) {
573 nvec->state = 0;
574 break;
575 }
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576 nvec->rx->data[0] = received;
577 nvec->rx->pos = 1;
578 nvec->state = 2;
579 }
580 break;
581 case 2: /* first byte after command */
582 if (status == (I2C_SL_IRQ | RNW | RCVD)) {
583 udelay(33);
584 if (nvec->rx->data[0] != 0x01) {
585 dev_err(nvec->dev,
586 "Read without prior read command\n");
587 nvec->state = 0;
588 break;
32890b98 589 }
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590 nvec_msg_free(nvec, nvec->rx);
591 nvec->state = 3;
592 nvec_tx_set(nvec);
593 BUG_ON(nvec->tx->size < 1);
594 to_send = nvec->tx->data[0];
595 nvec->tx->pos = 1;
596 } else if (status == (I2C_SL_IRQ)) {
597 BUG_ON(nvec->rx == NULL);
598 nvec->rx->data[1] = received;
599 nvec->rx->pos = 2;
600 nvec->state = 4;
601 } else {
602 nvec_invalid_flags(nvec, status, true);
32890b98 603 }
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604 break;
605 case 3: /* EC does a block read, we transmit data */
606 if (status & END_TRANS) {
607 nvec_tx_completed(nvec);
608 } else if ((status & RNW) == 0 || (status & RCVD)) {
609 nvec_invalid_flags(nvec, status, true);
610 } else if (nvec->tx && nvec->tx->pos < nvec->tx->size) {
611 to_send = nvec->tx->data[nvec->tx->pos++];
612 } else {
613 dev_err(nvec->dev, "tx buffer underflow on %p (%u > %u)\n",
614 nvec->tx,
615 (uint) (nvec->tx ? nvec->tx->pos : 0),
616 (uint) (nvec->tx ? nvec->tx->size : 0));
617 nvec->state = 0;
32890b98 618 }
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619 break;
620 case 4: /* EC does some write, we read the data */
621 if ((status & (END_TRANS | RNW)) == END_TRANS)
622 nvec_rx_completed(nvec);
623 else if (status & (RNW | RCVD))
624 nvec_invalid_flags(nvec, status, true);
625 else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE)
626 nvec->rx->data[nvec->rx->pos++] = received;
627 else
628 dev_err(nvec->dev,
629 "RX buffer overflow on %p: "
630 "Trying to write byte %u of %u\n",
631 nvec->rx, nvec->rx->pos, NVEC_MSG_SIZE);
632 break;
633 default:
634 nvec->state = 0;
635 }
32890b98 636
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637 /* If we are told that a new transfer starts, verify it */
638 if ((status & (RCVD | RNW)) == RCVD) {
639 if (received != nvec->i2c_addr)
640 dev_err(nvec->dev,
641 "received address 0x%02x, expected 0x%02x\n",
642 received, nvec->i2c_addr);
643 nvec->state = 1;
32890b98 644 }
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645
646 /* Send data if requested, but not on end of transmission */
647 if ((status & (RNW | END_TRANS)) == RNW)
648 writel(to_send, nvec->base + I2C_SL_RCVD);
649
650 /* If we have send the first byte */
651 if (status == (I2C_SL_IRQ | RNW | RCVD))
652 nvec_gpio_set_value(nvec, 1);
653
654 dev_dbg(nvec->dev,
655 "Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n",
656 (status & RNW) == 0 ? "received" : "R=",
657 received,
658 (status & (RNW | END_TRANS)) ? "sent" : "S=",
659 to_send,
660 state,
661 status & END_TRANS ? " END_TRANS" : "",
662 status & RCVD ? " RCVD" : "",
663 status & RNW ? " RNW" : "");
664
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665
666 /*
667 * TODO: A correct fix needs to be found for this.
668 *
669 * We experience less incomplete messages with this delay than without
670 * it, but we don't know why. Help is appreciated.
671 */
672 udelay(100);
673
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MD
674 return IRQ_HANDLED;
675}
676
f686e9af 677static void tegra_init_i2c_slave(struct nvec_chip *nvec)
32890b98
MD
678{
679 u32 val;
680
61c3b197 681 clk_prepare_enable(nvec->i2c_clk);
f686e9af
MD
682
683 tegra_periph_reset_assert(nvec->i2c_clk);
32890b98 684 udelay(2);
f686e9af 685 tegra_periph_reset_deassert(nvec->i2c_clk);
32890b98 686
32890b98 687 val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
ac810759 688 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
f686e9af 689 writel(val, nvec->base + I2C_CNFG);
ac810759
MD
690
691 clk_set_rate(nvec->i2c_clk, 8 * 80000);
692
d3f862ae 693 writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG);
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MD
694 writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT);
695
696 writel(nvec->i2c_addr>>1, nvec->base + I2C_SL_ADDR1);
697 writel(0, nvec->base + I2C_SL_ADDR2);
32890b98 698
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699 enable_irq(nvec->irq);
700
61c3b197 701 clk_disable_unprepare(nvec->i2c_clk);
ac810759
MD
702}
703
ebefae28 704#ifdef CONFIG_PM_SLEEP
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705static void nvec_disable_i2c_slave(struct nvec_chip *nvec)
706{
707 disable_irq(nvec->irq);
d3f862ae 708 writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG);
61c3b197 709 clk_disable_unprepare(nvec->i2c_clk);
32890b98 710}
ebefae28 711#endif
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MD
712
713static void nvec_power_off(void)
714{
715 nvec_write_async(nvec_power_handle, EC_DISABLE_EVENT_REPORTING, 3);
716 nvec_write_async(nvec_power_handle, "\x04\x01", 2);
717}
718
719static int __devinit tegra_nvec_probe(struct platform_device *pdev)
720{
f686e9af 721 int err, ret;
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MD
722 struct clk *i2c_clk;
723 struct nvec_platform_data *pdata = pdev->dev.platform_data;
724 struct nvec_chip *nvec;
725 struct nvec_msg *msg;
f686e9af 726 struct resource *res;
f686e9af 727 void __iomem *base;
32890b98 728
f5e3352e 729 nvec = devm_kzalloc(&pdev->dev, sizeof(struct nvec_chip), GFP_KERNEL);
162c7d8c 730 if (nvec == NULL) {
32890b98
MD
731 dev_err(&pdev->dev, "failed to reserve memory\n");
732 return -ENOMEM;
733 }
734 platform_set_drvdata(pdev, nvec);
735 nvec->dev = &pdev->dev;
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MD
736
737 if (pdata) {
738 nvec->gpio = pdata->gpio;
739 nvec->i2c_addr = pdata->i2c_addr;
740 } else if (nvec->dev->of_node) {
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MD
741 nvec->gpio = of_get_named_gpio(nvec->dev->of_node,
742 "request-gpios", 0);
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MD
743 if (nvec->gpio < 0) {
744 dev_err(&pdev->dev, "no gpio specified");
f5e3352e 745 return -ENODEV;
7990b0d7 746 }
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MD
747 if (of_property_read_u32(nvec->dev->of_node,
748 "slave-addr", &nvec->i2c_addr)) {
7990b0d7 749 dev_err(&pdev->dev, "no i2c address specified");
f5e3352e 750 return -ENODEV;
7990b0d7
MD
751 }
752 } else {
753 dev_err(&pdev->dev, "no platform data\n");
f5e3352e 754 return -ENODEV;
7990b0d7 755 }
f686e9af
MD
756
757 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
758 if (!res) {
759 dev_err(&pdev->dev, "no mem resource?\n");
760 return -ENODEV;
32890b98
MD
761 }
762
f5e3352e 763 base = devm_request_and_ioremap(&pdev->dev, res);
f686e9af
MD
764 if (!base) {
765 dev_err(&pdev->dev, "Can't ioremap I2C region\n");
766 return -ENOMEM;
32890b98
MD
767 }
768
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MD
769 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
770 if (!res) {
771 dev_err(&pdev->dev, "no irq resource?\n");
f5e3352e 772 return -ENODEV;
f686e9af 773 }
32890b98 774
4344379f 775 i2c_clk = clk_get_sys("tegra-i2c.2", "div-clk");
f686e9af
MD
776 if (IS_ERR(i2c_clk)) {
777 dev_err(nvec->dev, "failed to get controller clock\n");
f5e3352e 778 return -ENODEV;
32890b98
MD
779 }
780
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781 nvec->base = base;
782 nvec->irq = res->start;
783 nvec->i2c_clk = i2c_clk;
0cab4cb8 784 nvec->rx = &nvec->msg_pool[0];
f686e9af 785
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MD
786 ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list);
787
788 init_completion(&nvec->sync_write);
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789 init_completion(&nvec->ec_transfer);
790 mutex_init(&nvec->sync_write_mutex);
791 spin_lock_init(&nvec->tx_lock);
792 spin_lock_init(&nvec->rx_lock);
32890b98 793 INIT_LIST_HEAD(&nvec->rx_data);
0cab4cb8 794 INIT_LIST_HEAD(&nvec->tx_data);
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795 INIT_WORK(&nvec->rx_work, nvec_dispatch);
796 INIT_WORK(&nvec->tx_work, nvec_request_master);
797
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MD
798 err = devm_gpio_request_one(&pdev->dev, nvec->gpio, GPIOF_OUT_INIT_HIGH,
799 "nvec gpio");
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800 if (err < 0) {
801 dev_err(nvec->dev, "couldn't request gpio\n");
f5e3352e 802 return -ENODEV;
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803 }
804
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MD
805 err = devm_request_irq(&pdev->dev, nvec->irq, nvec_interrupt, 0,
806 "nvec", nvec);
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MD
807 if (err) {
808 dev_err(nvec->dev, "couldn't request irq\n");
f5e3352e 809 return -ENODEV;
f686e9af 810 }
ac810759 811 disable_irq(nvec->irq);
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MD
812
813 tegra_init_i2c_slave(nvec);
814
61c3b197 815 clk_prepare_enable(i2c_clk);
ac810759 816
f686e9af 817
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MD
818 /* enable event reporting */
819 nvec_write_async(nvec, EC_ENABLE_EVENT_REPORTING,
162c7d8c 820 sizeof(EC_ENABLE_EVENT_REPORTING));
32890b98 821
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MD
822 nvec->nvec_status_notifier.notifier_call = nvec_status_notifier;
823 nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0);
824
825 nvec_power_handle = nvec;
826 pm_power_off = nvec_power_off;
827
828 /* Get Firmware Version */
829 msg = nvec_write_sync(nvec, EC_GET_FIRMWARE_VERSION,
0cab4cb8 830 sizeof(EC_GET_FIRMWARE_VERSION));
32890b98 831
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832 if (msg) {
833 dev_warn(nvec->dev, "ec firmware version %02x.%02x.%02x / %02x\n",
834 msg->data[4], msg->data[5], msg->data[6], msg->data[7]);
32890b98 835
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836 nvec_msg_free(nvec, msg);
837 }
32890b98 838
f686e9af 839 ret = mfd_add_devices(nvec->dev, -1, nvec_devices,
0848c94f 840 ARRAY_SIZE(nvec_devices), base, 0, NULL);
162c7d8c 841 if (ret)
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MD
842 dev_err(nvec->dev, "error adding subdevices\n");
843
32890b98 844 /* unmute speakers? */
6dca320c 845 nvec_write_async(nvec, "\x0d\x10\x59\x95", 4);
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MD
846
847 /* enable lid switch event */
848 nvec_write_async(nvec, "\x01\x01\x01\x00\x00\x02\x00", 7);
849
850 /* enable power button event */
851 nvec_write_async(nvec, "\x01\x01\x01\x00\x00\x80\x00", 7);
852
853 return 0;
32890b98
MD
854}
855
856static int __devexit tegra_nvec_remove(struct platform_device *pdev)
857{
f686e9af
MD
858 struct nvec_chip *nvec = platform_get_drvdata(pdev);
859
860 nvec_write_async(nvec, EC_DISABLE_EVENT_REPORTING, 3);
861 mfd_remove_devices(nvec->dev);
eb1e40a4
TH
862 cancel_work_sync(&nvec->rx_work);
863 cancel_work_sync(&nvec->tx_work);
f686e9af 864
32890b98
MD
865 return 0;
866}
867
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MD
868#ifdef CONFIG_PM_SLEEP
869static int nvec_suspend(struct device *dev)
32890b98 870{
ebefae28 871 struct platform_device *pdev = to_platform_device(dev);
32890b98 872 struct nvec_chip *nvec = platform_get_drvdata(pdev);
9feeb014 873 struct nvec_msg *msg;
32890b98
MD
874
875 dev_dbg(nvec->dev, "suspending\n");
9feeb014
MD
876
877 /* keep these sync or you'll break suspend */
878 msg = nvec_write_sync(nvec, EC_DISABLE_EVENT_REPORTING, 3);
879 nvec_msg_free(nvec, msg);
880 msg = nvec_write_sync(nvec, "\x04\x02", 2);
881 nvec_msg_free(nvec, msg);
882
ac810759 883 nvec_disable_i2c_slave(nvec);
32890b98
MD
884
885 return 0;
886}
887
ebefae28 888static int nvec_resume(struct device *dev)
162c7d8c 889{
ebefae28 890 struct platform_device *pdev = to_platform_device(dev);
32890b98
MD
891 struct nvec_chip *nvec = platform_get_drvdata(pdev);
892
893 dev_dbg(nvec->dev, "resuming\n");
f686e9af 894 tegra_init_i2c_slave(nvec);
32890b98
MD
895 nvec_write_async(nvec, EC_ENABLE_EVENT_REPORTING, 3);
896
897 return 0;
898}
32890b98
MD
899#endif
900
ebefae28
MD
901static const SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume);
902
7990b0d7
MD
903/* Match table for of_platform binding */
904static const struct of_device_id nvidia_nvec_of_match[] __devinitconst = {
905 { .compatible = "nvidia,nvec", },
906 {},
907};
908MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match);
909
162c7d8c
MD
910static struct platform_driver nvec_device_driver = {
911 .probe = tegra_nvec_probe,
912 .remove = __devexit_p(tegra_nvec_remove),
162c7d8c 913 .driver = {
32890b98
MD
914 .name = "nvec",
915 .owner = THIS_MODULE,
ebefae28 916 .pm = &nvec_pm_ops,
7990b0d7 917 .of_match_table = nvidia_nvec_of_match,
32890b98
MD
918 }
919};
920
9891b1ce 921module_platform_driver(nvec_device_driver);
162c7d8c 922
32890b98 923MODULE_ALIAS("platform:nvec");
162c7d8c
MD
924MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface");
925MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>");
926MODULE_LICENSE("GPL");