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1 | /***********************license start*************** |
2 | * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights | |
3 | * reserved. | |
4 | * | |
5 | * | |
6 | * Redistribution and use in source and binary forms, with or without | |
7 | * modification, are permitted provided that the following conditions are | |
8 | * met: | |
9 | * | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * | |
13 | * * Redistributions in binary form must reproduce the above | |
14 | * copyright notice, this list of conditions and the following | |
15 | * disclaimer in the documentation and/or other materials provided | |
16 | * with the distribution. | |
17 | ||
18 | * * Neither the name of Cavium Networks nor the names of | |
19 | * its contributors may be used to endorse or promote products | |
20 | * derived from this software without specific prior written | |
21 | * permission. | |
22 | ||
b6bcaa48 AK |
23 | * This Software, including technical data, may be subject to U.S. export |
24 | * control laws, including the U.S. Export Administration Act and its associated | |
b164935b AK |
25 | * regulations, and may be subject to export or import regulations in other |
26 | * countries. | |
27 | ||
28 | * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" | |
b6bcaa48 | 29 | * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR |
b164935b | 30 | * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO |
b6bcaa48 AK |
31 | * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION |
32 | * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM | |
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33 | * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, |
34 | * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF | |
35 | * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR | |
36 | * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR | |
37 | * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. | |
38 | ***********************license end**************************************/ | |
39 | ||
40 | ||
41 | /** | |
42 | * cvmx-usbnx-defs.h | |
43 | * | |
44 | * Configuration and status register (CSR) type definitions for | |
45 | * Octeon usbnx. | |
46 | * | |
b164935b AK |
47 | */ |
48 | #ifndef __CVMX_USBNX_TYPEDEFS_H__ | |
49 | #define __CVMX_USBNX_TYPEDEFS_H__ | |
50 | ||
97d63efa AK |
51 | #define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull) |
52 | #define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull) | |
53 | ||
54 | #define CVMX_USBNXREG1(reg, bid) \ | |
55 | (CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid)) | |
56 | #define CVMX_USBNXREG2(reg, bid) \ | |
57 | (CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid)) | |
58 | ||
59 | #define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid) | |
60 | #define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid) | |
61 | #define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid) | |
62 | #define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid) | |
b164935b | 63 | |
b164935b AK |
64 | /** |
65 | * cvmx_usbn#_clk_ctl | |
66 | * | |
67 | * USBN_CLK_CTL = USBN's Clock Control | |
68 | * | |
47d8994b AK |
69 | * This register is used to control the frequency of the hclk and the |
70 | * hreset and phy_rst signals. | |
b164935b | 71 | */ |
7f4a470c | 72 | union cvmx_usbnx_clk_ctl { |
b164935b | 73 | uint64_t u64; |
d49e4112 AK |
74 | /** |
75 | * struct cvmx_usbnx_clk_ctl_s | |
76 | * @divide2: The 'hclk' used by the USB subsystem is derived | |
77 | * from the eclk. | |
78 | * Also see the field DIVIDE. DIVIDE2<1> must currently | |
79 | * be zero because it is not implemented, so the maximum | |
80 | * ratio of eclk/hclk is currently 16. | |
81 | * The actual divide number for hclk is: | |
82 | * (DIVIDE2 + 1) * (DIVIDE + 1) | |
83 | * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to | |
84 | * generate the hclk in the USB Subsystem is held | |
85 | * in reset. This bit must be set to '0' before | |
86 | * changing the value os DIVIDE in this register. | |
87 | * The reset to the HCLK_DIVIDERis also asserted | |
88 | * when core reset is asserted. | |
89 | * @p_x_on: Force USB-PHY on during suspend. | |
90 | * '1' USB-PHY XO block is powered-down during | |
91 | * suspend. | |
92 | * '0' USB-PHY XO block is powered-up during | |
93 | * suspend. | |
94 | * The value of this field must be set while POR is | |
95 | * active. | |
7d7bc26b AK |
96 | * @p_rtype: PHY reference clock type |
97 | * On CN50XX/CN52XX/CN56XX the values are: | |
98 | * '0' The USB-PHY uses a 12MHz crystal as a clock source | |
99 | * at the USB_XO and USB_XI pins. | |
100 | * '1' Reserved. | |
101 | * '2' The USB_PHY uses 12/24/48MHz 2.5V board clock at the | |
102 | * USB_XO pin. USB_XI should be tied to ground in this | |
103 | * case. | |
104 | * '3' Reserved. | |
105 | * On CN3xxx bits 14 and 15 are p_xenbn and p_rclk and values are: | |
106 | * '0' Reserved. | |
107 | * '1' Reserved. | |
108 | * '2' The PHY PLL uses the XO block output as a reference. | |
109 | * The XO block uses an external clock supplied on the | |
110 | * XO pin. USB_XI should be tied to ground for this | |
111 | * usage. | |
112 | * '3' The XO block uses the clock from a crystal. | |
d49e4112 AK |
113 | * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to |
114 | * remain powered in Suspend Mode. | |
115 | * '1' The USB-PHY XO Bias, Bandgap and PLL are | |
116 | * powered down in suspend mode. | |
117 | * The value of this field must be set while POR is | |
118 | * active. | |
119 | * @p_c_sel: Phy clock speed select. | |
120 | * Selects the reference clock / crystal frequency. | |
121 | * '11': Reserved | |
122 | * '10': 48 MHz (reserved when a crystal is used) | |
123 | * '01': 24 MHz (reserved when a crystal is used) | |
124 | * '00': 12 MHz | |
125 | * The value of this field must be set while POR is | |
126 | * active. | |
127 | * NOTE: if a crystal is used as a reference clock, | |
128 | * this field must be set to 12 MHz. | |
129 | * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV. | |
130 | * @sd_mode: Scaledown mode for the USBC. Control timing events | |
131 | * in the USBC, for normal operation this must be '0'. | |
132 | * @s_bist: Starts bist on the hclk memories, during the '0' | |
133 | * to '1' transition. | |
134 | * @por: Power On Reset for the PHY. | |
135 | * Resets all the PHYS registers and state machines. | |
136 | * @enable: When '1' allows the generation of the hclk. When | |
137 | * '0' the hclk will not be generated. SEE DIVIDE | |
138 | * field of this register. | |
139 | * @prst: When this field is '0' the reset associated with | |
140 | * the phy_clk functionality in the USB Subsystem is | |
141 | * help in reset. This bit should not be set to '1' | |
142 | * until the time it takes 6 clocks (hclk or phy_clk, | |
143 | * whichever is slower) has passed. Under normal | |
144 | * operation once this bit is set to '1' it should not | |
145 | * be set to '0'. | |
146 | * @hrst: When this field is '0' the reset associated with | |
147 | * the hclk functioanlity in the USB Subsystem is | |
148 | * held in reset.This bit should not be set to '1' | |
149 | * until 12ms after phy_clk is stable. Under normal | |
150 | * operation, once this bit is set to '1' it should | |
151 | * not be set to '0'. | |
152 | * @divide: The frequency of 'hclk' used by the USB subsystem | |
153 | * is the eclk frequency divided by the value of | |
154 | * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field | |
155 | * DIVIDE2 of this register. | |
156 | * The hclk frequency should be less than 125Mhz. | |
157 | * After writing a value to this field the SW should | |
158 | * read the field for the value written. | |
159 | * The ENABLE field of this register should not be set | |
160 | * until AFTER this field is set and then read. | |
161 | */ | |
7f4a470c | 162 | struct cvmx_usbnx_clk_ctl_s { |
39e873bb | 163 | uint64_t reserved_20_63 : 44; |
d49e4112 AK |
164 | uint64_t divide2 : 2; |
165 | uint64_t hclk_rst : 1; | |
166 | uint64_t p_x_on : 1; | |
34b70b9e | 167 | uint64_t p_rtype : 2; |
d49e4112 AK |
168 | uint64_t p_com_on : 1; |
169 | uint64_t p_c_sel : 2; | |
170 | uint64_t cdiv_byp : 1; | |
171 | uint64_t sd_mode : 2; | |
172 | uint64_t s_bist : 1; | |
173 | uint64_t por : 1; | |
174 | uint64_t enable : 1; | |
175 | uint64_t prst : 1; | |
176 | uint64_t hrst : 1; | |
177 | uint64_t divide : 3; | |
b164935b | 178 | } s; |
b164935b | 179 | }; |
b164935b | 180 | |
b164935b AK |
181 | /** |
182 | * cvmx_usbn#_usbp_ctl_status | |
183 | * | |
184 | * USBN_USBP_CTL_STATUS = USBP Control And Status Register | |
185 | * | |
186 | * Contains general control and status information for the USBN block. | |
187 | */ | |
7f4a470c | 188 | union cvmx_usbnx_usbp_ctl_status { |
b164935b | 189 | uint64_t u64; |
d49e4112 AK |
190 | /** |
191 | * struct cvmx_usbnx_usbp_ctl_status_s | |
192 | * @txrisetune: HS Transmitter Rise/Fall Time Adjustment | |
193 | * @txvreftune: HS DC Voltage Level Adjustment | |
194 | * @txfslstune: FS/LS Source Impedence Adjustment | |
195 | * @txhsxvtune: Transmitter High-Speed Crossover Adjustment | |
196 | * @sqrxtune: Squelch Threshold Adjustment | |
197 | * @compdistune: Disconnect Threshold Adjustment | |
198 | * @otgtune: VBUS Valid Threshold Adjustment | |
199 | * @otgdisable: OTG Block Disable | |
200 | * @portreset: Per_Port Reset | |
201 | * @drvvbus: Drive VBUS | |
202 | * @lsbist: Low-Speed BIST Enable. | |
203 | * @fsbist: Full-Speed BIST Enable. | |
204 | * @hsbist: High-Speed BIST Enable. | |
205 | * @bist_done: PHY Bist Done. | |
206 | * Asserted at the end of the PHY BIST sequence. | |
207 | * @bist_err: PHY Bist Error. | |
208 | * Indicates an internal error was detected during | |
209 | * the BIST sequence. | |
210 | * @tdata_out: PHY Test Data Out. | |
211 | * Presents either internaly generated signals or | |
212 | * test register contents, based upon the value of | |
213 | * test_data_out_sel. | |
214 | * @siddq: Drives the USBP (USB-PHY) SIDDQ input. | |
215 | * Normally should be set to zero. | |
216 | * When customers have no intent to use USB PHY | |
217 | * interface, they should: | |
218 | * - still provide 3.3V to USB_VDD33, and | |
219 | * - tie USB_REXT to 3.3V supply, and | |
220 | * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 | |
221 | * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable | |
222 | * @dma_bmode: When set to 1 the L2C DMA address will be updated | |
223 | * with byte-counts between packets. When set to 0 | |
224 | * the L2C DMA address is incremented to the next | |
225 | * 4-byte aligned address after adding byte-count. | |
226 | * @usbc_end: Bigendian input to the USB Core. This should be | |
227 | * set to '0' for operation. | |
228 | * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP. | |
229 | * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP. | |
230 | * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY. | |
231 | * This signal enables the pull-down resistance on | |
232 | * the D+ line. '1' pull down-resistance is connected | |
233 | * to D+/ '0' pull down resistance is not connected | |
234 | * to D+. When an A/B device is acting as a host | |
235 | * (downstream-facing port), dp_pulldown and | |
236 | * dm_pulldown are enabled. This must not toggle | |
237 | * during normal opeartion. | |
238 | * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY. | |
239 | * This signal enables the pull-down resistance on | |
240 | * the D- line. '1' pull down-resistance is connected | |
241 | * to D-. '0' pull down resistance is not connected | |
242 | * to D-. When an A/B device is acting as a host | |
243 | * (downstream-facing port), dp_pulldown and | |
244 | * dm_pulldown are enabled. This must not toggle | |
245 | * during normal opeartion. | |
246 | * @hst_mode: When '0' the USB is acting as HOST, when '1' | |
247 | * USB is acting as device. This field needs to be | |
248 | * set while the USB is in reset. | |
249 | * @tuning: Transmitter Tuning for High-Speed Operation. | |
250 | * Tunes the current supply and rise/fall output | |
251 | * times for high-speed operation. | |
252 | * [20:19] == 11: Current supply increased | |
253 | * approximately 9% | |
254 | * [20:19] == 10: Current supply increased | |
255 | * approximately 4.5% | |
256 | * [20:19] == 01: Design default. | |
257 | * [20:19] == 00: Current supply decreased | |
258 | * approximately 4.5% | |
259 | * [22:21] == 11: Rise and fall times are increased. | |
260 | * [22:21] == 10: Design default. | |
261 | * [22:21] == 01: Rise and fall times are decreased. | |
262 | * [22:21] == 00: Rise and fall times are decreased | |
263 | * further as compared to the 01 setting. | |
264 | * @tx_bs_enh: Transmit Bit Stuffing on [15:8]. | |
265 | * Enables or disables bit stuffing on data[15:8] | |
266 | * when bit-stuffing is enabled. | |
267 | * @tx_bs_en: Transmit Bit Stuffing on [7:0]. | |
268 | * Enables or disables bit stuffing on data[7:0] | |
269 | * when bit-stuffing is enabled. | |
270 | * @loop_enb: PHY Loopback Test Enable. | |
271 | * '1': During data transmission the receive is | |
272 | * enabled. | |
273 | * '0': During data transmission the receive is | |
274 | * disabled. | |
275 | * Must be '0' for normal operation. | |
276 | * @vtest_enb: Analog Test Pin Enable. | |
277 | * '1' The PHY's analog_test pin is enabled for the | |
278 | * input and output of applicable analog test signals. | |
279 | * '0' THe analog_test pin is disabled. | |
280 | * @bist_enb: Built-In Self Test Enable. | |
281 | * Used to activate BIST in the PHY. | |
282 | * @tdata_sel: Test Data Out Select. | |
283 | * '1' test_data_out[3:0] (PHY) register contents | |
284 | * are output. '0' internaly generated signals are | |
285 | * output. | |
286 | * @taddr_in: Mode Address for Test Interface. | |
287 | * Specifies the register address for writing to or | |
288 | * reading from the PHY test interface register. | |
289 | * @tdata_in: Internal Testing Register Input Data and Select | |
290 | * This is a test bus. Data is present on [3:0], | |
291 | * and its corresponding select (enable) is present | |
292 | * on bits [7:4]. | |
293 | * @ate_reset: Reset input from automatic test equipment. | |
294 | * This is a test signal. When the USB Core is | |
295 | * powered up (not in Susned Mode), an automatic | |
296 | * tester can use this to disable phy_clock and | |
297 | * free_clk, then re-eanable them with an aligned | |
298 | * phase. | |
299 | * '1': The phy_clk and free_clk outputs are | |
300 | * disabled. "0": The phy_clock and free_clk outputs | |
301 | * are available within a specific period after the | |
302 | * de-assertion. | |
303 | */ | |
7f4a470c | 304 | struct cvmx_usbnx_usbp_ctl_status_s { |
d49e4112 AK |
305 | uint64_t txrisetune : 1; |
306 | uint64_t txvreftune : 4; | |
307 | uint64_t txfslstune : 4; | |
308 | uint64_t txhsxvtune : 2; | |
309 | uint64_t sqrxtune : 3; | |
310 | uint64_t compdistune : 3; | |
311 | uint64_t otgtune : 3; | |
312 | uint64_t otgdisable : 1; | |
313 | uint64_t portreset : 1; | |
314 | uint64_t drvvbus : 1; | |
315 | uint64_t lsbist : 1; | |
316 | uint64_t fsbist : 1; | |
317 | uint64_t hsbist : 1; | |
318 | uint64_t bist_done : 1; | |
319 | uint64_t bist_err : 1; | |
320 | uint64_t tdata_out : 4; | |
321 | uint64_t siddq : 1; | |
322 | uint64_t txpreemphasistune : 1; | |
323 | uint64_t dma_bmode : 1; | |
324 | uint64_t usbc_end : 1; | |
325 | uint64_t usbp_bist : 1; | |
326 | uint64_t tclk : 1; | |
327 | uint64_t dp_pulld : 1; | |
328 | uint64_t dm_pulld : 1; | |
329 | uint64_t hst_mode : 1; | |
330 | uint64_t tuning : 4; | |
331 | uint64_t tx_bs_enh : 1; | |
332 | uint64_t tx_bs_en : 1; | |
333 | uint64_t loop_enb : 1; | |
334 | uint64_t vtest_enb : 1; | |
335 | uint64_t bist_enb : 1; | |
336 | uint64_t tdata_sel : 1; | |
337 | uint64_t taddr_in : 4; | |
338 | uint64_t tdata_in : 8; | |
339 | uint64_t ate_reset : 1; | |
b164935b | 340 | } s; |
b164935b | 341 | }; |
b164935b AK |
342 | |
343 | #endif |