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IB/hfi1: Ignore link downgrade with 0 lanes
[mirror_ubuntu-jammy-kernel.git] / drivers / staging / rdma / hfi1 / chip.c
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77241056 1/*
05d6ac1d 2 * Copyright(c) 2015, 2016 Intel Corporation.
77241056
MM		 3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
77241056
MM		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
77241056
MM		 20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48/*
49 * This file contains all of the code that is specific to the HFI chip
50 */
51
52#include <linux/pci.h>
53#include <linux/delay.h>
54#include <linux/interrupt.h>
55#include <linux/module.h>
56
57#include "hfi.h"
58#include "trace.h"
59#include "mad.h"
60#include "pio.h"
61#include "sdma.h"
62#include "eprom.h"
5d9157aa 63#include "efivar.h"
8ebd4cf1 64#include "platform.h"
affa48de 65#include "aspm.h"
77241056
MM		 66
67#define NUM_IB_PORTS 1
68
69uint kdeth_qp;
70module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO);
71MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix");
72
73uint num_vls = HFI1_MAX_VLS_SUPPORTED;
74module_param(num_vls, uint, S_IRUGO);
75MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
76
77/*
78 * Default time to aggregate two 10K packets from the idle state
79 * (timer not running). The timer starts at the end of the first packet,
80 * so only the time for one 10K packet and header plus a bit extra is needed.
81 * 10 * 1024 + 64 header byte = 10304 byte
82 * 10304 byte / 12.5 GB/s = 824.32ns
83 */
84uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
85module_param(rcv_intr_timeout, uint, S_IRUGO);
86MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
87
88uint rcv_intr_count = 16; /* same as qib */
89module_param(rcv_intr_count, uint, S_IRUGO);
90MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
91
92ushort link_crc_mask = SUPPORTED_CRCS;
93module_param(link_crc_mask, ushort, S_IRUGO);
94MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
95
96uint loopback;
97module_param_named(loopback, loopback, uint, S_IRUGO);
98MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
99
100/* Other driver tunables */
101uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
102static ushort crc_14b_sideband = 1;
103static uint use_flr = 1;
104uint quick_linkup; /* skip LNI */
105
106struct flag_table {
107 u64 flag; /* the flag */
108 char *str; /* description string */
109 u16 extra; /* extra information */
110 u16 unused0;
111 u32 unused1;
112};
113
114/* str must be a string constant */
115#define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
116#define FLAG_ENTRY0(str, flag) {flag, str, 0}
117
118/* Send Error Consequences */
119#define SEC_WRITE_DROPPED 0x1
120#define SEC_PACKET_DROPPED 0x2
121#define SEC_SC_HALTED 0x4 /* per-context only */
122#define SEC_SPC_FREEZE 0x8 /* per-HFI only */
123
77241056 124#define MIN_KERNEL_KCTXTS 2
82c2611d 125#define FIRST_KERNEL_KCTXT 1
372cc85a
DL		 126/* sizes for both the QP and RSM map tables */
127#define NUM_MAP_ENTRIES 256
77241056
MM		 128#define NUM_MAP_REGS 32
129
130/* Bit offset into the GUID which carries HFI id information */
131#define GUID_HFI_INDEX_SHIFT 39
132
133/* extract the emulation revision */
134#define emulator_rev(dd) ((dd)->irev >> 8)
135/* parallel and serial emulation versions are 3 and 4 respectively */
136#define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
137#define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
138
139/* RSM fields */
140
141/* packet type */
142#define IB_PACKET_TYPE 2ull
143#define QW_SHIFT 6ull
144/* QPN[7..1] */
145#define QPN_WIDTH 7ull
146
147/* LRH.BTH: QW 0, OFFSET 48 - for match */
148#define LRH_BTH_QW 0ull
149#define LRH_BTH_BIT_OFFSET 48ull
150#define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
151#define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
152#define LRH_BTH_SELECT
153#define LRH_BTH_MASK 3ull
154#define LRH_BTH_VALUE 2ull
155
156/* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
157#define LRH_SC_QW 0ull
158#define LRH_SC_BIT_OFFSET 56ull
159#define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
160#define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
161#define LRH_SC_MASK 128ull
162#define LRH_SC_VALUE 0ull
163
164/* SC[n..0] QW 0, OFFSET 60 - for select */
165#define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
166
167/* QPN[m+n:1] QW 1, OFFSET 1 */
168#define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
169
170/* defines to build power on SC2VL table */
171#define SC2VL_VAL( \
172 num, \
173 sc0, sc0val, \
174 sc1, sc1val, \
175 sc2, sc2val, \
176 sc3, sc3val, \
177 sc4, sc4val, \
178 sc5, sc5val, \
179 sc6, sc6val, \
180 sc7, sc7val) \
181( \
182 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
183 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
184 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
185 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
186 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
187 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
188 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
189 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
190)
191
192#define DC_SC_VL_VAL( \
193 range, \
194 e0, e0val, \
195 e1, e1val, \
196 e2, e2val, \
197 e3, e3val, \
198 e4, e4val, \
199 e5, e5val, \
200 e6, e6val, \
201 e7, e7val, \
202 e8, e8val, \
203 e9, e9val, \
204 e10, e10val, \
205 e11, e11val, \
206 e12, e12val, \
207 e13, e13val, \
208 e14, e14val, \
209 e15, e15val) \
210( \
211 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
212 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
213 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
214 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
215 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
216 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
217 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
218 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
219 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
220 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
221 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
222 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
223 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
224 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
225 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
226 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
227)
228
229/* all CceStatus sub-block freeze bits */
230#define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
231 | CCE_STATUS_RXE_FROZE_SMASK \
232 | CCE_STATUS_TXE_FROZE_SMASK \
233 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
234/* all CceStatus sub-block TXE pause bits */
235#define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
236 | CCE_STATUS_TXE_PAUSED_SMASK \
237 | CCE_STATUS_SDMA_PAUSED_SMASK)
238/* all CceStatus sub-block RXE pause bits */
239#define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
240
241/*
242 * CCE Error flags.
243 */
244static struct flag_table cce_err_status_flags[] = {
245/* 0*/ FLAG_ENTRY0("CceCsrParityErr",
246 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
247/* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr",
248 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
249/* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr",
250 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
251/* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
252 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
253/* 4*/ FLAG_ENTRY0("CceTrgtAccessErr",
254 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
255/* 5*/ FLAG_ENTRY0("CceRspdDataParityErr",
256 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
257/* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
258 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
259/* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr",
260 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
261/* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
262 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
263/* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
264 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
265/*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
266 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
267/*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
268 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
269/*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
270 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
271/*13*/ FLAG_ENTRY0("PcicRetryMemCorErr",
272 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
273/*14*/ FLAG_ENTRY0("PcicRetryMemCorErr",
274 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
275/*15*/ FLAG_ENTRY0("PcicPostHdQCorErr",
276 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
277/*16*/ FLAG_ENTRY0("PcicPostHdQCorErr",
278 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
279/*17*/ FLAG_ENTRY0("PcicPostHdQCorErr",
280 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
281/*18*/ FLAG_ENTRY0("PcicCplDatQCorErr",
282 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
283/*19*/ FLAG_ENTRY0("PcicNPostHQParityErr",
284 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
285/*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr",
286 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
287/*21*/ FLAG_ENTRY0("PcicRetryMemUncErr",
288 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
289/*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr",
290 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
291/*23*/ FLAG_ENTRY0("PcicPostHdQUncErr",
292 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
293/*24*/ FLAG_ENTRY0("PcicPostDatQUncErr",
294 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
295/*25*/ FLAG_ENTRY0("PcicCplHdQUncErr",
296 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
297/*26*/ FLAG_ENTRY0("PcicCplDatQUncErr",
298 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
299/*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr",
300 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
301/*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr",
302 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
303/*29*/ FLAG_ENTRY0("PcicReceiveParityErr",
304 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
305/*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr",
306 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
307/*31*/ FLAG_ENTRY0("LATriggered",
308 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
309/*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr",
310 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
311/*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr",
312 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
313/*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
314 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
315/*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
316 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
317/*36*/ FLAG_ENTRY0("CceMsixTableCorErr",
318 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
319/*37*/ FLAG_ENTRY0("CceMsixTableUncErr",
320 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
321/*38*/ FLAG_ENTRY0("CceIntMapCorErr",
322 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
323/*39*/ FLAG_ENTRY0("CceIntMapUncErr",
324 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
325/*40*/ FLAG_ENTRY0("CceMsixCsrParityErr",
326 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
327/*41-63 reserved*/
328};
329
330/*
331 * Misc Error flags
332 */
333#define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
334static struct flag_table misc_err_status_flags[] = {
335/* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
336/* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
337/* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
338/* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
339/* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
340/* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
341/* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
342/* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
343/* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
344/* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
345/*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
346/*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
347/*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
348};
349
350/*
351 * TXE PIO Error flags and consequences
352 */
353static struct flag_table pio_err_status_flags[] = {
354/* 0*/ FLAG_ENTRY("PioWriteBadCtxt",
355 SEC_WRITE_DROPPED,
356 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
357/* 1*/ FLAG_ENTRY("PioWriteAddrParity",
358 SEC_SPC_FREEZE,
359 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
360/* 2*/ FLAG_ENTRY("PioCsrParity",
361 SEC_SPC_FREEZE,
362 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
363/* 3*/ FLAG_ENTRY("PioSbMemFifo0",
364 SEC_SPC_FREEZE,
365 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
366/* 4*/ FLAG_ENTRY("PioSbMemFifo1",
367 SEC_SPC_FREEZE,
368 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
369/* 5*/ FLAG_ENTRY("PioPccFifoParity",
370 SEC_SPC_FREEZE,
371 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
372/* 6*/ FLAG_ENTRY("PioPecFifoParity",
373 SEC_SPC_FREEZE,
374 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
375/* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity",
376 SEC_SPC_FREEZE,
377 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
378/* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
379 SEC_SPC_FREEZE,
380 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
381/* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr",
382 SEC_SPC_FREEZE,
383 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
384/*10*/ FLAG_ENTRY("PioSmPktResetParity",
385 SEC_SPC_FREEZE,
386 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
387/*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc",
388 SEC_SPC_FREEZE,
389 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
390/*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc",
391 SEC_SPC_FREEZE,
392 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
393/*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor",
394 0,
395 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
396/*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor",
397 0,
398 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
399/*15*/ FLAG_ENTRY("PioCreditRetFifoParity",
400 SEC_SPC_FREEZE,
401 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
402/*16*/ FLAG_ENTRY("PioPpmcPblFifo",
403 SEC_SPC_FREEZE,
404 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
405/*17*/ FLAG_ENTRY("PioInitSmIn",
406 0,
407 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
408/*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm",
409 SEC_SPC_FREEZE,
410 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
411/*19*/ FLAG_ENTRY("PioHostAddrMemUnc",
412 SEC_SPC_FREEZE,
413 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
414/*20*/ FLAG_ENTRY("PioHostAddrMemCor",
415 0,
416 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
417/*21*/ FLAG_ENTRY("PioWriteDataParity",
418 SEC_SPC_FREEZE,
419 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
420/*22*/ FLAG_ENTRY("PioStateMachine",
421 SEC_SPC_FREEZE,
422 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
423/*23*/ FLAG_ENTRY("PioWriteQwValidParity",
8638b77f 424 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 425 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
426/*24*/ FLAG_ENTRY("PioBlockQwCountParity",
8638b77f 427 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 428 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
429/*25*/ FLAG_ENTRY("PioVlfVlLenParity",
430 SEC_SPC_FREEZE,
431 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
432/*26*/ FLAG_ENTRY("PioVlfSopParity",
433 SEC_SPC_FREEZE,
434 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
435/*27*/ FLAG_ENTRY("PioVlFifoParity",
436 SEC_SPC_FREEZE,
437 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
438/*28*/ FLAG_ENTRY("PioPpmcBqcMemParity",
439 SEC_SPC_FREEZE,
440 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
441/*29*/ FLAG_ENTRY("PioPpmcSopLen",
442 SEC_SPC_FREEZE,
443 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
444/*30-31 reserved*/
445/*32*/ FLAG_ENTRY("PioCurrentFreeCntParity",
446 SEC_SPC_FREEZE,
447 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
448/*33*/ FLAG_ENTRY("PioLastReturnedCntParity",
449 SEC_SPC_FREEZE,
450 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
451/*34*/ FLAG_ENTRY("PioPccSopHeadParity",
452 SEC_SPC_FREEZE,
453 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
454/*35*/ FLAG_ENTRY("PioPecSopHeadParityErr",
455 SEC_SPC_FREEZE,
456 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
457/*36-63 reserved*/
458};
459
460/* TXE PIO errors that cause an SPC freeze */
461#define ALL_PIO_FREEZE_ERR \
462 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
463 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
464 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
465 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
466 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
467 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
468 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
469 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
470 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
471 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
472 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
473 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
474 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
475 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
476 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
477 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
478 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
479 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
480 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
481 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
482 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
483 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
484 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
485 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
486 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
487 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
488 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
489 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
490 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
491
492/*
493 * TXE SDMA Error flags
494 */
495static struct flag_table sdma_err_status_flags[] = {
496/* 0*/ FLAG_ENTRY0("SDmaRpyTagErr",
497 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
498/* 1*/ FLAG_ENTRY0("SDmaCsrParityErr",
499 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
500/* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
501 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
502/* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
503 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
504/*04-63 reserved*/
505};
506
507/* TXE SDMA errors that cause an SPC freeze */
508#define ALL_SDMA_FREEZE_ERR \
509 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
510 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
511 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
512
69a00b8e
MM		 513/* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
514#define PORT_DISCARD_EGRESS_ERRS \
515 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
516 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
517 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
518
77241056
MM		 519/*
520 * TXE Egress Error flags
521 */
522#define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
523static struct flag_table egress_err_status_flags[] = {
524/* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
525/* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
526/* 2 reserved */
527/* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
528 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
529/* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
530/* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
531/* 6 reserved */
532/* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr",
533 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
534/* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
535 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
536/* 9-10 reserved */
537/*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
538 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
539/*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
540/*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
541/*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
542/*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
543/*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
544 SEES(TX_SDMA0_DISALLOWED_PACKET)),
545/*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
546 SEES(TX_SDMA1_DISALLOWED_PACKET)),
547/*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
548 SEES(TX_SDMA2_DISALLOWED_PACKET)),
549/*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
550 SEES(TX_SDMA3_DISALLOWED_PACKET)),
551/*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
552 SEES(TX_SDMA4_DISALLOWED_PACKET)),
553/*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
554 SEES(TX_SDMA5_DISALLOWED_PACKET)),
555/*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
556 SEES(TX_SDMA6_DISALLOWED_PACKET)),
557/*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
558 SEES(TX_SDMA7_DISALLOWED_PACKET)),
559/*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
560 SEES(TX_SDMA8_DISALLOWED_PACKET)),
561/*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
562 SEES(TX_SDMA9_DISALLOWED_PACKET)),
563/*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
564 SEES(TX_SDMA10_DISALLOWED_PACKET)),
565/*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
566 SEES(TX_SDMA11_DISALLOWED_PACKET)),
567/*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
568 SEES(TX_SDMA12_DISALLOWED_PACKET)),
569/*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
570 SEES(TX_SDMA13_DISALLOWED_PACKET)),
571/*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
572 SEES(TX_SDMA14_DISALLOWED_PACKET)),
573/*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
574 SEES(TX_SDMA15_DISALLOWED_PACKET)),
575/*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
576 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
577/*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
578 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
579/*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
580 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
581/*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
582 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
583/*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
584 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
585/*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
586 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
587/*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
588 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
589/*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
590 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
591/*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
592 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
593/*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
594/*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
595/*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
596/*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
597/*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
598/*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
599/*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
600/*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
601/*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
602/*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
603/*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
604/*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
605/*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
606/*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
607/*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
608/*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
609/*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
610/*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
611/*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
612/*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
613/*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
614/*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
615 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
616/*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
617 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
618};
619
620/*
621 * TXE Egress Error Info flags
622 */
623#define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
624static struct flag_table egress_err_info_flags[] = {
625/* 0*/ FLAG_ENTRY0("Reserved", 0ull),
626/* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)),
627/* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
628/* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
629/* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
630/* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
631/* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
632/* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
633/* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)),
634/* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
635/*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)),
636/*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
637/*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
638/*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
639/*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
640/*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
641/*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
642/*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
643/*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
644/*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
645/*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
646/*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
647};
648
649/* TXE Egress errors that cause an SPC freeze */
650#define ALL_TXE_EGRESS_FREEZE_ERR \
651 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
652 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
653 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
654 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
655 | SEES(TX_LAUNCH_CSR_PARITY) \
656 | SEES(TX_SBRD_CTL_CSR_PARITY) \
657 | SEES(TX_CONFIG_PARITY) \
658 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
659 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
660 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
661 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
662 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
663 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
664 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
665 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
666 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
667 | SEES(TX_CREDIT_RETURN_PARITY))
668
669/*
670 * TXE Send error flags
671 */
672#define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
673static struct flag_table send_err_status_flags[] = {
2c5b521a 674/* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
77241056
MM		 675/* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
676/* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
677};
678
679/*
680 * TXE Send Context Error flags and consequences
681 */
682static struct flag_table sc_err_status_flags[] = {
683/* 0*/ FLAG_ENTRY("InconsistentSop",
684 SEC_PACKET_DROPPED | SEC_SC_HALTED,
685 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
686/* 1*/ FLAG_ENTRY("DisallowedPacket",
687 SEC_PACKET_DROPPED | SEC_SC_HALTED,
688 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
689/* 2*/ FLAG_ENTRY("WriteCrossesBoundary",
690 SEC_WRITE_DROPPED | SEC_SC_HALTED,
691 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
692/* 3*/ FLAG_ENTRY("WriteOverflow",
693 SEC_WRITE_DROPPED | SEC_SC_HALTED,
694 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
695/* 4*/ FLAG_ENTRY("WriteOutOfBounds",
696 SEC_WRITE_DROPPED | SEC_SC_HALTED,
697 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
698/* 5-63 reserved*/
699};
700
701/*
702 * RXE Receive Error flags
703 */
704#define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
705static struct flag_table rxe_err_status_flags[] = {
706/* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
707/* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
708/* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
709/* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
710/* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
711/* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
712/* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
713/* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
714/* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
715/* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
716/*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
717/*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
718/*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
719/*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
720/*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
721/*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
722/*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
723 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
724/*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
725/*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
726/*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr",
727 RXES(RBUF_BLOCK_LIST_READ_UNC)),
728/*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr",
729 RXES(RBUF_BLOCK_LIST_READ_COR)),
730/*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
731 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
732/*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
733 RXES(RBUF_CSR_QENT_CNT_PARITY)),
734/*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
735 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
736/*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
737 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
738/*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
739/*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
740/*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
741 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
742/*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
743/*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
744/*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
745/*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
746/*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
747/*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
748/*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
749/*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
750 RXES(RBUF_FL_INITDONE_PARITY)),
751/*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
752 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
753/*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
754/*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
755/*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
756/*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
757 RXES(LOOKUP_DES_PART1_UNC_COR)),
758/*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr",
759 RXES(LOOKUP_DES_PART2_PARITY)),
760/*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
761/*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
762/*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
763/*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
764/*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
765/*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
766/*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
767/*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
768/*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
769/*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
770/*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
771/*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
772/*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
773/*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
774/*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
775/*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
776/*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
777/*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
778/*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
779/*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
780/*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
781/*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
782};
783
784/* RXE errors that will trigger an SPC freeze */
785#define ALL_RXE_FREEZE_ERR \
786 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
787 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
788 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
789 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
790 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
791 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
792 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
793 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
794 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
795 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
796 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
797 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
798 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
799 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
800 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
801 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
802 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
803 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
804 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
805 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
806 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
807 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
808 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
809 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
810 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
811 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
812 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
813 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
814 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
815 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
816 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
817 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
818 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
819 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
820 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
821 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
822 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
823 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
824 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
825 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
826 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
827 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
828 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
829 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
830
831#define RXE_FREEZE_ABORT_MASK \
832 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
833 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
834 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
835
836/*
837 * DCC Error Flags
838 */
839#define DCCE(name) DCC_ERR_FLG_##name##_SMASK
840static struct flag_table dcc_err_flags[] = {
841 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
842 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
843 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
844 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
845 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
846 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
847 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
848 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
849 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
850 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
851 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
852 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
853 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
854 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
855 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
856 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
857 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
858 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
859 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
860 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
861 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
862 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
863 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
864 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
865 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
866 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
867 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
868 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
869 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
870 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
871 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
872 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
873 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
874 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
875 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
876 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
877 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
878 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
879 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
880 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
881 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
882 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
883 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
884 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
885 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
886 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
887};
888
889/*
890 * LCB error flags
891 */
892#define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
893static struct flag_table lcb_err_flags[] = {
894/* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
895/* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
896/* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
897/* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
898 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
899/* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
900/* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
901/* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
902/* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
903/* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
904/* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
905/*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
906/*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
907/*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
908/*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
909 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
910/*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
911/*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
912/*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
913/*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
914/*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
915/*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
916 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
917/*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
918/*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
919/*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
920/*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
921/*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
922/*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
923/*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
924 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
925/*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
926/*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
927 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
928/*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
929 LCBE(REDUNDANT_FLIT_PARITY_ERR))
930};
931
932/*
933 * DC8051 Error Flags
934 */
935#define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
936static struct flag_table dc8051_err_flags[] = {
937 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
938 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
939 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
940 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
941 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
942 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
943 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
944 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
945 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
17fb4f29 946 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
77241056
MM		 947 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
948};
949
950/*
951 * DC8051 Information Error flags
952 *
953 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
954 */
955static struct flag_table dc8051_info_err_flags[] = {
956 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED),
957 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME),
958 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET),
959 FLAG_ENTRY0("Serdes internal loopback failure",
17fb4f29 960 FAILED_SERDES_INTERNAL_LOOPBACK),
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MM		 961 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT),
962 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING),
963 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE),
964 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM),
965 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ),
966 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
967 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
8fefef12
JJ		 968 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT),
969 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT)
77241056
MM		 970};
971
972/*
973 * DC8051 Information Host Information flags
974 *
975 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
976 */
977static struct flag_table dc8051_info_host_msg_flags[] = {
978 FLAG_ENTRY0("Host request done", 0x0001),
979 FLAG_ENTRY0("BC SMA message", 0x0002),
980 FLAG_ENTRY0("BC PWR_MGM message", 0x0004),
981 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
982 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
983 FLAG_ENTRY0("External device config request", 0x0020),
984 FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
985 FLAG_ENTRY0("LinkUp achieved", 0x0080),
986 FLAG_ENTRY0("Link going down", 0x0100),
987};
988
77241056
MM		 989static u32 encoded_size(u32 size);
990static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
991static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
992static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
993 u8 *continuous);
994static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
995 u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
996static void read_vc_remote_link_width(struct hfi1_devdata *dd,
997 u8 *remote_tx_rate, u16 *link_widths);
998static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
999 u8 *flag_bits, u16 *link_widths);
1000static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1001 u8 *device_rev);
1002static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed);
1003static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1004static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1005 u8 *tx_polarity_inversion,
1006 u8 *rx_polarity_inversion, u8 *max_rate);
1007static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1008 unsigned int context, u64 err_status);
1009static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1010static void handle_dcc_err(struct hfi1_devdata *dd,
1011 unsigned int context, u64 err_status);
1012static void handle_lcb_err(struct hfi1_devdata *dd,
1013 unsigned int context, u64 err_status);
1014static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1015static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1016static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1017static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1018static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1019static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1020static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1021static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1022static void set_partition_keys(struct hfi1_pportdata *);
1023static const char *link_state_name(u32 state);
1024static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1025 u32 state);
1026static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1027 u64 *out_data);
1028static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1029static int thermal_init(struct hfi1_devdata *dd);
1030
1031static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1032 int msecs);
1033static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
1034static void handle_temp_err(struct hfi1_devdata *);
1035static void dc_shutdown(struct hfi1_devdata *);
1036static void dc_start(struct hfi1_devdata *);
8f000f7f
DL		 1037static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
1038 unsigned int *np);
77241056
MM		 1039
1040/*
1041 * Error interrupt table entry. This is used as input to the interrupt
1042 * "clear down" routine used for all second tier error interrupt register.
1043 * Second tier interrupt registers have a single bit representing them
1044 * in the top-level CceIntStatus.
1045 */
1046struct err_reg_info {
1047 u32 status; /* status CSR offset */
1048 u32 clear; /* clear CSR offset */
1049 u32 mask; /* mask CSR offset */
1050 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1051 const char *desc;
1052};
1053
1054#define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1055#define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1056#define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1057
1058/*
1059 * Helpers for building HFI and DC error interrupt table entries. Different
1060 * helpers are needed because of inconsistent register names.
1061 */
1062#define EE(reg, handler, desc) \
1063 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1064 handler, desc }
1065#define DC_EE1(reg, handler, desc) \
1066 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1067#define DC_EE2(reg, handler, desc) \
1068 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1069
1070/*
1071 * Table of the "misc" grouping of error interrupts. Each entry refers to
1072 * another register containing more information.
1073 */
1074static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1075/* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"),
1076/* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"),
1077/* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"),
1078/* 3*/ { 0, 0, 0, NULL }, /* reserved */
1079/* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"),
1080/* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"),
1081/* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1082/* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr")
1083 /* the rest are reserved */
1084};
1085
1086/*
1087 * Index into the Various section of the interrupt sources
1088 * corresponding to the Critical Temperature interrupt.
1089 */
1090#define TCRIT_INT_SOURCE 4
1091
1092/*
1093 * SDMA error interrupt entry - refers to another register containing more
1094 * information.
1095 */
1096static const struct err_reg_info sdma_eng_err =
1097 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1098
1099static const struct err_reg_info various_err[NUM_VARIOUS] = {
1100/* 0*/ { 0, 0, 0, NULL }, /* PbcInt */
1101/* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */
1102/* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"),
1103/* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"),
1104/* 4*/ { 0, 0, 0, NULL }, /* TCritInt */
1105 /* rest are reserved */
1106};
1107
1108/*
1109 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1110 * register can not be derived from the MTU value because 10K is not
1111 * a power of 2. Therefore, we need a constant. Everything else can
1112 * be calculated.
1113 */
1114#define DCC_CFG_PORT_MTU_CAP_10240 7
1115
1116/*
1117 * Table of the DC grouping of error interrupts. Each entry refers to
1118 * another register containing more information.
1119 */
1120static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1121/* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"),
1122/* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"),
1123/* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"),
1124/* 3*/ /* dc_lbm_int - special, see is_dc_int() */
1125 /* the rest are reserved */
1126};
1127
1128struct cntr_entry {
1129 /*
1130 * counter name
1131 */
1132 char *name;
1133
1134 /*
1135 * csr to read for name (if applicable)
1136 */
1137 u64 csr;
1138
1139 /*
1140 * offset into dd or ppd to store the counter's value
1141 */
1142 int offset;
1143
1144 /*
1145 * flags
1146 */
1147 u8 flags;
1148
1149 /*
1150 * accessor for stat element, context either dd or ppd
1151 */
17fb4f29
JJ		 1152 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl,
1153 int mode, u64 data);
77241056
MM		 1154};
1155
1156#define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1157#define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1158
1159#define CNTR_ELEM(name, csr, offset, flags, accessor) \
1160{ \
1161 name, \
1162 csr, \
1163 offset, \
1164 flags, \
1165 accessor \
1166}
1167
1168/* 32bit RXE */
1169#define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1170CNTR_ELEM(#name, \
1171 (counter * 8 + RCV_COUNTER_ARRAY32), \
1172 0, flags | CNTR_32BIT, \
1173 port_access_u32_csr)
1174
1175#define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1176CNTR_ELEM(#name, \
1177 (counter * 8 + RCV_COUNTER_ARRAY32), \
1178 0, flags | CNTR_32BIT, \
1179 dev_access_u32_csr)
1180
1181/* 64bit RXE */
1182#define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1183CNTR_ELEM(#name, \
1184 (counter * 8 + RCV_COUNTER_ARRAY64), \
1185 0, flags, \
1186 port_access_u64_csr)
1187
1188#define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1189CNTR_ELEM(#name, \
1190 (counter * 8 + RCV_COUNTER_ARRAY64), \
1191 0, flags, \
1192 dev_access_u64_csr)
1193
1194#define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1195#define OVR_ELM(ctx) \
1196CNTR_ELEM("RcvHdrOvr" #ctx, \
8638b77f 1197 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
77241056
MM		 1198 0, CNTR_NORMAL, port_access_u64_csr)
1199
1200/* 32bit TXE */
1201#define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1202CNTR_ELEM(#name, \
1203 (counter * 8 + SEND_COUNTER_ARRAY32), \
1204 0, flags | CNTR_32BIT, \
1205 port_access_u32_csr)
1206
1207/* 64bit TXE */
1208#define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1209CNTR_ELEM(#name, \
1210 (counter * 8 + SEND_COUNTER_ARRAY64), \
1211 0, flags, \
1212 port_access_u64_csr)
1213
1214# define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1215CNTR_ELEM(#name,\
1216 counter * 8 + SEND_COUNTER_ARRAY64, \
1217 0, \
1218 flags, \
1219 dev_access_u64_csr)
1220
1221/* CCE */
1222#define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1223CNTR_ELEM(#name, \
1224 (counter * 8 + CCE_COUNTER_ARRAY32), \
1225 0, flags | CNTR_32BIT, \
1226 dev_access_u32_csr)
1227
1228#define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1229CNTR_ELEM(#name, \
1230 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1231 0, flags | CNTR_32BIT, \
1232 dev_access_u32_csr)
1233
1234/* DC */
1235#define DC_PERF_CNTR(name, counter, flags) \
1236CNTR_ELEM(#name, \
1237 counter, \
1238 0, \
1239 flags, \
1240 dev_access_u64_csr)
1241
1242#define DC_PERF_CNTR_LCB(name, counter, flags) \
1243CNTR_ELEM(#name, \
1244 counter, \
1245 0, \
1246 flags, \
1247 dc_access_lcb_cntr)
1248
1249/* ibp counters */
1250#define SW_IBP_CNTR(name, cntr) \
1251CNTR_ELEM(#name, \
1252 0, \
1253 0, \
1254 CNTR_SYNTH, \
1255 access_ibp_##cntr)
1256
1257u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1258{
77241056 1259 if (dd->flags & HFI1_PRESENT) {
6d210eef 1260 return readq((void __iomem *)dd->kregbase + offset);
77241056
MM		 1261 }
1262 return -1;
1263}
1264
1265void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1266{
1267 if (dd->flags & HFI1_PRESENT)
1268 writeq(value, (void __iomem *)dd->kregbase + offset);
1269}
1270
1271void __iomem *get_csr_addr(
1272 struct hfi1_devdata *dd,
1273 u32 offset)
1274{
1275 return (void __iomem *)dd->kregbase + offset;
1276}
1277
1278static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1279 int mode, u64 value)
1280{
1281 u64 ret;
1282
77241056
MM		 1283 if (mode == CNTR_MODE_R) {
1284 ret = read_csr(dd, csr);
1285 } else if (mode == CNTR_MODE_W) {
1286 write_csr(dd, csr, value);
1287 ret = value;
1288 } else {
1289 dd_dev_err(dd, "Invalid cntr register access mode");
1290 return 0;
1291 }
1292
1293 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1294 return ret;
1295}
1296
1297/* Dev Access */
1298static u64 dev_access_u32_csr(const struct cntr_entry *entry,
17fb4f29 1299 void *context, int vl, int mode, u64 data)
77241056 1300{
a787bde8 1301 struct hfi1_devdata *dd = context;
a699c6c2 1302 u64 csr = entry->csr;
77241056 1303
a699c6c2
VM		 1304 if (entry->flags & CNTR_SDMA) {
1305 if (vl == CNTR_INVALID_VL)
1306 return 0;
1307 csr += 0x100 * vl;
1308 } else {
1309 if (vl != CNTR_INVALID_VL)
1310 return 0;
1311 }
1312 return read_write_csr(dd, csr, mode, data);
1313}
1314
1315static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1316 void *context, int idx, int mode, u64 data)
1317{
1318 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1319
1320 if (dd->per_sdma && idx < dd->num_sdma)
1321 return dd->per_sdma[idx].err_cnt;
1322 return 0;
1323}
1324
1325static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1326 void *context, int idx, int mode, u64 data)
1327{
1328 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1329
1330 if (dd->per_sdma && idx < dd->num_sdma)
1331 return dd->per_sdma[idx].sdma_int_cnt;
1332 return 0;
1333}
1334
1335static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1336 void *context, int idx, int mode, u64 data)
1337{
1338 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1339
1340 if (dd->per_sdma && idx < dd->num_sdma)
1341 return dd->per_sdma[idx].idle_int_cnt;
1342 return 0;
1343}
1344
1345static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1346 void *context, int idx, int mode,
1347 u64 data)
1348{
1349 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1350
1351 if (dd->per_sdma && idx < dd->num_sdma)
1352 return dd->per_sdma[idx].progress_int_cnt;
1353 return 0;
77241056
MM		 1354}
1355
1356static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
17fb4f29 1357 int vl, int mode, u64 data)
77241056 1358{
a787bde8 1359 struct hfi1_devdata *dd = context;
77241056
MM		 1360
1361 u64 val = 0;
1362 u64 csr = entry->csr;
1363
1364 if (entry->flags & CNTR_VL) {
1365 if (vl == CNTR_INVALID_VL)
1366 return 0;
1367 csr += 8 * vl;
1368 } else {
1369 if (vl != CNTR_INVALID_VL)
1370 return 0;
1371 }
1372
1373 val = read_write_csr(dd, csr, mode, data);
1374 return val;
1375}
1376
1377static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
17fb4f29 1378 int vl, int mode, u64 data)
77241056 1379{
a787bde8 1380 struct hfi1_devdata *dd = context;
77241056
MM		 1381 u32 csr = entry->csr;
1382 int ret = 0;
1383
1384 if (vl != CNTR_INVALID_VL)
1385 return 0;
1386 if (mode == CNTR_MODE_R)
1387 ret = read_lcb_csr(dd, csr, &data);
1388 else if (mode == CNTR_MODE_W)
1389 ret = write_lcb_csr(dd, csr, data);
1390
1391 if (ret) {
1392 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1393 return 0;
1394 }
1395
1396 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1397 return data;
1398}
1399
1400/* Port Access */
1401static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
17fb4f29 1402 int vl, int mode, u64 data)
77241056 1403{
a787bde8 1404 struct hfi1_pportdata *ppd = context;
77241056
MM		 1405
1406 if (vl != CNTR_INVALID_VL)
1407 return 0;
1408 return read_write_csr(ppd->dd, entry->csr, mode, data);
1409}
1410
1411static u64 port_access_u64_csr(const struct cntr_entry *entry,
17fb4f29 1412 void *context, int vl, int mode, u64 data)
77241056 1413{
a787bde8 1414 struct hfi1_pportdata *ppd = context;
77241056
MM		 1415 u64 val;
1416 u64 csr = entry->csr;
1417
1418 if (entry->flags & CNTR_VL) {
1419 if (vl == CNTR_INVALID_VL)
1420 return 0;
1421 csr += 8 * vl;
1422 } else {
1423 if (vl != CNTR_INVALID_VL)
1424 return 0;
1425 }
1426 val = read_write_csr(ppd->dd, csr, mode, data);
1427 return val;
1428}
1429
1430/* Software defined */
1431static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1432 u64 data)
1433{
1434 u64 ret;
1435
1436 if (mode == CNTR_MODE_R) {
1437 ret = *cntr;
1438 } else if (mode == CNTR_MODE_W) {
1439 *cntr = data;
1440 ret = data;
1441 } else {
1442 dd_dev_err(dd, "Invalid cntr sw access mode");
1443 return 0;
1444 }
1445
1446 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1447
1448 return ret;
1449}
1450
1451static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
17fb4f29 1452 int vl, int mode, u64 data)
77241056 1453{
a787bde8 1454 struct hfi1_pportdata *ppd = context;
77241056
MM		 1455
1456 if (vl != CNTR_INVALID_VL)
1457 return 0;
1458 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1459}
1460
1461static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
17fb4f29 1462 int vl, int mode, u64 data)
77241056 1463{
a787bde8 1464 struct hfi1_pportdata *ppd = context;
77241056
MM		 1465
1466 if (vl != CNTR_INVALID_VL)
1467 return 0;
1468 return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1469}
1470
6d014530
DL		 1471static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1472 void *context, int vl, int mode,
1473 u64 data)
1474{
1475 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1476
1477 if (vl != CNTR_INVALID_VL)
1478 return 0;
1479 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1480}
1481
77241056 1482static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
17fb4f29 1483 void *context, int vl, int mode, u64 data)
77241056 1484{
69a00b8e
MM		 1485 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1486 u64 zero = 0;
1487 u64 *counter;
77241056 1488
69a00b8e
MM		 1489 if (vl == CNTR_INVALID_VL)
1490 counter = &ppd->port_xmit_discards;
1491 else if (vl >= 0 && vl < C_VL_COUNT)
1492 counter = &ppd->port_xmit_discards_vl[vl];
1493 else
1494 counter = &zero;
77241056 1495
69a00b8e 1496 return read_write_sw(ppd->dd, counter, mode, data);
77241056
MM		 1497}
1498
1499static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
17fb4f29
JJ		 1500 void *context, int vl, int mode,
1501 u64 data)
77241056 1502{
a787bde8 1503 struct hfi1_pportdata *ppd = context;
77241056
MM		 1504
1505 if (vl != CNTR_INVALID_VL)
1506 return 0;
1507
1508 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1509 mode, data);
1510}
1511
1512static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
17fb4f29 1513 void *context, int vl, int mode, u64 data)
77241056 1514{
a787bde8 1515 struct hfi1_pportdata *ppd = context;
77241056
MM		 1516
1517 if (vl != CNTR_INVALID_VL)
1518 return 0;
1519
1520 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1521 mode, data);
1522}
1523
1524u64 get_all_cpu_total(u64 __percpu *cntr)
1525{
1526 int cpu;
1527 u64 counter = 0;
1528
1529 for_each_possible_cpu(cpu)
1530 counter += *per_cpu_ptr(cntr, cpu);
1531 return counter;
1532}
1533
1534static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1535 u64 __percpu *cntr,
1536 int vl, int mode, u64 data)
1537{
77241056
MM		 1538 u64 ret = 0;
1539
1540 if (vl != CNTR_INVALID_VL)
1541 return 0;
1542
1543 if (mode == CNTR_MODE_R) {
1544 ret = get_all_cpu_total(cntr) - *z_val;
1545 } else if (mode == CNTR_MODE_W) {
1546 /* A write can only zero the counter */
1547 if (data == 0)
1548 *z_val = get_all_cpu_total(cntr);
1549 else
1550 dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1551 } else {
1552 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1553 return 0;
1554 }
1555
1556 return ret;
1557}
1558
1559static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1560 void *context, int vl, int mode, u64 data)
1561{
a787bde8 1562 struct hfi1_devdata *dd = context;
77241056
MM		 1563
1564 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1565 mode, data);
1566}
1567
1568static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
17fb4f29 1569 void *context, int vl, int mode, u64 data)
77241056 1570{
a787bde8 1571 struct hfi1_devdata *dd = context;
77241056
MM		 1572
1573 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1574 mode, data);
1575}
1576
1577static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1578 void *context, int vl, int mode, u64 data)
1579{
a787bde8 1580 struct hfi1_devdata *dd = context;
77241056
MM		 1581
1582 return dd->verbs_dev.n_piowait;
1583}
1584
14553ca1
MM		 1585static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1586 void *context, int vl, int mode, u64 data)
1587{
1588 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1589
1590 return dd->verbs_dev.n_piodrain;
1591}
1592
77241056
MM		 1593static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1594 void *context, int vl, int mode, u64 data)
1595{
a787bde8 1596 struct hfi1_devdata *dd = context;
77241056
MM		 1597
1598 return dd->verbs_dev.n_txwait;
1599}
1600
1601static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1602 void *context, int vl, int mode, u64 data)
1603{
a787bde8 1604 struct hfi1_devdata *dd = context;
77241056
MM		 1605
1606 return dd->verbs_dev.n_kmem_wait;
1607}
1608
b421922e 1609static u64 access_sw_send_schedule(const struct cntr_entry *entry,
17fb4f29 1610 void *context, int vl, int mode, u64 data)
b421922e
DL		 1611{
1612 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1613
89abfc8d
VM		 1614 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1615 mode, data);
b421922e
DL		 1616}
1617
2c5b521a
JR		 1618/* Software counters for the error status bits within MISC_ERR_STATUS */
1619static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1620 void *context, int vl, int mode,
1621 u64 data)
1622{
1623 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1624
1625 return dd->misc_err_status_cnt[12];
1626}
1627
1628static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1629 void *context, int vl, int mode,
1630 u64 data)
1631{
1632 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1633
1634 return dd->misc_err_status_cnt[11];
1635}
1636
1637static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1638 void *context, int vl, int mode,
1639 u64 data)
1640{
1641 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1642
1643 return dd->misc_err_status_cnt[10];
1644}
1645
1646static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1647 void *context, int vl,
1648 int mode, u64 data)
1649{
1650 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1651
1652 return dd->misc_err_status_cnt[9];
1653}
1654
1655static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1656 void *context, int vl, int mode,
1657 u64 data)
1658{
1659 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1660
1661 return dd->misc_err_status_cnt[8];
1662}
1663
1664static u64 access_misc_efuse_read_bad_addr_err_cnt(
1665 const struct cntr_entry *entry,
1666 void *context, int vl, int mode, u64 data)
1667{
1668 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1669
1670 return dd->misc_err_status_cnt[7];
1671}
1672
1673static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1674 void *context, int vl,
1675 int mode, u64 data)
1676{
1677 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1678
1679 return dd->misc_err_status_cnt[6];
1680}
1681
1682static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1683 void *context, int vl, int mode,
1684 u64 data)
1685{
1686 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1687
1688 return dd->misc_err_status_cnt[5];
1689}
1690
1691static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1692 void *context, int vl, int mode,
1693 u64 data)
1694{
1695 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1696
1697 return dd->misc_err_status_cnt[4];
1698}
1699
1700static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1701 void *context, int vl,
1702 int mode, u64 data)
1703{
1704 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1705
1706 return dd->misc_err_status_cnt[3];
1707}
1708
1709static u64 access_misc_csr_write_bad_addr_err_cnt(
1710 const struct cntr_entry *entry,
1711 void *context, int vl, int mode, u64 data)
1712{
1713 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1714
1715 return dd->misc_err_status_cnt[2];
1716}
1717
1718static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1719 void *context, int vl,
1720 int mode, u64 data)
1721{
1722 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1723
1724 return dd->misc_err_status_cnt[1];
1725}
1726
1727static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1728 void *context, int vl, int mode,
1729 u64 data)
1730{
1731 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1732
1733 return dd->misc_err_status_cnt[0];
1734}
1735
1736/*
1737 * Software counter for the aggregate of
1738 * individual CceErrStatus counters
1739 */
1740static u64 access_sw_cce_err_status_aggregated_cnt(
1741 const struct cntr_entry *entry,
1742 void *context, int vl, int mode, u64 data)
1743{
1744 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1745
1746 return dd->sw_cce_err_status_aggregate;
1747}
1748
1749/*
1750 * Software counters corresponding to each of the
1751 * error status bits within CceErrStatus
1752 */
1753static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1754 void *context, int vl, int mode,
1755 u64 data)
1756{
1757 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1758
1759 return dd->cce_err_status_cnt[40];
1760}
1761
1762static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1763 void *context, int vl, int mode,
1764 u64 data)
1765{
1766 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1767
1768 return dd->cce_err_status_cnt[39];
1769}
1770
1771static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1772 void *context, int vl, int mode,
1773 u64 data)
1774{
1775 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1776
1777 return dd->cce_err_status_cnt[38];
1778}
1779
1780static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1781 void *context, int vl, int mode,
1782 u64 data)
1783{
1784 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1785
1786 return dd->cce_err_status_cnt[37];
1787}
1788
1789static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1790 void *context, int vl, int mode,
1791 u64 data)
1792{
1793 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1794
1795 return dd->cce_err_status_cnt[36];
1796}
1797
1798static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1799 const struct cntr_entry *entry,
1800 void *context, int vl, int mode, u64 data)
1801{
1802 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1803
1804 return dd->cce_err_status_cnt[35];
1805}
1806
1807static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1808 const struct cntr_entry *entry,
1809 void *context, int vl, int mode, u64 data)
1810{
1811 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1812
1813 return dd->cce_err_status_cnt[34];
1814}
1815
1816static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1817 void *context, int vl,
1818 int mode, u64 data)
1819{
1820 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1821
1822 return dd->cce_err_status_cnt[33];
1823}
1824
1825static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1826 void *context, int vl, int mode,
1827 u64 data)
1828{
1829 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1830
1831 return dd->cce_err_status_cnt[32];
1832}
1833
1834static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1835 void *context, int vl, int mode, u64 data)
1836{
1837 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1838
1839 return dd->cce_err_status_cnt[31];
1840}
1841
1842static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1843 void *context, int vl, int mode,
1844 u64 data)
1845{
1846 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1847
1848 return dd->cce_err_status_cnt[30];
1849}
1850
1851static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1852 void *context, int vl, int mode,
1853 u64 data)
1854{
1855 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1856
1857 return dd->cce_err_status_cnt[29];
1858}
1859
1860static u64 access_pcic_transmit_back_parity_err_cnt(
1861 const struct cntr_entry *entry,
1862 void *context, int vl, int mode, u64 data)
1863{
1864 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1865
1866 return dd->cce_err_status_cnt[28];
1867}
1868
1869static u64 access_pcic_transmit_front_parity_err_cnt(
1870 const struct cntr_entry *entry,
1871 void *context, int vl, int mode, u64 data)
1872{
1873 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1874
1875 return dd->cce_err_status_cnt[27];
1876}
1877
1878static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1879 void *context, int vl, int mode,
1880 u64 data)
1881{
1882 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1883
1884 return dd->cce_err_status_cnt[26];
1885}
1886
1887static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1888 void *context, int vl, int mode,
1889 u64 data)
1890{
1891 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1892
1893 return dd->cce_err_status_cnt[25];
1894}
1895
1896static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1897 void *context, int vl, int mode,
1898 u64 data)
1899{
1900 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1901
1902 return dd->cce_err_status_cnt[24];
1903}
1904
1905static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1906 void *context, int vl, int mode,
1907 u64 data)
1908{
1909 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1910
1911 return dd->cce_err_status_cnt[23];
1912}
1913
1914static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
1915 void *context, int vl,
1916 int mode, u64 data)
1917{
1918 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1919
1920 return dd->cce_err_status_cnt[22];
1921}
1922
1923static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
1924 void *context, int vl, int mode,
1925 u64 data)
1926{
1927 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1928
1929 return dd->cce_err_status_cnt[21];
1930}
1931
1932static u64 access_pcic_n_post_dat_q_parity_err_cnt(
1933 const struct cntr_entry *entry,
1934 void *context, int vl, int mode, u64 data)
1935{
1936 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1937
1938 return dd->cce_err_status_cnt[20];
1939}
1940
1941static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
1942 void *context, int vl,
1943 int mode, u64 data)
1944{
1945 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1946
1947 return dd->cce_err_status_cnt[19];
1948}
1949
1950static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1951 void *context, int vl, int mode,
1952 u64 data)
1953{
1954 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1955
1956 return dd->cce_err_status_cnt[18];
1957}
1958
1959static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1960 void *context, int vl, int mode,
1961 u64 data)
1962{
1963 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1964
1965 return dd->cce_err_status_cnt[17];
1966}
1967
1968static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1969 void *context, int vl, int mode,
1970 u64 data)
1971{
1972 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1973
1974 return dd->cce_err_status_cnt[16];
1975}
1976
1977static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1978 void *context, int vl, int mode,
1979 u64 data)
1980{
1981 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1982
1983 return dd->cce_err_status_cnt[15];
1984}
1985
1986static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
1987 void *context, int vl,
1988 int mode, u64 data)
1989{
1990 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1991
1992 return dd->cce_err_status_cnt[14];
1993}
1994
1995static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
1996 void *context, int vl, int mode,
1997 u64 data)
1998{
1999 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2000
2001 return dd->cce_err_status_cnt[13];
2002}
2003
2004static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2005 const struct cntr_entry *entry,
2006 void *context, int vl, int mode, u64 data)
2007{
2008 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2009
2010 return dd->cce_err_status_cnt[12];
2011}
2012
2013static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2014 const struct cntr_entry *entry,
2015 void *context, int vl, int mode, u64 data)
2016{
2017 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2018
2019 return dd->cce_err_status_cnt[11];
2020}
2021
2022static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2023 const struct cntr_entry *entry,
2024 void *context, int vl, int mode, u64 data)
2025{
2026 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2027
2028 return dd->cce_err_status_cnt[10];
2029}
2030
2031static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2032 const struct cntr_entry *entry,
2033 void *context, int vl, int mode, u64 data)
2034{
2035 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2036
2037 return dd->cce_err_status_cnt[9];
2038}
2039
2040static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2041 const struct cntr_entry *entry,
2042 void *context, int vl, int mode, u64 data)
2043{
2044 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2045
2046 return dd->cce_err_status_cnt[8];
2047}
2048
2049static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2050 void *context, int vl,
2051 int mode, u64 data)
2052{
2053 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2054
2055 return dd->cce_err_status_cnt[7];
2056}
2057
2058static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2059 const struct cntr_entry *entry,
2060 void *context, int vl, int mode, u64 data)
2061{
2062 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2063
2064 return dd->cce_err_status_cnt[6];
2065}
2066
2067static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2068 void *context, int vl, int mode,
2069 u64 data)
2070{
2071 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2072
2073 return dd->cce_err_status_cnt[5];
2074}
2075
2076static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2077 void *context, int vl, int mode,
2078 u64 data)
2079{
2080 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2081
2082 return dd->cce_err_status_cnt[4];
2083}
2084
2085static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2086 const struct cntr_entry *entry,
2087 void *context, int vl, int mode, u64 data)
2088{
2089 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2090
2091 return dd->cce_err_status_cnt[3];
2092}
2093
2094static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2095 void *context, int vl,
2096 int mode, u64 data)
2097{
2098 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2099
2100 return dd->cce_err_status_cnt[2];
2101}
2102
2103static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2104 void *context, int vl,
2105 int mode, u64 data)
2106{
2107 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2108
2109 return dd->cce_err_status_cnt[1];
2110}
2111
2112static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2113 void *context, int vl, int mode,
2114 u64 data)
2115{
2116 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2117
2118 return dd->cce_err_status_cnt[0];
2119}
2120
2121/*
2122 * Software counters corresponding to each of the
2123 * error status bits within RcvErrStatus
2124 */
2125static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2126 void *context, int vl, int mode,
2127 u64 data)
2128{
2129 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2130
2131 return dd->rcv_err_status_cnt[63];
2132}
2133
2134static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2135 void *context, int vl,
2136 int mode, u64 data)
2137{
2138 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2139
2140 return dd->rcv_err_status_cnt[62];
2141}
2142
2143static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2144 void *context, int vl, int mode,
2145 u64 data)
2146{
2147 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2148
2149 return dd->rcv_err_status_cnt[61];
2150}
2151
2152static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2153 void *context, int vl, int mode,
2154 u64 data)
2155{
2156 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2157
2158 return dd->rcv_err_status_cnt[60];
2159}
2160
2161static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2162 void *context, int vl,
2163 int mode, u64 data)
2164{
2165 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2166
2167 return dd->rcv_err_status_cnt[59];
2168}
2169
2170static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2171 void *context, int vl,
2172 int mode, u64 data)
2173{
2174 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2175
2176 return dd->rcv_err_status_cnt[58];
2177}
2178
2179static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2180 void *context, int vl, int mode,
2181 u64 data)
2182{
2183 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2184
2185 return dd->rcv_err_status_cnt[57];
2186}
2187
2188static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2189 void *context, int vl, int mode,
2190 u64 data)
2191{
2192 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2193
2194 return dd->rcv_err_status_cnt[56];
2195}
2196
2197static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2198 void *context, int vl, int mode,
2199 u64 data)
2200{
2201 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2202
2203 return dd->rcv_err_status_cnt[55];
2204}
2205
2206static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2207 const struct cntr_entry *entry,
2208 void *context, int vl, int mode, u64 data)
2209{
2210 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2211
2212 return dd->rcv_err_status_cnt[54];
2213}
2214
2215static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2216 const struct cntr_entry *entry,
2217 void *context, int vl, int mode, u64 data)
2218{
2219 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2220
2221 return dd->rcv_err_status_cnt[53];
2222}
2223
2224static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2225 void *context, int vl,
2226 int mode, u64 data)
2227{
2228 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2229
2230 return dd->rcv_err_status_cnt[52];
2231}
2232
2233static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2234 void *context, int vl,
2235 int mode, u64 data)
2236{
2237 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2238
2239 return dd->rcv_err_status_cnt[51];
2240}
2241
2242static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2243 void *context, int vl,
2244 int mode, u64 data)
2245{
2246 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2247
2248 return dd->rcv_err_status_cnt[50];
2249}
2250
2251static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2252 void *context, int vl,
2253 int mode, u64 data)
2254{
2255 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2256
2257 return dd->rcv_err_status_cnt[49];
2258}
2259
2260static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2261 void *context, int vl,
2262 int mode, u64 data)
2263{
2264 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2265
2266 return dd->rcv_err_status_cnt[48];
2267}
2268
2269static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2270 void *context, int vl,
2271 int mode, u64 data)
2272{
2273 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2274
2275 return dd->rcv_err_status_cnt[47];
2276}
2277
2278static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2279 void *context, int vl, int mode,
2280 u64 data)
2281{
2282 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2283
2284 return dd->rcv_err_status_cnt[46];
2285}
2286
2287static u64 access_rx_hq_intr_csr_parity_err_cnt(
2288 const struct cntr_entry *entry,
2289 void *context, int vl, int mode, u64 data)
2290{
2291 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2292
2293 return dd->rcv_err_status_cnt[45];
2294}
2295
2296static u64 access_rx_lookup_csr_parity_err_cnt(
2297 const struct cntr_entry *entry,
2298 void *context, int vl, int mode, u64 data)
2299{
2300 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2301
2302 return dd->rcv_err_status_cnt[44];
2303}
2304
2305static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2306 const struct cntr_entry *entry,
2307 void *context, int vl, int mode, u64 data)
2308{
2309 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2310
2311 return dd->rcv_err_status_cnt[43];
2312}
2313
2314static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2315 const struct cntr_entry *entry,
2316 void *context, int vl, int mode, u64 data)
2317{
2318 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2319
2320 return dd->rcv_err_status_cnt[42];
2321}
2322
2323static u64 access_rx_lookup_des_part2_parity_err_cnt(
2324 const struct cntr_entry *entry,
2325 void *context, int vl, int mode, u64 data)
2326{
2327 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2328
2329 return dd->rcv_err_status_cnt[41];
2330}
2331
2332static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2333 const struct cntr_entry *entry,
2334 void *context, int vl, int mode, u64 data)
2335{
2336 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2337
2338 return dd->rcv_err_status_cnt[40];
2339}
2340
2341static u64 access_rx_lookup_des_part1_unc_err_cnt(
2342 const struct cntr_entry *entry,
2343 void *context, int vl, int mode, u64 data)
2344{
2345 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2346
2347 return dd->rcv_err_status_cnt[39];
2348}
2349
2350static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2351 const struct cntr_entry *entry,
2352 void *context, int vl, int mode, u64 data)
2353{
2354 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2355
2356 return dd->rcv_err_status_cnt[38];
2357}
2358
2359static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2360 const struct cntr_entry *entry,
2361 void *context, int vl, int mode, u64 data)
2362{
2363 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2364
2365 return dd->rcv_err_status_cnt[37];
2366}
2367
2368static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2369 const struct cntr_entry *entry,
2370 void *context, int vl, int mode, u64 data)
2371{
2372 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2373
2374 return dd->rcv_err_status_cnt[36];
2375}
2376
2377static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2378 const struct cntr_entry *entry,
2379 void *context, int vl, int mode, u64 data)
2380{
2381 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2382
2383 return dd->rcv_err_status_cnt[35];
2384}
2385
2386static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2387 const struct cntr_entry *entry,
2388 void *context, int vl, int mode, u64 data)
2389{
2390 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2391
2392 return dd->rcv_err_status_cnt[34];
2393}
2394
2395static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2396 const struct cntr_entry *entry,
2397 void *context, int vl, int mode, u64 data)
2398{
2399 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2400
2401 return dd->rcv_err_status_cnt[33];
2402}
2403
2404static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2405 void *context, int vl, int mode,
2406 u64 data)
2407{
2408 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2409
2410 return dd->rcv_err_status_cnt[32];
2411}
2412
2413static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2414 void *context, int vl, int mode,
2415 u64 data)
2416{
2417 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2418
2419 return dd->rcv_err_status_cnt[31];
2420}
2421
2422static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2423 void *context, int vl, int mode,
2424 u64 data)
2425{
2426 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2427
2428 return dd->rcv_err_status_cnt[30];
2429}
2430
2431static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2432 void *context, int vl, int mode,
2433 u64 data)
2434{
2435 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2436
2437 return dd->rcv_err_status_cnt[29];
2438}
2439
2440static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2441 void *context, int vl,
2442 int mode, u64 data)
2443{
2444 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2445
2446 return dd->rcv_err_status_cnt[28];
2447}
2448
2449static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2450 const struct cntr_entry *entry,
2451 void *context, int vl, int mode, u64 data)
2452{
2453 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2454
2455 return dd->rcv_err_status_cnt[27];
2456}
2457
2458static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2459 const struct cntr_entry *entry,
2460 void *context, int vl, int mode, u64 data)
2461{
2462 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2463
2464 return dd->rcv_err_status_cnt[26];
2465}
2466
2467static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2468 const struct cntr_entry *entry,
2469 void *context, int vl, int mode, u64 data)
2470{
2471 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2472
2473 return dd->rcv_err_status_cnt[25];
2474}
2475
2476static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2477 const struct cntr_entry *entry,
2478 void *context, int vl, int mode, u64 data)
2479{
2480 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2481
2482 return dd->rcv_err_status_cnt[24];
2483}
2484
2485static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2486 const struct cntr_entry *entry,
2487 void *context, int vl, int mode, u64 data)
2488{
2489 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2490
2491 return dd->rcv_err_status_cnt[23];
2492}
2493
2494static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2495 const struct cntr_entry *entry,
2496 void *context, int vl, int mode, u64 data)
2497{
2498 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2499
2500 return dd->rcv_err_status_cnt[22];
2501}
2502
2503static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2504 const struct cntr_entry *entry,
2505 void *context, int vl, int mode, u64 data)
2506{
2507 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2508
2509 return dd->rcv_err_status_cnt[21];
2510}
2511
2512static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2513 const struct cntr_entry *entry,
2514 void *context, int vl, int mode, u64 data)
2515{
2516 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2517
2518 return dd->rcv_err_status_cnt[20];
2519}
2520
2521static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2522 const struct cntr_entry *entry,
2523 void *context, int vl, int mode, u64 data)
2524{
2525 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2526
2527 return dd->rcv_err_status_cnt[19];
2528}
2529
2530static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2531 void *context, int vl,
2532 int mode, u64 data)
2533{
2534 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2535
2536 return dd->rcv_err_status_cnt[18];
2537}
2538
2539static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2540 void *context, int vl,
2541 int mode, u64 data)
2542{
2543 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2544
2545 return dd->rcv_err_status_cnt[17];
2546}
2547
2548static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2549 const struct cntr_entry *entry,
2550 void *context, int vl, int mode, u64 data)
2551{
2552 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2553
2554 return dd->rcv_err_status_cnt[16];
2555}
2556
2557static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2558 const struct cntr_entry *entry,
2559 void *context, int vl, int mode, u64 data)
2560{
2561 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2562
2563 return dd->rcv_err_status_cnt[15];
2564}
2565
2566static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2567 void *context, int vl,
2568 int mode, u64 data)
2569{
2570 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2571
2572 return dd->rcv_err_status_cnt[14];
2573}
2574
2575static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2576 void *context, int vl,
2577 int mode, u64 data)
2578{
2579 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2580
2581 return dd->rcv_err_status_cnt[13];
2582}
2583
2584static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2585 void *context, int vl, int mode,
2586 u64 data)
2587{
2588 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2589
2590 return dd->rcv_err_status_cnt[12];
2591}
2592
2593static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2594 void *context, int vl, int mode,
2595 u64 data)
2596{
2597 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2598
2599 return dd->rcv_err_status_cnt[11];
2600}
2601
2602static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2603 void *context, int vl, int mode,
2604 u64 data)
2605{
2606 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2607
2608 return dd->rcv_err_status_cnt[10];
2609}
2610
2611static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2612 void *context, int vl, int mode,
2613 u64 data)
2614{
2615 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2616
2617 return dd->rcv_err_status_cnt[9];
2618}
2619
2620static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2621 void *context, int vl, int mode,
2622 u64 data)
2623{
2624 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2625
2626 return dd->rcv_err_status_cnt[8];
2627}
2628
2629static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2630 const struct cntr_entry *entry,
2631 void *context, int vl, int mode, u64 data)
2632{
2633 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2634
2635 return dd->rcv_err_status_cnt[7];
2636}
2637
2638static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2639 const struct cntr_entry *entry,
2640 void *context, int vl, int mode, u64 data)
2641{
2642 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2643
2644 return dd->rcv_err_status_cnt[6];
2645}
2646
2647static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2648 void *context, int vl, int mode,
2649 u64 data)
2650{
2651 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2652
2653 return dd->rcv_err_status_cnt[5];
2654}
2655
2656static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2657 void *context, int vl, int mode,
2658 u64 data)
2659{
2660 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2661
2662 return dd->rcv_err_status_cnt[4];
2663}
2664
2665static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2666 void *context, int vl, int mode,
2667 u64 data)
2668{
2669 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2670
2671 return dd->rcv_err_status_cnt[3];
2672}
2673
2674static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2675 void *context, int vl, int mode,
2676 u64 data)
2677{
2678 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2679
2680 return dd->rcv_err_status_cnt[2];
2681}
2682
2683static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2684 void *context, int vl, int mode,
2685 u64 data)
2686{
2687 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2688
2689 return dd->rcv_err_status_cnt[1];
2690}
2691
2692static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2693 void *context, int vl, int mode,
2694 u64 data)
2695{
2696 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2697
2698 return dd->rcv_err_status_cnt[0];
2699}
2700
2701/*
2702 * Software counters corresponding to each of the
2703 * error status bits within SendPioErrStatus
2704 */
2705static u64 access_pio_pec_sop_head_parity_err_cnt(
2706 const struct cntr_entry *entry,
2707 void *context, int vl, int mode, u64 data)
2708{
2709 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2710
2711 return dd->send_pio_err_status_cnt[35];
2712}
2713
2714static u64 access_pio_pcc_sop_head_parity_err_cnt(
2715 const struct cntr_entry *entry,
2716 void *context, int vl, int mode, u64 data)
2717{
2718 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2719
2720 return dd->send_pio_err_status_cnt[34];
2721}
2722
2723static u64 access_pio_last_returned_cnt_parity_err_cnt(
2724 const struct cntr_entry *entry,
2725 void *context, int vl, int mode, u64 data)
2726{
2727 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2728
2729 return dd->send_pio_err_status_cnt[33];
2730}
2731
2732static u64 access_pio_current_free_cnt_parity_err_cnt(
2733 const struct cntr_entry *entry,
2734 void *context, int vl, int mode, u64 data)
2735{
2736 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2737
2738 return dd->send_pio_err_status_cnt[32];
2739}
2740
2741static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2742 void *context, int vl, int mode,
2743 u64 data)
2744{
2745 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2746
2747 return dd->send_pio_err_status_cnt[31];
2748}
2749
2750static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2751 void *context, int vl, int mode,
2752 u64 data)
2753{
2754 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2755
2756 return dd->send_pio_err_status_cnt[30];
2757}
2758
2759static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2760 void *context, int vl, int mode,
2761 u64 data)
2762{
2763 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2764
2765 return dd->send_pio_err_status_cnt[29];
2766}
2767
2768static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2769 const struct cntr_entry *entry,
2770 void *context, int vl, int mode, u64 data)
2771{
2772 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2773
2774 return dd->send_pio_err_status_cnt[28];
2775}
2776
2777static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2778 void *context, int vl, int mode,
2779 u64 data)
2780{
2781 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2782
2783 return dd->send_pio_err_status_cnt[27];
2784}
2785
2786static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2787 void *context, int vl, int mode,
2788 u64 data)
2789{
2790 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2791
2792 return dd->send_pio_err_status_cnt[26];
2793}
2794
2795static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2796 void *context, int vl,
2797 int mode, u64 data)
2798{
2799 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2800
2801 return dd->send_pio_err_status_cnt[25];
2802}
2803
2804static u64 access_pio_block_qw_count_parity_err_cnt(
2805 const struct cntr_entry *entry,
2806 void *context, int vl, int mode, u64 data)
2807{
2808 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2809
2810 return dd->send_pio_err_status_cnt[24];
2811}
2812
2813static u64 access_pio_write_qw_valid_parity_err_cnt(
2814 const struct cntr_entry *entry,
2815 void *context, int vl, int mode, u64 data)
2816{
2817 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2818
2819 return dd->send_pio_err_status_cnt[23];
2820}
2821
2822static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2823 void *context, int vl, int mode,
2824 u64 data)
2825{
2826 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2827
2828 return dd->send_pio_err_status_cnt[22];
2829}
2830
2831static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2832 void *context, int vl,
2833 int mode, u64 data)
2834{
2835 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2836
2837 return dd->send_pio_err_status_cnt[21];
2838}
2839
2840static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2841 void *context, int vl,
2842 int mode, u64 data)
2843{
2844 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2845
2846 return dd->send_pio_err_status_cnt[20];
2847}
2848
2849static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2850 void *context, int vl,
2851 int mode, u64 data)
2852{
2853 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2854
2855 return dd->send_pio_err_status_cnt[19];
2856}
2857
2858static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2859 const struct cntr_entry *entry,
2860 void *context, int vl, int mode, u64 data)
2861{
2862 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2863
2864 return dd->send_pio_err_status_cnt[18];
2865}
2866
2867static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2868 void *context, int vl, int mode,
2869 u64 data)
2870{
2871 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2872
2873 return dd->send_pio_err_status_cnt[17];
2874}
2875
2876static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2877 void *context, int vl, int mode,
2878 u64 data)
2879{
2880 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2881
2882 return dd->send_pio_err_status_cnt[16];
2883}
2884
2885static u64 access_pio_credit_ret_fifo_parity_err_cnt(
2886 const struct cntr_entry *entry,
2887 void *context, int vl, int mode, u64 data)
2888{
2889 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2890
2891 return dd->send_pio_err_status_cnt[15];
2892}
2893
2894static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
2895 const struct cntr_entry *entry,
2896 void *context, int vl, int mode, u64 data)
2897{
2898 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2899
2900 return dd->send_pio_err_status_cnt[14];
2901}
2902
2903static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
2904 const struct cntr_entry *entry,
2905 void *context, int vl, int mode, u64 data)
2906{
2907 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2908
2909 return dd->send_pio_err_status_cnt[13];
2910}
2911
2912static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
2913 const struct cntr_entry *entry,
2914 void *context, int vl, int mode, u64 data)
2915{
2916 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2917
2918 return dd->send_pio_err_status_cnt[12];
2919}
2920
2921static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
2922 const struct cntr_entry *entry,
2923 void *context, int vl, int mode, u64 data)
2924{
2925 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2926
2927 return dd->send_pio_err_status_cnt[11];
2928}
2929
2930static u64 access_pio_sm_pkt_reset_parity_err_cnt(
2931 const struct cntr_entry *entry,
2932 void *context, int vl, int mode, u64 data)
2933{
2934 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2935
2936 return dd->send_pio_err_status_cnt[10];
2937}
2938
2939static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
2940 const struct cntr_entry *entry,
2941 void *context, int vl, int mode, u64 data)
2942{
2943 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2944
2945 return dd->send_pio_err_status_cnt[9];
2946}
2947
2948static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
2949 const struct cntr_entry *entry,
2950 void *context, int vl, int mode, u64 data)
2951{
2952 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2953
2954 return dd->send_pio_err_status_cnt[8];
2955}
2956
2957static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
2958 const struct cntr_entry *entry,
2959 void *context, int vl, int mode, u64 data)
2960{
2961 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2962
2963 return dd->send_pio_err_status_cnt[7];
2964}
2965
2966static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
2967 void *context, int vl, int mode,
2968 u64 data)
2969{
2970 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2971
2972 return dd->send_pio_err_status_cnt[6];
2973}
2974
2975static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
2976 void *context, int vl, int mode,
2977 u64 data)
2978{
2979 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2980
2981 return dd->send_pio_err_status_cnt[5];
2982}
2983
2984static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
2985 void *context, int vl, int mode,
2986 u64 data)
2987{
2988 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2989
2990 return dd->send_pio_err_status_cnt[4];
2991}
2992
2993static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
2994 void *context, int vl, int mode,
2995 u64 data)
2996{
2997 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2998
2999 return dd->send_pio_err_status_cnt[3];
3000}
3001
3002static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3003 void *context, int vl, int mode,
3004 u64 data)
3005{
3006 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3007
3008 return dd->send_pio_err_status_cnt[2];
3009}
3010
3011static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3012 void *context, int vl,
3013 int mode, u64 data)
3014{
3015 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3016
3017 return dd->send_pio_err_status_cnt[1];
3018}
3019
3020static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3021 void *context, int vl, int mode,
3022 u64 data)
3023{
3024 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3025
3026 return dd->send_pio_err_status_cnt[0];
3027}
3028
3029/*
3030 * Software counters corresponding to each of the
3031 * error status bits within SendDmaErrStatus
3032 */
3033static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3034 const struct cntr_entry *entry,
3035 void *context, int vl, int mode, u64 data)
3036{
3037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3038
3039 return dd->send_dma_err_status_cnt[3];
3040}
3041
3042static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3043 const struct cntr_entry *entry,
3044 void *context, int vl, int mode, u64 data)
3045{
3046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3047
3048 return dd->send_dma_err_status_cnt[2];
3049}
3050
3051static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3052 void *context, int vl, int mode,
3053 u64 data)
3054{
3055 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3056
3057 return dd->send_dma_err_status_cnt[1];
3058}
3059
3060static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3061 void *context, int vl, int mode,
3062 u64 data)
3063{
3064 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3065
3066 return dd->send_dma_err_status_cnt[0];
3067}
3068
3069/*
3070 * Software counters corresponding to each of the
3071 * error status bits within SendEgressErrStatus
3072 */
3073static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3074 const struct cntr_entry *entry,
3075 void *context, int vl, int mode, u64 data)
3076{
3077 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3078
3079 return dd->send_egress_err_status_cnt[63];
3080}
3081
3082static u64 access_tx_read_sdma_memory_csr_err_cnt(
3083 const struct cntr_entry *entry,
3084 void *context, int vl, int mode, u64 data)
3085{
3086 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3087
3088 return dd->send_egress_err_status_cnt[62];
3089}
3090
3091static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3092 void *context, int vl, int mode,
3093 u64 data)
3094{
3095 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3096
3097 return dd->send_egress_err_status_cnt[61];
3098}
3099
3100static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3101 void *context, int vl,
3102 int mode, u64 data)
3103{
3104 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3105
3106 return dd->send_egress_err_status_cnt[60];
3107}
3108
3109static u64 access_tx_read_sdma_memory_cor_err_cnt(
3110 const struct cntr_entry *entry,
3111 void *context, int vl, int mode, u64 data)
3112{
3113 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3114
3115 return dd->send_egress_err_status_cnt[59];
3116}
3117
3118static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3119 void *context, int vl, int mode,
3120 u64 data)
3121{
3122 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3123
3124 return dd->send_egress_err_status_cnt[58];
3125}
3126
3127static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3128 void *context, int vl, int mode,
3129 u64 data)
3130{
3131 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3132
3133 return dd->send_egress_err_status_cnt[57];
3134}
3135
3136static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3137 void *context, int vl, int mode,
3138 u64 data)
3139{
3140 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3141
3142 return dd->send_egress_err_status_cnt[56];
3143}
3144
3145static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3146 void *context, int vl, int mode,
3147 u64 data)
3148{
3149 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3150
3151 return dd->send_egress_err_status_cnt[55];
3152}
3153
3154static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3155 void *context, int vl, int mode,
3156 u64 data)
3157{
3158 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3159
3160 return dd->send_egress_err_status_cnt[54];
3161}
3162
3163static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3164 void *context, int vl, int mode,
3165 u64 data)
3166{
3167 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3168
3169 return dd->send_egress_err_status_cnt[53];
3170}
3171
3172static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3173 void *context, int vl, int mode,
3174 u64 data)
3175{
3176 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3177
3178 return dd->send_egress_err_status_cnt[52];
3179}
3180
3181static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3182 void *context, int vl, int mode,
3183 u64 data)
3184{
3185 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3186
3187 return dd->send_egress_err_status_cnt[51];
3188}
3189
3190static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3191 void *context, int vl, int mode,
3192 u64 data)
3193{
3194 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3195
3196 return dd->send_egress_err_status_cnt[50];
3197}
3198
3199static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3200 void *context, int vl, int mode,
3201 u64 data)
3202{
3203 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3204
3205 return dd->send_egress_err_status_cnt[49];
3206}
3207
3208static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3209 void *context, int vl, int mode,
3210 u64 data)
3211{
3212 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3213
3214 return dd->send_egress_err_status_cnt[48];
3215}
3216
3217static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3218 void *context, int vl, int mode,
3219 u64 data)
3220{
3221 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3222
3223 return dd->send_egress_err_status_cnt[47];
3224}
3225
3226static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3227 void *context, int vl, int mode,
3228 u64 data)
3229{
3230 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3231
3232 return dd->send_egress_err_status_cnt[46];
3233}
3234
3235static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3236 void *context, int vl, int mode,
3237 u64 data)
3238{
3239 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3240
3241 return dd->send_egress_err_status_cnt[45];
3242}
3243
3244static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3245 void *context, int vl,
3246 int mode, u64 data)
3247{
3248 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3249
3250 return dd->send_egress_err_status_cnt[44];
3251}
3252
3253static u64 access_tx_read_sdma_memory_unc_err_cnt(
3254 const struct cntr_entry *entry,
3255 void *context, int vl, int mode, u64 data)
3256{
3257 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3258
3259 return dd->send_egress_err_status_cnt[43];
3260}
3261
3262static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3263 void *context, int vl, int mode,
3264 u64 data)
3265{
3266 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3267
3268 return dd->send_egress_err_status_cnt[42];
3269}
3270
3271static u64 access_tx_credit_return_partiy_err_cnt(
3272 const struct cntr_entry *entry,
3273 void *context, int vl, int mode, u64 data)
3274{
3275 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3276
3277 return dd->send_egress_err_status_cnt[41];
3278}
3279
3280static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3281 const struct cntr_entry *entry,
3282 void *context, int vl, int mode, u64 data)
3283{
3284 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3285
3286 return dd->send_egress_err_status_cnt[40];
3287}
3288
3289static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3290 const struct cntr_entry *entry,
3291 void *context, int vl, int mode, u64 data)
3292{
3293 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3294
3295 return dd->send_egress_err_status_cnt[39];
3296}
3297
3298static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3299 const struct cntr_entry *entry,
3300 void *context, int vl, int mode, u64 data)
3301{
3302 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3303
3304 return dd->send_egress_err_status_cnt[38];
3305}
3306
3307static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3308 const struct cntr_entry *entry,
3309 void *context, int vl, int mode, u64 data)
3310{
3311 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3312
3313 return dd->send_egress_err_status_cnt[37];
3314}
3315
3316static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3317 const struct cntr_entry *entry,
3318 void *context, int vl, int mode, u64 data)
3319{
3320 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3321
3322 return dd->send_egress_err_status_cnt[36];
3323}
3324
3325static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3326 const struct cntr_entry *entry,
3327 void *context, int vl, int mode, u64 data)
3328{
3329 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3330
3331 return dd->send_egress_err_status_cnt[35];
3332}
3333
3334static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3335 const struct cntr_entry *entry,
3336 void *context, int vl, int mode, u64 data)
3337{
3338 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3339
3340 return dd->send_egress_err_status_cnt[34];
3341}
3342
3343static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3344 const struct cntr_entry *entry,
3345 void *context, int vl, int mode, u64 data)
3346{
3347 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3348
3349 return dd->send_egress_err_status_cnt[33];
3350}
3351
3352static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3353 const struct cntr_entry *entry,
3354 void *context, int vl, int mode, u64 data)
3355{
3356 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3357
3358 return dd->send_egress_err_status_cnt[32];
3359}
3360
3361static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3362 const struct cntr_entry *entry,
3363 void *context, int vl, int mode, u64 data)
3364{
3365 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3366
3367 return dd->send_egress_err_status_cnt[31];
3368}
3369
3370static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3371 const struct cntr_entry *entry,
3372 void *context, int vl, int mode, u64 data)
3373{
3374 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3375
3376 return dd->send_egress_err_status_cnt[30];
3377}
3378
3379static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3380 const struct cntr_entry *entry,
3381 void *context, int vl, int mode, u64 data)
3382{
3383 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3384
3385 return dd->send_egress_err_status_cnt[29];
3386}
3387
3388static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3389 const struct cntr_entry *entry,
3390 void *context, int vl, int mode, u64 data)
3391{
3392 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3393
3394 return dd->send_egress_err_status_cnt[28];
3395}
3396
3397static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3398 const struct cntr_entry *entry,
3399 void *context, int vl, int mode, u64 data)
3400{
3401 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3402
3403 return dd->send_egress_err_status_cnt[27];
3404}
3405
3406static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3407 const struct cntr_entry *entry,
3408 void *context, int vl, int mode, u64 data)
3409{
3410 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3411
3412 return dd->send_egress_err_status_cnt[26];
3413}
3414
3415static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3416 const struct cntr_entry *entry,
3417 void *context, int vl, int mode, u64 data)
3418{
3419 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3420
3421 return dd->send_egress_err_status_cnt[25];
3422}
3423
3424static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3425 const struct cntr_entry *entry,
3426 void *context, int vl, int mode, u64 data)
3427{
3428 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3429
3430 return dd->send_egress_err_status_cnt[24];
3431}
3432
3433static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3434 const struct cntr_entry *entry,
3435 void *context, int vl, int mode, u64 data)
3436{
3437 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3438
3439 return dd->send_egress_err_status_cnt[23];
3440}
3441
3442static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3443 const struct cntr_entry *entry,
3444 void *context, int vl, int mode, u64 data)
3445{
3446 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3447
3448 return dd->send_egress_err_status_cnt[22];
3449}
3450
3451static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3452 const struct cntr_entry *entry,
3453 void *context, int vl, int mode, u64 data)
3454{
3455 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3456
3457 return dd->send_egress_err_status_cnt[21];
3458}
3459
3460static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3461 const struct cntr_entry *entry,
3462 void *context, int vl, int mode, u64 data)
3463{
3464 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3465
3466 return dd->send_egress_err_status_cnt[20];
3467}
3468
3469static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3470 const struct cntr_entry *entry,
3471 void *context, int vl, int mode, u64 data)
3472{
3473 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3474
3475 return dd->send_egress_err_status_cnt[19];
3476}
3477
3478static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3479 const struct cntr_entry *entry,
3480 void *context, int vl, int mode, u64 data)
3481{
3482 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3483
3484 return dd->send_egress_err_status_cnt[18];
3485}
3486
3487static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3488 const struct cntr_entry *entry,
3489 void *context, int vl, int mode, u64 data)
3490{
3491 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3492
3493 return dd->send_egress_err_status_cnt[17];
3494}
3495
3496static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3497 const struct cntr_entry *entry,
3498 void *context, int vl, int mode, u64 data)
3499{
3500 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3501
3502 return dd->send_egress_err_status_cnt[16];
3503}
3504
3505static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3506 void *context, int vl, int mode,
3507 u64 data)
3508{
3509 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3510
3511 return dd->send_egress_err_status_cnt[15];
3512}
3513
3514static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3515 void *context, int vl,
3516 int mode, u64 data)
3517{
3518 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3519
3520 return dd->send_egress_err_status_cnt[14];
3521}
3522
3523static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3524 void *context, int vl, int mode,
3525 u64 data)
3526{
3527 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3528
3529 return dd->send_egress_err_status_cnt[13];
3530}
3531
3532static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3533 void *context, int vl, int mode,
3534 u64 data)
3535{
3536 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3537
3538 return dd->send_egress_err_status_cnt[12];
3539}
3540
3541static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3542 const struct cntr_entry *entry,
3543 void *context, int vl, int mode, u64 data)
3544{
3545 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3546
3547 return dd->send_egress_err_status_cnt[11];
3548}
3549
3550static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3551 void *context, int vl, int mode,
3552 u64 data)
3553{
3554 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3555
3556 return dd->send_egress_err_status_cnt[10];
3557}
3558
3559static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3560 void *context, int vl, int mode,
3561 u64 data)
3562{
3563 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3564
3565 return dd->send_egress_err_status_cnt[9];
3566}
3567
3568static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3569 const struct cntr_entry *entry,
3570 void *context, int vl, int mode, u64 data)
3571{
3572 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3573
3574 return dd->send_egress_err_status_cnt[8];
3575}
3576
3577static u64 access_tx_pio_launch_intf_parity_err_cnt(
3578 const struct cntr_entry *entry,
3579 void *context, int vl, int mode, u64 data)
3580{
3581 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3582
3583 return dd->send_egress_err_status_cnt[7];
3584}
3585
3586static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3587 void *context, int vl, int mode,
3588 u64 data)
3589{
3590 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3591
3592 return dd->send_egress_err_status_cnt[6];
3593}
3594
3595static u64 access_tx_incorrect_link_state_err_cnt(
3596 const struct cntr_entry *entry,
3597 void *context, int vl, int mode, u64 data)
3598{
3599 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3600
3601 return dd->send_egress_err_status_cnt[5];
3602}
3603
3604static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3605 void *context, int vl, int mode,
3606 u64 data)
3607{
3608 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3609
3610 return dd->send_egress_err_status_cnt[4];
3611}
3612
3613static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3614 const struct cntr_entry *entry,
3615 void *context, int vl, int mode, u64 data)
3616{
3617 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3618
3619 return dd->send_egress_err_status_cnt[3];
3620}
3621
3622static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3623 void *context, int vl, int mode,
3624 u64 data)
3625{
3626 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3627
3628 return dd->send_egress_err_status_cnt[2];
3629}
3630
3631static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3632 const struct cntr_entry *entry,
3633 void *context, int vl, int mode, u64 data)
3634{
3635 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3636
3637 return dd->send_egress_err_status_cnt[1];
3638}
3639
3640static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3641 const struct cntr_entry *entry,
3642 void *context, int vl, int mode, u64 data)
3643{
3644 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3645
3646 return dd->send_egress_err_status_cnt[0];
3647}
3648
3649/*
3650 * Software counters corresponding to each of the
3651 * error status bits within SendErrStatus
3652 */
3653static u64 access_send_csr_write_bad_addr_err_cnt(
3654 const struct cntr_entry *entry,
3655 void *context, int vl, int mode, u64 data)
3656{
3657 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3658
3659 return dd->send_err_status_cnt[2];
3660}
3661
3662static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3663 void *context, int vl,
3664 int mode, u64 data)
3665{
3666 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3667
3668 return dd->send_err_status_cnt[1];
3669}
3670
3671static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3672 void *context, int vl, int mode,
3673 u64 data)
3674{
3675 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3676
3677 return dd->send_err_status_cnt[0];
3678}
3679
3680/*
3681 * Software counters corresponding to each of the
3682 * error status bits within SendCtxtErrStatus
3683 */
3684static u64 access_pio_write_out_of_bounds_err_cnt(
3685 const struct cntr_entry *entry,
3686 void *context, int vl, int mode, u64 data)
3687{
3688 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3689
3690 return dd->sw_ctxt_err_status_cnt[4];
3691}
3692
3693static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3694 void *context, int vl, int mode,
3695 u64 data)
3696{
3697 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3698
3699 return dd->sw_ctxt_err_status_cnt[3];
3700}
3701
3702static u64 access_pio_write_crosses_boundary_err_cnt(
3703 const struct cntr_entry *entry,
3704 void *context, int vl, int mode, u64 data)
3705{
3706 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3707
3708 return dd->sw_ctxt_err_status_cnt[2];
3709}
3710
3711static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3712 void *context, int vl,
3713 int mode, u64 data)
3714{
3715 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3716
3717 return dd->sw_ctxt_err_status_cnt[1];
3718}
3719
3720static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3721 void *context, int vl, int mode,
3722 u64 data)
3723{
3724 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3725
3726 return dd->sw_ctxt_err_status_cnt[0];
3727}
3728
3729/*
3730 * Software counters corresponding to each of the
3731 * error status bits within SendDmaEngErrStatus
3732 */
3733static u64 access_sdma_header_request_fifo_cor_err_cnt(
3734 const struct cntr_entry *entry,
3735 void *context, int vl, int mode, u64 data)
3736{
3737 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3738
3739 return dd->sw_send_dma_eng_err_status_cnt[23];
3740}
3741
3742static u64 access_sdma_header_storage_cor_err_cnt(
3743 const struct cntr_entry *entry,
3744 void *context, int vl, int mode, u64 data)
3745{
3746 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3747
3748 return dd->sw_send_dma_eng_err_status_cnt[22];
3749}
3750
3751static u64 access_sdma_packet_tracking_cor_err_cnt(
3752 const struct cntr_entry *entry,
3753 void *context, int vl, int mode, u64 data)
3754{
3755 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3756
3757 return dd->sw_send_dma_eng_err_status_cnt[21];
3758}
3759
3760static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3761 void *context, int vl, int mode,
3762 u64 data)
3763{
3764 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3765
3766 return dd->sw_send_dma_eng_err_status_cnt[20];
3767}
3768
3769static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3770 void *context, int vl, int mode,
3771 u64 data)
3772{
3773 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3774
3775 return dd->sw_send_dma_eng_err_status_cnt[19];
3776}
3777
3778static u64 access_sdma_header_request_fifo_unc_err_cnt(
3779 const struct cntr_entry *entry,
3780 void *context, int vl, int mode, u64 data)
3781{
3782 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3783
3784 return dd->sw_send_dma_eng_err_status_cnt[18];
3785}
3786
3787static u64 access_sdma_header_storage_unc_err_cnt(
3788 const struct cntr_entry *entry,
3789 void *context, int vl, int mode, u64 data)
3790{
3791 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3792
3793 return dd->sw_send_dma_eng_err_status_cnt[17];
3794}
3795
3796static u64 access_sdma_packet_tracking_unc_err_cnt(
3797 const struct cntr_entry *entry,
3798 void *context, int vl, int mode, u64 data)
3799{
3800 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3801
3802 return dd->sw_send_dma_eng_err_status_cnt[16];
3803}
3804
3805static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3806 void *context, int vl, int mode,
3807 u64 data)
3808{
3809 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3810
3811 return dd->sw_send_dma_eng_err_status_cnt[15];
3812}
3813
3814static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3815 void *context, int vl, int mode,
3816 u64 data)
3817{
3818 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3819
3820 return dd->sw_send_dma_eng_err_status_cnt[14];
3821}
3822
3823static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3824 void *context, int vl, int mode,
3825 u64 data)
3826{
3827 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3828
3829 return dd->sw_send_dma_eng_err_status_cnt[13];
3830}
3831
3832static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3833 void *context, int vl, int mode,
3834 u64 data)
3835{
3836 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3837
3838 return dd->sw_send_dma_eng_err_status_cnt[12];
3839}
3840
3841static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3842 void *context, int vl, int mode,
3843 u64 data)
3844{
3845 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3846
3847 return dd->sw_send_dma_eng_err_status_cnt[11];
3848}
3849
3850static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3851 void *context, int vl, int mode,
3852 u64 data)
3853{
3854 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3855
3856 return dd->sw_send_dma_eng_err_status_cnt[10];
3857}
3858
3859static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3860 void *context, int vl, int mode,
3861 u64 data)
3862{
3863 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3864
3865 return dd->sw_send_dma_eng_err_status_cnt[9];
3866}
3867
3868static u64 access_sdma_packet_desc_overflow_err_cnt(
3869 const struct cntr_entry *entry,
3870 void *context, int vl, int mode, u64 data)
3871{
3872 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3873
3874 return dd->sw_send_dma_eng_err_status_cnt[8];
3875}
3876
3877static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3878 void *context, int vl,
3879 int mode, u64 data)
3880{
3881 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3882
3883 return dd->sw_send_dma_eng_err_status_cnt[7];
3884}
3885
3886static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
3887 void *context, int vl, int mode, u64 data)
3888{
3889 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3890
3891 return dd->sw_send_dma_eng_err_status_cnt[6];
3892}
3893
3894static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
3895 void *context, int vl, int mode,
3896 u64 data)
3897{
3898 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3899
3900 return dd->sw_send_dma_eng_err_status_cnt[5];
3901}
3902
3903static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
3904 void *context, int vl, int mode,
3905 u64 data)
3906{
3907 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3908
3909 return dd->sw_send_dma_eng_err_status_cnt[4];
3910}
3911
3912static u64 access_sdma_tail_out_of_bounds_err_cnt(
3913 const struct cntr_entry *entry,
3914 void *context, int vl, int mode, u64 data)
3915{
3916 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3917
3918 return dd->sw_send_dma_eng_err_status_cnt[3];
3919}
3920
3921static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
3922 void *context, int vl, int mode,
3923 u64 data)
3924{
3925 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3926
3927 return dd->sw_send_dma_eng_err_status_cnt[2];
3928}
3929
3930static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
3931 void *context, int vl, int mode,
3932 u64 data)
3933{
3934 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3935
3936 return dd->sw_send_dma_eng_err_status_cnt[1];
3937}
3938
3939static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
3940 void *context, int vl, int mode,
3941 u64 data)
3942{
3943 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3944
3945 return dd->sw_send_dma_eng_err_status_cnt[0];
3946}
3947
77241056
MM		 3948#define def_access_sw_cpu(cntr) \
3949static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
3950 void *context, int vl, int mode, u64 data) \
3951{ \
3952 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4eb06882
DD		 3953 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
3954 ppd->ibport_data.rvp.cntr, vl, \
77241056
MM		 3955 mode, data); \
3956}
3957
3958def_access_sw_cpu(rc_acks);
3959def_access_sw_cpu(rc_qacks);
3960def_access_sw_cpu(rc_delayed_comp);
3961
3962#define def_access_ibp_counter(cntr) \
3963static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
3964 void *context, int vl, int mode, u64 data) \
3965{ \
3966 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
3967 \
3968 if (vl != CNTR_INVALID_VL) \
3969 return 0; \
3970 \
4eb06882 3971 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
77241056
MM		 3972 mode, data); \
3973}
3974
3975def_access_ibp_counter(loop_pkts);
3976def_access_ibp_counter(rc_resends);
3977def_access_ibp_counter(rnr_naks);
3978def_access_ibp_counter(other_naks);
3979def_access_ibp_counter(rc_timeouts);
3980def_access_ibp_counter(pkt_drops);
3981def_access_ibp_counter(dmawait);
3982def_access_ibp_counter(rc_seqnak);
3983def_access_ibp_counter(rc_dupreq);
3984def_access_ibp_counter(rdma_seq);
3985def_access_ibp_counter(unaligned);
3986def_access_ibp_counter(seq_naks);
3987
3988static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
3989[C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
3990[C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
3991 CNTR_NORMAL),
3992[C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
3993 CNTR_NORMAL),
3994[C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
3995 RCV_TID_FLOW_GEN_MISMATCH_CNT,
3996 CNTR_NORMAL),
77241056
MM		 3997[C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
3998 CNTR_NORMAL),
3999[C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
4000 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
4001[C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4002 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4003[C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4004 CNTR_NORMAL),
4005[C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4006 CNTR_NORMAL),
4007[C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4008 CNTR_NORMAL),
4009[C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4010 CNTR_NORMAL),
4011[C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4012 CNTR_NORMAL),
4013[C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4014 CNTR_NORMAL),
4015[C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4016 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4017[C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4018 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4019[C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4020 CNTR_SYNTH),
4021[C_DC_RCV_ERR] = DC_PERF_CNTR(DcRecvErr, DCC_ERR_PORTRCV_ERR_CNT, CNTR_SYNTH),
4022[C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4023 CNTR_SYNTH),
4024[C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4025 CNTR_SYNTH),
4026[C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4027 CNTR_SYNTH),
4028[C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4029 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4030[C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4031 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4032 CNTR_SYNTH),
4033[C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4034 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4035[C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4036 CNTR_SYNTH),
4037[C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4038 CNTR_SYNTH),
4039[C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4040 CNTR_SYNTH),
4041[C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4042 CNTR_SYNTH),
4043[C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4044 CNTR_SYNTH),
4045[C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4046 CNTR_SYNTH),
4047[C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4048 CNTR_SYNTH),
4049[C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4050 CNTR_SYNTH | CNTR_VL),
4051[C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4052 CNTR_SYNTH | CNTR_VL),
4053[C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4054[C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4055 CNTR_SYNTH | CNTR_VL),
4056[C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4057[C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4058 CNTR_SYNTH | CNTR_VL),
4059[C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4060 CNTR_SYNTH),
4061[C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4062 CNTR_SYNTH | CNTR_VL),
4063[C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4064 CNTR_SYNTH),
4065[C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4066 CNTR_SYNTH | CNTR_VL),
4067[C_DC_TOTAL_CRC] =
4068 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4069 CNTR_SYNTH),
4070[C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4071 CNTR_SYNTH),
4072[C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4073 CNTR_SYNTH),
4074[C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4075 CNTR_SYNTH),
4076[C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4077 CNTR_SYNTH),
4078[C_DC_CRC_MULT_LN] =
4079 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4080 CNTR_SYNTH),
4081[C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4082 CNTR_SYNTH),
4083[C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4084 CNTR_SYNTH),
4085[C_DC_SEQ_CRC_CNT] =
4086 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4087 CNTR_SYNTH),
4088[C_DC_ESC0_ONLY_CNT] =
4089 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4090 CNTR_SYNTH),
4091[C_DC_ESC0_PLUS1_CNT] =
4092 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4093 CNTR_SYNTH),
4094[C_DC_ESC0_PLUS2_CNT] =
4095 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4096 CNTR_SYNTH),
4097[C_DC_REINIT_FROM_PEER_CNT] =
4098 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4099 CNTR_SYNTH),
4100[C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4101 CNTR_SYNTH),
4102[C_DC_MISC_FLG_CNT] =
4103 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4104 CNTR_SYNTH),
4105[C_DC_PRF_GOOD_LTP_CNT] =
4106 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4107[C_DC_PRF_ACCEPTED_LTP_CNT] =
4108 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4109 CNTR_SYNTH),
4110[C_DC_PRF_RX_FLIT_CNT] =
4111 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4112[C_DC_PRF_TX_FLIT_CNT] =
4113 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4114[C_DC_PRF_CLK_CNTR] =
4115 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4116[C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4117 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4118[C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4119 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4120 CNTR_SYNTH),
4121[C_DC_PG_STS_TX_SBE_CNT] =
4122 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4123[C_DC_PG_STS_TX_MBE_CNT] =
4124 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4125 CNTR_SYNTH),
4126[C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4127 access_sw_cpu_intr),
4128[C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4129 access_sw_cpu_rcv_limit),
4130[C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4131 access_sw_vtx_wait),
4132[C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4133 access_sw_pio_wait),
14553ca1
MM		 4134[C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4135 access_sw_pio_drain),
77241056
MM		 4136[C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4137 access_sw_kmem_wait),
b421922e
DL		 4138[C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4139 access_sw_send_schedule),
a699c6c2
VM		 4140[C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4141 SEND_DMA_DESC_FETCHED_CNT, 0,
4142 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4143 dev_access_u32_csr),
4144[C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4145 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4146 access_sde_int_cnt),
4147[C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4148 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4149 access_sde_err_cnt),
4150[C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4151 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4152 access_sde_idle_int_cnt),
4153[C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4154 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4155 access_sde_progress_int_cnt),
2c5b521a
JR		 4156/* MISC_ERR_STATUS */
4157[C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4158 CNTR_NORMAL,
4159 access_misc_pll_lock_fail_err_cnt),
4160[C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4161 CNTR_NORMAL,
4162 access_misc_mbist_fail_err_cnt),
4163[C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4164 CNTR_NORMAL,
4165 access_misc_invalid_eep_cmd_err_cnt),
4166[C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4167 CNTR_NORMAL,
4168 access_misc_efuse_done_parity_err_cnt),
4169[C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4170 CNTR_NORMAL,
4171 access_misc_efuse_write_err_cnt),
4172[C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4173 0, CNTR_NORMAL,
4174 access_misc_efuse_read_bad_addr_err_cnt),
4175[C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4176 CNTR_NORMAL,
4177 access_misc_efuse_csr_parity_err_cnt),
4178[C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4179 CNTR_NORMAL,
4180 access_misc_fw_auth_failed_err_cnt),
4181[C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4182 CNTR_NORMAL,
4183 access_misc_key_mismatch_err_cnt),
4184[C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4185 CNTR_NORMAL,
4186 access_misc_sbus_write_failed_err_cnt),
4187[C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4188 CNTR_NORMAL,
4189 access_misc_csr_write_bad_addr_err_cnt),
4190[C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4191 CNTR_NORMAL,
4192 access_misc_csr_read_bad_addr_err_cnt),
4193[C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4194 CNTR_NORMAL,
4195 access_misc_csr_parity_err_cnt),
4196/* CceErrStatus */
4197[C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4198 CNTR_NORMAL,
4199 access_sw_cce_err_status_aggregated_cnt),
4200[C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4201 CNTR_NORMAL,
4202 access_cce_msix_csr_parity_err_cnt),
4203[C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4204 CNTR_NORMAL,
4205 access_cce_int_map_unc_err_cnt),
4206[C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4207 CNTR_NORMAL,
4208 access_cce_int_map_cor_err_cnt),
4209[C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4210 CNTR_NORMAL,
4211 access_cce_msix_table_unc_err_cnt),
4212[C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4213 CNTR_NORMAL,
4214 access_cce_msix_table_cor_err_cnt),
4215[C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4216 0, CNTR_NORMAL,
4217 access_cce_rxdma_conv_fifo_parity_err_cnt),
4218[C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4219 0, CNTR_NORMAL,
4220 access_cce_rcpl_async_fifo_parity_err_cnt),
4221[C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4222 CNTR_NORMAL,
4223 access_cce_seg_write_bad_addr_err_cnt),
4224[C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4225 CNTR_NORMAL,
4226 access_cce_seg_read_bad_addr_err_cnt),
4227[C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4228 CNTR_NORMAL,
4229 access_la_triggered_cnt),
4230[C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4231 CNTR_NORMAL,
4232 access_cce_trgt_cpl_timeout_err_cnt),
4233[C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4234 CNTR_NORMAL,
4235 access_pcic_receive_parity_err_cnt),
4236[C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4237 CNTR_NORMAL,
4238 access_pcic_transmit_back_parity_err_cnt),
4239[C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4240 0, CNTR_NORMAL,
4241 access_pcic_transmit_front_parity_err_cnt),
4242[C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4243 CNTR_NORMAL,
4244 access_pcic_cpl_dat_q_unc_err_cnt),
4245[C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4246 CNTR_NORMAL,
4247 access_pcic_cpl_hd_q_unc_err_cnt),
4248[C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4249 CNTR_NORMAL,
4250 access_pcic_post_dat_q_unc_err_cnt),
4251[C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4252 CNTR_NORMAL,
4253 access_pcic_post_hd_q_unc_err_cnt),
4254[C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4255 CNTR_NORMAL,
4256 access_pcic_retry_sot_mem_unc_err_cnt),
4257[C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4258 CNTR_NORMAL,
4259 access_pcic_retry_mem_unc_err),
4260[C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4261 CNTR_NORMAL,
4262 access_pcic_n_post_dat_q_parity_err_cnt),
4263[C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4264 CNTR_NORMAL,
4265 access_pcic_n_post_h_q_parity_err_cnt),
4266[C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4267 CNTR_NORMAL,
4268 access_pcic_cpl_dat_q_cor_err_cnt),
4269[C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4270 CNTR_NORMAL,
4271 access_pcic_cpl_hd_q_cor_err_cnt),
4272[C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4273 CNTR_NORMAL,
4274 access_pcic_post_dat_q_cor_err_cnt),
4275[C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4276 CNTR_NORMAL,
4277 access_pcic_post_hd_q_cor_err_cnt),
4278[C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4279 CNTR_NORMAL,
4280 access_pcic_retry_sot_mem_cor_err_cnt),
4281[C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4282 CNTR_NORMAL,
4283 access_pcic_retry_mem_cor_err_cnt),
4284[C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4285 "CceCli1AsyncFifoDbgParityError", 0, 0,
4286 CNTR_NORMAL,
4287 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4288[C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4289 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4290 CNTR_NORMAL,
4291 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4292 ),
4293[C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4294 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4295 CNTR_NORMAL,
4296 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4297[C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4298 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4299 CNTR_NORMAL,
4300 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4301[C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4302 0, CNTR_NORMAL,
4303 access_cce_cli2_async_fifo_parity_err_cnt),
4304[C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4305 CNTR_NORMAL,
4306 access_cce_csr_cfg_bus_parity_err_cnt),
4307[C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4308 0, CNTR_NORMAL,
4309 access_cce_cli0_async_fifo_parity_err_cnt),
4310[C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4311 CNTR_NORMAL,
4312 access_cce_rspd_data_parity_err_cnt),
4313[C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4314 CNTR_NORMAL,
4315 access_cce_trgt_access_err_cnt),
4316[C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4317 0, CNTR_NORMAL,
4318 access_cce_trgt_async_fifo_parity_err_cnt),
4319[C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4320 CNTR_NORMAL,
4321 access_cce_csr_write_bad_addr_err_cnt),
4322[C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4323 CNTR_NORMAL,
4324 access_cce_csr_read_bad_addr_err_cnt),
4325[C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4326 CNTR_NORMAL,
4327 access_ccs_csr_parity_err_cnt),
4328
4329/* RcvErrStatus */
4330[C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4331 CNTR_NORMAL,
4332 access_rx_csr_parity_err_cnt),
4333[C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4334 CNTR_NORMAL,
4335 access_rx_csr_write_bad_addr_err_cnt),
4336[C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4337 CNTR_NORMAL,
4338 access_rx_csr_read_bad_addr_err_cnt),
4339[C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4340 CNTR_NORMAL,
4341 access_rx_dma_csr_unc_err_cnt),
4342[C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4343 CNTR_NORMAL,
4344 access_rx_dma_dq_fsm_encoding_err_cnt),
4345[C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4346 CNTR_NORMAL,
4347 access_rx_dma_eq_fsm_encoding_err_cnt),
4348[C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4349 CNTR_NORMAL,
4350 access_rx_dma_csr_parity_err_cnt),
4351[C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4352 CNTR_NORMAL,
4353 access_rx_rbuf_data_cor_err_cnt),
4354[C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4355 CNTR_NORMAL,
4356 access_rx_rbuf_data_unc_err_cnt),
4357[C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4358 CNTR_NORMAL,
4359 access_rx_dma_data_fifo_rd_cor_err_cnt),
4360[C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4361 CNTR_NORMAL,
4362 access_rx_dma_data_fifo_rd_unc_err_cnt),
4363[C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4364 CNTR_NORMAL,
4365 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4366[C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4367 CNTR_NORMAL,
4368 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4369[C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4370 CNTR_NORMAL,
4371 access_rx_rbuf_desc_part2_cor_err_cnt),
4372[C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4373 CNTR_NORMAL,
4374 access_rx_rbuf_desc_part2_unc_err_cnt),
4375[C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4376 CNTR_NORMAL,
4377 access_rx_rbuf_desc_part1_cor_err_cnt),
4378[C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4379 CNTR_NORMAL,
4380 access_rx_rbuf_desc_part1_unc_err_cnt),
4381[C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4382 CNTR_NORMAL,
4383 access_rx_hq_intr_fsm_err_cnt),
4384[C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4385 CNTR_NORMAL,
4386 access_rx_hq_intr_csr_parity_err_cnt),
4387[C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4388 CNTR_NORMAL,
4389 access_rx_lookup_csr_parity_err_cnt),
4390[C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4391 CNTR_NORMAL,
4392 access_rx_lookup_rcv_array_cor_err_cnt),
4393[C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4394 CNTR_NORMAL,
4395 access_rx_lookup_rcv_array_unc_err_cnt),
4396[C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4397 0, CNTR_NORMAL,
4398 access_rx_lookup_des_part2_parity_err_cnt),
4399[C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4400 0, CNTR_NORMAL,
4401 access_rx_lookup_des_part1_unc_cor_err_cnt),
4402[C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4403 CNTR_NORMAL,
4404 access_rx_lookup_des_part1_unc_err_cnt),
4405[C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4406 CNTR_NORMAL,
4407 access_rx_rbuf_next_free_buf_cor_err_cnt),
4408[C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4409 CNTR_NORMAL,
4410 access_rx_rbuf_next_free_buf_unc_err_cnt),
4411[C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4412 "RxRbufFlInitWrAddrParityErr", 0, 0,
4413 CNTR_NORMAL,
4414 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4415[C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4416 0, CNTR_NORMAL,
4417 access_rx_rbuf_fl_initdone_parity_err_cnt),
4418[C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4419 0, CNTR_NORMAL,
4420 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4421[C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4422 CNTR_NORMAL,
4423 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4424[C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4425 CNTR_NORMAL,
4426 access_rx_rbuf_empty_err_cnt),
4427[C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4428 CNTR_NORMAL,
4429 access_rx_rbuf_full_err_cnt),
4430[C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4431 CNTR_NORMAL,
4432 access_rbuf_bad_lookup_err_cnt),
4433[C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4434 CNTR_NORMAL,
4435 access_rbuf_ctx_id_parity_err_cnt),
4436[C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4437 CNTR_NORMAL,
4438 access_rbuf_csr_qeopdw_parity_err_cnt),
4439[C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4440 "RxRbufCsrQNumOfPktParityErr", 0, 0,
4441 CNTR_NORMAL,
4442 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4443[C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4444 "RxRbufCsrQTlPtrParityErr", 0, 0,
4445 CNTR_NORMAL,
4446 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4447[C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4448 0, CNTR_NORMAL,
4449 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4450[C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4451 0, CNTR_NORMAL,
4452 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4453[C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4454 0, 0, CNTR_NORMAL,
4455 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4456[C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4457 0, CNTR_NORMAL,
4458 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4459[C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4460 "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4461 CNTR_NORMAL,
4462 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4463[C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4464 0, CNTR_NORMAL,
4465 access_rx_rbuf_block_list_read_cor_err_cnt),
4466[C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4467 0, CNTR_NORMAL,
4468 access_rx_rbuf_block_list_read_unc_err_cnt),
4469[C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4470 CNTR_NORMAL,
4471 access_rx_rbuf_lookup_des_cor_err_cnt),
4472[C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4473 CNTR_NORMAL,
4474 access_rx_rbuf_lookup_des_unc_err_cnt),
4475[C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4476 "RxRbufLookupDesRegUncCorErr", 0, 0,
4477 CNTR_NORMAL,
4478 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4479[C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4480 CNTR_NORMAL,
4481 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4482[C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4483 CNTR_NORMAL,
4484 access_rx_rbuf_free_list_cor_err_cnt),
4485[C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4486 CNTR_NORMAL,
4487 access_rx_rbuf_free_list_unc_err_cnt),
4488[C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4489 CNTR_NORMAL,
4490 access_rx_rcv_fsm_encoding_err_cnt),
4491[C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4492 CNTR_NORMAL,
4493 access_rx_dma_flag_cor_err_cnt),
4494[C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4495 CNTR_NORMAL,
4496 access_rx_dma_flag_unc_err_cnt),
4497[C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4498 CNTR_NORMAL,
4499 access_rx_dc_sop_eop_parity_err_cnt),
4500[C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4501 CNTR_NORMAL,
4502 access_rx_rcv_csr_parity_err_cnt),
4503[C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4504 CNTR_NORMAL,
4505 access_rx_rcv_qp_map_table_cor_err_cnt),
4506[C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4507 CNTR_NORMAL,
4508 access_rx_rcv_qp_map_table_unc_err_cnt),
4509[C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4510 CNTR_NORMAL,
4511 access_rx_rcv_data_cor_err_cnt),
4512[C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4513 CNTR_NORMAL,
4514 access_rx_rcv_data_unc_err_cnt),
4515[C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4516 CNTR_NORMAL,
4517 access_rx_rcv_hdr_cor_err_cnt),
4518[C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4519 CNTR_NORMAL,
4520 access_rx_rcv_hdr_unc_err_cnt),
4521[C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4522 CNTR_NORMAL,
4523 access_rx_dc_intf_parity_err_cnt),
4524[C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4525 CNTR_NORMAL,
4526 access_rx_dma_csr_cor_err_cnt),
4527/* SendPioErrStatus */
4528[C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4529 CNTR_NORMAL,
4530 access_pio_pec_sop_head_parity_err_cnt),
4531[C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4532 CNTR_NORMAL,
4533 access_pio_pcc_sop_head_parity_err_cnt),
4534[C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4535 0, 0, CNTR_NORMAL,
4536 access_pio_last_returned_cnt_parity_err_cnt),
4537[C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4538 0, CNTR_NORMAL,
4539 access_pio_current_free_cnt_parity_err_cnt),
4540[C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4541 CNTR_NORMAL,
4542 access_pio_reserved_31_err_cnt),
4543[C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4544 CNTR_NORMAL,
4545 access_pio_reserved_30_err_cnt),
4546[C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4547 CNTR_NORMAL,
4548 access_pio_ppmc_sop_len_err_cnt),
4549[C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4550 CNTR_NORMAL,
4551 access_pio_ppmc_bqc_mem_parity_err_cnt),
4552[C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4553 CNTR_NORMAL,
4554 access_pio_vl_fifo_parity_err_cnt),
4555[C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4556 CNTR_NORMAL,
4557 access_pio_vlf_sop_parity_err_cnt),
4558[C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4559 CNTR_NORMAL,
4560 access_pio_vlf_v1_len_parity_err_cnt),
4561[C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4562 CNTR_NORMAL,
4563 access_pio_block_qw_count_parity_err_cnt),
4564[C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4565 CNTR_NORMAL,
4566 access_pio_write_qw_valid_parity_err_cnt),
4567[C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4568 CNTR_NORMAL,
4569 access_pio_state_machine_err_cnt),
4570[C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4571 CNTR_NORMAL,
4572 access_pio_write_data_parity_err_cnt),
4573[C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4574 CNTR_NORMAL,
4575 access_pio_host_addr_mem_cor_err_cnt),
4576[C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4577 CNTR_NORMAL,
4578 access_pio_host_addr_mem_unc_err_cnt),
4579[C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4580 CNTR_NORMAL,
4581 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4582[C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4583 CNTR_NORMAL,
4584 access_pio_init_sm_in_err_cnt),
4585[C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4586 CNTR_NORMAL,
4587 access_pio_ppmc_pbl_fifo_err_cnt),
4588[C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4589 0, CNTR_NORMAL,
4590 access_pio_credit_ret_fifo_parity_err_cnt),
4591[C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4592 CNTR_NORMAL,
4593 access_pio_v1_len_mem_bank1_cor_err_cnt),
4594[C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4595 CNTR_NORMAL,
4596 access_pio_v1_len_mem_bank0_cor_err_cnt),
4597[C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4598 CNTR_NORMAL,
4599 access_pio_v1_len_mem_bank1_unc_err_cnt),
4600[C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4601 CNTR_NORMAL,
4602 access_pio_v1_len_mem_bank0_unc_err_cnt),
4603[C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4604 CNTR_NORMAL,
4605 access_pio_sm_pkt_reset_parity_err_cnt),
4606[C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4607 CNTR_NORMAL,
4608 access_pio_pkt_evict_fifo_parity_err_cnt),
4609[C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4610 "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4611 CNTR_NORMAL,
4612 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4613[C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4614 CNTR_NORMAL,
4615 access_pio_sbrdctl_crrel_parity_err_cnt),
4616[C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4617 CNTR_NORMAL,
4618 access_pio_pec_fifo_parity_err_cnt),
4619[C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4620 CNTR_NORMAL,
4621 access_pio_pcc_fifo_parity_err_cnt),
4622[C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4623 CNTR_NORMAL,
4624 access_pio_sb_mem_fifo1_err_cnt),
4625[C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4626 CNTR_NORMAL,
4627 access_pio_sb_mem_fifo0_err_cnt),
4628[C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4629 CNTR_NORMAL,
4630 access_pio_csr_parity_err_cnt),
4631[C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4632 CNTR_NORMAL,
4633 access_pio_write_addr_parity_err_cnt),
4634[C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4635 CNTR_NORMAL,
4636 access_pio_write_bad_ctxt_err_cnt),
4637/* SendDmaErrStatus */
4638[C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4639 0, CNTR_NORMAL,
4640 access_sdma_pcie_req_tracking_cor_err_cnt),
4641[C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4642 0, CNTR_NORMAL,
4643 access_sdma_pcie_req_tracking_unc_err_cnt),
4644[C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4645 CNTR_NORMAL,
4646 access_sdma_csr_parity_err_cnt),
4647[C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4648 CNTR_NORMAL,
4649 access_sdma_rpy_tag_err_cnt),
4650/* SendEgressErrStatus */
4651[C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4652 CNTR_NORMAL,
4653 access_tx_read_pio_memory_csr_unc_err_cnt),
4654[C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4655 0, CNTR_NORMAL,
4656 access_tx_read_sdma_memory_csr_err_cnt),
4657[C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4658 CNTR_NORMAL,
4659 access_tx_egress_fifo_cor_err_cnt),
4660[C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4661 CNTR_NORMAL,
4662 access_tx_read_pio_memory_cor_err_cnt),
4663[C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4664 CNTR_NORMAL,
4665 access_tx_read_sdma_memory_cor_err_cnt),
4666[C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4667 CNTR_NORMAL,
4668 access_tx_sb_hdr_cor_err_cnt),
4669[C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4670 CNTR_NORMAL,
4671 access_tx_credit_overrun_err_cnt),
4672[C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4673 CNTR_NORMAL,
4674 access_tx_launch_fifo8_cor_err_cnt),
4675[C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4676 CNTR_NORMAL,
4677 access_tx_launch_fifo7_cor_err_cnt),
4678[C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4679 CNTR_NORMAL,
4680 access_tx_launch_fifo6_cor_err_cnt),
4681[C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4682 CNTR_NORMAL,
4683 access_tx_launch_fifo5_cor_err_cnt),
4684[C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4685 CNTR_NORMAL,
4686 access_tx_launch_fifo4_cor_err_cnt),
4687[C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4688 CNTR_NORMAL,
4689 access_tx_launch_fifo3_cor_err_cnt),
4690[C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4691 CNTR_NORMAL,
4692 access_tx_launch_fifo2_cor_err_cnt),
4693[C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4694 CNTR_NORMAL,
4695 access_tx_launch_fifo1_cor_err_cnt),
4696[C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4697 CNTR_NORMAL,
4698 access_tx_launch_fifo0_cor_err_cnt),
4699[C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4700 CNTR_NORMAL,
4701 access_tx_credit_return_vl_err_cnt),
4702[C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4703 CNTR_NORMAL,
4704 access_tx_hcrc_insertion_err_cnt),
4705[C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4706 CNTR_NORMAL,
4707 access_tx_egress_fifo_unc_err_cnt),
4708[C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4709 CNTR_NORMAL,
4710 access_tx_read_pio_memory_unc_err_cnt),
4711[C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4712 CNTR_NORMAL,
4713 access_tx_read_sdma_memory_unc_err_cnt),
4714[C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4715 CNTR_NORMAL,
4716 access_tx_sb_hdr_unc_err_cnt),
4717[C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4718 CNTR_NORMAL,
4719 access_tx_credit_return_partiy_err_cnt),
4720[C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4721 0, 0, CNTR_NORMAL,
4722 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4723[C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4724 0, 0, CNTR_NORMAL,
4725 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4726[C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4727 0, 0, CNTR_NORMAL,
4728 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4729[C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4730 0, 0, CNTR_NORMAL,
4731 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4732[C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4733 0, 0, CNTR_NORMAL,
4734 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4735[C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4736 0, 0, CNTR_NORMAL,
4737 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4738[C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4739 0, 0, CNTR_NORMAL,
4740 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4741[C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4742 0, 0, CNTR_NORMAL,
4743 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4744[C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4745 0, 0, CNTR_NORMAL,
4746 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4747[C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4748 0, 0, CNTR_NORMAL,
4749 access_tx_sdma15_disallowed_packet_err_cnt),
4750[C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4751 0, 0, CNTR_NORMAL,
4752 access_tx_sdma14_disallowed_packet_err_cnt),
4753[C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4754 0, 0, CNTR_NORMAL,
4755 access_tx_sdma13_disallowed_packet_err_cnt),
4756[C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4757 0, 0, CNTR_NORMAL,
4758 access_tx_sdma12_disallowed_packet_err_cnt),
4759[C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4760 0, 0, CNTR_NORMAL,
4761 access_tx_sdma11_disallowed_packet_err_cnt),
4762[C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4763 0, 0, CNTR_NORMAL,
4764 access_tx_sdma10_disallowed_packet_err_cnt),
4765[C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4766 0, 0, CNTR_NORMAL,
4767 access_tx_sdma9_disallowed_packet_err_cnt),
4768[C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4769 0, 0, CNTR_NORMAL,
4770 access_tx_sdma8_disallowed_packet_err_cnt),
4771[C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4772 0, 0, CNTR_NORMAL,
4773 access_tx_sdma7_disallowed_packet_err_cnt),
4774[C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4775 0, 0, CNTR_NORMAL,
4776 access_tx_sdma6_disallowed_packet_err_cnt),
4777[C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4778 0, 0, CNTR_NORMAL,
4779 access_tx_sdma5_disallowed_packet_err_cnt),
4780[C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4781 0, 0, CNTR_NORMAL,
4782 access_tx_sdma4_disallowed_packet_err_cnt),
4783[C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4784 0, 0, CNTR_NORMAL,
4785 access_tx_sdma3_disallowed_packet_err_cnt),
4786[C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4787 0, 0, CNTR_NORMAL,
4788 access_tx_sdma2_disallowed_packet_err_cnt),
4789[C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4790 0, 0, CNTR_NORMAL,
4791 access_tx_sdma1_disallowed_packet_err_cnt),
4792[C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4793 0, 0, CNTR_NORMAL,
4794 access_tx_sdma0_disallowed_packet_err_cnt),
4795[C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4796 CNTR_NORMAL,
4797 access_tx_config_parity_err_cnt),
4798[C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4799 CNTR_NORMAL,
4800 access_tx_sbrd_ctl_csr_parity_err_cnt),
4801[C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4802 CNTR_NORMAL,
4803 access_tx_launch_csr_parity_err_cnt),
4804[C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4805 CNTR_NORMAL,
4806 access_tx_illegal_vl_err_cnt),
4807[C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4808 "TxSbrdCtlStateMachineParityErr", 0, 0,
4809 CNTR_NORMAL,
4810 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4811[C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4812 CNTR_NORMAL,
4813 access_egress_reserved_10_err_cnt),
4814[C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4815 CNTR_NORMAL,
4816 access_egress_reserved_9_err_cnt),
4817[C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4818 0, 0, CNTR_NORMAL,
4819 access_tx_sdma_launch_intf_parity_err_cnt),
4820[C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4821 CNTR_NORMAL,
4822 access_tx_pio_launch_intf_parity_err_cnt),
4823[C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4824 CNTR_NORMAL,
4825 access_egress_reserved_6_err_cnt),
4826[C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4827 CNTR_NORMAL,
4828 access_tx_incorrect_link_state_err_cnt),
4829[C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4830 CNTR_NORMAL,
4831 access_tx_linkdown_err_cnt),
4832[C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4833 "EgressFifoUnderrunOrParityErr", 0, 0,
4834 CNTR_NORMAL,
4835 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4836[C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4837 CNTR_NORMAL,
4838 access_egress_reserved_2_err_cnt),
4839[C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4840 CNTR_NORMAL,
4841 access_tx_pkt_integrity_mem_unc_err_cnt),
4842[C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4843 CNTR_NORMAL,
4844 access_tx_pkt_integrity_mem_cor_err_cnt),
4845/* SendErrStatus */
4846[C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4847 CNTR_NORMAL,
4848 access_send_csr_write_bad_addr_err_cnt),
4849[C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4850 CNTR_NORMAL,
4851 access_send_csr_read_bad_addr_err_cnt),
4852[C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4853 CNTR_NORMAL,
4854 access_send_csr_parity_cnt),
4855/* SendCtxtErrStatus */
4856[C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4857 CNTR_NORMAL,
4858 access_pio_write_out_of_bounds_err_cnt),
4859[C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4860 CNTR_NORMAL,
4861 access_pio_write_overflow_err_cnt),
4862[C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4863 0, 0, CNTR_NORMAL,
4864 access_pio_write_crosses_boundary_err_cnt),
4865[C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4866 CNTR_NORMAL,
4867 access_pio_disallowed_packet_err_cnt),
4868[C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4869 CNTR_NORMAL,
4870 access_pio_inconsistent_sop_err_cnt),
4871/* SendDmaEngErrStatus */
4872[C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4873 0, 0, CNTR_NORMAL,
4874 access_sdma_header_request_fifo_cor_err_cnt),
4875[C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4876 CNTR_NORMAL,
4877 access_sdma_header_storage_cor_err_cnt),
4878[C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4879 CNTR_NORMAL,
4880 access_sdma_packet_tracking_cor_err_cnt),
4881[C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4882 CNTR_NORMAL,
4883 access_sdma_assembly_cor_err_cnt),
4884[C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
4885 CNTR_NORMAL,
4886 access_sdma_desc_table_cor_err_cnt),
4887[C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
4888 0, 0, CNTR_NORMAL,
4889 access_sdma_header_request_fifo_unc_err_cnt),
4890[C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
4891 CNTR_NORMAL,
4892 access_sdma_header_storage_unc_err_cnt),
4893[C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
4894 CNTR_NORMAL,
4895 access_sdma_packet_tracking_unc_err_cnt),
4896[C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
4897 CNTR_NORMAL,
4898 access_sdma_assembly_unc_err_cnt),
4899[C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
4900 CNTR_NORMAL,
4901 access_sdma_desc_table_unc_err_cnt),
4902[C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
4903 CNTR_NORMAL,
4904 access_sdma_timeout_err_cnt),
4905[C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
4906 CNTR_NORMAL,
4907 access_sdma_header_length_err_cnt),
4908[C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
4909 CNTR_NORMAL,
4910 access_sdma_header_address_err_cnt),
4911[C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
4912 CNTR_NORMAL,
4913 access_sdma_header_select_err_cnt),
4914[C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
4915 CNTR_NORMAL,
4916 access_sdma_reserved_9_err_cnt),
4917[C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
4918 CNTR_NORMAL,
4919 access_sdma_packet_desc_overflow_err_cnt),
4920[C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
4921 CNTR_NORMAL,
4922 access_sdma_length_mismatch_err_cnt),
4923[C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
4924 CNTR_NORMAL,
4925 access_sdma_halt_err_cnt),
4926[C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
4927 CNTR_NORMAL,
4928 access_sdma_mem_read_err_cnt),
4929[C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
4930 CNTR_NORMAL,
4931 access_sdma_first_desc_err_cnt),
4932[C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
4933 CNTR_NORMAL,
4934 access_sdma_tail_out_of_bounds_err_cnt),
4935[C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
4936 CNTR_NORMAL,
4937 access_sdma_too_long_err_cnt),
4938[C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
4939 CNTR_NORMAL,
4940 access_sdma_gen_mismatch_err_cnt),
4941[C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
4942 CNTR_NORMAL,
4943 access_sdma_wrong_dw_err_cnt),
77241056
MM		 4944};
4945
4946static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
4947[C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
4948 CNTR_NORMAL),
4949[C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
4950 CNTR_NORMAL),
4951[C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
4952 CNTR_NORMAL),
4953[C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
4954 CNTR_NORMAL),
4955[C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
4956 CNTR_NORMAL),
4957[C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
4958 CNTR_NORMAL),
4959[C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
4960 CNTR_NORMAL),
4961[C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
4962[C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
4963[C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
4964[C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
17fb4f29 4965 CNTR_SYNTH | CNTR_VL),
77241056 4966[C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
17fb4f29 4967 CNTR_SYNTH | CNTR_VL),
77241056 4968[C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
17fb4f29 4969 CNTR_SYNTH | CNTR_VL),
77241056
MM		 4970[C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
4971[C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
4972[C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 4973 access_sw_link_dn_cnt),
77241056 4974[C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 4975 access_sw_link_up_cnt),
6d014530
DL		 4976[C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
4977 access_sw_unknown_frame_cnt),
77241056 4978[C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
17fb4f29 4979 access_sw_xmit_discards),
77241056 4980[C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
17fb4f29
JJ		 4981 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
4982 access_sw_xmit_discards),
77241056 4983[C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
17fb4f29 4984 access_xmit_constraint_errs),
77241056 4985[C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
17fb4f29 4986 access_rcv_constraint_errs),
77241056
MM		 4987[C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
4988[C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
4989[C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
4990[C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
4991[C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
4992[C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
4993[C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
4994[C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
4995[C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
4996[C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
4997[C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
4998[C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
4999[C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
5000 access_sw_cpu_rc_acks),
5001[C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
17fb4f29 5002 access_sw_cpu_rc_qacks),
77241056 5003[C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
17fb4f29 5004 access_sw_cpu_rc_delayed_comp),
77241056
MM		 5005[OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5006[OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5007[OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5008[OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5009[OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5010[OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5011[OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5012[OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5013[OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5014[OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5015[OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5016[OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5017[OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5018[OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5019[OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5020[OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5021[OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5022[OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5023[OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5024[OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5025[OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5026[OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5027[OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5028[OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5029[OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5030[OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5031[OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5032[OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5033[OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5034[OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5035[OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5036[OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5037[OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5038[OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5039[OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5040[OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5041[OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5042[OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5043[OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5044[OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5045[OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5046[OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5047[OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5048[OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5049[OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5050[OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5051[OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5052[OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5053[OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5054[OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5055[OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5056[OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5057[OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5058[OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5059[OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5060[OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5061[OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5062[OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5063[OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5064[OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5065[OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5066[OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5067[OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5068[OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5069[OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5070[OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5071[OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5072[OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5073[OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5074[OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5075[OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5076[OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5077[OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5078[OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5079[OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5080[OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5081[OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5082[OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5083[OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5084[OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5085};
5086
5087/* ======================================================================== */
5088
77241056
MM		 5089/* return true if this is chip revision revision a */
5090int is_ax(struct hfi1_devdata *dd)
5091{
5092 u8 chip_rev_minor =
5093 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5094 & CCE_REVISION_CHIP_REV_MINOR_MASK;
5095 return (chip_rev_minor & 0xf0) == 0;
5096}
5097
5098/* return true if this is chip revision revision b */
5099int is_bx(struct hfi1_devdata *dd)
5100{
5101 u8 chip_rev_minor =
5102 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5103 & CCE_REVISION_CHIP_REV_MINOR_MASK;
995deafa 5104 return (chip_rev_minor & 0xF0) == 0x10;
77241056
MM		 5105}
5106
5107/*
5108 * Append string s to buffer buf. Arguments curp and len are the current
5109 * position and remaining length, respectively.
5110 *
5111 * return 0 on success, 1 on out of room
5112 */
5113static int append_str(char *buf, char **curp, int *lenp, const char *s)
5114{
5115 char *p = *curp;
5116 int len = *lenp;
5117 int result = 0; /* success */
5118 char c;
5119
5120 /* add a comma, if first in the buffer */
5121 if (p != buf) {
5122 if (len == 0) {
5123 result = 1; /* out of room */
5124 goto done;
5125 }
5126 *p++ = ',';
5127 len--;
5128 }
5129
5130 /* copy the string */
5131 while ((c = *s++) != 0) {
5132 if (len == 0) {
5133 result = 1; /* out of room */
5134 goto done;
5135 }
5136 *p++ = c;
5137 len--;
5138 }
5139
5140done:
5141 /* write return values */
5142 *curp = p;
5143 *lenp = len;
5144
5145 return result;
5146}
5147
5148/*
5149 * Using the given flag table, print a comma separated string into
5150 * the buffer. End in '*' if the buffer is too short.
5151 */
5152static char *flag_string(char *buf, int buf_len, u64 flags,
17fb4f29 5153 struct flag_table *table, int table_size)
77241056
MM		 5154{
5155 char extra[32];
5156 char *p = buf;
5157 int len = buf_len;
5158 int no_room = 0;
5159 int i;
5160
5161 /* make sure there is at least 2 so we can form "*" */
5162 if (len < 2)
5163 return "";
5164
5165 len--; /* leave room for a nul */
5166 for (i = 0; i < table_size; i++) {
5167 if (flags & table[i].flag) {
5168 no_room = append_str(buf, &p, &len, table[i].str);
5169 if (no_room)
5170 break;
5171 flags &= ~table[i].flag;
5172 }
5173 }
5174
5175 /* any undocumented bits left? */
5176 if (!no_room && flags) {
5177 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5178 no_room = append_str(buf, &p, &len, extra);
5179 }
5180
5181 /* add * if ran out of room */
5182 if (no_room) {
5183 /* may need to back up to add space for a '*' */
5184 if (len == 0)
5185 --p;
5186 *p++ = '*';
5187 }
5188
5189 /* add final nul - space already allocated above */
5190 *p = 0;
5191 return buf;
5192}
5193
5194/* first 8 CCE error interrupt source names */
5195static const char * const cce_misc_names[] = {
5196 "CceErrInt", /* 0 */
5197 "RxeErrInt", /* 1 */
5198 "MiscErrInt", /* 2 */
5199 "Reserved3", /* 3 */
5200 "PioErrInt", /* 4 */
5201 "SDmaErrInt", /* 5 */
5202 "EgressErrInt", /* 6 */
5203 "TxeErrInt" /* 7 */
5204};
5205
5206/*
5207 * Return the miscellaneous error interrupt name.
5208 */
5209static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5210{
5211 if (source < ARRAY_SIZE(cce_misc_names))
5212 strncpy(buf, cce_misc_names[source], bsize);
5213 else
17fb4f29
JJ		 5214 snprintf(buf, bsize, "Reserved%u",
5215 source + IS_GENERAL_ERR_START);
77241056
MM		 5216
5217 return buf;
5218}
5219
5220/*
5221 * Return the SDMA engine error interrupt name.
5222 */
5223static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5224{
5225 snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5226 return buf;
5227}
5228
5229/*
5230 * Return the send context error interrupt name.
5231 */
5232static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5233{
5234 snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5235 return buf;
5236}
5237
5238static const char * const various_names[] = {
5239 "PbcInt",
5240 "GpioAssertInt",
5241 "Qsfp1Int",
5242 "Qsfp2Int",
5243 "TCritInt"
5244};
5245
5246/*
5247 * Return the various interrupt name.
5248 */
5249static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5250{
5251 if (source < ARRAY_SIZE(various_names))
5252 strncpy(buf, various_names[source], bsize);
5253 else
8638b77f 5254 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
77241056
MM		 5255 return buf;
5256}
5257
5258/*
5259 * Return the DC interrupt name.
5260 */
5261static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5262{
5263 static const char * const dc_int_names[] = {
5264 "common",
5265 "lcb",
5266 "8051",
5267 "lbm" /* local block merge */
5268 };
5269
5270 if (source < ARRAY_SIZE(dc_int_names))
5271 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5272 else
5273 snprintf(buf, bsize, "DCInt%u", source);
5274 return buf;
5275}
5276
5277static const char * const sdma_int_names[] = {
5278 "SDmaInt",
5279 "SdmaIdleInt",
5280 "SdmaProgressInt",
5281};
5282
5283/*
5284 * Return the SDMA engine interrupt name.
5285 */
5286static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5287{
5288 /* what interrupt */
5289 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
5290 /* which engine */
5291 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5292
5293 if (likely(what < 3))
5294 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5295 else
5296 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5297 return buf;
5298}
5299
5300/*
5301 * Return the receive available interrupt name.
5302 */
5303static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5304{
5305 snprintf(buf, bsize, "RcvAvailInt%u", source);
5306 return buf;
5307}
5308
5309/*
5310 * Return the receive urgent interrupt name.
5311 */
5312static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5313{
5314 snprintf(buf, bsize, "RcvUrgentInt%u", source);
5315 return buf;
5316}
5317
5318/*
5319 * Return the send credit interrupt name.
5320 */
5321static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5322{
5323 snprintf(buf, bsize, "SendCreditInt%u", source);
5324 return buf;
5325}
5326
5327/*
5328 * Return the reserved interrupt name.
5329 */
5330static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5331{
5332 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5333 return buf;
5334}
5335
5336static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5337{
5338 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5339 cce_err_status_flags,
5340 ARRAY_SIZE(cce_err_status_flags));
77241056
MM		 5341}
5342
5343static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5344{
5345 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5346 rxe_err_status_flags,
5347 ARRAY_SIZE(rxe_err_status_flags));
77241056
MM		 5348}
5349
5350static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5351{
5352 return flag_string(buf, buf_len, flags, misc_err_status_flags,
17fb4f29 5353 ARRAY_SIZE(misc_err_status_flags));
77241056
MM		 5354}
5355
5356static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5357{
5358 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5359 pio_err_status_flags,
5360 ARRAY_SIZE(pio_err_status_flags));
77241056
MM		 5361}
5362
5363static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5364{
5365 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5366 sdma_err_status_flags,
5367 ARRAY_SIZE(sdma_err_status_flags));
77241056
MM		 5368}
5369
5370static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5371{
5372 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5373 egress_err_status_flags,
5374 ARRAY_SIZE(egress_err_status_flags));
77241056
MM		 5375}
5376
5377static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5378{
5379 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5380 egress_err_info_flags,
5381 ARRAY_SIZE(egress_err_info_flags));
77241056
MM		 5382}
5383
5384static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5385{
5386 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5387 send_err_status_flags,
5388 ARRAY_SIZE(send_err_status_flags));
77241056
MM		 5389}
5390
5391static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5392{
5393 char buf[96];
2c5b521a 5394 int i = 0;
77241056
MM		 5395
5396 /*
5397 * For most these errors, there is nothing that can be done except
5398 * report or record it.
5399 */
5400 dd_dev_info(dd, "CCE Error: %s\n",
17fb4f29 5401 cce_err_status_string(buf, sizeof(buf), reg));
77241056 5402
995deafa
MM		 5403 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5404 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
77241056
MM		 5405 /* this error requires a manual drop into SPC freeze mode */
5406 /* then a fix up */
5407 start_freeze_handling(dd->pport, FREEZE_SELF);
5408 }
2c5b521a
JR		 5409
5410 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5411 if (reg & (1ull << i)) {
5412 incr_cntr64(&dd->cce_err_status_cnt[i]);
5413 /* maintain a counter over all cce_err_status errors */
5414 incr_cntr64(&dd->sw_cce_err_status_aggregate);
5415 }
5416 }
77241056
MM		 5417}
5418
5419/*
5420 * Check counters for receive errors that do not have an interrupt
5421 * associated with them.
5422 */
5423#define RCVERR_CHECK_TIME 10
5424static void update_rcverr_timer(unsigned long opaque)
5425{
5426 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
5427 struct hfi1_pportdata *ppd = dd->pport;
5428 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5429
5430 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
17fb4f29 5431 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
77241056 5432 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
17fb4f29
JJ		 5433 set_link_down_reason(
5434 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5435 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
77241056
MM		 5436 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
5437 }
50e5dcbe 5438 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
77241056
MM		 5439
5440 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5441}
5442
5443static int init_rcverr(struct hfi1_devdata *dd)
5444{
24523a94 5445 setup_timer(&dd->rcverr_timer, update_rcverr_timer, (unsigned long)dd);
77241056
MM		 5446 /* Assume the hardware counter has been reset */
5447 dd->rcv_ovfl_cnt = 0;
5448 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5449}
5450
5451static void free_rcverr(struct hfi1_devdata *dd)
5452{
5453 if (dd->rcverr_timer.data)
5454 del_timer_sync(&dd->rcverr_timer);
5455 dd->rcverr_timer.data = 0;
5456}
5457
5458static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5459{
5460 char buf[96];
2c5b521a 5461 int i = 0;
77241056
MM		 5462
5463 dd_dev_info(dd, "Receive Error: %s\n",
17fb4f29 5464 rxe_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5465
5466 if (reg & ALL_RXE_FREEZE_ERR) {
5467 int flags = 0;
5468
5469 /*
5470 * Freeze mode recovery is disabled for the errors
5471 * in RXE_FREEZE_ABORT_MASK
5472 */
995deafa 5473 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
77241056
MM		 5474 flags = FREEZE_ABORT;
5475
5476 start_freeze_handling(dd->pport, flags);
5477 }
2c5b521a
JR		 5478
5479 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5480 if (reg & (1ull << i))
5481 incr_cntr64(&dd->rcv_err_status_cnt[i]);
5482 }
77241056
MM		 5483}
5484
5485static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5486{
5487 char buf[96];
2c5b521a 5488 int i = 0;
77241056
MM		 5489
5490 dd_dev_info(dd, "Misc Error: %s",
17fb4f29 5491 misc_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5492 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5493 if (reg & (1ull << i))
5494 incr_cntr64(&dd->misc_err_status_cnt[i]);
5495 }
77241056
MM		 5496}
5497
5498static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5499{
5500 char buf[96];
2c5b521a 5501 int i = 0;
77241056
MM		 5502
5503 dd_dev_info(dd, "PIO Error: %s\n",
17fb4f29 5504 pio_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5505
5506 if (reg & ALL_PIO_FREEZE_ERR)
5507 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5508
5509 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5510 if (reg & (1ull << i))
5511 incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5512 }
77241056
MM		 5513}
5514
5515static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5516{
5517 char buf[96];
2c5b521a 5518 int i = 0;
77241056
MM		 5519
5520 dd_dev_info(dd, "SDMA Error: %s\n",
17fb4f29 5521 sdma_err_status_string(buf, sizeof(buf), reg));
77241056
MM		 5522
5523 if (reg & ALL_SDMA_FREEZE_ERR)
5524 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5525
5526 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5527 if (reg & (1ull << i))
5528 incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5529 }
77241056
MM		 5530}
5531
69a00b8e 5532static inline void __count_port_discards(struct hfi1_pportdata *ppd)
77241056 5533{
69a00b8e
MM		 5534 incr_cntr64(&ppd->port_xmit_discards);
5535}
77241056 5536
69a00b8e
MM		 5537static void count_port_inactive(struct hfi1_devdata *dd)
5538{
5539 __count_port_discards(dd->pport);
77241056
MM		 5540}
5541
5542/*
5543 * We have had a "disallowed packet" error during egress. Determine the
5544 * integrity check which failed, and update relevant error counter, etc.
5545 *
5546 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5547 * bit of state per integrity check, and so we can miss the reason for an
5548 * egress error if more than one packet fails the same integrity check
5549 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5550 */
69a00b8e
MM		 5551static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5552 int vl)
77241056
MM		 5553{
5554 struct hfi1_pportdata *ppd = dd->pport;
5555 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5556 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5557 char buf[96];
5558
5559 /* clear down all observed info as quickly as possible after read */
5560 write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5561
5562 dd_dev_info(dd,
17fb4f29
JJ		 5563 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5564 info, egress_err_info_string(buf, sizeof(buf), info), src);
77241056
MM		 5565
5566 /* Eventually add other counters for each bit */
69a00b8e
MM		 5567 if (info & PORT_DISCARD_EGRESS_ERRS) {
5568 int weight, i;
77241056 5569
69a00b8e 5570 /*
4c9e7aac
DL		 5571 * Count all applicable bits as individual errors and
5572 * attribute them to the packet that triggered this handler.
5573 * This may not be completely accurate due to limitations
5574 * on the available hardware error information. There is
5575 * a single information register and any number of error
5576 * packets may have occurred and contributed to it before
5577 * this routine is called. This means that:
5578 * a) If multiple packets with the same error occur before
5579 * this routine is called, earlier packets are missed.
5580 * There is only a single bit for each error type.
5581 * b) Errors may not be attributed to the correct VL.
5582 * The driver is attributing all bits in the info register
5583 * to the packet that triggered this call, but bits
5584 * could be an accumulation of different packets with
5585 * different VLs.
5586 * c) A single error packet may have multiple counts attached
5587 * to it. There is no way for the driver to know if
5588 * multiple bits set in the info register are due to a
5589 * single packet or multiple packets. The driver assumes
5590 * multiple packets.
69a00b8e 5591 */
4c9e7aac 5592 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS);
69a00b8e
MM		 5593 for (i = 0; i < weight; i++) {
5594 __count_port_discards(ppd);
5595 if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5596 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5597 else if (vl == 15)
5598 incr_cntr64(&ppd->port_xmit_discards_vl
5599 [C_VL_15]);
5600 }
77241056
MM		 5601 }
5602}
5603
5604/*
5605 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5606 * register. Does it represent a 'port inactive' error?
5607 */
5608static inline int port_inactive_err(u64 posn)
5609{
5610 return (posn >= SEES(TX_LINKDOWN) &&
5611 posn <= SEES(TX_INCORRECT_LINK_STATE));
5612}
5613
5614/*
5615 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5616 * register. Does it represent a 'disallowed packet' error?
5617 */
69a00b8e 5618static inline int disallowed_pkt_err(int posn)
77241056
MM		 5619{
5620 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5621 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5622}
5623
69a00b8e
MM		 5624/*
5625 * Input value is a bit position of one of the SDMA engine disallowed
5626 * packet errors. Return which engine. Use of this must be guarded by
5627 * disallowed_pkt_err().
5628 */
5629static inline int disallowed_pkt_engine(int posn)
5630{
5631 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5632}
5633
5634/*
5635 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5636 * be done.
5637 */
5638static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5639{
5640 struct sdma_vl_map *m;
5641 int vl;
5642
5643 /* range check */
5644 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5645 return -1;
5646
5647 rcu_read_lock();
5648 m = rcu_dereference(dd->sdma_map);
5649 vl = m->engine_to_vl[engine];
5650 rcu_read_unlock();
5651
5652 return vl;
5653}
5654
5655/*
5656 * Translate the send context (sofware index) into a VL. Return -1 if the
5657 * translation cannot be done.
5658 */
5659static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5660{
5661 struct send_context_info *sci;
5662 struct send_context *sc;
5663 int i;
5664
5665 sci = &dd->send_contexts[sw_index];
5666
5667 /* there is no information for user (PSM) and ack contexts */
44306f15 5668 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15))
69a00b8e
MM		 5669 return -1;
5670
5671 sc = sci->sc;
5672 if (!sc)
5673 return -1;
5674 if (dd->vld[15].sc == sc)
5675 return 15;
5676 for (i = 0; i < num_vls; i++)
5677 if (dd->vld[i].sc == sc)
5678 return i;
5679
5680 return -1;
5681}
5682
77241056
MM		 5683static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5684{
5685 u64 reg_copy = reg, handled = 0;
5686 char buf[96];
2c5b521a 5687 int i = 0;
77241056
MM		 5688
5689 if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5690 start_freeze_handling(dd->pport, 0);
69a00b8e
MM		 5691 else if (is_ax(dd) &&
5692 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5693 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
77241056
MM		 5694 start_freeze_handling(dd->pport, 0);
5695
5696 while (reg_copy) {
5697 int posn = fls64(reg_copy);
69a00b8e 5698 /* fls64() returns a 1-based offset, we want it zero based */
77241056 5699 int shift = posn - 1;
69a00b8e 5700 u64 mask = 1ULL << shift;
77241056
MM		 5701
5702 if (port_inactive_err(shift)) {
5703 count_port_inactive(dd);
69a00b8e 5704 handled |= mask;
77241056 5705 } else if (disallowed_pkt_err(shift)) {
69a00b8e
MM		 5706 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5707
5708 handle_send_egress_err_info(dd, vl);
5709 handled |= mask;
77241056 5710 }
69a00b8e 5711 reg_copy &= ~mask;
77241056
MM		 5712 }
5713
5714 reg &= ~handled;
5715
5716 if (reg)
5717 dd_dev_info(dd, "Egress Error: %s\n",
17fb4f29 5718 egress_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5719
5720 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5721 if (reg & (1ull << i))
5722 incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5723 }
77241056
MM		 5724}
5725
5726static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5727{
5728 char buf[96];
2c5b521a 5729 int i = 0;
77241056
MM		 5730
5731 dd_dev_info(dd, "Send Error: %s\n",
17fb4f29 5732 send_err_status_string(buf, sizeof(buf), reg));
77241056 5733
2c5b521a
JR		 5734 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5735 if (reg & (1ull << i))
5736 incr_cntr64(&dd->send_err_status_cnt[i]);
5737 }
77241056
MM		 5738}
5739
5740/*
5741 * The maximum number of times the error clear down will loop before
5742 * blocking a repeating error. This value is arbitrary.
5743 */
5744#define MAX_CLEAR_COUNT 20
5745
5746/*
5747 * Clear and handle an error register. All error interrupts are funneled
5748 * through here to have a central location to correctly handle single-
5749 * or multi-shot errors.
5750 *
5751 * For non per-context registers, call this routine with a context value
5752 * of 0 so the per-context offset is zero.
5753 *
5754 * If the handler loops too many times, assume that something is wrong
5755 * and can't be fixed, so mask the error bits.
5756 */
5757static void interrupt_clear_down(struct hfi1_devdata *dd,
5758 u32 context,
5759 const struct err_reg_info *eri)
5760{
5761 u64 reg;
5762 u32 count;
5763
5764 /* read in a loop until no more errors are seen */
5765 count = 0;
5766 while (1) {
5767 reg = read_kctxt_csr(dd, context, eri->status);
5768 if (reg == 0)
5769 break;
5770 write_kctxt_csr(dd, context, eri->clear, reg);
5771 if (likely(eri->handler))
5772 eri->handler(dd, context, reg);
5773 count++;
5774 if (count > MAX_CLEAR_COUNT) {
5775 u64 mask;
5776
5777 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
17fb4f29 5778 eri->desc, reg);
77241056
MM		 5779 /*
5780 * Read-modify-write so any other masked bits
5781 * remain masked.
5782 */
5783 mask = read_kctxt_csr(dd, context, eri->mask);
5784 mask &= ~reg;
5785 write_kctxt_csr(dd, context, eri->mask, mask);
5786 break;
5787 }
5788 }
5789}
5790
5791/*
5792 * CCE block "misc" interrupt. Source is < 16.
5793 */
5794static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5795{
5796 const struct err_reg_info *eri = &misc_errs[source];
5797
5798 if (eri->handler) {
5799 interrupt_clear_down(dd, 0, eri);
5800 } else {
5801 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
17fb4f29 5802 source);
77241056
MM		 5803 }
5804}
5805
5806static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5807{
5808 return flag_string(buf, buf_len, flags,
17fb4f29
JJ		 5809 sc_err_status_flags,
5810 ARRAY_SIZE(sc_err_status_flags));
77241056
MM		 5811}
5812
5813/*
5814 * Send context error interrupt. Source (hw_context) is < 160.
5815 *
5816 * All send context errors cause the send context to halt. The normal
5817 * clear-down mechanism cannot be used because we cannot clear the
5818 * error bits until several other long-running items are done first.
5819 * This is OK because with the context halted, nothing else is going
5820 * to happen on it anyway.
5821 */
5822static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5823 unsigned int hw_context)
5824{
5825 struct send_context_info *sci;
5826 struct send_context *sc;
5827 char flags[96];
5828 u64 status;
5829 u32 sw_index;
2c5b521a 5830 int i = 0;
77241056
MM		 5831
5832 sw_index = dd->hw_to_sw[hw_context];
5833 if (sw_index >= dd->num_send_contexts) {
5834 dd_dev_err(dd,
17fb4f29
JJ		 5835 "out of range sw index %u for send context %u\n",
5836 sw_index, hw_context);
77241056
MM		 5837 return;
5838 }
5839 sci = &dd->send_contexts[sw_index];
5840 sc = sci->sc;
5841 if (!sc) {
5842 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
17fb4f29 5843 sw_index, hw_context);
77241056
MM		 5844 return;
5845 }
5846
5847 /* tell the software that a halt has begun */
5848 sc_stop(sc, SCF_HALTED);
5849
5850 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
5851
5852 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
17fb4f29
JJ		 5853 send_context_err_status_string(flags, sizeof(flags),
5854 status));
77241056
MM		 5855
5856 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
69a00b8e 5857 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
77241056
MM		 5858
5859 /*
5860 * Automatically restart halted kernel contexts out of interrupt
5861 * context. User contexts must ask the driver to restart the context.
5862 */
5863 if (sc->type != SC_USER)
5864 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
2c5b521a
JR		 5865
5866 /*
5867 * Update the counters for the corresponding status bits.
5868 * Note that these particular counters are aggregated over all
5869 * 160 contexts.
5870 */
5871 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
5872 if (status & (1ull << i))
5873 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
5874 }
77241056
MM		 5875}
5876
5877static void handle_sdma_eng_err(struct hfi1_devdata *dd,
5878 unsigned int source, u64 status)
5879{
5880 struct sdma_engine *sde;
2c5b521a 5881 int i = 0;
77241056
MM		 5882
5883 sde = &dd->per_sdma[source];
5884#ifdef CONFIG_SDMA_VERBOSITY
5885 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5886 slashstrip(__FILE__), __LINE__, __func__);
5887 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
5888 sde->this_idx, source, (unsigned long long)status);
5889#endif
a699c6c2 5890 sde->err_cnt++;
77241056 5891 sdma_engine_error(sde, status);
2c5b521a
JR		 5892
5893 /*
5894 * Update the counters for the corresponding status bits.
5895 * Note that these particular counters are aggregated over
5896 * all 16 DMA engines.
5897 */
5898 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
5899 if (status & (1ull << i))
5900 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
5901 }
77241056
MM		 5902}
5903
5904/*
5905 * CCE block SDMA error interrupt. Source is < 16.
5906 */
5907static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
5908{
5909#ifdef CONFIG_SDMA_VERBOSITY
5910 struct sdma_engine *sde = &dd->per_sdma[source];
5911
5912 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5913 slashstrip(__FILE__), __LINE__, __func__);
5914 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
5915 source);
5916 sdma_dumpstate(sde);
5917#endif
5918 interrupt_clear_down(dd, source, &sdma_eng_err);
5919}
5920
5921/*
5922 * CCE block "various" interrupt. Source is < 8.
5923 */
5924static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
5925{
5926 const struct err_reg_info *eri = &various_err[source];
5927
5928 /*
5929 * TCritInt cannot go through interrupt_clear_down()
5930 * because it is not a second tier interrupt. The handler
5931 * should be called directly.
5932 */
5933 if (source == TCRIT_INT_SOURCE)
5934 handle_temp_err(dd);
5935 else if (eri->handler)
5936 interrupt_clear_down(dd, 0, eri);
5937 else
5938 dd_dev_info(dd,
17fb4f29
JJ		 5939 "%s: Unimplemented/reserved interrupt %d\n",
5940 __func__, source);
77241056
MM		 5941}
5942
5943static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
5944{
8ebd4cf1 5945 /* src_ctx is always zero */
77241056
MM		 5946 struct hfi1_pportdata *ppd = dd->pport;
5947 unsigned long flags;
5948 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
5949
5950 if (reg & QSFP_HFI0_MODPRST_N) {
77241056 5951 if (!qsfp_mod_present(ppd)) {
e8aa284b
EH		 5952 dd_dev_info(dd, "%s: QSFP module removed\n",
5953 __func__);
5954
77241056
MM		 5955 ppd->driver_link_ready = 0;
5956 /*
5957 * Cable removed, reset all our information about the
5958 * cache and cable capabilities
5959 */
5960
5961 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
5962 /*
5963 * We don't set cache_refresh_required here as we expect
5964 * an interrupt when a cable is inserted
5965 */
5966 ppd->qsfp_info.cache_valid = 0;
8ebd4cf1
EH		 5967 ppd->qsfp_info.reset_needed = 0;
5968 ppd->qsfp_info.limiting_active = 0;
77241056 5969 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 5970 flags);
8ebd4cf1
EH		 5971 /* Invert the ModPresent pin now to detect plug-in */
5972 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
5973 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
a9c05e35
BM		 5974
5975 if ((ppd->offline_disabled_reason >
5976 HFI1_ODR_MASK(
e1bf0d5e 5977 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
a9c05e35
BM		 5978 (ppd->offline_disabled_reason ==
5979 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
5980 ppd->offline_disabled_reason =
5981 HFI1_ODR_MASK(
e1bf0d5e 5982 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
a9c05e35 5983
77241056
MM		 5984 if (ppd->host_link_state == HLS_DN_POLL) {
5985 /*
5986 * The link is still in POLL. This means
5987 * that the normal link down processing
5988 * will not happen. We have to do it here
5989 * before turning the DC off.
5990 */
5991 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
5992 }
5993 } else {
e8aa284b
EH		 5994 dd_dev_info(dd, "%s: QSFP module inserted\n",
5995 __func__);
5996
77241056
MM		 5997 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
5998 ppd->qsfp_info.cache_valid = 0;
5999 ppd->qsfp_info.cache_refresh_required = 1;
6000 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 6001 flags);
77241056 6002
8ebd4cf1
EH		 6003 /*
6004 * Stop inversion of ModPresent pin to detect
6005 * removal of the cable
6006 */
77241056 6007 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
8ebd4cf1
EH		 6008 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6009 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6010
6011 ppd->offline_disabled_reason =
6012 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 6013 }
6014 }
6015
6016 if (reg & QSFP_HFI0_INT_N) {
e8aa284b 6017 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n",
17fb4f29 6018 __func__);
77241056
MM		 6019 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6020 ppd->qsfp_info.check_interrupt_flags = 1;
77241056
MM		 6021 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6022 }
6023
6024 /* Schedule the QSFP work only if there is a cable attached. */
6025 if (qsfp_mod_present(ppd))
6026 queue_work(ppd->hfi1_wq, &ppd->qsfp_info.qsfp_work);
6027}
6028
6029static int request_host_lcb_access(struct hfi1_devdata *dd)
6030{
6031 int ret;
6032
6033 ret = do_8051_command(dd, HCMD_MISC,
17fb4f29
JJ		 6034 (u64)HCMD_MISC_REQUEST_LCB_ACCESS <<
6035 LOAD_DATA_FIELD_ID_SHIFT, NULL);
77241056
MM		 6036 if (ret != HCMD_SUCCESS) {
6037 dd_dev_err(dd, "%s: command failed with error %d\n",
17fb4f29 6038 __func__, ret);
77241056
MM		 6039 }
6040 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6041}
6042
6043static int request_8051_lcb_access(struct hfi1_devdata *dd)
6044{
6045 int ret;
6046
6047 ret = do_8051_command(dd, HCMD_MISC,
17fb4f29
JJ		 6048 (u64)HCMD_MISC_GRANT_LCB_ACCESS <<
6049 LOAD_DATA_FIELD_ID_SHIFT, NULL);
77241056
MM		 6050 if (ret != HCMD_SUCCESS) {
6051 dd_dev_err(dd, "%s: command failed with error %d\n",
17fb4f29 6052 __func__, ret);
77241056
MM		 6053 }
6054 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6055}
6056
6057/*
6058 * Set the LCB selector - allow host access. The DCC selector always
6059 * points to the host.
6060 */
6061static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6062{
6063 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
17fb4f29
JJ		 6064 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6065 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
77241056
MM		 6066}
6067
6068/*
6069 * Clear the LCB selector - allow 8051 access. The DCC selector always
6070 * points to the host.
6071 */
6072static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6073{
6074 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
17fb4f29 6075 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
77241056
MM		 6076}
6077
6078/*
6079 * Acquire LCB access from the 8051. If the host already has access,
6080 * just increment a counter. Otherwise, inform the 8051 that the
6081 * host is taking access.
6082 *
6083 * Returns:
6084 * 0 on success
6085 * -EBUSY if the 8051 has control and cannot be disturbed
6086 * -errno if unable to acquire access from the 8051
6087 */
6088int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6089{
6090 struct hfi1_pportdata *ppd = dd->pport;
6091 int ret = 0;
6092
6093 /*
6094 * Use the host link state lock so the operation of this routine
6095 * { link state check, selector change, count increment } can occur
6096 * as a unit against a link state change. Otherwise there is a
6097 * race between the state change and the count increment.
6098 */
6099 if (sleep_ok) {
6100 mutex_lock(&ppd->hls_lock);
6101 } else {
951842b0 6102 while (!mutex_trylock(&ppd->hls_lock))
77241056
MM		 6103 udelay(1);
6104 }
6105
6106 /* this access is valid only when the link is up */
6107 if ((ppd->host_link_state & HLS_UP) == 0) {
6108 dd_dev_info(dd, "%s: link state %s not up\n",
17fb4f29 6109 __func__, link_state_name(ppd->host_link_state));
77241056
MM		 6110 ret = -EBUSY;
6111 goto done;
6112 }
6113
6114 if (dd->lcb_access_count == 0) {
6115 ret = request_host_lcb_access(dd);
6116 if (ret) {
6117 dd_dev_err(dd,
17fb4f29
JJ		 6118 "%s: unable to acquire LCB access, err %d\n",
6119 __func__, ret);
77241056
MM		 6120 goto done;
6121 }
6122 set_host_lcb_access(dd);
6123 }
6124 dd->lcb_access_count++;
6125done:
6126 mutex_unlock(&ppd->hls_lock);
6127 return ret;
6128}
6129
6130/*
6131 * Release LCB access by decrementing the use count. If the count is moving
6132 * from 1 to 0, inform 8051 that it has control back.
6133 *
6134 * Returns:
6135 * 0 on success
6136 * -errno if unable to release access to the 8051
6137 */
6138int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6139{
6140 int ret = 0;
6141
6142 /*
6143 * Use the host link state lock because the acquire needed it.
6144 * Here, we only need to keep { selector change, count decrement }
6145 * as a unit.
6146 */
6147 if (sleep_ok) {
6148 mutex_lock(&dd->pport->hls_lock);
6149 } else {
951842b0 6150 while (!mutex_trylock(&dd->pport->hls_lock))
77241056
MM		 6151 udelay(1);
6152 }
6153
6154 if (dd->lcb_access_count == 0) {
6155 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n",
17fb4f29 6156 __func__);
77241056
MM		 6157 goto done;
6158 }
6159
6160 if (dd->lcb_access_count == 1) {
6161 set_8051_lcb_access(dd);
6162 ret = request_8051_lcb_access(dd);
6163 if (ret) {
6164 dd_dev_err(dd,
17fb4f29
JJ		 6165 "%s: unable to release LCB access, err %d\n",
6166 __func__, ret);
77241056
MM		 6167 /* restore host access if the grant didn't work */
6168 set_host_lcb_access(dd);
6169 goto done;
6170 }
6171 }
6172 dd->lcb_access_count--;
6173done:
6174 mutex_unlock(&dd->pport->hls_lock);
6175 return ret;
6176}
6177
6178/*
6179 * Initialize LCB access variables and state. Called during driver load,
6180 * after most of the initialization is finished.
6181 *
6182 * The DC default is LCB access on for the host. The driver defaults to
6183 * leaving access to the 8051. Assign access now - this constrains the call
6184 * to this routine to be after all LCB set-up is done. In particular, after
6185 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6186 */
6187static void init_lcb_access(struct hfi1_devdata *dd)
6188{
6189 dd->lcb_access_count = 0;
6190}
6191
6192/*
6193 * Write a response back to a 8051 request.
6194 */
6195static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6196{
6197 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
17fb4f29
JJ		 6198 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6199 (u64)return_code <<
6200 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6201 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
77241056
MM		 6202}
6203
6204/*
cbac386a 6205 * Handle host requests from the 8051.
77241056 6206 */
145dd2b3 6207static void handle_8051_request(struct hfi1_pportdata *ppd)
77241056 6208{
cbac386a 6209 struct hfi1_devdata *dd = ppd->dd;
77241056 6210 u64 reg;
cbac386a 6211 u16 data = 0;
145dd2b3 6212 u8 type;
77241056
MM		 6213
6214 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6215 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6216 return; /* no request */
6217
6218 /* zero out COMPLETED so the response is seen */
6219 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6220
6221 /* extract request details */
6222 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6223 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6224 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6225 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6226
6227 switch (type) {
6228 case HREQ_LOAD_CONFIG:
6229 case HREQ_SAVE_CONFIG:
6230 case HREQ_READ_CONFIG:
6231 case HREQ_SET_TX_EQ_ABS:
6232 case HREQ_SET_TX_EQ_REL:
145dd2b3 6233 case HREQ_ENABLE:
77241056 6234 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
17fb4f29 6235 type);
77241056
MM		 6236 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6237 break;
77241056
MM		 6238 case HREQ_CONFIG_DONE:
6239 hreq_response(dd, HREQ_SUCCESS, 0);
6240 break;
6241
6242 case HREQ_INTERFACE_TEST:
6243 hreq_response(dd, HREQ_SUCCESS, data);
6244 break;
77241056
MM		 6245 default:
6246 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6247 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6248 break;
6249 }
6250}
6251
6252static void write_global_credit(struct hfi1_devdata *dd,
6253 u8 vau, u16 total, u16 shared)
6254{
6255 write_csr(dd, SEND_CM_GLOBAL_CREDIT,
17fb4f29
JJ		 6256 ((u64)total <<
6257 SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) |
6258 ((u64)shared <<
6259 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) |
6260 ((u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT));
77241056
MM		 6261}
6262
6263/*
6264 * Set up initial VL15 credits of the remote. Assumes the rest of
6265 * the CM credit registers are zero from a previous global or credit reset .
6266 */
6267void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf)
6268{
6269 /* leave shared count at zero for both global and VL15 */
6270 write_global_credit(dd, vau, vl15buf, 0);
6271
6272 /* We may need some credits for another VL when sending packets
6273 * with the snoop interface. Dividing it down the middle for VL15
6274 * and VL0 should suffice.
6275 */
6276 if (unlikely(dd->hfi1_snoop.mode_flag == HFI1_PORT_SNOOP_MODE)) {
6277 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)(vl15buf >> 1)
6278 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6279 write_csr(dd, SEND_CM_CREDIT_VL, (u64)(vl15buf >> 1)
6280 << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT);
6281 } else {
6282 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6283 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6284 }
6285}
6286
6287/*
6288 * Zero all credit details from the previous connection and
6289 * reset the CM manager's internal counters.
6290 */
6291void reset_link_credits(struct hfi1_devdata *dd)
6292{
6293 int i;
6294
6295 /* remove all previous VL credit limits */
6296 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 6297 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056
MM		 6298 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6299 write_global_credit(dd, 0, 0, 0);
6300 /* reset the CM block */
6301 pio_send_control(dd, PSC_CM_RESET);
6302}
6303
6304/* convert a vCU to a CU */
6305static u32 vcu_to_cu(u8 vcu)
6306{
6307 return 1 << vcu;
6308}
6309
6310/* convert a CU to a vCU */
6311static u8 cu_to_vcu(u32 cu)
6312{
6313 return ilog2(cu);
6314}
6315
6316/* convert a vAU to an AU */
6317static u32 vau_to_au(u8 vau)
6318{
6319 return 8 * (1 << vau);
6320}
6321
6322static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6323{
6324 ppd->sm_trap_qp = 0x0;
6325 ppd->sa_qp = 0x1;
6326}
6327
6328/*
6329 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6330 */
6331static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6332{
6333 u64 reg;
6334
6335 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6336 write_csr(dd, DC_LCB_CFG_RUN, 0);
6337 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6338 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
17fb4f29 6339 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
77241056
MM		 6340 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6341 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6342 reg = read_csr(dd, DCC_CFG_RESET);
17fb4f29
JJ		 6343 write_csr(dd, DCC_CFG_RESET, reg |
6344 (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT) |
6345 (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT));
50e5dcbe 6346 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
77241056
MM		 6347 if (!abort) {
6348 udelay(1); /* must hold for the longer of 16cclks or 20ns */
6349 write_csr(dd, DCC_CFG_RESET, reg);
6350 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6351 }
6352}
6353
6354/*
6355 * This routine should be called after the link has been transitioned to
6356 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6357 * reset).
6358 *
6359 * The expectation is that the caller of this routine would have taken
6360 * care of properly transitioning the link into the correct state.
6361 */
6362static void dc_shutdown(struct hfi1_devdata *dd)
6363{
6364 unsigned long flags;
6365
6366 spin_lock_irqsave(&dd->dc8051_lock, flags);
6367 if (dd->dc_shutdown) {
6368 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6369 return;
6370 }
6371 dd->dc_shutdown = 1;
6372 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6373 /* Shutdown the LCB */
6374 lcb_shutdown(dd, 1);
4d114fdd
JJ		 6375 /*
6376 * Going to OFFLINE would have causes the 8051 to put the
77241056 6377 * SerDes into reset already. Just need to shut down the 8051,
4d114fdd
JJ		 6378 * itself.
6379 */
77241056
MM		 6380 write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6381}
6382
4d114fdd
JJ		 6383/*
6384 * Calling this after the DC has been brought out of reset should not
6385 * do any damage.
6386 */
77241056
MM		 6387static void dc_start(struct hfi1_devdata *dd)
6388{
6389 unsigned long flags;
6390 int ret;
6391
6392 spin_lock_irqsave(&dd->dc8051_lock, flags);
6393 if (!dd->dc_shutdown)
6394 goto done;
6395 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6396 /* Take the 8051 out of reset */
6397 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6398 /* Wait until 8051 is ready */
6399 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
6400 if (ret) {
6401 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
17fb4f29 6402 __func__);
77241056
MM		 6403 }
6404 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6405 write_csr(dd, DCC_CFG_RESET, 0x10);
6406 /* lcb_shutdown() with abort=1 does not restore these */
6407 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6408 spin_lock_irqsave(&dd->dc8051_lock, flags);
6409 dd->dc_shutdown = 0;
6410done:
6411 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6412}
6413
6414/*
6415 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6416 */
6417static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6418{
6419 u64 rx_radr, tx_radr;
6420 u32 version;
6421
6422 if (dd->icode != ICODE_FPGA_EMULATION)
6423 return;
6424
6425 /*
6426 * These LCB defaults on emulator _s are good, nothing to do here:
6427 * LCB_CFG_TX_FIFOS_RADR
6428 * LCB_CFG_RX_FIFOS_RADR
6429 * LCB_CFG_LN_DCLK
6430 * LCB_CFG_IGNORE_LOST_RCLK
6431 */
6432 if (is_emulator_s(dd))
6433 return;
6434 /* else this is _p */
6435
6436 version = emulator_rev(dd);
995deafa 6437 if (!is_ax(dd))
77241056
MM		 6438 version = 0x2d; /* all B0 use 0x2d or higher settings */
6439
6440 if (version <= 0x12) {
6441 /* release 0x12 and below */
6442
6443 /*
6444 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6445 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6446 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6447 */
6448 rx_radr =
6449 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6450 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6451 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6452 /*
6453 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6454 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6455 */
6456 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6457 } else if (version <= 0x18) {
6458 /* release 0x13 up to 0x18 */
6459 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6460 rx_radr =
6461 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6462 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6463 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6464 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6465 } else if (version == 0x19) {
6466 /* release 0x19 */
6467 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6468 rx_radr =
6469 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6470 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6471 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6472 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6473 } else if (version == 0x1a) {
6474 /* release 0x1a */
6475 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6476 rx_radr =
6477 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6478 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6479 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6480 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6481 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6482 } else {
6483 /* release 0x1b and higher */
6484 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6485 rx_radr =
6486 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6487 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6488 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6489 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6490 }
6491
6492 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6493 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6494 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
17fb4f29 6495 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
77241056
MM		 6496 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6497}
6498
6499/*
6500 * Handle a SMA idle message
6501 *
6502 * This is a work-queue function outside of the interrupt.
6503 */
6504void handle_sma_message(struct work_struct *work)
6505{
6506 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6507 sma_message_work);
6508 struct hfi1_devdata *dd = ppd->dd;
6509 u64 msg;
6510 int ret;
6511
4d114fdd
JJ		 6512 /*
6513 * msg is bytes 1-4 of the 40-bit idle message - the command code
6514 * is stripped off
6515 */
77241056
MM		 6516 ret = read_idle_sma(dd, &msg);
6517 if (ret)
6518 return;
6519 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6520 /*
6521 * React to the SMA message. Byte[1] (0 for us) is the command.
6522 */
6523 switch (msg & 0xff) {
6524 case SMA_IDLE_ARM:
6525 /*
6526 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6527 * State Transitions
6528 *
6529 * Only expected in INIT or ARMED, discard otherwise.
6530 */
6531 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6532 ppd->neighbor_normal = 1;
6533 break;
6534 case SMA_IDLE_ACTIVE:
6535 /*
6536 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6537 * State Transitions
6538 *
6539 * Can activate the node. Discard otherwise.
6540 */
d0d236ea
JJ		 6541 if (ppd->host_link_state == HLS_UP_ARMED &&
6542 ppd->is_active_optimize_enabled) {
77241056
MM		 6543 ppd->neighbor_normal = 1;
6544 ret = set_link_state(ppd, HLS_UP_ACTIVE);
6545 if (ret)
6546 dd_dev_err(
6547 dd,
6548 "%s: received Active SMA idle message, couldn't set link to Active\n",
6549 __func__);
6550 }
6551 break;
6552 default:
6553 dd_dev_err(dd,
17fb4f29
JJ		 6554 "%s: received unexpected SMA idle message 0x%llx\n",
6555 __func__, msg);
77241056
MM		 6556 break;
6557 }
6558}
6559
6560static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6561{
6562 u64 rcvctrl;
6563 unsigned long flags;
6564
6565 spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6566 rcvctrl = read_csr(dd, RCV_CTRL);
6567 rcvctrl |= add;
6568 rcvctrl &= ~clear;
6569 write_csr(dd, RCV_CTRL, rcvctrl);
6570 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6571}
6572
6573static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6574{
6575 adjust_rcvctrl(dd, add, 0);
6576}
6577
6578static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6579{
6580 adjust_rcvctrl(dd, 0, clear);
6581}
6582
6583/*
6584 * Called from all interrupt handlers to start handling an SPC freeze.
6585 */
6586void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6587{
6588 struct hfi1_devdata *dd = ppd->dd;
6589 struct send_context *sc;
6590 int i;
6591
6592 if (flags & FREEZE_SELF)
6593 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6594
6595 /* enter frozen mode */
6596 dd->flags |= HFI1_FROZEN;
6597
6598 /* notify all SDMA engines that they are going into a freeze */
6599 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6600
6601 /* do halt pre-handling on all enabled send contexts */
6602 for (i = 0; i < dd->num_send_contexts; i++) {
6603 sc = dd->send_contexts[i].sc;
6604 if (sc && (sc->flags & SCF_ENABLED))
6605 sc_stop(sc, SCF_FROZEN | SCF_HALTED);
6606 }
6607
6608 /* Send context are frozen. Notify user space */
6609 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6610
6611 if (flags & FREEZE_ABORT) {
6612 dd_dev_err(dd,
6613 "Aborted freeze recovery. Please REBOOT system\n");
6614 return;
6615 }
6616 /* queue non-interrupt handler */
6617 queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6618}
6619
6620/*
6621 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6622 * depending on the "freeze" parameter.
6623 *
6624 * No need to return an error if it times out, our only option
6625 * is to proceed anyway.
6626 */
6627static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6628{
6629 unsigned long timeout;
6630 u64 reg;
6631
6632 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6633 while (1) {
6634 reg = read_csr(dd, CCE_STATUS);
6635 if (freeze) {
6636 /* waiting until all indicators are set */
6637 if ((reg & ALL_FROZE) == ALL_FROZE)
6638 return; /* all done */
6639 } else {
6640 /* waiting until all indicators are clear */
6641 if ((reg & ALL_FROZE) == 0)
6642 return; /* all done */
6643 }
6644
6645 if (time_after(jiffies, timeout)) {
6646 dd_dev_err(dd,
17fb4f29
JJ		 6647 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6648 freeze ? "" : "un", reg & ALL_FROZE,
6649 freeze ? ALL_FROZE : 0ull);
77241056
MM		 6650 return;
6651 }
6652 usleep_range(80, 120);
6653 }
6654}
6655
6656/*
6657 * Do all freeze handling for the RXE block.
6658 */
6659static void rxe_freeze(struct hfi1_devdata *dd)
6660{
6661 int i;
6662
6663 /* disable port */
6664 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6665
6666 /* disable all receive contexts */
6667 for (i = 0; i < dd->num_rcv_contexts; i++)
6668 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, i);
6669}
6670
6671/*
6672 * Unfreeze handling for the RXE block - kernel contexts only.
6673 * This will also enable the port. User contexts will do unfreeze
6674 * handling on a per-context basis as they call into the driver.
6675 *
6676 */
6677static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6678{
566c157c 6679 u32 rcvmask;
77241056
MM		 6680 int i;
6681
6682 /* enable all kernel contexts */
566c157c
MH		 6683 for (i = 0; i < dd->n_krcv_queues; i++) {
6684 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6685 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6686 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
6687 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6688 hfi1_rcvctrl(dd, rcvmask, i);
6689 }
77241056
MM		 6690
6691 /* enable port */
6692 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6693}
6694
6695/*
6696 * Non-interrupt SPC freeze handling.
6697 *
6698 * This is a work-queue function outside of the triggering interrupt.
6699 */
6700void handle_freeze(struct work_struct *work)
6701{
6702 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6703 freeze_work);
6704 struct hfi1_devdata *dd = ppd->dd;
6705
6706 /* wait for freeze indicators on all affected blocks */
77241056
MM		 6707 wait_for_freeze_status(dd, 1);
6708
6709 /* SPC is now frozen */
6710
6711 /* do send PIO freeze steps */
6712 pio_freeze(dd);
6713
6714 /* do send DMA freeze steps */
6715 sdma_freeze(dd);
6716
6717 /* do send egress freeze steps - nothing to do */
6718
6719 /* do receive freeze steps */
6720 rxe_freeze(dd);
6721
6722 /*
6723 * Unfreeze the hardware - clear the freeze, wait for each
6724 * block's frozen bit to clear, then clear the frozen flag.
6725 */
6726 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6727 wait_for_freeze_status(dd, 0);
6728
995deafa 6729 if (is_ax(dd)) {
77241056
MM		 6730 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6731 wait_for_freeze_status(dd, 1);
6732 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6733 wait_for_freeze_status(dd, 0);
6734 }
6735
6736 /* do send PIO unfreeze steps for kernel contexts */
6737 pio_kernel_unfreeze(dd);
6738
6739 /* do send DMA unfreeze steps */
6740 sdma_unfreeze(dd);
6741
6742 /* do send egress unfreeze steps - nothing to do */
6743
6744 /* do receive unfreeze steps for kernel contexts */
6745 rxe_kernel_unfreeze(dd);
6746
6747 /*
6748 * The unfreeze procedure touches global device registers when
6749 * it disables and re-enables RXE. Mark the device unfrozen
6750 * after all that is done so other parts of the driver waiting
6751 * for the device to unfreeze don't do things out of order.
6752 *
6753 * The above implies that the meaning of HFI1_FROZEN flag is
6754 * "Device has gone into freeze mode and freeze mode handling
6755 * is still in progress."
6756 *
6757 * The flag will be removed when freeze mode processing has
6758 * completed.
6759 */
6760 dd->flags &= ~HFI1_FROZEN;
6761 wake_up(&dd->event_queue);
6762
6763 /* no longer frozen */
77241056
MM		 6764}
6765
6766/*
6767 * Handle a link up interrupt from the 8051.
6768 *
6769 * This is a work-queue function outside of the interrupt.
6770 */
6771void handle_link_up(struct work_struct *work)
6772{
6773 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
17fb4f29 6774 link_up_work);
77241056
MM		 6775 set_link_state(ppd, HLS_UP_INIT);
6776
6777 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6778 read_ltp_rtt(ppd->dd);
6779 /*
6780 * OPA specifies that certain counters are cleared on a transition
6781 * to link up, so do that.
6782 */
6783 clear_linkup_counters(ppd->dd);
6784 /*
6785 * And (re)set link up default values.
6786 */
6787 set_linkup_defaults(ppd);
6788
6789 /* enforce link speed enabled */
6790 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6791 /* oops - current speed is not enabled, bounce */
6792 dd_dev_err(ppd->dd,
17fb4f29
JJ		 6793 "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6794 ppd->link_speed_active, ppd->link_speed_enabled);
77241056 6795 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
17fb4f29 6796 OPA_LINKDOWN_REASON_SPEED_POLICY);
77241056 6797 set_link_state(ppd, HLS_DN_OFFLINE);
8ebd4cf1 6798 tune_serdes(ppd);
77241056
MM		 6799 start_link(ppd);
6800 }
6801}
6802
4d114fdd
JJ		 6803/*
6804 * Several pieces of LNI information were cached for SMA in ppd.
6805 * Reset these on link down
6806 */
77241056
MM		 6807static void reset_neighbor_info(struct hfi1_pportdata *ppd)
6808{
6809 ppd->neighbor_guid = 0;
6810 ppd->neighbor_port_number = 0;
6811 ppd->neighbor_type = 0;
6812 ppd->neighbor_fm_security = 0;
6813}
6814
6815/*
6816 * Handle a link down interrupt from the 8051.
6817 *
6818 * This is a work-queue function outside of the interrupt.
6819 */
6820void handle_link_down(struct work_struct *work)
6821{
6822 u8 lcl_reason, neigh_reason = 0;
6823 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6824 link_down_work);
6825
8ebd4cf1
EH		 6826 if ((ppd->host_link_state &
6827 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
6828 ppd->port_type == PORT_TYPE_FIXED)
6829 ppd->offline_disabled_reason =
6830 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
6831
6832 /* Go offline first, then deal with reading/writing through 8051 */
77241056
MM		 6833 set_link_state(ppd, HLS_DN_OFFLINE);
6834
6835 lcl_reason = 0;
6836 read_planned_down_reason_code(ppd->dd, &neigh_reason);
6837
6838 /*
6839 * If no reason, assume peer-initiated but missed
6840 * LinkGoingDown idle flits.
6841 */
6842 if (neigh_reason == 0)
6843 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
6844
6845 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
6846
6847 reset_neighbor_info(ppd);
6848
6849 /* disable the port */
6850 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6851
4d114fdd
JJ		 6852 /*
6853 * If there is no cable attached, turn the DC off. Otherwise,
6854 * start the link bring up.
6855 */
623bba2d 6856 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd)) {
77241056 6857 dc_shutdown(ppd->dd);
8ebd4cf1
EH		 6858 } else {
6859 tune_serdes(ppd);
77241056 6860 start_link(ppd);
8ebd4cf1 6861 }
77241056
MM		 6862}
6863
6864void handle_link_bounce(struct work_struct *work)
6865{
6866 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6867 link_bounce_work);
6868
6869 /*
6870 * Only do something if the link is currently up.
6871 */
6872 if (ppd->host_link_state & HLS_UP) {
6873 set_link_state(ppd, HLS_DN_OFFLINE);
8ebd4cf1 6874 tune_serdes(ppd);
77241056
MM		 6875 start_link(ppd);
6876 } else {
6877 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
17fb4f29 6878 __func__, link_state_name(ppd->host_link_state));
77241056
MM		 6879 }
6880}
6881
6882/*
6883 * Mask conversion: Capability exchange to Port LTP. The capability
6884 * exchange has an implicit 16b CRC that is mandatory.
6885 */
6886static int cap_to_port_ltp(int cap)
6887{
6888 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
6889
6890 if (cap & CAP_CRC_14B)
6891 port_ltp |= PORT_LTP_CRC_MODE_14;
6892 if (cap & CAP_CRC_48B)
6893 port_ltp |= PORT_LTP_CRC_MODE_48;
6894 if (cap & CAP_CRC_12B_16B_PER_LANE)
6895 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
6896
6897 return port_ltp;
6898}
6899
6900/*
6901 * Convert an OPA Port LTP mask to capability mask
6902 */
6903int port_ltp_to_cap(int port_ltp)
6904{
6905 int cap_mask = 0;
6906
6907 if (port_ltp & PORT_LTP_CRC_MODE_14)
6908 cap_mask |= CAP_CRC_14B;
6909 if (port_ltp & PORT_LTP_CRC_MODE_48)
6910 cap_mask |= CAP_CRC_48B;
6911 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
6912 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
6913
6914 return cap_mask;
6915}
6916
6917/*
6918 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
6919 */
6920static int lcb_to_port_ltp(int lcb_crc)
6921{
6922 int port_ltp = 0;
6923
6924 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
6925 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
6926 else if (lcb_crc == LCB_CRC_48B)
6927 port_ltp = PORT_LTP_CRC_MODE_48;
6928 else if (lcb_crc == LCB_CRC_14B)
6929 port_ltp = PORT_LTP_CRC_MODE_14;
6930 else
6931 port_ltp = PORT_LTP_CRC_MODE_16;
6932
6933 return port_ltp;
6934}
6935
6936/*
6937 * Our neighbor has indicated that we are allowed to act as a fabric
6938 * manager, so place the full management partition key in the second
6939 * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
6940 * that we should already have the limited management partition key in
6941 * array element 1, and also that the port is not yet up when
6942 * add_full_mgmt_pkey() is invoked.
6943 */
6944static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
6945{
6946 struct hfi1_devdata *dd = ppd->dd;
6947
8764522e
DL		 6948 /* Sanity check - ppd->pkeys[2] should be 0, or already initalized */
6949 if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
6950 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
6951 __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
77241056
MM		 6952 ppd->pkeys[2] = FULL_MGMT_P_KEY;
6953 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
6954}
6955
6956/*
6957 * Convert the given link width to the OPA link width bitmask.
6958 */
6959static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
6960{
6961 switch (width) {
6962 case 0:
6963 /*
6964 * Simulator and quick linkup do not set the width.
6965 * Just set it to 4x without complaint.
6966 */
6967 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
6968 return OPA_LINK_WIDTH_4X;
6969 return 0; /* no lanes up */
6970 case 1: return OPA_LINK_WIDTH_1X;
6971 case 2: return OPA_LINK_WIDTH_2X;
6972 case 3: return OPA_LINK_WIDTH_3X;
6973 default:
6974 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
17fb4f29 6975 __func__, width);
77241056
MM		 6976 /* fall through */
6977 case 4: return OPA_LINK_WIDTH_4X;
6978 }
6979}
6980
6981/*
6982 * Do a population count on the bottom nibble.
6983 */
6984static const u8 bit_counts[16] = {
6985 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
6986};
f4d507cd 6987
77241056
MM		 6988static inline u8 nibble_to_count(u8 nibble)
6989{
6990 return bit_counts[nibble & 0xf];
6991}
6992
6993/*
6994 * Read the active lane information from the 8051 registers and return
6995 * their widths.
6996 *
6997 * Active lane information is found in these 8051 registers:
6998 * enable_lane_tx
6999 * enable_lane_rx
7000 */
7001static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7002 u16 *rx_width)
7003{
7004 u16 tx, rx;
7005 u8 enable_lane_rx;
7006 u8 enable_lane_tx;
7007 u8 tx_polarity_inversion;
7008 u8 rx_polarity_inversion;
7009 u8 max_rate;
7010
7011 /* read the active lanes */
7012 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
17fb4f29 7013 &rx_polarity_inversion, &max_rate);
77241056
MM		 7014 read_local_lni(dd, &enable_lane_rx);
7015
7016 /* convert to counts */
7017 tx = nibble_to_count(enable_lane_tx);
7018 rx = nibble_to_count(enable_lane_rx);
7019
7020 /*
7021 * Set link_speed_active here, overriding what was set in
7022 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7023 * set the max_rate field in handle_verify_cap until v0.19.
7024 */
d0d236ea
JJ		 7025 if ((dd->icode == ICODE_RTL_SILICON) &&
7026 (dd->dc8051_ver < dc8051_ver(0, 19))) {
77241056
MM		 7027 /* max_rate: 0 = 12.5G, 1 = 25G */
7028 switch (max_rate) {
7029 case 0:
7030 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7031 break;
7032 default:
7033 dd_dev_err(dd,
17fb4f29
JJ		 7034 "%s: unexpected max rate %d, using 25Gb\n",
7035 __func__, (int)max_rate);
77241056
MM		 7036 /* fall through */
7037 case 1:
7038 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7039 break;
7040 }
7041 }
7042
7043 dd_dev_info(dd,
17fb4f29
JJ		 7044 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7045 enable_lane_tx, tx, enable_lane_rx, rx);
77241056
MM		 7046 *tx_width = link_width_to_bits(dd, tx);
7047 *rx_width = link_width_to_bits(dd, rx);
7048}
7049
7050/*
7051 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7052 * Valid after the end of VerifyCap and during LinkUp. Does not change
7053 * after link up. I.e. look elsewhere for downgrade information.
7054 *
7055 * Bits are:
7056 * + bits [7:4] contain the number of active transmitters
7057 * + bits [3:0] contain the number of active receivers
7058 * These are numbers 1 through 4 and can be different values if the
7059 * link is asymmetric.
7060 *
7061 * verify_cap_local_fm_link_width[0] retains its original value.
7062 */
7063static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7064 u16 *rx_width)
7065{
7066 u16 widths, tx, rx;
7067 u8 misc_bits, local_flags;
7068 u16 active_tx, active_rx;
7069
7070 read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths);
7071 tx = widths >> 12;
7072 rx = (widths >> 8) & 0xf;
7073
7074 *tx_width = link_width_to_bits(dd, tx);
7075 *rx_width = link_width_to_bits(dd, rx);
7076
7077 /* print the active widths */
7078 get_link_widths(dd, &active_tx, &active_rx);
7079}
7080
7081/*
7082 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7083 * hardware information when the link first comes up.
7084 *
7085 * The link width is not available until after VerifyCap.AllFramesReceived
7086 * (the trigger for handle_verify_cap), so this is outside that routine
7087 * and should be called when the 8051 signals linkup.
7088 */
7089void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7090{
7091 u16 tx_width, rx_width;
7092
7093 /* get end-of-LNI link widths */
7094 get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7095
7096 /* use tx_width as the link is supposed to be symmetric on link up */
7097 ppd->link_width_active = tx_width;
7098 /* link width downgrade active (LWD.A) starts out matching LW.A */
7099 ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7100 ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7101 /* per OPA spec, on link up LWD.E resets to LWD.S */
7102 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7103 /* cache the active egress rate (units {10^6 bits/sec]) */
7104 ppd->current_egress_rate = active_egress_rate(ppd);
7105}
7106
7107/*
7108 * Handle a verify capabilities interrupt from the 8051.
7109 *
7110 * This is a work-queue function outside of the interrupt.
7111 */
7112void handle_verify_cap(struct work_struct *work)
7113{
7114 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7115 link_vc_work);
7116 struct hfi1_devdata *dd = ppd->dd;
7117 u64 reg;
7118 u8 power_management;
7119 u8 continious;
7120 u8 vcu;
7121 u8 vau;
7122 u8 z;
7123 u16 vl15buf;
7124 u16 link_widths;
7125 u16 crc_mask;
7126 u16 crc_val;
7127 u16 device_id;
7128 u16 active_tx, active_rx;
7129 u8 partner_supported_crc;
7130 u8 remote_tx_rate;
7131 u8 device_rev;
7132
7133 set_link_state(ppd, HLS_VERIFY_CAP);
7134
7135 lcb_shutdown(dd, 0);
7136 adjust_lcb_for_fpga_serdes(dd);
7137
7138 /*
7139 * These are now valid:
7140 * remote VerifyCap fields in the general LNI config
7141 * CSR DC8051_STS_REMOTE_GUID
7142 * CSR DC8051_STS_REMOTE_NODE_TYPE
7143 * CSR DC8051_STS_REMOTE_FM_SECURITY
7144 * CSR DC8051_STS_REMOTE_PORT_NO
7145 */
7146
7147 read_vc_remote_phy(dd, &power_management, &continious);
17fb4f29
JJ		 7148 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf,
7149 &partner_supported_crc);
77241056
MM		 7150 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7151 read_remote_device_id(dd, &device_id, &device_rev);
7152 /*
7153 * And the 'MgmtAllowed' information, which is exchanged during
7154 * LNI, is also be available at this point.
7155 */
7156 read_mgmt_allowed(dd, &ppd->mgmt_allowed);
7157 /* print the active widths */
7158 get_link_widths(dd, &active_tx, &active_rx);
7159 dd_dev_info(dd,
17fb4f29
JJ		 7160 "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7161 (int)power_management, (int)continious);
77241056 7162 dd_dev_info(dd,
17fb4f29
JJ		 7163 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7164 (int)vau, (int)z, (int)vcu, (int)vl15buf,
7165 (int)partner_supported_crc);
77241056 7166 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
17fb4f29 7167 (u32)remote_tx_rate, (u32)link_widths);
77241056 7168 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
17fb4f29 7169 (u32)device_id, (u32)device_rev);
77241056
MM		 7170 /*
7171 * The peer vAU value just read is the peer receiver value. HFI does
7172 * not support a transmit vAU of 0 (AU == 8). We advertised that
7173 * with Z=1 in the fabric capabilities sent to the peer. The peer
7174 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7175 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7176 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7177 * subject to the Z value exception.
7178 */
7179 if (vau == 0)
7180 vau = 1;
7181 set_up_vl15(dd, vau, vl15buf);
7182
7183 /* set up the LCB CRC mode */
7184 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7185
7186 /* order is important: use the lowest bit in common */
7187 if (crc_mask & CAP_CRC_14B)
7188 crc_val = LCB_CRC_14B;
7189 else if (crc_mask & CAP_CRC_48B)
7190 crc_val = LCB_CRC_48B;
7191 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7192 crc_val = LCB_CRC_12B_16B_PER_LANE;
7193 else
7194 crc_val = LCB_CRC_16B;
7195
7196 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7197 write_csr(dd, DC_LCB_CFG_CRC_MODE,
7198 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7199
7200 /* set (14b only) or clear sideband credit */
7201 reg = read_csr(dd, SEND_CM_CTRL);
7202 if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7203 write_csr(dd, SEND_CM_CTRL,
17fb4f29 7204 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
77241056
MM		 7205 } else {
7206 write_csr(dd, SEND_CM_CTRL,
17fb4f29 7207 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
77241056
MM		 7208 }
7209
7210 ppd->link_speed_active = 0; /* invalid value */
7211 if (dd->dc8051_ver < dc8051_ver(0, 20)) {
7212 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7213 switch (remote_tx_rate) {
7214 case 0:
7215 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7216 break;
7217 case 1:
7218 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7219 break;
7220 }
7221 } else {
7222 /* actual rate is highest bit of the ANDed rates */
7223 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7224
7225 if (rate & 2)
7226 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7227 else if (rate & 1)
7228 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7229 }
7230 if (ppd->link_speed_active == 0) {
7231 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
17fb4f29 7232 __func__, (int)remote_tx_rate);
77241056
MM		 7233 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7234 }
7235
7236 /*
7237 * Cache the values of the supported, enabled, and active
7238 * LTP CRC modes to return in 'portinfo' queries. But the bit
7239 * flags that are returned in the portinfo query differ from
7240 * what's in the link_crc_mask, crc_sizes, and crc_val
7241 * variables. Convert these here.
7242 */
7243 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7244 /* supported crc modes */
7245 ppd->port_ltp_crc_mode |=
7246 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7247 /* enabled crc modes */
7248 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7249 /* active crc mode */
7250
7251 /* set up the remote credit return table */
7252 assign_remote_cm_au_table(dd, vcu);
7253
7254 /*
7255 * The LCB is reset on entry to handle_verify_cap(), so this must
7256 * be applied on every link up.
7257 *
7258 * Adjust LCB error kill enable to kill the link if
7259 * these RBUF errors are seen:
7260 * REPLAY_BUF_MBE_SMASK
7261 * FLIT_INPUT_BUF_MBE_SMASK
7262 */
995deafa 7263 if (is_ax(dd)) { /* fixed in B0 */
77241056
MM		 7264 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7265 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7266 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7267 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7268 }
7269
7270 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7271 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7272
7273 /* give 8051 access to the LCB CSRs */
7274 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7275 set_8051_lcb_access(dd);
7276
7277 ppd->neighbor_guid =
7278 read_csr(dd, DC_DC8051_STS_REMOTE_GUID);
7279 ppd->neighbor_port_number = read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) &
7280 DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK;
7281 ppd->neighbor_type =
7282 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) &
7283 DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK;
7284 ppd->neighbor_fm_security =
7285 read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) &
7286 DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK;
7287 dd_dev_info(dd,
17fb4f29
JJ		 7288 "Neighbor Guid: %llx Neighbor type %d MgmtAllowed %d FM security bypass %d\n",
7289 ppd->neighbor_guid, ppd->neighbor_type,
7290 ppd->mgmt_allowed, ppd->neighbor_fm_security);
77241056
MM		 7291 if (ppd->mgmt_allowed)
7292 add_full_mgmt_pkey(ppd);
7293
7294 /* tell the 8051 to go to LinkUp */
7295 set_link_state(ppd, HLS_GOING_UP);
7296}
7297
7298/*
7299 * Apply the link width downgrade enabled policy against the current active
7300 * link widths.
7301 *
7302 * Called when the enabled policy changes or the active link widths change.
7303 */
7304void apply_link_downgrade_policy(struct hfi1_pportdata *ppd, int refresh_widths)
7305{
77241056 7306 int do_bounce = 0;
323fd785
DL		 7307 int tries;
7308 u16 lwde;
77241056
MM		 7309 u16 tx, rx;
7310
323fd785
DL		 7311 /* use the hls lock to avoid a race with actual link up */
7312 tries = 0;
7313retry:
77241056
MM		 7314 mutex_lock(&ppd->hls_lock);
7315 /* only apply if the link is up */
323fd785
DL		 7316 if (!(ppd->host_link_state & HLS_UP)) {
7317 /* still going up..wait and retry */
7318 if (ppd->host_link_state & HLS_GOING_UP) {
7319 if (++tries < 1000) {
7320 mutex_unlock(&ppd->hls_lock);
7321 usleep_range(100, 120); /* arbitrary */
7322 goto retry;
7323 }
7324 dd_dev_err(ppd->dd,
7325 "%s: giving up waiting for link state change\n",
7326 __func__);
7327 }
7328 goto done;
7329 }
7330
7331 lwde = ppd->link_width_downgrade_enabled;
77241056
MM		 7332
7333 if (refresh_widths) {
7334 get_link_widths(ppd->dd, &tx, &rx);
7335 ppd->link_width_downgrade_tx_active = tx;
7336 ppd->link_width_downgrade_rx_active = rx;
7337 }
7338
f9b5635c
DL		 7339 if (ppd->link_width_downgrade_tx_active == 0 ||
7340 ppd->link_width_downgrade_rx_active == 0) {
7341 /* the 8051 reported a dead link as a downgrade */
7342 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n");
7343 } else if (lwde == 0) {
77241056
MM		 7344 /* downgrade is disabled */
7345
7346 /* bounce if not at starting active width */
7347 if ((ppd->link_width_active !=
17fb4f29
JJ		 7348 ppd->link_width_downgrade_tx_active) ||
7349 (ppd->link_width_active !=
7350 ppd->link_width_downgrade_rx_active)) {
77241056 7351 dd_dev_err(ppd->dd,
17fb4f29 7352 "Link downgrade is disabled and link has downgraded, downing link\n");
77241056 7353 dd_dev_err(ppd->dd,
17fb4f29
JJ		 7354 " original 0x%x, tx active 0x%x, rx active 0x%x\n",
7355 ppd->link_width_active,
7356 ppd->link_width_downgrade_tx_active,
7357 ppd->link_width_downgrade_rx_active);
77241056
MM		 7358 do_bounce = 1;
7359 }
d0d236ea
JJ		 7360 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 ||
7361 (lwde & ppd->link_width_downgrade_rx_active) == 0) {
77241056
MM		 7362 /* Tx or Rx is outside the enabled policy */
7363 dd_dev_err(ppd->dd,
17fb4f29 7364 "Link is outside of downgrade allowed, downing link\n");
77241056 7365 dd_dev_err(ppd->dd,
17fb4f29
JJ		 7366 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7367 lwde, ppd->link_width_downgrade_tx_active,
7368 ppd->link_width_downgrade_rx_active);
77241056
MM		 7369 do_bounce = 1;
7370 }
7371
323fd785
DL		 7372done:
7373 mutex_unlock(&ppd->hls_lock);
7374
77241056
MM		 7375 if (do_bounce) {
7376 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
17fb4f29 7377 OPA_LINKDOWN_REASON_WIDTH_POLICY);
77241056 7378 set_link_state(ppd, HLS_DN_OFFLINE);
8ebd4cf1 7379 tune_serdes(ppd);
77241056
MM		 7380 start_link(ppd);
7381 }
7382}
7383
7384/*
7385 * Handle a link downgrade interrupt from the 8051.
7386 *
7387 * This is a work-queue function outside of the interrupt.
7388 */
7389void handle_link_downgrade(struct work_struct *work)
7390{
7391 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7392 link_downgrade_work);
7393
7394 dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7395 apply_link_downgrade_policy(ppd, 1);
7396}
7397
7398static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7399{
7400 return flag_string(buf, buf_len, flags, dcc_err_flags,
7401 ARRAY_SIZE(dcc_err_flags));
7402}
7403
7404static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7405{
7406 return flag_string(buf, buf_len, flags, lcb_err_flags,
7407 ARRAY_SIZE(lcb_err_flags));
7408}
7409
7410static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7411{
7412 return flag_string(buf, buf_len, flags, dc8051_err_flags,
7413 ARRAY_SIZE(dc8051_err_flags));
7414}
7415
7416static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7417{
7418 return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7419 ARRAY_SIZE(dc8051_info_err_flags));
7420}
7421
7422static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7423{
7424 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7425 ARRAY_SIZE(dc8051_info_host_msg_flags));
7426}
7427
7428static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7429{
7430 struct hfi1_pportdata *ppd = dd->pport;
7431 u64 info, err, host_msg;
7432 int queue_link_down = 0;
7433 char buf[96];
7434
7435 /* look at the flags */
7436 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7437 /* 8051 information set by firmware */
7438 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7439 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7440 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7441 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7442 host_msg = (info >>
7443 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7444 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7445
7446 /*
7447 * Handle error flags.
7448 */
7449 if (err & FAILED_LNI) {
7450 /*
7451 * LNI error indications are cleared by the 8051
7452 * only when starting polling. Only pay attention
7453 * to them when in the states that occur during
7454 * LNI.
7455 */
7456 if (ppd->host_link_state
7457 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7458 queue_link_down = 1;
7459 dd_dev_info(dd, "Link error: %s\n",
17fb4f29
JJ		 7460 dc8051_info_err_string(buf,
7461 sizeof(buf),
7462 err &
7463 FAILED_LNI));
77241056
MM		 7464 }
7465 err &= ~(u64)FAILED_LNI;
7466 }
6d014530
DL		 7467 /* unknown frames can happen durning LNI, just count */
7468 if (err & UNKNOWN_FRAME) {
7469 ppd->unknown_frame_count++;
7470 err &= ~(u64)UNKNOWN_FRAME;
7471 }
77241056
MM		 7472 if (err) {
7473 /* report remaining errors, but do not do anything */
7474 dd_dev_err(dd, "8051 info error: %s\n",
17fb4f29
JJ		 7475 dc8051_info_err_string(buf, sizeof(buf),
7476 err));
77241056
MM		 7477 }
7478
7479 /*
7480 * Handle host message flags.
7481 */
7482 if (host_msg & HOST_REQ_DONE) {
7483 /*
7484 * Presently, the driver does a busy wait for
7485 * host requests to complete. This is only an
7486 * informational message.
7487 * NOTE: The 8051 clears the host message
7488 * information *on the next 8051 command*.
7489 * Therefore, when linkup is achieved,
7490 * this flag will still be set.
7491 */
7492 host_msg &= ~(u64)HOST_REQ_DONE;
7493 }
7494 if (host_msg & BC_SMA_MSG) {
7495 queue_work(ppd->hfi1_wq, &ppd->sma_message_work);
7496 host_msg &= ~(u64)BC_SMA_MSG;
7497 }
7498 if (host_msg & LINKUP_ACHIEVED) {
7499 dd_dev_info(dd, "8051: Link up\n");
7500 queue_work(ppd->hfi1_wq, &ppd->link_up_work);
7501 host_msg &= ~(u64)LINKUP_ACHIEVED;
7502 }
7503 if (host_msg & EXT_DEVICE_CFG_REQ) {
145dd2b3 7504 handle_8051_request(ppd);
77241056
MM		 7505 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7506 }
7507 if (host_msg & VERIFY_CAP_FRAME) {
7508 queue_work(ppd->hfi1_wq, &ppd->link_vc_work);
7509 host_msg &= ~(u64)VERIFY_CAP_FRAME;
7510 }
7511 if (host_msg & LINK_GOING_DOWN) {
7512 const char *extra = "";
7513 /* no downgrade action needed if going down */
7514 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7515 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7516 extra = " (ignoring downgrade)";
7517 }
7518 dd_dev_info(dd, "8051: Link down%s\n", extra);
7519 queue_link_down = 1;
7520 host_msg &= ~(u64)LINK_GOING_DOWN;
7521 }
7522 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7523 queue_work(ppd->hfi1_wq, &ppd->link_downgrade_work);
7524 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7525 }
7526 if (host_msg) {
7527 /* report remaining messages, but do not do anything */
7528 dd_dev_info(dd, "8051 info host message: %s\n",
17fb4f29
JJ		 7529 dc8051_info_host_msg_string(buf,
7530 sizeof(buf),
7531 host_msg));
77241056
MM		 7532 }
7533
7534 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7535 }
7536 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7537 /*
7538 * Lost the 8051 heartbeat. If this happens, we
7539 * receive constant interrupts about it. Disable
7540 * the interrupt after the first.
7541 */
7542 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7543 write_csr(dd, DC_DC8051_ERR_EN,
17fb4f29
JJ		 7544 read_csr(dd, DC_DC8051_ERR_EN) &
7545 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
77241056
MM		 7546
7547 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7548 }
7549 if (reg) {
7550 /* report the error, but do not do anything */
7551 dd_dev_err(dd, "8051 error: %s\n",
17fb4f29 7552 dc8051_err_string(buf, sizeof(buf), reg));
77241056
MM		 7553 }
7554
7555 if (queue_link_down) {
4d114fdd
JJ		 7556 /*
7557 * if the link is already going down or disabled, do not
7558 * queue another
7559 */
d0d236ea
JJ		 7560 if ((ppd->host_link_state &
7561 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
7562 ppd->link_enabled == 0) {
77241056 7563 dd_dev_info(dd, "%s: not queuing link down\n",
17fb4f29 7564 __func__);
77241056
MM		 7565 } else {
7566 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
7567 }
7568 }
7569}
7570
7571static const char * const fm_config_txt[] = {
7572[0] =
7573 "BadHeadDist: Distance violation between two head flits",
7574[1] =
7575 "BadTailDist: Distance violation between two tail flits",
7576[2] =
7577 "BadCtrlDist: Distance violation between two credit control flits",
7578[3] =
7579 "BadCrdAck: Credits return for unsupported VL",
7580[4] =
7581 "UnsupportedVLMarker: Received VL Marker",
7582[5] =
7583 "BadPreempt: Exceeded the preemption nesting level",
7584[6] =
7585 "BadControlFlit: Received unsupported control flit",
7586/* no 7 */
7587[8] =
7588 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7589};
7590
7591static const char * const port_rcv_txt[] = {
7592[1] =
7593 "BadPktLen: Illegal PktLen",
7594[2] =
7595 "PktLenTooLong: Packet longer than PktLen",
7596[3] =
7597 "PktLenTooShort: Packet shorter than PktLen",
7598[4] =
7599 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7600[5] =
7601 "BadDLID: Illegal DLID (0, doesn't match HFI)",
7602[6] =
7603 "BadL2: Illegal L2 opcode",
7604[7] =
7605 "BadSC: Unsupported SC",
7606[9] =
7607 "BadRC: Illegal RC",
7608[11] =
7609 "PreemptError: Preempting with same VL",
7610[12] =
7611 "PreemptVL15: Preempting a VL15 packet",
7612};
7613
7614#define OPA_LDR_FMCONFIG_OFFSET 16
7615#define OPA_LDR_PORTRCV_OFFSET 0
7616static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7617{
7618 u64 info, hdr0, hdr1;
7619 const char *extra;
7620 char buf[96];
7621 struct hfi1_pportdata *ppd = dd->pport;
7622 u8 lcl_reason = 0;
7623 int do_bounce = 0;
7624
7625 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7626 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7627 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7628 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7629 /* set status bit */
7630 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7631 }
7632 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7633 }
7634
7635 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7636 struct hfi1_pportdata *ppd = dd->pport;
7637 /* this counter saturates at (2^32) - 1 */
7638 if (ppd->link_downed < (u32)UINT_MAX)
7639 ppd->link_downed++;
7640 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7641 }
7642
7643 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7644 u8 reason_valid = 1;
7645
7646 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7647 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7648 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7649 /* set status bit */
7650 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
7651 }
7652 switch (info) {
7653 case 0:
7654 case 1:
7655 case 2:
7656 case 3:
7657 case 4:
7658 case 5:
7659 case 6:
7660 extra = fm_config_txt[info];
7661 break;
7662 case 8:
7663 extra = fm_config_txt[info];
7664 if (ppd->port_error_action &
7665 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7666 do_bounce = 1;
7667 /*
7668 * lcl_reason cannot be derived from info
7669 * for this error
7670 */
7671 lcl_reason =
7672 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7673 }
7674 break;
7675 default:
7676 reason_valid = 0;
7677 snprintf(buf, sizeof(buf), "reserved%lld", info);
7678 extra = buf;
7679 break;
7680 }
7681
7682 if (reason_valid && !do_bounce) {
7683 do_bounce = ppd->port_error_action &
7684 (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
7685 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
7686 }
7687
7688 /* just report this */
7689 dd_dev_info(dd, "DCC Error: fmconfig error: %s\n", extra);
7690 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
7691 }
7692
7693 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
7694 u8 reason_valid = 1;
7695
7696 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
7697 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
7698 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
7699 if (!(dd->err_info_rcvport.status_and_code &
7700 OPA_EI_STATUS_SMASK)) {
7701 dd->err_info_rcvport.status_and_code =
7702 info & OPA_EI_CODE_SMASK;
7703 /* set status bit */
7704 dd->err_info_rcvport.status_and_code |=
7705 OPA_EI_STATUS_SMASK;
4d114fdd
JJ		 7706 /*
7707 * save first 2 flits in the packet that caused
7708 * the error
7709 */
77241056
MM		 7710 dd->err_info_rcvport.packet_flit1 = hdr0;
7711 dd->err_info_rcvport.packet_flit2 = hdr1;
7712 }
7713 switch (info) {
7714 case 1:
7715 case 2:
7716 case 3:
7717 case 4:
7718 case 5:
7719 case 6:
7720 case 7:
7721 case 9:
7722 case 11:
7723 case 12:
7724 extra = port_rcv_txt[info];
7725 break;
7726 default:
7727 reason_valid = 0;
7728 snprintf(buf, sizeof(buf), "reserved%lld", info);
7729 extra = buf;
7730 break;
7731 }
7732
7733 if (reason_valid && !do_bounce) {
7734 do_bounce = ppd->port_error_action &
7735 (1 << (OPA_LDR_PORTRCV_OFFSET + info));
7736 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
7737 }
7738
7739 /* just report this */
7740 dd_dev_info(dd, "DCC Error: PortRcv error: %s\n", extra);
7741 dd_dev_info(dd, " hdr0 0x%llx, hdr1 0x%llx\n",
17fb4f29 7742 hdr0, hdr1);
77241056
MM		 7743
7744 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
7745 }
7746
7747 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
7748 /* informative only */
7749 dd_dev_info(dd, "8051 access to LCB blocked\n");
7750 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
7751 }
7752 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
7753 /* informative only */
7754 dd_dev_info(dd, "host access to LCB blocked\n");
7755 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
7756 }
7757
7758 /* report any remaining errors */
7759 if (reg)
7760 dd_dev_info(dd, "DCC Error: %s\n",
17fb4f29 7761 dcc_err_string(buf, sizeof(buf), reg));
77241056
MM		 7762
7763 if (lcl_reason == 0)
7764 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
7765
7766 if (do_bounce) {
7767 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
7768 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
7769 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
7770 }
7771}
7772
7773static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7774{
7775 char buf[96];
7776
7777 dd_dev_info(dd, "LCB Error: %s\n",
17fb4f29 7778 lcb_err_string(buf, sizeof(buf), reg));
77241056
MM		 7779}
7780
7781/*
7782 * CCE block DC interrupt. Source is < 8.
7783 */
7784static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
7785{
7786 const struct err_reg_info *eri = &dc_errs[source];
7787
7788 if (eri->handler) {
7789 interrupt_clear_down(dd, 0, eri);
7790 } else if (source == 3 /* dc_lbm_int */) {
7791 /*
7792 * This indicates that a parity error has occurred on the
7793 * address/control lines presented to the LBM. The error
7794 * is a single pulse, there is no associated error flag,
7795 * and it is non-maskable. This is because if a parity
7796 * error occurs on the request the request is dropped.
7797 * This should never occur, but it is nice to know if it
7798 * ever does.
7799 */
7800 dd_dev_err(dd, "Parity error in DC LBM block\n");
7801 } else {
7802 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
7803 }
7804}
7805
7806/*
7807 * TX block send credit interrupt. Source is < 160.
7808 */
7809static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
7810{
7811 sc_group_release_update(dd, source);
7812}
7813
7814/*
7815 * TX block SDMA interrupt. Source is < 48.
7816 *
7817 * SDMA interrupts are grouped by type:
7818 *
7819 * 0 - N-1 = SDma
7820 * N - 2N-1 = SDmaProgress
7821 * 2N - 3N-1 = SDmaIdle
7822 */
7823static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
7824{
7825 /* what interrupt */
7826 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
7827 /* which engine */
7828 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
7829
7830#ifdef CONFIG_SDMA_VERBOSITY
7831 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
7832 slashstrip(__FILE__), __LINE__, __func__);
7833 sdma_dumpstate(&dd->per_sdma[which]);
7834#endif
7835
7836 if (likely(what < 3 && which < dd->num_sdma)) {
7837 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
7838 } else {
7839 /* should not happen */
7840 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
7841 }
7842}
7843
7844/*
7845 * RX block receive available interrupt. Source is < 160.
7846 */
7847static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
7848{
7849 struct hfi1_ctxtdata *rcd;
7850 char *err_detail;
7851
7852 if (likely(source < dd->num_rcv_contexts)) {
7853 rcd = dd->rcd[source];
7854 if (rcd) {
7855 if (source < dd->first_user_ctxt)
f4f30031 7856 rcd->do_interrupt(rcd, 0);
77241056
MM		 7857 else
7858 handle_user_interrupt(rcd);
7859 return; /* OK */
7860 }
7861 /* received an interrupt, but no rcd */
7862 err_detail = "dataless";
7863 } else {
7864 /* received an interrupt, but are not using that context */
7865 err_detail = "out of range";
7866 }
7867 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
17fb4f29 7868 err_detail, source);
77241056
MM		 7869}
7870
7871/*
7872 * RX block receive urgent interrupt. Source is < 160.
7873 */
7874static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
7875{
7876 struct hfi1_ctxtdata *rcd;
7877 char *err_detail;
7878
7879 if (likely(source < dd->num_rcv_contexts)) {
7880 rcd = dd->rcd[source];
7881 if (rcd) {
7882 /* only pay attention to user urgent interrupts */
7883 if (source >= dd->first_user_ctxt)
7884 handle_user_interrupt(rcd);
7885 return; /* OK */
7886 }
7887 /* received an interrupt, but no rcd */
7888 err_detail = "dataless";
7889 } else {
7890 /* received an interrupt, but are not using that context */
7891 err_detail = "out of range";
7892 }
7893 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
17fb4f29 7894 err_detail, source);
77241056
MM		 7895}
7896
7897/*
7898 * Reserved range interrupt. Should not be called in normal operation.
7899 */
7900static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
7901{
7902 char name[64];
7903
7904 dd_dev_err(dd, "unexpected %s interrupt\n",
17fb4f29 7905 is_reserved_name(name, sizeof(name), source));
77241056
MM		 7906}
7907
7908static const struct is_table is_table[] = {
4d114fdd
JJ		 7909/*
7910 * start end
7911 * name func interrupt func
7912 */
77241056
MM		 7913{ IS_GENERAL_ERR_START, IS_GENERAL_ERR_END,
7914 is_misc_err_name, is_misc_err_int },
7915{ IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END,
7916 is_sdma_eng_err_name, is_sdma_eng_err_int },
7917{ IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
7918 is_sendctxt_err_name, is_sendctxt_err_int },
7919{ IS_SDMA_START, IS_SDMA_END,
7920 is_sdma_eng_name, is_sdma_eng_int },
7921{ IS_VARIOUS_START, IS_VARIOUS_END,
7922 is_various_name, is_various_int },
7923{ IS_DC_START, IS_DC_END,
7924 is_dc_name, is_dc_int },
7925{ IS_RCVAVAIL_START, IS_RCVAVAIL_END,
7926 is_rcv_avail_name, is_rcv_avail_int },
7927{ IS_RCVURGENT_START, IS_RCVURGENT_END,
7928 is_rcv_urgent_name, is_rcv_urgent_int },
7929{ IS_SENDCREDIT_START, IS_SENDCREDIT_END,
7930 is_send_credit_name, is_send_credit_int},
7931{ IS_RESERVED_START, IS_RESERVED_END,
7932 is_reserved_name, is_reserved_int},
7933};
7934
7935/*
7936 * Interrupt source interrupt - called when the given source has an interrupt.
7937 * Source is a bit index into an array of 64-bit integers.
7938 */
7939static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
7940{
7941 const struct is_table *entry;
7942
7943 /* avoids a double compare by walking the table in-order */
7944 for (entry = &is_table[0]; entry->is_name; entry++) {
7945 if (source < entry->end) {
7946 trace_hfi1_interrupt(dd, entry, source);
7947 entry->is_int(dd, source - entry->start);
7948 return;
7949 }
7950 }
7951 /* fell off the end */
7952 dd_dev_err(dd, "invalid interrupt source %u\n", source);
7953}
7954
7955/*
7956 * General interrupt handler. This is able to correctly handle
7957 * all interrupts in case INTx is used.
7958 */
7959static irqreturn_t general_interrupt(int irq, void *data)
7960{
7961 struct hfi1_devdata *dd = data;
7962 u64 regs[CCE_NUM_INT_CSRS];
7963 u32 bit;
7964 int i;
7965
7966 this_cpu_inc(*dd->int_counter);
7967
7968 /* phase 1: scan and clear all handled interrupts */
7969 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
7970 if (dd->gi_mask[i] == 0) {
7971 regs[i] = 0; /* used later */
7972 continue;
7973 }
7974 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
7975 dd->gi_mask[i];
7976 /* only clear if anything is set */
7977 if (regs[i])
7978 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
7979 }
7980
7981 /* phase 2: call the appropriate handler */
7982 for_each_set_bit(bit, (unsigned long *)&regs[0],
17fb4f29 7983 CCE_NUM_INT_CSRS * 64) {
77241056
MM		 7984 is_interrupt(dd, bit);
7985 }
7986
7987 return IRQ_HANDLED;
7988}
7989
7990static irqreturn_t sdma_interrupt(int irq, void *data)
7991{
7992 struct sdma_engine *sde = data;
7993 struct hfi1_devdata *dd = sde->dd;
7994 u64 status;
7995
7996#ifdef CONFIG_SDMA_VERBOSITY
7997 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
7998 slashstrip(__FILE__), __LINE__, __func__);
7999 sdma_dumpstate(sde);
8000#endif
8001
8002 this_cpu_inc(*dd->int_counter);
8003
8004 /* This read_csr is really bad in the hot path */
8005 status = read_csr(dd,
17fb4f29
JJ		 8006 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
8007 & sde->imask;
77241056
MM		 8008 if (likely(status)) {
8009 /* clear the interrupt(s) */
8010 write_csr(dd,
17fb4f29
JJ		 8011 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
8012 status);
77241056
MM		 8013
8014 /* handle the interrupt(s) */
8015 sdma_engine_interrupt(sde, status);
8016 } else
8017 dd_dev_err(dd, "SDMA engine %u interrupt, but no status bits set\n",
17fb4f29 8018 sde->this_idx);
77241056
MM		 8019
8020 return IRQ_HANDLED;
8021}
8022
8023/*
ecd42f8d
DL		 8024 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8025 * to insure that the write completed. This does NOT guarantee that
8026 * queued DMA writes to memory from the chip are pushed.
f4f30031
DL		 8027 */
8028static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8029{
8030 struct hfi1_devdata *dd = rcd->dd;
8031 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8032
8033 mmiowb(); /* make sure everything before is written */
8034 write_csr(dd, addr, rcd->imask);
8035 /* force the above write on the chip and get a value back */
8036 (void)read_csr(dd, addr);
8037}
8038
8039/* force the receive interrupt */
fb9036dd 8040void force_recv_intr(struct hfi1_ctxtdata *rcd)
f4f30031
DL		 8041{
8042 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8043}
8044
ecd42f8d
DL		 8045/*
8046 * Return non-zero if a packet is present.
8047 *
8048 * This routine is called when rechecking for packets after the RcvAvail
8049 * interrupt has been cleared down. First, do a quick check of memory for
8050 * a packet present. If not found, use an expensive CSR read of the context
8051 * tail to determine the actual tail. The CSR read is necessary because there
8052 * is no method to push pending DMAs to memory other than an interrupt and we
8053 * are trying to determine if we need to force an interrupt.
8054 */
f4f30031
DL		 8055static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8056{
ecd42f8d
DL		 8057 u32 tail;
8058 int present;
8059
f4f30031 8060 if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
ecd42f8d 8061 present = (rcd->seq_cnt ==
f4f30031 8062 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
ecd42f8d
DL		 8063 else /* is RDMA rtail */
8064 present = (rcd->head != get_rcvhdrtail(rcd));
8065
8066 if (present)
8067 return 1;
f4f30031 8068
ecd42f8d
DL		 8069 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8070 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8071 return rcd->head != tail;
f4f30031
DL		 8072}
8073
8074/*
8075 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8076 * This routine will try to handle packets immediately (latency), but if
8077 * it finds too many, it will invoke the thread handler (bandwitdh). The
16733b88 8078 * chip receive interrupt is *not* cleared down until this or the thread (if
f4f30031
DL		 8079 * invoked) is finished. The intent is to avoid extra interrupts while we
8080 * are processing packets anyway.
77241056
MM		 8081 */
8082static irqreturn_t receive_context_interrupt(int irq, void *data)
8083{
8084 struct hfi1_ctxtdata *rcd = data;
8085 struct hfi1_devdata *dd = rcd->dd;
f4f30031
DL		 8086 int disposition;
8087 int present;
77241056
MM		 8088
8089 trace_hfi1_receive_interrupt(dd, rcd->ctxt);
8090 this_cpu_inc(*dd->int_counter);
affa48de 8091 aspm_ctx_disable(rcd);
77241056 8092
f4f30031
DL		 8093 /* receive interrupt remains blocked while processing packets */
8094 disposition = rcd->do_interrupt(rcd, 0);
77241056 8095
f4f30031
DL		 8096 /*
8097 * Too many packets were seen while processing packets in this
8098 * IRQ handler. Invoke the handler thread. The receive interrupt
8099 * remains blocked.
8100 */
8101 if (disposition == RCV_PKT_LIMIT)
8102 return IRQ_WAKE_THREAD;
8103
8104 /*
8105 * The packet processor detected no more packets. Clear the receive
8106 * interrupt and recheck for a packet packet that may have arrived
8107 * after the previous check and interrupt clear. If a packet arrived,
8108 * force another interrupt.
8109 */
8110 clear_recv_intr(rcd);
8111 present = check_packet_present(rcd);
8112 if (present)
8113 force_recv_intr(rcd);
8114
8115 return IRQ_HANDLED;
8116}
8117
8118/*
8119 * Receive packet thread handler. This expects to be invoked with the
8120 * receive interrupt still blocked.
8121 */
8122static irqreturn_t receive_context_thread(int irq, void *data)
8123{
8124 struct hfi1_ctxtdata *rcd = data;
8125 int present;
8126
8127 /* receive interrupt is still blocked from the IRQ handler */
8128 (void)rcd->do_interrupt(rcd, 1);
8129
8130 /*
8131 * The packet processor will only return if it detected no more
8132 * packets. Hold IRQs here so we can safely clear the interrupt and
8133 * recheck for a packet that may have arrived after the previous
8134 * check and the interrupt clear. If a packet arrived, force another
8135 * interrupt.
8136 */
8137 local_irq_disable();
8138 clear_recv_intr(rcd);
8139 present = check_packet_present(rcd);
8140 if (present)
8141 force_recv_intr(rcd);
8142 local_irq_enable();
77241056
MM		 8143
8144 return IRQ_HANDLED;
8145}
8146
8147/* ========================================================================= */
8148
8149u32 read_physical_state(struct hfi1_devdata *dd)
8150{
8151 u64 reg;
8152
8153 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8154 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8155 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8156}
8157
fb9036dd 8158u32 read_logical_state(struct hfi1_devdata *dd)
77241056
MM		 8159{
8160 u64 reg;
8161
8162 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8163 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8164 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8165}
8166
8167static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8168{
8169 u64 reg;
8170
8171 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8172 /* clear current state, set new state */
8173 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8174 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8175 write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8176}
8177
8178/*
8179 * Use the 8051 to read a LCB CSR.
8180 */
8181static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8182{
8183 u32 regno;
8184 int ret;
8185
8186 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8187 if (acquire_lcb_access(dd, 0) == 0) {
8188 *data = read_csr(dd, addr);
8189 release_lcb_access(dd, 0);
8190 return 0;
8191 }
8192 return -EBUSY;
8193 }
8194
8195 /* register is an index of LCB registers: (offset - base) / 8 */
8196 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8197 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8198 if (ret != HCMD_SUCCESS)
8199 return -EBUSY;
8200 return 0;
8201}
8202
8203/*
8204 * Read an LCB CSR. Access may not be in host control, so check.
8205 * Return 0 on success, -EBUSY on failure.
8206 */
8207int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8208{
8209 struct hfi1_pportdata *ppd = dd->pport;
8210
8211 /* if up, go through the 8051 for the value */
8212 if (ppd->host_link_state & HLS_UP)
8213 return read_lcb_via_8051(dd, addr, data);
8214 /* if going up or down, no access */
8215 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8216 return -EBUSY;
8217 /* otherwise, host has access */
8218 *data = read_csr(dd, addr);
8219 return 0;
8220}
8221
8222/*
8223 * Use the 8051 to write a LCB CSR.
8224 */
8225static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8226{
3bf40d65
DL		 8227 u32 regno;
8228 int ret;
77241056 8229
3bf40d65
DL		 8230 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
8231 (dd->dc8051_ver < dc8051_ver(0, 20))) {
8232 if (acquire_lcb_access(dd, 0) == 0) {
8233 write_csr(dd, addr, data);
8234 release_lcb_access(dd, 0);
8235 return 0;
8236 }
8237 return -EBUSY;
77241056 8238 }
3bf40d65
DL		 8239
8240 /* register is an index of LCB registers: (offset - base) / 8 */
8241 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8242 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8243 if (ret != HCMD_SUCCESS)
8244 return -EBUSY;
8245 return 0;
77241056
MM		 8246}
8247
8248/*
8249 * Write an LCB CSR. Access may not be in host control, so check.
8250 * Return 0 on success, -EBUSY on failure.
8251 */
8252int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8253{
8254 struct hfi1_pportdata *ppd = dd->pport;
8255
8256 /* if up, go through the 8051 for the value */
8257 if (ppd->host_link_state & HLS_UP)
8258 return write_lcb_via_8051(dd, addr, data);
8259 /* if going up or down, no access */
8260 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8261 return -EBUSY;
8262 /* otherwise, host has access */
8263 write_csr(dd, addr, data);
8264 return 0;
8265}
8266
8267/*
8268 * Returns:
8269 * < 0 = Linux error, not able to get access
8270 * > 0 = 8051 command RETURN_CODE
8271 */
8272static int do_8051_command(
8273 struct hfi1_devdata *dd,
8274 u32 type,
8275 u64 in_data,
8276 u64 *out_data)
8277{
8278 u64 reg, completed;
8279 int return_code;
8280 unsigned long flags;
8281 unsigned long timeout;
8282
8283 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8284
8285 /*
8286 * Alternative to holding the lock for a long time:
8287 * - keep busy wait - have other users bounce off
8288 */
8289 spin_lock_irqsave(&dd->dc8051_lock, flags);
8290
8291 /* We can't send any commands to the 8051 if it's in reset */
8292 if (dd->dc_shutdown) {
8293 return_code = -ENODEV;
8294 goto fail;
8295 }
8296
8297 /*
8298 * If an 8051 host command timed out previously, then the 8051 is
8299 * stuck.
8300 *
8301 * On first timeout, attempt to reset and restart the entire DC
8302 * block (including 8051). (Is this too big of a hammer?)
8303 *
8304 * If the 8051 times out a second time, the reset did not bring it
8305 * back to healthy life. In that case, fail any subsequent commands.
8306 */
8307 if (dd->dc8051_timed_out) {
8308 if (dd->dc8051_timed_out > 1) {
8309 dd_dev_err(dd,
8310 "Previous 8051 host command timed out, skipping command %u\n",
8311 type);
8312 return_code = -ENXIO;
8313 goto fail;
8314 }
8315 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8316 dc_shutdown(dd);
8317 dc_start(dd);
8318 spin_lock_irqsave(&dd->dc8051_lock, flags);
8319 }
8320
8321 /*
8322 * If there is no timeout, then the 8051 command interface is
8323 * waiting for a command.
8324 */
8325
3bf40d65
DL		 8326 /*
8327 * When writing a LCB CSR, out_data contains the full value to
8328 * to be written, while in_data contains the relative LCB
8329 * address in 7:0. Do the work here, rather than the caller,
8330 * of distrubting the write data to where it needs to go:
8331 *
8332 * Write data
8333 * 39:00 -> in_data[47:8]
8334 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8335 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8336 */
8337 if (type == HCMD_WRITE_LCB_CSR) {
8338 in_data |= ((*out_data) & 0xffffffffffull) << 8;
8339 reg = ((((*out_data) >> 40) & 0xff) <<
8340 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8341 | ((((*out_data) >> 48) & 0xffff) <<
8342 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8343 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8344 }
8345
77241056
MM		 8346 /*
8347 * Do two writes: the first to stabilize the type and req_data, the
8348 * second to activate.
8349 */
8350 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8351 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8352 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8353 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8354 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8355 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8356 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8357
8358 /* wait for completion, alternate: interrupt */
8359 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8360 while (1) {
8361 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8362 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8363 if (completed)
8364 break;
8365 if (time_after(jiffies, timeout)) {
8366 dd->dc8051_timed_out++;
8367 dd_dev_err(dd, "8051 host command %u timeout\n", type);
8368 if (out_data)
8369 *out_data = 0;
8370 return_code = -ETIMEDOUT;
8371 goto fail;
8372 }
8373 udelay(2);
8374 }
8375
8376 if (out_data) {
8377 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8378 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8379 if (type == HCMD_READ_LCB_CSR) {
8380 /* top 16 bits are in a different register */
8381 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8382 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8383 << (48
8384 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8385 }
8386 }
8387 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8388 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8389 dd->dc8051_timed_out = 0;
8390 /*
8391 * Clear command for next user.
8392 */
8393 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8394
8395fail:
8396 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8397
8398 return return_code;
8399}
8400
8401static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8402{
8403 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8404}
8405
8ebd4cf1
EH		 8406int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8407 u8 lane_id, u32 config_data)
77241056
MM		 8408{
8409 u64 data;
8410 int ret;
8411
8412 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8413 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8414 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8415 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8416 if (ret != HCMD_SUCCESS) {
8417 dd_dev_err(dd,
17fb4f29
JJ		 8418 "load 8051 config: field id %d, lane %d, err %d\n",
8419 (int)field_id, (int)lane_id, ret);
77241056
MM		 8420 }
8421 return ret;
8422}
8423
8424/*
8425 * Read the 8051 firmware "registers". Use the RAM directly. Always
8426 * set the result, even on error.
8427 * Return 0 on success, -errno on failure
8428 */
8ebd4cf1
EH		 8429int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8430 u32 *result)
77241056
MM		 8431{
8432 u64 big_data;
8433 u32 addr;
8434 int ret;
8435
8436 /* address start depends on the lane_id */
8437 if (lane_id < 4)
8438 addr = (4 * NUM_GENERAL_FIELDS)
8439 + (lane_id * 4 * NUM_LANE_FIELDS);
8440 else
8441 addr = 0;
8442 addr += field_id * 4;
8443
8444 /* read is in 8-byte chunks, hardware will truncate the address down */
8445 ret = read_8051_data(dd, addr, 8, &big_data);
8446
8447 if (ret == 0) {
8448 /* extract the 4 bytes we want */
8449 if (addr & 0x4)
8450 *result = (u32)(big_data >> 32);
8451 else
8452 *result = (u32)big_data;
8453 } else {
8454 *result = 0;
8455 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
17fb4f29 8456 __func__, lane_id, field_id);
77241056
MM		 8457 }
8458
8459 return ret;
8460}
8461
8462static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8463 u8 continuous)
8464{
8465 u32 frame;
8466
8467 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8468 | power_management << POWER_MANAGEMENT_SHIFT;
8469 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8470 GENERAL_CONFIG, frame);
8471}
8472
8473static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8474 u16 vl15buf, u8 crc_sizes)
8475{
8476 u32 frame;
8477
8478 frame = (u32)vau << VAU_SHIFT
8479 | (u32)z << Z_SHIFT
8480 | (u32)vcu << VCU_SHIFT
8481 | (u32)vl15buf << VL15BUF_SHIFT
8482 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8483 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8484 GENERAL_CONFIG, frame);
8485}
8486
8487static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
8488 u8 *flag_bits, u16 *link_widths)
8489{
8490 u32 frame;
8491
8492 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
17fb4f29 8493 &frame);
77241056
MM		 8494 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8495 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8496 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8497}
8498
8499static int write_vc_local_link_width(struct hfi1_devdata *dd,
8500 u8 misc_bits,
8501 u8 flag_bits,
8502 u16 link_widths)
8503{
8504 u32 frame;
8505
8506 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8507 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8508 | (u32)link_widths << LINK_WIDTH_SHIFT;
8509 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8510 frame);
8511}
8512
8513static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8514 u8 device_rev)
8515{
8516 u32 frame;
8517
8518 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8519 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8520 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8521}
8522
8523static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8524 u8 *device_rev)
8525{
8526 u32 frame;
8527
8528 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
8529 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
8530 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
8531 & REMOTE_DEVICE_REV_MASK;
8532}
8533
8534void read_misc_status(struct hfi1_devdata *dd, u8 *ver_a, u8 *ver_b)
8535{
8536 u32 frame;
8537
8538 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
8539 *ver_a = (frame >> STS_FM_VERSION_A_SHIFT) & STS_FM_VERSION_A_MASK;
8540 *ver_b = (frame >> STS_FM_VERSION_B_SHIFT) & STS_FM_VERSION_B_MASK;
8541}
8542
8543static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
8544 u8 *continuous)
8545{
8546 u32 frame;
8547
8548 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
8549 *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
8550 & POWER_MANAGEMENT_MASK;
8551 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
8552 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
8553}
8554
8555static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
8556 u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
8557{
8558 u32 frame;
8559
8560 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
8561 *vau = (frame >> VAU_SHIFT) & VAU_MASK;
8562 *z = (frame >> Z_SHIFT) & Z_MASK;
8563 *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
8564 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
8565 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
8566}
8567
8568static void read_vc_remote_link_width(struct hfi1_devdata *dd,
8569 u8 *remote_tx_rate,
8570 u16 *link_widths)
8571{
8572 u32 frame;
8573
8574 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
17fb4f29 8575 &frame);
77241056
MM		 8576 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
8577 & REMOTE_TX_RATE_MASK;
8578 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8579}
8580
8581static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8582{
8583 u32 frame;
8584
8585 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
8586 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8587}
8588
8589static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed)
8590{
8591 u32 frame;
8592
8593 read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
8594 *mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT) & MGMT_ALLOWED_MASK;
8595}
8596
8597static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8598{
8599 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
8600}
8601
8602static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
8603{
8604 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
8605}
8606
8607void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
8608{
8609 u32 frame;
8610 int ret;
8611
8612 *link_quality = 0;
8613 if (dd->pport->host_link_state & HLS_UP) {
8614 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
17fb4f29 8615 &frame);
77241056
MM		 8616 if (ret == 0)
8617 *link_quality = (frame >> LINK_QUALITY_SHIFT)
8618 & LINK_QUALITY_MASK;
8619 }
8620}
8621
8622static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
8623{
8624 u32 frame;
8625
8626 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
8627 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
8628}
8629
8630static int read_tx_settings(struct hfi1_devdata *dd,
8631 u8 *enable_lane_tx,
8632 u8 *tx_polarity_inversion,
8633 u8 *rx_polarity_inversion,
8634 u8 *max_rate)
8635{
8636 u32 frame;
8637 int ret;
8638
8639 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
8640 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
8641 & ENABLE_LANE_TX_MASK;
8642 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
8643 & TX_POLARITY_INVERSION_MASK;
8644 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
8645 & RX_POLARITY_INVERSION_MASK;
8646 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
8647 return ret;
8648}
8649
8650static int write_tx_settings(struct hfi1_devdata *dd,
8651 u8 enable_lane_tx,
8652 u8 tx_polarity_inversion,
8653 u8 rx_polarity_inversion,
8654 u8 max_rate)
8655{
8656 u32 frame;
8657
8658 /* no need to mask, all variable sizes match field widths */
8659 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
8660 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
8661 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
8662 | max_rate << MAX_RATE_SHIFT;
8663 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
8664}
8665
8666static void check_fabric_firmware_versions(struct hfi1_devdata *dd)
8667{
8668 u32 frame, version, prod_id;
8669 int ret, lane;
8670
8671 /* 4 lanes */
8672 for (lane = 0; lane < 4; lane++) {
8673 ret = read_8051_config(dd, SPICO_FW_VERSION, lane, &frame);
8674 if (ret) {
17fb4f29
JJ		 8675 dd_dev_err(dd,
8676 "Unable to read lane %d firmware details\n",
8677 lane);
77241056
MM		 8678 continue;
8679 }
8680 version = (frame >> SPICO_ROM_VERSION_SHIFT)
8681 & SPICO_ROM_VERSION_MASK;
8682 prod_id = (frame >> SPICO_ROM_PROD_ID_SHIFT)
8683 & SPICO_ROM_PROD_ID_MASK;
8684 dd_dev_info(dd,
17fb4f29
JJ		 8685 "Lane %d firmware: version 0x%04x, prod_id 0x%04x\n",
8686 lane, version, prod_id);
77241056
MM		 8687 }
8688}
8689
8690/*
8691 * Read an idle LCB message.
8692 *
8693 * Returns 0 on success, -EINVAL on error
8694 */
8695static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
8696{
8697 int ret;
8698
17fb4f29 8699 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out);
77241056
MM		 8700 if (ret != HCMD_SUCCESS) {
8701 dd_dev_err(dd, "read idle message: type %d, err %d\n",
17fb4f29 8702 (u32)type, ret);
77241056
MM		 8703 return -EINVAL;
8704 }
8705 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
8706 /* return only the payload as we already know the type */
8707 *data_out >>= IDLE_PAYLOAD_SHIFT;
8708 return 0;
8709}
8710
8711/*
8712 * Read an idle SMA message. To be done in response to a notification from
8713 * the 8051.
8714 *
8715 * Returns 0 on success, -EINVAL on error
8716 */
8717static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
8718{
17fb4f29
JJ		 8719 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT,
8720 data);
77241056
MM		 8721}
8722
8723/*
8724 * Send an idle LCB message.
8725 *
8726 * Returns 0 on success, -EINVAL on error
8727 */
8728static int send_idle_message(struct hfi1_devdata *dd, u64 data)
8729{
8730 int ret;
8731
8732 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
8733 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
8734 if (ret != HCMD_SUCCESS) {
8735 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
17fb4f29 8736 data, ret);
77241056
MM		 8737 return -EINVAL;
8738 }
8739 return 0;
8740}
8741
8742/*
8743 * Send an idle SMA message.
8744 *
8745 * Returns 0 on success, -EINVAL on error
8746 */
8747int send_idle_sma(struct hfi1_devdata *dd, u64 message)
8748{
8749 u64 data;
8750
17fb4f29
JJ		 8751 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) |
8752 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
77241056
MM		 8753 return send_idle_message(dd, data);
8754}
8755
8756/*
8757 * Initialize the LCB then do a quick link up. This may or may not be
8758 * in loopback.
8759 *
8760 * return 0 on success, -errno on error
8761 */
8762static int do_quick_linkup(struct hfi1_devdata *dd)
8763{
8764 u64 reg;
8765 unsigned long timeout;
8766 int ret;
8767
8768 lcb_shutdown(dd, 0);
8769
8770 if (loopback) {
8771 /* LCB_CFG_LOOPBACK.VAL = 2 */
8772 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
8773 write_csr(dd, DC_LCB_CFG_LOOPBACK,
17fb4f29 8774 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
77241056
MM		 8775 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
8776 }
8777
8778 /* start the LCBs */
8779 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
8780 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
8781
8782 /* simulator only loopback steps */
8783 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8784 /* LCB_CFG_RUN.EN = 1 */
8785 write_csr(dd, DC_LCB_CFG_RUN,
17fb4f29 8786 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
77241056
MM		 8787
8788 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
8789 timeout = jiffies + msecs_to_jiffies(10);
8790 while (1) {
17fb4f29 8791 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
77241056
MM		 8792 if (reg)
8793 break;
8794 if (time_after(jiffies, timeout)) {
8795 dd_dev_err(dd,
17fb4f29 8796 "timeout waiting for LINK_TRANSFER_ACTIVE\n");
77241056
MM		 8797 return -ETIMEDOUT;
8798 }
8799 udelay(2);
8800 }
8801
8802 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
17fb4f29 8803 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
77241056
MM		 8804 }
8805
8806 if (!loopback) {
8807 /*
8808 * When doing quick linkup and not in loopback, both
8809 * sides must be done with LCB set-up before either
8810 * starts the quick linkup. Put a delay here so that
8811 * both sides can be started and have a chance to be
8812 * done with LCB set up before resuming.
8813 */
8814 dd_dev_err(dd,
17fb4f29 8815 "Pausing for peer to be finished with LCB set up\n");
77241056 8816 msleep(5000);
17fb4f29 8817 dd_dev_err(dd, "Continuing with quick linkup\n");
77241056
MM		 8818 }
8819
8820 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
8821 set_8051_lcb_access(dd);
8822
8823 /*
8824 * State "quick" LinkUp request sets the physical link state to
8825 * LinkUp without a verify capability sequence.
8826 * This state is in simulator v37 and later.
8827 */
8828 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
8829 if (ret != HCMD_SUCCESS) {
8830 dd_dev_err(dd,
17fb4f29
JJ		 8831 "%s: set physical link state to quick LinkUp failed with return %d\n",
8832 __func__, ret);
77241056
MM		 8833
8834 set_host_lcb_access(dd);
8835 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
8836
8837 if (ret >= 0)
8838 ret = -EINVAL;
8839 return ret;
8840 }
8841
8842 return 0; /* success */
8843}
8844
8845/*
8846 * Set the SerDes to internal loopback mode.
8847 * Returns 0 on success, -errno on error.
8848 */
8849static int set_serdes_loopback_mode(struct hfi1_devdata *dd)
8850{
8851 int ret;
8852
8853 ret = set_physical_link_state(dd, PLS_INTERNAL_SERDES_LOOPBACK);
8854 if (ret == HCMD_SUCCESS)
8855 return 0;
8856 dd_dev_err(dd,
17fb4f29
JJ		 8857 "Set physical link state to SerDes Loopback failed with return %d\n",
8858 ret);
77241056
MM		 8859 if (ret >= 0)
8860 ret = -EINVAL;
8861 return ret;
8862}
8863
8864/*
8865 * Do all special steps to set up loopback.
8866 */
8867static int init_loopback(struct hfi1_devdata *dd)
8868{
8869 dd_dev_info(dd, "Entering loopback mode\n");
8870
8871 /* all loopbacks should disable self GUID check */
8872 write_csr(dd, DC_DC8051_CFG_MODE,
17fb4f29 8873 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
77241056
MM		 8874
8875 /*
8876 * The simulator has only one loopback option - LCB. Switch
8877 * to that option, which includes quick link up.
8878 *
8879 * Accept all valid loopback values.
8880 */
d0d236ea
JJ		 8881 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) &&
8882 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB ||
8883 loopback == LOOPBACK_CABLE)) {
77241056
MM		 8884 loopback = LOOPBACK_LCB;
8885 quick_linkup = 1;
8886 return 0;
8887 }
8888
8889 /* handle serdes loopback */
8890 if (loopback == LOOPBACK_SERDES) {
8891 /* internal serdes loopack needs quick linkup on RTL */
8892 if (dd->icode == ICODE_RTL_SILICON)
8893 quick_linkup = 1;
8894 return set_serdes_loopback_mode(dd);
8895 }
8896
8897 /* LCB loopback - handled at poll time */
8898 if (loopback == LOOPBACK_LCB) {
8899 quick_linkup = 1; /* LCB is always quick linkup */
8900
8901 /* not supported in emulation due to emulation RTL changes */
8902 if (dd->icode == ICODE_FPGA_EMULATION) {
8903 dd_dev_err(dd,
17fb4f29 8904 "LCB loopback not supported in emulation\n");
77241056
MM		 8905 return -EINVAL;
8906 }
8907 return 0;
8908 }
8909
8910 /* external cable loopback requires no extra steps */
8911 if (loopback == LOOPBACK_CABLE)
8912 return 0;
8913
8914 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
8915 return -EINVAL;
8916}
8917
8918/*
8919 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
8920 * used in the Verify Capability link width attribute.
8921 */
8922static u16 opa_to_vc_link_widths(u16 opa_widths)
8923{
8924 int i;
8925 u16 result = 0;
8926
8927 static const struct link_bits {
8928 u16 from;
8929 u16 to;
8930 } opa_link_xlate[] = {
8638b77f
JJ		 8931 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) },
8932 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) },
8933 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) },
8934 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) },
77241056
MM		 8935 };
8936
8937 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
8938 if (opa_widths & opa_link_xlate[i].from)
8939 result |= opa_link_xlate[i].to;
8940 }
8941 return result;
8942}
8943
8944/*
8945 * Set link attributes before moving to polling.
8946 */
8947static int set_local_link_attributes(struct hfi1_pportdata *ppd)
8948{
8949 struct hfi1_devdata *dd = ppd->dd;
8950 u8 enable_lane_tx;
8951 u8 tx_polarity_inversion;
8952 u8 rx_polarity_inversion;
8953 int ret;
8954
8955 /* reset our fabric serdes to clear any lingering problems */
8956 fabric_serdes_reset(dd);
8957
8958 /* set the local tx rate - need to read-modify-write */
8959 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
17fb4f29 8960 &rx_polarity_inversion, &ppd->local_tx_rate);
77241056
MM		 8961 if (ret)
8962 goto set_local_link_attributes_fail;
8963
8964 if (dd->dc8051_ver < dc8051_ver(0, 20)) {
8965 /* set the tx rate to the fastest enabled */
8966 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
8967 ppd->local_tx_rate = 1;
8968 else
8969 ppd->local_tx_rate = 0;
8970 } else {
8971 /* set the tx rate to all enabled */
8972 ppd->local_tx_rate = 0;
8973 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
8974 ppd->local_tx_rate |= 2;
8975 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
8976 ppd->local_tx_rate |= 1;
8977 }
febffe2c
EH		 8978
8979 enable_lane_tx = 0xF; /* enable all four lanes */
77241056 8980 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
17fb4f29 8981 rx_polarity_inversion, ppd->local_tx_rate);
77241056
MM		 8982 if (ret != HCMD_SUCCESS)
8983 goto set_local_link_attributes_fail;
8984
8985 /*
8986 * DC supports continuous updates.
8987 */
17fb4f29
JJ		 8988 ret = write_vc_local_phy(dd,
8989 0 /* no power management */,
8990 1 /* continuous updates */);
77241056
MM		 8991 if (ret != HCMD_SUCCESS)
8992 goto set_local_link_attributes_fail;
8993
8994 /* z=1 in the next call: AU of 0 is not supported by the hardware */
8995 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
8996 ppd->port_crc_mode_enabled);
8997 if (ret != HCMD_SUCCESS)
8998 goto set_local_link_attributes_fail;
8999
9000 ret = write_vc_local_link_width(dd, 0, 0,
17fb4f29
JJ		 9001 opa_to_vc_link_widths(
9002 ppd->link_width_enabled));
77241056
MM		 9003 if (ret != HCMD_SUCCESS)
9004 goto set_local_link_attributes_fail;
9005
9006 /* let peer know who we are */
9007 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9008 if (ret == HCMD_SUCCESS)
9009 return 0;
9010
9011set_local_link_attributes_fail:
9012 dd_dev_err(dd,
17fb4f29
JJ		 9013 "Failed to set local link attributes, return 0x%x\n",
9014 ret);
77241056
MM		 9015 return ret;
9016}
9017
9018/*
623bba2d
EH		 9019 * Call this to start the link.
9020 * Do not do anything if the link is disabled.
9021 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
77241056
MM		 9022 */
9023int start_link(struct hfi1_pportdata *ppd)
9024{
9025 if (!ppd->link_enabled) {
9026 dd_dev_info(ppd->dd,
17fb4f29
JJ		 9027 "%s: stopping link start because link is disabled\n",
9028 __func__);
77241056
MM		 9029 return 0;
9030 }
9031 if (!ppd->driver_link_ready) {
9032 dd_dev_info(ppd->dd,
17fb4f29
JJ		 9033 "%s: stopping link start because driver is not ready\n",
9034 __func__);
77241056
MM		 9035 return 0;
9036 }
9037
623bba2d 9038 return set_link_state(ppd, HLS_DN_POLL);
77241056
MM		 9039}
9040
8ebd4cf1
EH		 9041static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9042{
9043 struct hfi1_devdata *dd = ppd->dd;
9044 u64 mask;
9045 unsigned long timeout;
9046
9047 /*
9048 * Check for QSFP interrupt for t_init (SFF 8679)
9049 */
9050 timeout = jiffies + msecs_to_jiffies(2000);
9051 while (1) {
9052 mask = read_csr(dd, dd->hfi1_id ?
9053 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
9054 if (!(mask & QSFP_HFI0_INT_N)) {
9055 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR :
9056 ASIC_QSFP1_CLEAR, QSFP_HFI0_INT_N);
9057 break;
9058 }
9059 if (time_after(jiffies, timeout)) {
9060 dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9061 __func__);
9062 break;
9063 }
9064 udelay(2);
9065 }
9066}
9067
9068static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9069{
9070 struct hfi1_devdata *dd = ppd->dd;
9071 u64 mask;
9072
9073 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9074 if (enable)
9075 mask |= (u64)QSFP_HFI0_INT_N;
9076 else
9077 mask &= ~(u64)QSFP_HFI0_INT_N;
9078 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9079}
9080
9081void reset_qsfp(struct hfi1_pportdata *ppd)
77241056
MM		 9082{
9083 struct hfi1_devdata *dd = ppd->dd;
9084 u64 mask, qsfp_mask;
9085
8ebd4cf1
EH		 9086 /* Disable INT_N from triggering QSFP interrupts */
9087 set_qsfp_int_n(ppd, 0);
9088
9089 /* Reset the QSFP */
77241056 9090 mask = (u64)QSFP_HFI0_RESET_N;
8ebd4cf1 9091 qsfp_mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_OE : ASIC_QSFP1_OE);
77241056 9092 qsfp_mask |= mask;
17fb4f29 9093 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_OE : ASIC_QSFP1_OE, qsfp_mask);
77241056
MM		 9094
9095 qsfp_mask = read_csr(dd,
17fb4f29 9096 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
77241056
MM		 9097 qsfp_mask &= ~mask;
9098 write_csr(dd,
17fb4f29 9099 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
77241056
MM		 9100
9101 udelay(10);
9102
9103 qsfp_mask |= mask;
9104 write_csr(dd,
17fb4f29 9105 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
8ebd4cf1
EH		 9106
9107 wait_for_qsfp_init(ppd);
9108
9109 /*
9110 * Allow INT_N to trigger the QSFP interrupt to watch
9111 * for alarms and warnings
9112 */
9113 set_qsfp_int_n(ppd, 1);
77241056
MM		 9114}
9115
9116static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9117 u8 *qsfp_interrupt_status)
9118{
9119 struct hfi1_devdata *dd = ppd->dd;
9120
9121 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
17fb4f29
JJ		 9122 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
9123 dd_dev_info(dd, "%s: QSFP cable on fire\n",
9124 __func__);
77241056
MM		 9125
9126 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
17fb4f29
JJ		 9127 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9128 dd_dev_info(dd, "%s: QSFP cable temperature too low\n",
9129 __func__);
77241056
MM		 9130
9131 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
17fb4f29
JJ		 9132 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9133 dd_dev_info(dd, "%s: QSFP supply voltage too high\n",
9134 __func__);
77241056
MM		 9135
9136 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
17fb4f29
JJ		 9137 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9138 dd_dev_info(dd, "%s: QSFP supply voltage too low\n",
9139 __func__);
77241056
MM		 9140
9141 /* Byte 2 is vendor specific */
9142
9143 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9144 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9145 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too high\n",
9146 __func__);
77241056
MM		 9147
9148 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9149 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9150 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too low\n",
9151 __func__);
77241056
MM		 9152
9153 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9154 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9155 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too high\n",
9156 __func__);
77241056
MM		 9157
9158 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9159 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9160 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too low\n",
9161 __func__);
77241056
MM		 9162
9163 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
17fb4f29
JJ		 9164 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9165 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too high\n",
9166 __func__);
77241056
MM		 9167
9168 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
17fb4f29
JJ		 9169 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9170 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too low\n",
9171 __func__);
77241056
MM		 9172
9173 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
17fb4f29
JJ		 9174 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9175 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too high\n",
9176 __func__);
77241056
MM		 9177
9178 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
17fb4f29
JJ		 9179 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9180 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too low\n",
9181 __func__);
77241056
MM		 9182
9183 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9184 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9185 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too high\n",
9186 __func__);
77241056
MM		 9187
9188 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9189 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9190 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too low\n",
9191 __func__);
77241056
MM		 9192
9193 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
17fb4f29
JJ		 9194 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9195 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too high\n",
9196 __func__);
77241056
MM		 9197
9198 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
17fb4f29
JJ		 9199 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9200 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too low\n",
9201 __func__);
77241056
MM		 9202
9203 /* Bytes 9-10 and 11-12 are reserved */
9204 /* Bytes 13-15 are vendor specific */
9205
9206 return 0;
9207}
9208
623bba2d 9209/* This routine will only be scheduled if the QSFP module present is asserted */
8ebd4cf1 9210void qsfp_event(struct work_struct *work)
77241056
MM		 9211{
9212 struct qsfp_data *qd;
9213 struct hfi1_pportdata *ppd;
9214 struct hfi1_devdata *dd;
9215
9216 qd = container_of(work, struct qsfp_data, qsfp_work);
9217 ppd = qd->ppd;
9218 dd = ppd->dd;
9219
9220 /* Sanity check */
9221 if (!qsfp_mod_present(ppd))
9222 return;
9223
9224 /*
9225 * Turn DC back on after cables has been
9226 * re-inserted. Up until now, the DC has been in
9227 * reset to save power.
9228 */
9229 dc_start(dd);
9230
9231 if (qd->cache_refresh_required) {
8ebd4cf1 9232 set_qsfp_int_n(ppd, 0);
77241056 9233
8ebd4cf1
EH		 9234 wait_for_qsfp_init(ppd);
9235
9236 /*
9237 * Allow INT_N to trigger the QSFP interrupt to watch
9238 * for alarms and warnings
77241056 9239 */
8ebd4cf1
EH		 9240 set_qsfp_int_n(ppd, 1);
9241
9242 tune_serdes(ppd);
9243
9244 start_link(ppd);
77241056
MM		 9245 }
9246
9247 if (qd->check_interrupt_flags) {
9248 u8 qsfp_interrupt_status[16] = {0,};
9249
765a6fac
DL		 9250 if (one_qsfp_read(ppd, dd->hfi1_id, 6,
9251 &qsfp_interrupt_status[0], 16) != 16) {
77241056 9252 dd_dev_info(dd,
17fb4f29
JJ		 9253 "%s: Failed to read status of QSFP module\n",
9254 __func__);
77241056
MM		 9255 } else {
9256 unsigned long flags;
77241056 9257
8ebd4cf1
EH		 9258 handle_qsfp_error_conditions(
9259 ppd, qsfp_interrupt_status);
77241056
MM		 9260 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9261 ppd->qsfp_info.check_interrupt_flags = 0;
9262 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
17fb4f29 9263 flags);
77241056
MM		 9264 }
9265 }
9266}
9267
8ebd4cf1 9268static void init_qsfp_int(struct hfi1_devdata *dd)
77241056 9269{
8ebd4cf1
EH		 9270 struct hfi1_pportdata *ppd = dd->pport;
9271 u64 qsfp_mask, cce_int_mask;
9272 const int qsfp1_int_smask = QSFP1_INT % 64;
9273 const int qsfp2_int_smask = QSFP2_INT % 64;
77241056 9274
8ebd4cf1
EH		 9275 /*
9276 * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9277 * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9278 * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9279 * the index of the appropriate CSR in the CCEIntMask CSR array
9280 */
9281 cce_int_mask = read_csr(dd, CCE_INT_MASK +
9282 (8 * (QSFP1_INT / 64)));
9283 if (dd->hfi1_id) {
9284 cce_int_mask &= ~((u64)1 << qsfp1_int_smask);
9285 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)),
9286 cce_int_mask);
9287 } else {
9288 cce_int_mask &= ~((u64)1 << qsfp2_int_smask);
9289 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)),
9290 cce_int_mask);
77241056
MM		 9291 }
9292
77241056
MM		 9293 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9294 /* Clear current status to avoid spurious interrupts */
8ebd4cf1
EH		 9295 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9296 qsfp_mask);
9297 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9298 qsfp_mask);
9299
9300 set_qsfp_int_n(ppd, 0);
77241056
MM		 9301
9302 /* Handle active low nature of INT_N and MODPRST_N pins */
9303 if (qsfp_mod_present(ppd))
9304 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9305 write_csr(dd,
9306 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9307 qsfp_mask);
77241056
MM		 9308}
9309
bbdeb33d
DL		 9310/*
9311 * Do a one-time initialize of the LCB block.
9312 */
9313static void init_lcb(struct hfi1_devdata *dd)
9314{
a59329d5
DL		 9315 /* simulator does not correctly handle LCB cclk loopback, skip */
9316 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9317 return;
9318
bbdeb33d
DL		 9319 /* the DC has been reset earlier in the driver load */
9320
9321 /* set LCB for cclk loopback on the port */
9322 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9323 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9324 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9325 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9326 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9327 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9328 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9329}
9330
77241056
MM		 9331int bringup_serdes(struct hfi1_pportdata *ppd)
9332{
9333 struct hfi1_devdata *dd = ppd->dd;
9334 u64 guid;
9335 int ret;
9336
9337 if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9338 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9339
9340 guid = ppd->guid;
9341 if (!guid) {
9342 if (dd->base_guid)
9343 guid = dd->base_guid + ppd->port - 1;
9344 ppd->guid = guid;
9345 }
9346
77241056
MM		 9347 /* Set linkinit_reason on power up per OPA spec */
9348 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9349
bbdeb33d
DL		 9350 /* one-time init of the LCB */
9351 init_lcb(dd);
9352
77241056
MM		 9353 if (loopback) {
9354 ret = init_loopback(dd);
9355 if (ret < 0)
9356 return ret;
9357 }
9358
8ebd4cf1
EH		 9359 /* tune the SERDES to a ballpark setting for
9360 * optimal signal and bit error rate
9361 * Needs to be done before starting the link
9362 */
9363 tune_serdes(ppd);
9364
77241056
MM		 9365 return start_link(ppd);
9366}
9367
9368void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9369{
9370 struct hfi1_devdata *dd = ppd->dd;
9371
9372 /*
9373 * Shut down the link and keep it down. First turn off that the
9374 * driver wants to allow the link to be up (driver_link_ready).
9375 * Then make sure the link is not automatically restarted
9376 * (link_enabled). Cancel any pending restart. And finally
9377 * go offline.
9378 */
9379 ppd->driver_link_ready = 0;
9380 ppd->link_enabled = 0;
9381
8ebd4cf1
EH		 9382 ppd->offline_disabled_reason =
9383 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED);
77241056 9384 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SMA_DISABLED, 0,
17fb4f29 9385 OPA_LINKDOWN_REASON_SMA_DISABLED);
77241056
MM		 9386 set_link_state(ppd, HLS_DN_OFFLINE);
9387
9388 /* disable the port */
9389 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9390}
9391
9392static inline int init_cpu_counters(struct hfi1_devdata *dd)
9393{
9394 struct hfi1_pportdata *ppd;
9395 int i;
9396
9397 ppd = (struct hfi1_pportdata *)(dd + 1);
9398 for (i = 0; i < dd->num_pports; i++, ppd++) {
4eb06882
DD		 9399 ppd->ibport_data.rvp.rc_acks = NULL;
9400 ppd->ibport_data.rvp.rc_qacks = NULL;
9401 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9402 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9403 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9404 if (!ppd->ibport_data.rvp.rc_acks ||
9405 !ppd->ibport_data.rvp.rc_delayed_comp ||
9406 !ppd->ibport_data.rvp.rc_qacks)
77241056
MM		 9407 return -ENOMEM;
9408 }
9409
9410 return 0;
9411}
9412
9413static const char * const pt_names[] = {
9414 "expected",
9415 "eager",
9416 "invalid"
9417};
9418
9419static const char *pt_name(u32 type)
9420{
9421 return type >= ARRAY_SIZE(pt_names) ? "unknown" : pt_names[type];
9422}
9423
9424/*
9425 * index is the index into the receive array
9426 */
9427void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9428 u32 type, unsigned long pa, u16 order)
9429{
9430 u64 reg;
9431 void __iomem *base = (dd->rcvarray_wc ? dd->rcvarray_wc :
9432 (dd->kregbase + RCV_ARRAY));
9433
9434 if (!(dd->flags & HFI1_PRESENT))
9435 goto done;
9436
9437 if (type == PT_INVALID) {
9438 pa = 0;
9439 } else if (type > PT_INVALID) {
9440 dd_dev_err(dd,
17fb4f29
JJ		 9441 "unexpected receive array type %u for index %u, not handled\n",
9442 type, index);
77241056
MM		 9443 goto done;
9444 }
9445
9446 hfi1_cdbg(TID, "type %s, index 0x%x, pa 0x%lx, bsize 0x%lx",
9447 pt_name(type), index, pa, (unsigned long)order);
9448
9449#define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */
9450 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9451 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9452 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9453 << RCV_ARRAY_RT_ADDR_SHIFT;
9454 writeq(reg, base + (index * 8));
9455
9456 if (type == PT_EAGER)
9457 /*
9458 * Eager entries are written one-by-one so we have to push them
9459 * after we write the entry.
9460 */
9461 flush_wc();
9462done:
9463 return;
9464}
9465
9466void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9467{
9468 struct hfi1_devdata *dd = rcd->dd;
9469 u32 i;
9470
9471 /* this could be optimized */
9472 for (i = rcd->eager_base; i < rcd->eager_base +
9473 rcd->egrbufs.alloced; i++)
9474 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9475
9476 for (i = rcd->expected_base;
9477 i < rcd->expected_base + rcd->expected_count; i++)
9478 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9479}
9480
9481int hfi1_get_base_kinfo(struct hfi1_ctxtdata *rcd,
9482 struct hfi1_ctxt_info *kinfo)
9483{
9484 kinfo->runtime_flags = (HFI1_MISC_GET() << HFI1_CAP_USER_SHIFT) |
9485 HFI1_CAP_UGET(MASK) | HFI1_CAP_KGET(K2U);
9486 return 0;
9487}
9488
9489struct hfi1_message_header *hfi1_get_msgheader(
9490 struct hfi1_devdata *dd, __le32 *rhf_addr)
9491{
9492 u32 offset = rhf_hdrq_offset(rhf_to_cpu(rhf_addr));
9493
9494 return (struct hfi1_message_header *)
9495 (rhf_addr - dd->rhf_offset + offset);
9496}
9497
9498static const char * const ib_cfg_name_strings[] = {
9499 "HFI1_IB_CFG_LIDLMC",
9500 "HFI1_IB_CFG_LWID_DG_ENB",
9501 "HFI1_IB_CFG_LWID_ENB",
9502 "HFI1_IB_CFG_LWID",
9503 "HFI1_IB_CFG_SPD_ENB",
9504 "HFI1_IB_CFG_SPD",
9505 "HFI1_IB_CFG_RXPOL_ENB",
9506 "HFI1_IB_CFG_LREV_ENB",
9507 "HFI1_IB_CFG_LINKLATENCY",
9508 "HFI1_IB_CFG_HRTBT",
9509 "HFI1_IB_CFG_OP_VLS",
9510 "HFI1_IB_CFG_VL_HIGH_CAP",
9511 "HFI1_IB_CFG_VL_LOW_CAP",
9512 "HFI1_IB_CFG_OVERRUN_THRESH",
9513 "HFI1_IB_CFG_PHYERR_THRESH",
9514 "HFI1_IB_CFG_LINKDEFAULT",
9515 "HFI1_IB_CFG_PKEYS",
9516 "HFI1_IB_CFG_MTU",
9517 "HFI1_IB_CFG_LSTATE",
9518 "HFI1_IB_CFG_VL_HIGH_LIMIT",
9519 "HFI1_IB_CFG_PMA_TICKS",
9520 "HFI1_IB_CFG_PORT"
9521};
9522
9523static const char *ib_cfg_name(int which)
9524{
9525 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
9526 return "invalid";
9527 return ib_cfg_name_strings[which];
9528}
9529
9530int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9531{
9532 struct hfi1_devdata *dd = ppd->dd;
9533 int val = 0;
9534
9535 switch (which) {
9536 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
9537 val = ppd->link_width_enabled;
9538 break;
9539 case HFI1_IB_CFG_LWID: /* currently active Link-width */
9540 val = ppd->link_width_active;
9541 break;
9542 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
9543 val = ppd->link_speed_enabled;
9544 break;
9545 case HFI1_IB_CFG_SPD: /* current Link speed */
9546 val = ppd->link_speed_active;
9547 break;
9548
9549 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
9550 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
9551 case HFI1_IB_CFG_LINKLATENCY:
9552 goto unimplemented;
9553
9554 case HFI1_IB_CFG_OP_VLS:
9555 val = ppd->vls_operational;
9556 break;
9557 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9558 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
9559 break;
9560 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
9561 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
9562 break;
9563 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
9564 val = ppd->overrun_threshold;
9565 break;
9566 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
9567 val = ppd->phy_error_threshold;
9568 break;
9569 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9570 val = dd->link_default;
9571 break;
9572
9573 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
9574 case HFI1_IB_CFG_PMA_TICKS:
9575 default:
9576unimplemented:
9577 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
9578 dd_dev_info(
9579 dd,
9580 "%s: which %s: not implemented\n",
9581 __func__,
9582 ib_cfg_name(which));
9583 break;
9584 }
9585
9586 return val;
9587}
9588
9589/*
9590 * The largest MAD packet size.
9591 */
9592#define MAX_MAD_PACKET 2048
9593
9594/*
9595 * Return the maximum header bytes that can go on the _wire_
9596 * for this device. This count includes the ICRC which is
9597 * not part of the packet held in memory but it is appended
9598 * by the HW.
9599 * This is dependent on the device's receive header entry size.
9600 * HFI allows this to be set per-receive context, but the
9601 * driver presently enforces a global value.
9602 */
9603u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
9604{
9605 /*
9606 * The maximum non-payload (MTU) bytes in LRH.PktLen are
9607 * the Receive Header Entry Size minus the PBC (or RHF) size
9608 * plus one DW for the ICRC appended by HW.
9609 *
9610 * dd->rcd[0].rcvhdrqentsize is in DW.
9611 * We use rcd[0] as all context will have the same value. Also,
9612 * the first kernel context would have been allocated by now so
9613 * we are guaranteed a valid value.
9614 */
9615 return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
9616}
9617
9618/*
9619 * Set Send Length
9620 * @ppd - per port data
9621 *
9622 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
9623 * registers compare against LRH.PktLen, so use the max bytes included
9624 * in the LRH.
9625 *
9626 * This routine changes all VL values except VL15, which it maintains at
9627 * the same value.
9628 */
9629static void set_send_length(struct hfi1_pportdata *ppd)
9630{
9631 struct hfi1_devdata *dd = ppd->dd;
6cc6ad2e
HC		 9632 u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
9633 u32 maxvlmtu = dd->vld[15].mtu;
77241056
MM		 9634 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
9635 & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
9636 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
9637 int i;
44306f15 9638 u32 thres;
77241056
MM		 9639
9640 for (i = 0; i < ppd->vls_supported; i++) {
9641 if (dd->vld[i].mtu > maxvlmtu)
9642 maxvlmtu = dd->vld[i].mtu;
9643 if (i <= 3)
9644 len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
9645 & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
9646 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
9647 else
9648 len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
9649 & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
9650 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
9651 }
9652 write_csr(dd, SEND_LEN_CHECK0, len1);
9653 write_csr(dd, SEND_LEN_CHECK1, len2);
9654 /* adjust kernel credit return thresholds based on new MTUs */
9655 /* all kernel receive contexts have the same hdrqentsize */
9656 for (i = 0; i < ppd->vls_supported; i++) {
44306f15
JX		 9657 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50),
9658 sc_mtu_to_threshold(dd->vld[i].sc,
9659 dd->vld[i].mtu,
17fb4f29 9660 dd->rcd[0]->rcvhdrqentsize));
44306f15
JX		 9661 sc_set_cr_threshold(dd->vld[i].sc, thres);
9662 }
9663 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50),
9664 sc_mtu_to_threshold(dd->vld[15].sc,
9665 dd->vld[15].mtu,
9666 dd->rcd[0]->rcvhdrqentsize));
9667 sc_set_cr_threshold(dd->vld[15].sc, thres);
77241056
MM		 9668
9669 /* Adjust maximum MTU for the port in DC */
9670 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
9671 (ilog2(maxvlmtu >> 8) + 1);
9672 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
9673 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
9674 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
9675 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
9676 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
9677}
9678
9679static void set_lidlmc(struct hfi1_pportdata *ppd)
9680{
9681 int i;
9682 u64 sreg = 0;
9683 struct hfi1_devdata *dd = ppd->dd;
9684 u32 mask = ~((1U << ppd->lmc) - 1);
9685 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
9686
9687 if (dd->hfi1_snoop.mode_flag)
9688 dd_dev_info(dd, "Set lid/lmc while snooping");
9689
9690 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
9691 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
9692 c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
8638b77f 9693 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
77241056
MM		 9694 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
9695 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
9696 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
9697
9698 /*
9699 * Iterate over all the send contexts and set their SLID check
9700 */
9701 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
9702 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
9703 (((ppd->lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
9704 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
9705
9706 for (i = 0; i < dd->chip_send_contexts; i++) {
9707 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
9708 i, (u32)sreg);
9709 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
9710 }
9711
9712 /* Now we have to do the same thing for the sdma engines */
9713 sdma_update_lmc(dd, mask, ppd->lid);
9714}
9715
9716static int wait_phy_linkstate(struct hfi1_devdata *dd, u32 state, u32 msecs)
9717{
9718 unsigned long timeout;
9719 u32 curr_state;
9720
9721 timeout = jiffies + msecs_to_jiffies(msecs);
9722 while (1) {
9723 curr_state = read_physical_state(dd);
9724 if (curr_state == state)
9725 break;
9726 if (time_after(jiffies, timeout)) {
9727 dd_dev_err(dd,
17fb4f29
JJ		 9728 "timeout waiting for phy link state 0x%x, current state is 0x%x\n",
9729 state, curr_state);
77241056
MM		 9730 return -ETIMEDOUT;
9731 }
9732 usleep_range(1950, 2050); /* sleep 2ms-ish */
9733 }
9734
9735 return 0;
9736}
9737
9738/*
9739 * Helper for set_link_state(). Do not call except from that routine.
9740 * Expects ppd->hls_mutex to be held.
9741 *
9742 * @rem_reason value to be sent to the neighbor
9743 *
9744 * LinkDownReasons only set if transition succeeds.
9745 */
9746static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
9747{
9748 struct hfi1_devdata *dd = ppd->dd;
9749 u32 pstate, previous_state;
9750 u32 last_local_state;
9751 u32 last_remote_state;
9752 int ret;
9753 int do_transition;
9754 int do_wait;
9755
9756 previous_state = ppd->host_link_state;
9757 ppd->host_link_state = HLS_GOING_OFFLINE;
9758 pstate = read_physical_state(dd);
9759 if (pstate == PLS_OFFLINE) {
9760 do_transition = 0; /* in right state */
9761 do_wait = 0; /* ...no need to wait */
9762 } else if ((pstate & 0xff) == PLS_OFFLINE) {
9763 do_transition = 0; /* in an offline transient state */
9764 do_wait = 1; /* ...wait for it to settle */
9765 } else {
9766 do_transition = 1; /* need to move to offline */
9767 do_wait = 1; /* ...will need to wait */
9768 }
9769
9770 if (do_transition) {
9771 ret = set_physical_link_state(dd,
bf640096 9772 (rem_reason << 8) | PLS_OFFLINE);
77241056
MM		 9773
9774 if (ret != HCMD_SUCCESS) {
9775 dd_dev_err(dd,
17fb4f29
JJ		 9776 "Failed to transition to Offline link state, return %d\n",
9777 ret);
77241056
MM		 9778 return -EINVAL;
9779 }
a9c05e35
BM		 9780 if (ppd->offline_disabled_reason ==
9781 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
77241056 9782 ppd->offline_disabled_reason =
a9c05e35 9783 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 9784 }
9785
9786 if (do_wait) {
9787 /* it can take a while for the link to go down */
dc060245 9788 ret = wait_phy_linkstate(dd, PLS_OFFLINE, 10000);
77241056
MM		 9789 if (ret < 0)
9790 return ret;
9791 }
9792
9793 /* make sure the logical state is also down */
9794 wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
9795
9796 /*
9797 * Now in charge of LCB - must be after the physical state is
9798 * offline.quiet and before host_link_state is changed.
9799 */
9800 set_host_lcb_access(dd);
9801 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9802 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
9803
8ebd4cf1
EH		 9804 if (ppd->port_type == PORT_TYPE_QSFP &&
9805 ppd->qsfp_info.limiting_active &&
9806 qsfp_mod_present(ppd)) {
765a6fac
DL		 9807 int ret;
9808
9809 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT);
9810 if (ret == 0) {
9811 set_qsfp_tx(ppd, 0);
9812 release_chip_resource(dd, qsfp_resource(dd));
9813 } else {
9814 /* not fatal, but should warn */
9815 dd_dev_err(dd,
9816 "Unable to acquire lock to turn off QSFP TX\n");
9817 }
8ebd4cf1
EH		 9818 }
9819
77241056
MM		 9820 /*
9821 * The LNI has a mandatory wait time after the physical state
9822 * moves to Offline.Quiet. The wait time may be different
9823 * depending on how the link went down. The 8051 firmware
9824 * will observe the needed wait time and only move to ready
9825 * when that is completed. The largest of the quiet timeouts
05087f3b
DL		 9826 * is 6s, so wait that long and then at least 0.5s more for
9827 * other transitions, and another 0.5s for a buffer.
77241056 9828 */
05087f3b 9829 ret = wait_fm_ready(dd, 7000);
77241056
MM		 9830 if (ret) {
9831 dd_dev_err(dd,
17fb4f29 9832 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
77241056
MM		 9833 /* state is really offline, so make it so */
9834 ppd->host_link_state = HLS_DN_OFFLINE;
9835 return ret;
9836 }
9837
9838 /*
9839 * The state is now offline and the 8051 is ready to accept host
9840 * requests.
9841 * - change our state
9842 * - notify others if we were previously in a linkup state
9843 */
9844 ppd->host_link_state = HLS_DN_OFFLINE;
9845 if (previous_state & HLS_UP) {
9846 /* went down while link was up */
9847 handle_linkup_change(dd, 0);
9848 } else if (previous_state
9849 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
9850 /* went down while attempting link up */
9851 /* byte 1 of last_*_state is the failure reason */
9852 read_last_local_state(dd, &last_local_state);
9853 read_last_remote_state(dd, &last_remote_state);
9854 dd_dev_err(dd,
17fb4f29
JJ		 9855 "LNI failure last states: local 0x%08x, remote 0x%08x\n",
9856 last_local_state, last_remote_state);
77241056
MM		 9857 }
9858
9859 /* the active link width (downgrade) is 0 on link down */
9860 ppd->link_width_active = 0;
9861 ppd->link_width_downgrade_tx_active = 0;
9862 ppd->link_width_downgrade_rx_active = 0;
9863 ppd->current_egress_rate = 0;
9864 return 0;
9865}
9866
9867/* return the link state name */
9868static const char *link_state_name(u32 state)
9869{
9870 const char *name;
9871 int n = ilog2(state);
9872 static const char * const names[] = {
9873 [__HLS_UP_INIT_BP] = "INIT",
9874 [__HLS_UP_ARMED_BP] = "ARMED",
9875 [__HLS_UP_ACTIVE_BP] = "ACTIVE",
9876 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF",
9877 [__HLS_DN_POLL_BP] = "POLL",
9878 [__HLS_DN_DISABLE_BP] = "DISABLE",
9879 [__HLS_DN_OFFLINE_BP] = "OFFLINE",
9880 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP",
9881 [__HLS_GOING_UP_BP] = "GOING_UP",
9882 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
9883 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
9884 };
9885
9886 name = n < ARRAY_SIZE(names) ? names[n] : NULL;
9887 return name ? name : "unknown";
9888}
9889
9890/* return the link state reason name */
9891static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
9892{
9893 if (state == HLS_UP_INIT) {
9894 switch (ppd->linkinit_reason) {
9895 case OPA_LINKINIT_REASON_LINKUP:
9896 return "(LINKUP)";
9897 case OPA_LINKINIT_REASON_FLAPPING:
9898 return "(FLAPPING)";
9899 case OPA_LINKINIT_OUTSIDE_POLICY:
9900 return "(OUTSIDE_POLICY)";
9901 case OPA_LINKINIT_QUARANTINED:
9902 return "(QUARANTINED)";
9903 case OPA_LINKINIT_INSUFIC_CAPABILITY:
9904 return "(INSUFIC_CAPABILITY)";
9905 default:
9906 break;
9907 }
9908 }
9909 return "";
9910}
9911
9912/*
9913 * driver_physical_state - convert the driver's notion of a port's
9914 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
9915 * Return -1 (converted to a u32) to indicate error.
9916 */
9917u32 driver_physical_state(struct hfi1_pportdata *ppd)
9918{
9919 switch (ppd->host_link_state) {
9920 case HLS_UP_INIT:
9921 case HLS_UP_ARMED:
9922 case HLS_UP_ACTIVE:
9923 return IB_PORTPHYSSTATE_LINKUP;
9924 case HLS_DN_POLL:
9925 return IB_PORTPHYSSTATE_POLLING;
9926 case HLS_DN_DISABLE:
9927 return IB_PORTPHYSSTATE_DISABLED;
9928 case HLS_DN_OFFLINE:
9929 return OPA_PORTPHYSSTATE_OFFLINE;
9930 case HLS_VERIFY_CAP:
9931 return IB_PORTPHYSSTATE_POLLING;
9932 case HLS_GOING_UP:
9933 return IB_PORTPHYSSTATE_POLLING;
9934 case HLS_GOING_OFFLINE:
9935 return OPA_PORTPHYSSTATE_OFFLINE;
9936 case HLS_LINK_COOLDOWN:
9937 return OPA_PORTPHYSSTATE_OFFLINE;
9938 case HLS_DN_DOWNDEF:
9939 default:
9940 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
9941 ppd->host_link_state);
9942 return -1;
9943 }
9944}
9945
9946/*
9947 * driver_logical_state - convert the driver's notion of a port's
9948 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
9949 * (converted to a u32) to indicate error.
9950 */
9951u32 driver_logical_state(struct hfi1_pportdata *ppd)
9952{
9953 if (ppd->host_link_state && !(ppd->host_link_state & HLS_UP))
9954 return IB_PORT_DOWN;
9955
9956 switch (ppd->host_link_state & HLS_UP) {
9957 case HLS_UP_INIT:
9958 return IB_PORT_INIT;
9959 case HLS_UP_ARMED:
9960 return IB_PORT_ARMED;
9961 case HLS_UP_ACTIVE:
9962 return IB_PORT_ACTIVE;
9963 default:
9964 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
9965 ppd->host_link_state);
9966 return -1;
9967 }
9968}
9969
9970void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
9971 u8 neigh_reason, u8 rem_reason)
9972{
9973 if (ppd->local_link_down_reason.latest == 0 &&
9974 ppd->neigh_link_down_reason.latest == 0) {
9975 ppd->local_link_down_reason.latest = lcl_reason;
9976 ppd->neigh_link_down_reason.latest = neigh_reason;
9977 ppd->remote_link_down_reason = rem_reason;
9978 }
9979}
9980
9981/*
9982 * Change the physical and/or logical link state.
9983 *
9984 * Do not call this routine while inside an interrupt. It contains
9985 * calls to routines that can take multiple seconds to finish.
9986 *
9987 * Returns 0 on success, -errno on failure.
9988 */
9989int set_link_state(struct hfi1_pportdata *ppd, u32 state)
9990{
9991 struct hfi1_devdata *dd = ppd->dd;
9992 struct ib_event event = {.device = NULL};
9993 int ret1, ret = 0;
9994 int was_up, is_down;
9995 int orig_new_state, poll_bounce;
9996
9997 mutex_lock(&ppd->hls_lock);
9998
9999 orig_new_state = state;
10000 if (state == HLS_DN_DOWNDEF)
10001 state = dd->link_default;
10002
10003 /* interpret poll -> poll as a link bounce */
d0d236ea
JJ		 10004 poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
10005 state == HLS_DN_POLL;
77241056
MM		 10006
10007 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
17fb4f29
JJ		 10008 link_state_name(ppd->host_link_state),
10009 link_state_name(orig_new_state),
10010 poll_bounce ? "(bounce) " : "",
10011 link_state_reason_name(ppd, state));
77241056
MM		 10012
10013 was_up = !!(ppd->host_link_state & HLS_UP);
10014
10015 /*
10016 * If we're going to a (HLS_*) link state that implies the logical
10017 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10018 * reset is_sm_config_started to 0.
10019 */
10020 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10021 ppd->is_sm_config_started = 0;
10022
10023 /*
10024 * Do nothing if the states match. Let a poll to poll link bounce
10025 * go through.
10026 */
10027 if (ppd->host_link_state == state && !poll_bounce)
10028 goto done;
10029
10030 switch (state) {
10031 case HLS_UP_INIT:
d0d236ea
JJ		 10032 if (ppd->host_link_state == HLS_DN_POLL &&
10033 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
77241056
MM		 10034 /*
10035 * Quick link up jumps from polling to here.
10036 *
10037 * Whether in normal or loopback mode, the
10038 * simulator jumps from polling to link up.
10039 * Accept that here.
10040 */
17fb4f29 10041 /* OK */
77241056
MM		 10042 } else if (ppd->host_link_state != HLS_GOING_UP) {
10043 goto unexpected;
10044 }
10045
10046 ppd->host_link_state = HLS_UP_INIT;
10047 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10048 if (ret) {
10049 /* logical state didn't change, stay at going_up */
10050 ppd->host_link_state = HLS_GOING_UP;
10051 dd_dev_err(dd,
17fb4f29
JJ		 10052 "%s: logical state did not change to INIT\n",
10053 __func__);
77241056
MM		 10054 } else {
10055 /* clear old transient LINKINIT_REASON code */
10056 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10057 ppd->linkinit_reason =
10058 OPA_LINKINIT_REASON_LINKUP;
10059
10060 /* enable the port */
10061 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10062
10063 handle_linkup_change(dd, 1);
10064 }
10065 break;
10066 case HLS_UP_ARMED:
10067 if (ppd->host_link_state != HLS_UP_INIT)
10068 goto unexpected;
10069
10070 ppd->host_link_state = HLS_UP_ARMED;
10071 set_logical_state(dd, LSTATE_ARMED);
10072 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10073 if (ret) {
10074 /* logical state didn't change, stay at init */
10075 ppd->host_link_state = HLS_UP_INIT;
10076 dd_dev_err(dd,
17fb4f29
JJ		 10077 "%s: logical state did not change to ARMED\n",
10078 __func__);
77241056
MM		 10079 }
10080 /*
10081 * The simulator does not currently implement SMA messages,
10082 * so neighbor_normal is not set. Set it here when we first
10083 * move to Armed.
10084 */
10085 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10086 ppd->neighbor_normal = 1;
10087 break;
10088 case HLS_UP_ACTIVE:
10089 if (ppd->host_link_state != HLS_UP_ARMED)
10090 goto unexpected;
10091
10092 ppd->host_link_state = HLS_UP_ACTIVE;
10093 set_logical_state(dd, LSTATE_ACTIVE);
10094 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10095 if (ret) {
10096 /* logical state didn't change, stay at armed */
10097 ppd->host_link_state = HLS_UP_ARMED;
10098 dd_dev_err(dd,
17fb4f29
JJ		 10099 "%s: logical state did not change to ACTIVE\n",
10100 __func__);
77241056 10101 } else {
77241056
MM		 10102 /* tell all engines to go running */
10103 sdma_all_running(dd);
10104
10105 /* Signal the IB layer that the port has went active */
ec3f2c12 10106 event.device = &dd->verbs_dev.rdi.ibdev;
77241056
MM		 10107 event.element.port_num = ppd->port;
10108 event.event = IB_EVENT_PORT_ACTIVE;
10109 }
10110 break;
10111 case HLS_DN_POLL:
10112 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10113 ppd->host_link_state == HLS_DN_OFFLINE) &&
10114 dd->dc_shutdown)
10115 dc_start(dd);
10116 /* Hand LED control to the DC */
10117 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10118
10119 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10120 u8 tmp = ppd->link_enabled;
10121
10122 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10123 if (ret) {
10124 ppd->link_enabled = tmp;
10125 break;
10126 }
10127 ppd->remote_link_down_reason = 0;
10128
10129 if (ppd->driver_link_ready)
10130 ppd->link_enabled = 1;
10131 }
10132
fb9036dd 10133 set_all_slowpath(ppd->dd);
77241056
MM		 10134 ret = set_local_link_attributes(ppd);
10135 if (ret)
10136 break;
10137
10138 ppd->port_error_action = 0;
10139 ppd->host_link_state = HLS_DN_POLL;
10140
10141 if (quick_linkup) {
10142 /* quick linkup does not go into polling */
10143 ret = do_quick_linkup(dd);
10144 } else {
10145 ret1 = set_physical_link_state(dd, PLS_POLLING);
10146 if (ret1 != HCMD_SUCCESS) {
10147 dd_dev_err(dd,
17fb4f29
JJ		 10148 "Failed to transition to Polling link state, return 0x%x\n",
10149 ret1);
77241056
MM		 10150 ret = -EINVAL;
10151 }
10152 }
a9c05e35
BM		 10153 ppd->offline_disabled_reason =
10154 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
77241056
MM		 10155 /*
10156 * If an error occurred above, go back to offline. The
10157 * caller may reschedule another attempt.
10158 */
10159 if (ret)
10160 goto_offline(ppd, 0);
10161 break;
10162 case HLS_DN_DISABLE:
10163 /* link is disabled */
10164 ppd->link_enabled = 0;
10165
10166 /* allow any state to transition to disabled */
10167
10168 /* must transition to offline first */
10169 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10170 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10171 if (ret)
10172 break;
10173 ppd->remote_link_down_reason = 0;
10174 }
10175
10176 ret1 = set_physical_link_state(dd, PLS_DISABLED);
10177 if (ret1 != HCMD_SUCCESS) {
10178 dd_dev_err(dd,
17fb4f29
JJ		 10179 "Failed to transition to Disabled link state, return 0x%x\n",
10180 ret1);
77241056
MM		 10181 ret = -EINVAL;
10182 break;
10183 }
10184 ppd->host_link_state = HLS_DN_DISABLE;
10185 dc_shutdown(dd);
10186 break;
10187 case HLS_DN_OFFLINE:
10188 if (ppd->host_link_state == HLS_DN_DISABLE)
10189 dc_start(dd);
10190
10191 /* allow any state to transition to offline */
10192 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10193 if (!ret)
10194 ppd->remote_link_down_reason = 0;
10195 break;
10196 case HLS_VERIFY_CAP:
10197 if (ppd->host_link_state != HLS_DN_POLL)
10198 goto unexpected;
10199 ppd->host_link_state = HLS_VERIFY_CAP;
10200 break;
10201 case HLS_GOING_UP:
10202 if (ppd->host_link_state != HLS_VERIFY_CAP)
10203 goto unexpected;
10204
10205 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10206 if (ret1 != HCMD_SUCCESS) {
10207 dd_dev_err(dd,
17fb4f29
JJ		 10208 "Failed to transition to link up state, return 0x%x\n",
10209 ret1);
77241056
MM		 10210 ret = -EINVAL;
10211 break;
10212 }
10213 ppd->host_link_state = HLS_GOING_UP;
10214 break;
10215
10216 case HLS_GOING_OFFLINE: /* transient within goto_offline() */
10217 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */
10218 default:
10219 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
17fb4f29 10220 __func__, state);
77241056
MM		 10221 ret = -EINVAL;
10222 break;
10223 }
10224
10225 is_down = !!(ppd->host_link_state & (HLS_DN_POLL |
10226 HLS_DN_DISABLE | HLS_DN_OFFLINE));
10227
10228 if (was_up && is_down && ppd->local_link_down_reason.sma == 0 &&
10229 ppd->neigh_link_down_reason.sma == 0) {
10230 ppd->local_link_down_reason.sma =
10231 ppd->local_link_down_reason.latest;
10232 ppd->neigh_link_down_reason.sma =
10233 ppd->neigh_link_down_reason.latest;
10234 }
10235
10236 goto done;
10237
10238unexpected:
10239 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
17fb4f29
JJ		 10240 __func__, link_state_name(ppd->host_link_state),
10241 link_state_name(state));
77241056
MM		 10242 ret = -EINVAL;
10243
10244done:
10245 mutex_unlock(&ppd->hls_lock);
10246
10247 if (event.device)
10248 ib_dispatch_event(&event);
10249
10250 return ret;
10251}
10252
10253int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
10254{
10255 u64 reg;
10256 int ret = 0;
10257
10258 switch (which) {
10259 case HFI1_IB_CFG_LIDLMC:
10260 set_lidlmc(ppd);
10261 break;
10262 case HFI1_IB_CFG_VL_HIGH_LIMIT:
10263 /*
10264 * The VL Arbitrator high limit is sent in units of 4k
10265 * bytes, while HFI stores it in units of 64 bytes.
10266 */
8638b77f 10267 val *= 4096 / 64;
77241056
MM		 10268 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
10269 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
10270 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
10271 break;
10272 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10273 /* HFI only supports POLL as the default link down state */
10274 if (val != HLS_DN_POLL)
10275 ret = -EINVAL;
10276 break;
10277 case HFI1_IB_CFG_OP_VLS:
10278 if (ppd->vls_operational != val) {
10279 ppd->vls_operational = val;
10280 if (!ppd->port)
10281 ret = -EINVAL;
77241056
MM		 10282 }
10283 break;
10284 /*
10285 * For link width, link width downgrade, and speed enable, always AND
10286 * the setting with what is actually supported. This has two benefits.
10287 * First, enabled can't have unsupported values, no matter what the
10288 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
10289 * "fill in with your supported value" have all the bits in the
10290 * field set, so simply ANDing with supported has the desired result.
10291 */
10292 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
10293 ppd->link_width_enabled = val & ppd->link_width_supported;
10294 break;
10295 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
10296 ppd->link_width_downgrade_enabled =
10297 val & ppd->link_width_downgrade_supported;
10298 break;
10299 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10300 ppd->link_speed_enabled = val & ppd->link_speed_supported;
10301 break;
10302 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10303 /*
10304 * HFI does not follow IB specs, save this value
10305 * so we can report it, if asked.
10306 */
10307 ppd->overrun_threshold = val;
10308 break;
10309 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10310 /*
10311 * HFI does not follow IB specs, save this value
10312 * so we can report it, if asked.
10313 */
10314 ppd->phy_error_threshold = val;
10315 break;
10316
10317 case HFI1_IB_CFG_MTU:
10318 set_send_length(ppd);
10319 break;
10320
10321 case HFI1_IB_CFG_PKEYS:
10322 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
10323 set_partition_keys(ppd);
10324 break;
10325
10326 default:
10327 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10328 dd_dev_info(ppd->dd,
17fb4f29
JJ		 10329 "%s: which %s, val 0x%x: not implemented\n",
10330 __func__, ib_cfg_name(which), val);
77241056
MM		 10331 break;
10332 }
10333 return ret;
10334}
10335
10336/* begin functions related to vl arbitration table caching */
10337static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
10338{
10339 int i;
10340
10341 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10342 VL_ARB_LOW_PRIO_TABLE_SIZE);
10343 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10344 VL_ARB_HIGH_PRIO_TABLE_SIZE);
10345
10346 /*
10347 * Note that we always return values directly from the
10348 * 'vl_arb_cache' (and do no CSR reads) in response to a
10349 * 'Get(VLArbTable)'. This is obviously correct after a
10350 * 'Set(VLArbTable)', since the cache will then be up to
10351 * date. But it's also correct prior to any 'Set(VLArbTable)'
10352 * since then both the cache, and the relevant h/w registers
10353 * will be zeroed.
10354 */
10355
10356 for (i = 0; i < MAX_PRIO_TABLE; i++)
10357 spin_lock_init(&ppd->vl_arb_cache[i].lock);
10358}
10359
10360/*
10361 * vl_arb_lock_cache
10362 *
10363 * All other vl_arb_* functions should be called only after locking
10364 * the cache.
10365 */
10366static inline struct vl_arb_cache *
10367vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
10368{
10369 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
10370 return NULL;
10371 spin_lock(&ppd->vl_arb_cache[idx].lock);
10372 return &ppd->vl_arb_cache[idx];
10373}
10374
10375static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
10376{
10377 spin_unlock(&ppd->vl_arb_cache[idx].lock);
10378}
10379
10380static void vl_arb_get_cache(struct vl_arb_cache *cache,
10381 struct ib_vl_weight_elem *vl)
10382{
10383 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
10384}
10385
10386static void vl_arb_set_cache(struct vl_arb_cache *cache,
10387 struct ib_vl_weight_elem *vl)
10388{
10389 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10390}
10391
10392static int vl_arb_match_cache(struct vl_arb_cache *cache,
10393 struct ib_vl_weight_elem *vl)
10394{
10395 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10396}
f4d507cd 10397
77241056
MM		 10398/* end functions related to vl arbitration table caching */
10399
10400static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
10401 u32 size, struct ib_vl_weight_elem *vl)
10402{
10403 struct hfi1_devdata *dd = ppd->dd;
10404 u64 reg;
10405 unsigned int i, is_up = 0;
10406 int drain, ret = 0;
10407
10408 mutex_lock(&ppd->hls_lock);
10409
10410 if (ppd->host_link_state & HLS_UP)
10411 is_up = 1;
10412
10413 drain = !is_ax(dd) && is_up;
10414
10415 if (drain)
10416 /*
10417 * Before adjusting VL arbitration weights, empty per-VL
10418 * FIFOs, otherwise a packet whose VL weight is being
10419 * set to 0 could get stuck in a FIFO with no chance to
10420 * egress.
10421 */
10422 ret = stop_drain_data_vls(dd);
10423
10424 if (ret) {
10425 dd_dev_err(
10426 dd,
10427 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
10428 __func__);
10429 goto err;
10430 }
10431
10432 for (i = 0; i < size; i++, vl++) {
10433 /*
10434 * NOTE: The low priority shift and mask are used here, but
10435 * they are the same for both the low and high registers.
10436 */
10437 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
10438 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
10439 | (((u64)vl->weight
10440 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
10441 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
10442 write_csr(dd, target + (i * 8), reg);
10443 }
10444 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
10445
10446 if (drain)
10447 open_fill_data_vls(dd); /* reopen all VLs */
10448
10449err:
10450 mutex_unlock(&ppd->hls_lock);
10451
10452 return ret;
10453}
10454
10455/*
10456 * Read one credit merge VL register.
10457 */
10458static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
10459 struct vl_limit *vll)
10460{
10461 u64 reg = read_csr(dd, csr);
10462
10463 vll->dedicated = cpu_to_be16(
10464 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
10465 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
10466 vll->shared = cpu_to_be16(
10467 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
10468 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
10469}
10470
10471/*
10472 * Read the current credit merge limits.
10473 */
10474static int get_buffer_control(struct hfi1_devdata *dd,
10475 struct buffer_control *bc, u16 *overall_limit)
10476{
10477 u64 reg;
10478 int i;
10479
10480 /* not all entries are filled in */
10481 memset(bc, 0, sizeof(*bc));
10482
10483 /* OPA and HFI have a 1-1 mapping */
10484 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 10485 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
77241056
MM		 10486
10487 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
10488 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
10489
10490 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10491 bc->overall_shared_limit = cpu_to_be16(
10492 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
10493 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
10494 if (overall_limit)
10495 *overall_limit = (reg
10496 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
10497 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
10498 return sizeof(struct buffer_control);
10499}
10500
10501static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10502{
10503 u64 reg;
10504 int i;
10505
10506 /* each register contains 16 SC->VLnt mappings, 4 bits each */
10507 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
10508 for (i = 0; i < sizeof(u64); i++) {
10509 u8 byte = *(((u8 *)&reg) + i);
10510
10511 dp->vlnt[2 * i] = byte & 0xf;
10512 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
10513 }
10514
10515 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
10516 for (i = 0; i < sizeof(u64); i++) {
10517 u8 byte = *(((u8 *)&reg) + i);
10518
10519 dp->vlnt[16 + (2 * i)] = byte & 0xf;
10520 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
10521 }
10522 return sizeof(struct sc2vlnt);
10523}
10524
10525static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
10526 struct ib_vl_weight_elem *vl)
10527{
10528 unsigned int i;
10529
10530 for (i = 0; i < nelems; i++, vl++) {
10531 vl->vl = 0xf;
10532 vl->weight = 0;
10533 }
10534}
10535
10536static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10537{
10538 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
17fb4f29
JJ		 10539 DC_SC_VL_VAL(15_0,
10540 0, dp->vlnt[0] & 0xf,
10541 1, dp->vlnt[1] & 0xf,
10542 2, dp->vlnt[2] & 0xf,
10543 3, dp->vlnt[3] & 0xf,
10544 4, dp->vlnt[4] & 0xf,
10545 5, dp->vlnt[5] & 0xf,
10546 6, dp->vlnt[6] & 0xf,
10547 7, dp->vlnt[7] & 0xf,
10548 8, dp->vlnt[8] & 0xf,
10549 9, dp->vlnt[9] & 0xf,
10550 10, dp->vlnt[10] & 0xf,
10551 11, dp->vlnt[11] & 0xf,
10552 12, dp->vlnt[12] & 0xf,
10553 13, dp->vlnt[13] & 0xf,
10554 14, dp->vlnt[14] & 0xf,
10555 15, dp->vlnt[15] & 0xf));
77241056 10556 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
17fb4f29
JJ		 10557 DC_SC_VL_VAL(31_16,
10558 16, dp->vlnt[16] & 0xf,
10559 17, dp->vlnt[17] & 0xf,
10560 18, dp->vlnt[18] & 0xf,
10561 19, dp->vlnt[19] & 0xf,
10562 20, dp->vlnt[20] & 0xf,
10563 21, dp->vlnt[21] & 0xf,
10564 22, dp->vlnt[22] & 0xf,
10565 23, dp->vlnt[23] & 0xf,
10566 24, dp->vlnt[24] & 0xf,
10567 25, dp->vlnt[25] & 0xf,
10568 26, dp->vlnt[26] & 0xf,
10569 27, dp->vlnt[27] & 0xf,
10570 28, dp->vlnt[28] & 0xf,
10571 29, dp->vlnt[29] & 0xf,
10572 30, dp->vlnt[30] & 0xf,
10573 31, dp->vlnt[31] & 0xf));
77241056
MM		 10574}
10575
10576static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
10577 u16 limit)
10578{
10579 if (limit != 0)
10580 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
17fb4f29 10581 what, (int)limit, idx);
77241056
MM		 10582}
10583
10584/* change only the shared limit portion of SendCmGLobalCredit */
10585static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
10586{
10587 u64 reg;
10588
10589 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10590 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
10591 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
10592 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10593}
10594
10595/* change only the total credit limit portion of SendCmGLobalCredit */
10596static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
10597{
10598 u64 reg;
10599
10600 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10601 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
10602 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
10603 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10604}
10605
10606/* set the given per-VL shared limit */
10607static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
10608{
10609 u64 reg;
10610 u32 addr;
10611
10612 if (vl < TXE_NUM_DATA_VL)
10613 addr = SEND_CM_CREDIT_VL + (8 * vl);
10614 else
10615 addr = SEND_CM_CREDIT_VL15;
10616
10617 reg = read_csr(dd, addr);
10618 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
10619 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
10620 write_csr(dd, addr, reg);
10621}
10622
10623/* set the given per-VL dedicated limit */
10624static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
10625{
10626 u64 reg;
10627 u32 addr;
10628
10629 if (vl < TXE_NUM_DATA_VL)
10630 addr = SEND_CM_CREDIT_VL + (8 * vl);
10631 else
10632 addr = SEND_CM_CREDIT_VL15;
10633
10634 reg = read_csr(dd, addr);
10635 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
10636 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
10637 write_csr(dd, addr, reg);
10638}
10639
10640/* spin until the given per-VL status mask bits clear */
10641static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
10642 const char *which)
10643{
10644 unsigned long timeout;
10645 u64 reg;
10646
10647 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
10648 while (1) {
10649 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
10650
10651 if (reg == 0)
10652 return; /* success */
10653 if (time_after(jiffies, timeout))
10654 break; /* timed out */
10655 udelay(1);
10656 }
10657
10658 dd_dev_err(dd,
17fb4f29
JJ		 10659 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
10660 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
77241056
MM		 10661 /*
10662 * If this occurs, it is likely there was a credit loss on the link.
10663 * The only recovery from that is a link bounce.
10664 */
10665 dd_dev_err(dd,
17fb4f29 10666 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n");
77241056
MM		 10667}
10668
10669/*
10670 * The number of credits on the VLs may be changed while everything
10671 * is "live", but the following algorithm must be followed due to
10672 * how the hardware is actually implemented. In particular,
10673 * Return_Credit_Status[] is the only correct status check.
10674 *
10675 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
10676 * set Global_Shared_Credit_Limit = 0
10677 * use_all_vl = 1
10678 * mask0 = all VLs that are changing either dedicated or shared limits
10679 * set Shared_Limit[mask0] = 0
10680 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
10681 * if (changing any dedicated limit)
10682 * mask1 = all VLs that are lowering dedicated limits
10683 * lower Dedicated_Limit[mask1]
10684 * spin until Return_Credit_Status[mask1] == 0
10685 * raise Dedicated_Limits
10686 * raise Shared_Limits
10687 * raise Global_Shared_Credit_Limit
10688 *
10689 * lower = if the new limit is lower, set the limit to the new value
10690 * raise = if the new limit is higher than the current value (may be changed
10691 * earlier in the algorithm), set the new limit to the new value
10692 */
8a4d3444
MM		 10693int set_buffer_control(struct hfi1_pportdata *ppd,
10694 struct buffer_control *new_bc)
77241056 10695{
8a4d3444 10696 struct hfi1_devdata *dd = ppd->dd;
77241056
MM		 10697 u64 changing_mask, ld_mask, stat_mask;
10698 int change_count;
10699 int i, use_all_mask;
10700 int this_shared_changing;
8a4d3444 10701 int vl_count = 0, ret;
77241056
MM		 10702 /*
10703 * A0: add the variable any_shared_limit_changing below and in the
10704 * algorithm above. If removing A0 support, it can be removed.
10705 */
10706 int any_shared_limit_changing;
10707 struct buffer_control cur_bc;
10708 u8 changing[OPA_MAX_VLS];
10709 u8 lowering_dedicated[OPA_MAX_VLS];
10710 u16 cur_total;
10711 u32 new_total = 0;
10712 const u64 all_mask =
10713 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
10714 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
10715 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
10716 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
10717 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
10718 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
10719 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
10720 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
10721 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
10722
10723#define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
10724#define NUM_USABLE_VLS 16 /* look at VL15 and less */
10725
77241056
MM		 10726 /* find the new total credits, do sanity check on unused VLs */
10727 for (i = 0; i < OPA_MAX_VLS; i++) {
10728 if (valid_vl(i)) {
10729 new_total += be16_to_cpu(new_bc->vl[i].dedicated);
10730 continue;
10731 }
10732 nonzero_msg(dd, i, "dedicated",
17fb4f29 10733 be16_to_cpu(new_bc->vl[i].dedicated));
77241056 10734 nonzero_msg(dd, i, "shared",
17fb4f29 10735 be16_to_cpu(new_bc->vl[i].shared));
77241056
MM		 10736 new_bc->vl[i].dedicated = 0;
10737 new_bc->vl[i].shared = 0;
10738 }
10739 new_total += be16_to_cpu(new_bc->overall_shared_limit);
bff14bb6 10740
77241056
MM		 10741 /* fetch the current values */
10742 get_buffer_control(dd, &cur_bc, &cur_total);
10743
10744 /*
10745 * Create the masks we will use.
10746 */
10747 memset(changing, 0, sizeof(changing));
10748 memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
4d114fdd
JJ		 10749 /*
10750 * NOTE: Assumes that the individual VL bits are adjacent and in
10751 * increasing order
10752 */
77241056
MM		 10753 stat_mask =
10754 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
10755 changing_mask = 0;
10756 ld_mask = 0;
10757 change_count = 0;
10758 any_shared_limit_changing = 0;
10759 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
10760 if (!valid_vl(i))
10761 continue;
10762 this_shared_changing = new_bc->vl[i].shared
10763 != cur_bc.vl[i].shared;
10764 if (this_shared_changing)
10765 any_shared_limit_changing = 1;
d0d236ea
JJ		 10766 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated ||
10767 this_shared_changing) {
77241056
MM		 10768 changing[i] = 1;
10769 changing_mask |= stat_mask;
10770 change_count++;
10771 }
10772 if (be16_to_cpu(new_bc->vl[i].dedicated) <
10773 be16_to_cpu(cur_bc.vl[i].dedicated)) {
10774 lowering_dedicated[i] = 1;
10775 ld_mask |= stat_mask;
10776 }
10777 }
10778
10779 /* bracket the credit change with a total adjustment */
10780 if (new_total > cur_total)
10781 set_global_limit(dd, new_total);
10782
10783 /*
10784 * Start the credit change algorithm.
10785 */
10786 use_all_mask = 0;
10787 if ((be16_to_cpu(new_bc->overall_shared_limit) <
995deafa
MM		 10788 be16_to_cpu(cur_bc.overall_shared_limit)) ||
10789 (is_ax(dd) && any_shared_limit_changing)) {
77241056
MM		 10790 set_global_shared(dd, 0);
10791 cur_bc.overall_shared_limit = 0;
10792 use_all_mask = 1;
10793 }
10794
10795 for (i = 0; i < NUM_USABLE_VLS; i++) {
10796 if (!valid_vl(i))
10797 continue;
10798
10799 if (changing[i]) {
10800 set_vl_shared(dd, i, 0);
10801 cur_bc.vl[i].shared = 0;
10802 }
10803 }
10804
10805 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
17fb4f29 10806 "shared");
77241056
MM		 10807
10808 if (change_count > 0) {
10809 for (i = 0; i < NUM_USABLE_VLS; i++) {
10810 if (!valid_vl(i))
10811 continue;
10812
10813 if (lowering_dedicated[i]) {
10814 set_vl_dedicated(dd, i,
17fb4f29
JJ		 10815 be16_to_cpu(new_bc->
10816 vl[i].dedicated));
77241056
MM		 10817 cur_bc.vl[i].dedicated =
10818 new_bc->vl[i].dedicated;
10819 }
10820 }
10821
10822 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
10823
10824 /* now raise all dedicated that are going up */
10825 for (i = 0; i < NUM_USABLE_VLS; i++) {
10826 if (!valid_vl(i))
10827 continue;
10828
10829 if (be16_to_cpu(new_bc->vl[i].dedicated) >
10830 be16_to_cpu(cur_bc.vl[i].dedicated))
10831 set_vl_dedicated(dd, i,
17fb4f29
JJ		 10832 be16_to_cpu(new_bc->
10833 vl[i].dedicated));
77241056
MM		 10834 }
10835 }
10836
10837 /* next raise all shared that are going up */
10838 for (i = 0; i < NUM_USABLE_VLS; i++) {
10839 if (!valid_vl(i))
10840 continue;
10841
10842 if (be16_to_cpu(new_bc->vl[i].shared) >
10843 be16_to_cpu(cur_bc.vl[i].shared))
10844 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
10845 }
10846
10847 /* finally raise the global shared */
10848 if (be16_to_cpu(new_bc->overall_shared_limit) >
17fb4f29 10849 be16_to_cpu(cur_bc.overall_shared_limit))
77241056 10850 set_global_shared(dd,
17fb4f29 10851 be16_to_cpu(new_bc->overall_shared_limit));
77241056
MM		 10852
10853 /* bracket the credit change with a total adjustment */
10854 if (new_total < cur_total)
10855 set_global_limit(dd, new_total);
8a4d3444
MM		 10856
10857 /*
10858 * Determine the actual number of operational VLS using the number of
10859 * dedicated and shared credits for each VL.
10860 */
10861 if (change_count > 0) {
10862 for (i = 0; i < TXE_NUM_DATA_VL; i++)
10863 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
10864 be16_to_cpu(new_bc->vl[i].shared) > 0)
10865 vl_count++;
10866 ppd->actual_vls_operational = vl_count;
10867 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
10868 ppd->actual_vls_operational :
10869 ppd->vls_operational,
10870 NULL);
10871 if (ret == 0)
10872 ret = pio_map_init(dd, ppd->port - 1, vl_count ?
10873 ppd->actual_vls_operational :
10874 ppd->vls_operational, NULL);
10875 if (ret)
10876 return ret;
10877 }
77241056
MM		 10878 return 0;
10879}
10880
10881/*
10882 * Read the given fabric manager table. Return the size of the
10883 * table (in bytes) on success, and a negative error code on
10884 * failure.
10885 */
10886int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
10887
10888{
10889 int size;
10890 struct vl_arb_cache *vlc;
10891
10892 switch (which) {
10893 case FM_TBL_VL_HIGH_ARB:
10894 size = 256;
10895 /*
10896 * OPA specifies 128 elements (of 2 bytes each), though
10897 * HFI supports only 16 elements in h/w.
10898 */
10899 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
10900 vl_arb_get_cache(vlc, t);
10901 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
10902 break;
10903 case FM_TBL_VL_LOW_ARB:
10904 size = 256;
10905 /*
10906 * OPA specifies 128 elements (of 2 bytes each), though
10907 * HFI supports only 16 elements in h/w.
10908 */
10909 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
10910 vl_arb_get_cache(vlc, t);
10911 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
10912 break;
10913 case FM_TBL_BUFFER_CONTROL:
10914 size = get_buffer_control(ppd->dd, t, NULL);
10915 break;
10916 case FM_TBL_SC2VLNT:
10917 size = get_sc2vlnt(ppd->dd, t);
10918 break;
10919 case FM_TBL_VL_PREEMPT_ELEMS:
10920 size = 256;
10921 /* OPA specifies 128 elements, of 2 bytes each */
10922 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
10923 break;
10924 case FM_TBL_VL_PREEMPT_MATRIX:
10925 size = 256;
10926 /*
10927 * OPA specifies that this is the same size as the VL
10928 * arbitration tables (i.e., 256 bytes).
10929 */
10930 break;
10931 default:
10932 return -EINVAL;
10933 }
10934 return size;
10935}
10936
10937/*
10938 * Write the given fabric manager table.
10939 */
10940int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
10941{
10942 int ret = 0;
10943 struct vl_arb_cache *vlc;
10944
10945 switch (which) {
10946 case FM_TBL_VL_HIGH_ARB:
10947 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
10948 if (vl_arb_match_cache(vlc, t)) {
10949 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
10950 break;
10951 }
10952 vl_arb_set_cache(vlc, t);
10953 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
10954 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
10955 VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
10956 break;
10957 case FM_TBL_VL_LOW_ARB:
10958 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
10959 if (vl_arb_match_cache(vlc, t)) {
10960 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
10961 break;
10962 }
10963 vl_arb_set_cache(vlc, t);
10964 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
10965 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
10966 VL_ARB_LOW_PRIO_TABLE_SIZE, t);
10967 break;
10968 case FM_TBL_BUFFER_CONTROL:
8a4d3444 10969 ret = set_buffer_control(ppd, t);
77241056
MM		 10970 break;
10971 case FM_TBL_SC2VLNT:
10972 set_sc2vlnt(ppd->dd, t);
10973 break;
10974 default:
10975 ret = -EINVAL;
10976 }
10977 return ret;
10978}
10979
10980/*
10981 * Disable all data VLs.
10982 *
10983 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
10984 */
10985static int disable_data_vls(struct hfi1_devdata *dd)
10986{
995deafa 10987 if (is_ax(dd))
77241056
MM		 10988 return 1;
10989
10990 pio_send_control(dd, PSC_DATA_VL_DISABLE);
10991
10992 return 0;
10993}
10994
10995/*
10996 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
10997 * Just re-enables all data VLs (the "fill" part happens
10998 * automatically - the name was chosen for symmetry with
10999 * stop_drain_data_vls()).
11000 *
11001 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11002 */
11003int open_fill_data_vls(struct hfi1_devdata *dd)
11004{
995deafa 11005 if (is_ax(dd))
77241056
MM		 11006 return 1;
11007
11008 pio_send_control(dd, PSC_DATA_VL_ENABLE);
11009
11010 return 0;
11011}
11012
11013/*
11014 * drain_data_vls() - assumes that disable_data_vls() has been called,
11015 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11016 * engines to drop to 0.
11017 */
11018static void drain_data_vls(struct hfi1_devdata *dd)
11019{
11020 sc_wait(dd);
11021 sdma_wait(dd);
11022 pause_for_credit_return(dd);
11023}
11024
11025/*
11026 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11027 *
11028 * Use open_fill_data_vls() to resume using data VLs. This pair is
11029 * meant to be used like this:
11030 *
11031 * stop_drain_data_vls(dd);
11032 * // do things with per-VL resources
11033 * open_fill_data_vls(dd);
11034 */
11035int stop_drain_data_vls(struct hfi1_devdata *dd)
11036{
11037 int ret;
11038
11039 ret = disable_data_vls(dd);
11040 if (ret == 0)
11041 drain_data_vls(dd);
11042
11043 return ret;
11044}
11045
11046/*
11047 * Convert a nanosecond time to a cclock count. No matter how slow
11048 * the cclock, a non-zero ns will always have a non-zero result.
11049 */
11050u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11051{
11052 u32 cclocks;
11053
11054 if (dd->icode == ICODE_FPGA_EMULATION)
11055 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11056 else /* simulation pretends to be ASIC */
11057 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11058 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */
11059 cclocks = 1;
11060 return cclocks;
11061}
11062
11063/*
11064 * Convert a cclock count to nanoseconds. Not matter how slow
11065 * the cclock, a non-zero cclocks will always have a non-zero result.
11066 */
11067u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11068{
11069 u32 ns;
11070
11071 if (dd->icode == ICODE_FPGA_EMULATION)
11072 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11073 else /* simulation pretends to be ASIC */
11074 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11075 if (cclocks && !ns)
11076 ns = 1;
11077 return ns;
11078}
11079
11080/*
11081 * Dynamically adjust the receive interrupt timeout for a context based on
11082 * incoming packet rate.
11083 *
11084 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11085 */
11086static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11087{
11088 struct hfi1_devdata *dd = rcd->dd;
11089 u32 timeout = rcd->rcvavail_timeout;
11090
11091 /*
11092 * This algorithm doubles or halves the timeout depending on whether
11093 * the number of packets received in this interrupt were less than or
11094 * greater equal the interrupt count.
11095 *
11096 * The calculations below do not allow a steady state to be achieved.
11097 * Only at the endpoints it is possible to have an unchanging
11098 * timeout.
11099 */
11100 if (npkts < rcv_intr_count) {
11101 /*
11102 * Not enough packets arrived before the timeout, adjust
11103 * timeout downward.
11104 */
11105 if (timeout < 2) /* already at minimum? */
11106 return;
11107 timeout >>= 1;
11108 } else {
11109 /*
11110 * More than enough packets arrived before the timeout, adjust
11111 * timeout upward.
11112 */
11113 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11114 return;
11115 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11116 }
11117
11118 rcd->rcvavail_timeout = timeout;
4d114fdd
JJ		 11119 /*
11120 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11121 * been verified to be in range
11122 */
77241056 11123 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
17fb4f29
JJ		 11124 (u64)timeout <<
11125 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
77241056
MM		 11126}
11127
11128void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11129 u32 intr_adjust, u32 npkts)
11130{
11131 struct hfi1_devdata *dd = rcd->dd;
11132 u64 reg;
11133 u32 ctxt = rcd->ctxt;
11134
11135 /*
11136 * Need to write timeout register before updating RcvHdrHead to ensure
11137 * that a new value is used when the HW decides to restart counting.
11138 */
11139 if (intr_adjust)
11140 adjust_rcv_timeout(rcd, npkts);
11141 if (updegr) {
11142 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11143 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11144 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11145 }
11146 mmiowb();
11147 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11148 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11149 << RCV_HDR_HEAD_HEAD_SHIFT);
11150 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11151 mmiowb();
11152}
11153
11154u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11155{
11156 u32 head, tail;
11157
11158 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11159 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11160
11161 if (rcd->rcvhdrtail_kvaddr)
11162 tail = get_rcvhdrtail(rcd);
11163 else
11164 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11165
11166 return head == tail;
11167}
11168
11169/*
11170 * Context Control and Receive Array encoding for buffer size:
11171 * 0x0 invalid
11172 * 0x1 4 KB
11173 * 0x2 8 KB
11174 * 0x3 16 KB
11175 * 0x4 32 KB
11176 * 0x5 64 KB
11177 * 0x6 128 KB
11178 * 0x7 256 KB
11179 * 0x8 512 KB (Receive Array only)
11180 * 0x9 1 MB (Receive Array only)
11181 * 0xa 2 MB (Receive Array only)
11182 *
11183 * 0xB-0xF - reserved (Receive Array only)
11184 *
11185 *
11186 * This routine assumes that the value has already been sanity checked.
11187 */
11188static u32 encoded_size(u32 size)
11189{
11190 switch (size) {
8638b77f
JJ		 11191 case 4 * 1024: return 0x1;
11192 case 8 * 1024: return 0x2;
11193 case 16 * 1024: return 0x3;
11194 case 32 * 1024: return 0x4;
11195 case 64 * 1024: return 0x5;
11196 case 128 * 1024: return 0x6;
11197 case 256 * 1024: return 0x7;
11198 case 512 * 1024: return 0x8;
11199 case 1 * 1024 * 1024: return 0x9;
11200 case 2 * 1024 * 1024: return 0xa;
77241056
MM		 11201 }
11202 return 0x1; /* if invalid, go with the minimum size */
11203}
11204
11205void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt)
11206{
11207 struct hfi1_ctxtdata *rcd;
11208 u64 rcvctrl, reg;
11209 int did_enable = 0;
11210
11211 rcd = dd->rcd[ctxt];
11212 if (!rcd)
11213 return;
11214
11215 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11216
11217 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11218 /* if the context already enabled, don't do the extra steps */
d0d236ea
JJ		 11219 if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11220 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
77241056
MM		 11221 /* reset the tail and hdr addresses, and sequence count */
11222 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
11223 rcd->rcvhdrq_phys);
11224 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11225 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11226 rcd->rcvhdrqtailaddr_phys);
11227 rcd->seq_cnt = 1;
11228
11229 /* reset the cached receive header queue head value */
11230 rcd->head = 0;
11231
11232 /*
11233 * Zero the receive header queue so we don't get false
11234 * positives when checking the sequence number. The
11235 * sequence numbers could land exactly on the same spot.
11236 * E.g. a rcd restart before the receive header wrapped.
11237 */
11238 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
11239
11240 /* starting timeout */
11241 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
11242
11243 /* enable the context */
11244 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
11245
11246 /* clean the egr buffer size first */
11247 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11248 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
11249 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
11250 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
11251
11252 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11253 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
11254 did_enable = 1;
11255
11256 /* zero RcvEgrIndexHead */
11257 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
11258
11259 /* set eager count and base index */
11260 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
11261 & RCV_EGR_CTRL_EGR_CNT_MASK)
11262 << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
11263 (((rcd->eager_base >> RCV_SHIFT)
11264 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
11265 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
11266 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
11267
11268 /*
11269 * Set TID (expected) count and base index.
11270 * rcd->expected_count is set to individual RcvArray entries,
11271 * not pairs, and the CSR takes a pair-count in groups of
11272 * four, so divide by 8.
11273 */
11274 reg = (((rcd->expected_count >> RCV_SHIFT)
11275 & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
11276 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
11277 (((rcd->expected_base >> RCV_SHIFT)
11278 & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
11279 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
11280 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
82c2611d
NV		 11281 if (ctxt == HFI1_CTRL_CTXT)
11282 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
77241056
MM		 11283 }
11284 if (op & HFI1_RCVCTRL_CTXT_DIS) {
11285 write_csr(dd, RCV_VL15, 0);
46b010d3
MB		 11286 /*
11287 * When receive context is being disabled turn on tail
11288 * update with a dummy tail address and then disable
11289 * receive context.
11290 */
11291 if (dd->rcvhdrtail_dummy_physaddr) {
11292 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11293 dd->rcvhdrtail_dummy_physaddr);
566c157c 11294 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
46b010d3
MB		 11295 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11296 }
11297
77241056
MM		 11298 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11299 }
11300 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11301 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11302 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11303 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11304 if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_phys)
11305 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
566c157c
MH		 11306 if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11307 /* See comment on RcvCtxtCtrl.TailUpd above */
11308 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11309 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11310 }
77241056
MM		 11311 if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11312 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11313 if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
11314 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11315 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
4d114fdd
JJ		 11316 /*
11317 * In one-packet-per-eager mode, the size comes from
11318 * the RcvArray entry.
11319 */
77241056
MM		 11320 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11321 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11322 }
11323 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
11324 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11325 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
11326 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11327 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
11328 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11329 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
11330 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11331 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
11332 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11333 rcd->rcvctrl = rcvctrl;
11334 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
11335 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl);
11336
11337 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
d0d236ea
JJ		 11338 if (did_enable &&
11339 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
77241056
MM		 11340 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11341 if (reg != 0) {
11342 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
17fb4f29 11343 ctxt, reg);
77241056
MM		 11344 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11345 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
11346 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
11347 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11348 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11349 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
17fb4f29 11350 ctxt, reg, reg == 0 ? "not" : "still");
77241056
MM		 11351 }
11352 }
11353
11354 if (did_enable) {
11355 /*
11356 * The interrupt timeout and count must be set after
11357 * the context is enabled to take effect.
11358 */
11359 /* set interrupt timeout */
11360 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
17fb4f29 11361 (u64)rcd->rcvavail_timeout <<
77241056
MM		 11362 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11363
11364 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11365 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
11366 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11367 }
11368
11369 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11370 /*
11371 * If the context has been disabled and the Tail Update has
46b010d3
MB		 11372 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11373 * so it doesn't contain an address that is invalid.
77241056 11374 */
46b010d3
MB		 11375 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11376 dd->rcvhdrtail_dummy_physaddr);
77241056
MM		 11377}
11378
582e05c3 11379u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
77241056
MM		 11380{
11381 int ret;
11382 u64 val = 0;
11383
11384 if (namep) {
11385 ret = dd->cntrnameslen;
77241056
MM		 11386 *namep = dd->cntrnames;
11387 } else {
11388 const struct cntr_entry *entry;
11389 int i, j;
11390
11391 ret = (dd->ndevcntrs) * sizeof(u64);
77241056
MM		 11392
11393 /* Get the start of the block of counters */
11394 *cntrp = dd->cntrs;
11395
11396 /*
11397 * Now go and fill in each counter in the block.
11398 */
11399 for (i = 0; i < DEV_CNTR_LAST; i++) {
11400 entry = &dev_cntrs[i];
11401 hfi1_cdbg(CNTR, "reading %s", entry->name);
11402 if (entry->flags & CNTR_DISABLED) {
11403 /* Nothing */
11404 hfi1_cdbg(CNTR, "\tDisabled\n");
11405 } else {
11406 if (entry->flags & CNTR_VL) {
11407 hfi1_cdbg(CNTR, "\tPer VL\n");
11408 for (j = 0; j < C_VL_COUNT; j++) {
11409 val = entry->rw_cntr(entry,
11410 dd, j,
11411 CNTR_MODE_R,
11412 0);
11413 hfi1_cdbg(
11414 CNTR,
11415 "\t\tRead 0x%llx for %d\n",
11416 val, j);
11417 dd->cntrs[entry->offset + j] =
11418 val;
11419 }
a699c6c2
VM		 11420 } else if (entry->flags & CNTR_SDMA) {
11421 hfi1_cdbg(CNTR,
11422 "\t Per SDMA Engine\n");
11423 for (j = 0; j < dd->chip_sdma_engines;
11424 j++) {
11425 val =
11426 entry->rw_cntr(entry, dd, j,
11427 CNTR_MODE_R, 0);
11428 hfi1_cdbg(CNTR,
11429 "\t\tRead 0x%llx for %d\n",
11430 val, j);
11431 dd->cntrs[entry->offset + j] =
11432 val;
11433 }
77241056
MM		 11434 } else {
11435 val = entry->rw_cntr(entry, dd,
11436 CNTR_INVALID_VL,
11437 CNTR_MODE_R, 0);
11438 dd->cntrs[entry->offset] = val;
11439 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11440 }
11441 }
11442 }
11443 }
11444 return ret;
11445}
11446
11447/*
11448 * Used by sysfs to create files for hfi stats to read
11449 */
582e05c3 11450u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp)
77241056
MM		 11451{
11452 int ret;
11453 u64 val = 0;
11454
11455 if (namep) {
582e05c3
DL		 11456 ret = ppd->dd->portcntrnameslen;
11457 *namep = ppd->dd->portcntrnames;
77241056
MM		 11458 } else {
11459 const struct cntr_entry *entry;
77241056
MM		 11460 int i, j;
11461
582e05c3 11462 ret = ppd->dd->nportcntrs * sizeof(u64);
77241056
MM		 11463 *cntrp = ppd->cntrs;
11464
11465 for (i = 0; i < PORT_CNTR_LAST; i++) {
11466 entry = &port_cntrs[i];
11467 hfi1_cdbg(CNTR, "reading %s", entry->name);
11468 if (entry->flags & CNTR_DISABLED) {
11469 /* Nothing */
11470 hfi1_cdbg(CNTR, "\tDisabled\n");
11471 continue;
11472 }
11473
11474 if (entry->flags & CNTR_VL) {
11475 hfi1_cdbg(CNTR, "\tPer VL");
11476 for (j = 0; j < C_VL_COUNT; j++) {
11477 val = entry->rw_cntr(entry, ppd, j,
11478 CNTR_MODE_R,
11479 0);
11480 hfi1_cdbg(
11481 CNTR,
11482 "\t\tRead 0x%llx for %d",
11483 val, j);
11484 ppd->cntrs[entry->offset + j] = val;
11485 }
11486 } else {
11487 val = entry->rw_cntr(entry, ppd,
11488 CNTR_INVALID_VL,
11489 CNTR_MODE_R,
11490 0);
11491 ppd->cntrs[entry->offset] = val;
11492 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11493 }
11494 }
11495 }
11496 return ret;
11497}
11498
11499static void free_cntrs(struct hfi1_devdata *dd)
11500{
11501 struct hfi1_pportdata *ppd;
11502 int i;
11503
11504 if (dd->synth_stats_timer.data)
11505 del_timer_sync(&dd->synth_stats_timer);
11506 dd->synth_stats_timer.data = 0;
11507 ppd = (struct hfi1_pportdata *)(dd + 1);
11508 for (i = 0; i < dd->num_pports; i++, ppd++) {
11509 kfree(ppd->cntrs);
11510 kfree(ppd->scntrs);
4eb06882
DD		 11511 free_percpu(ppd->ibport_data.rvp.rc_acks);
11512 free_percpu(ppd->ibport_data.rvp.rc_qacks);
11513 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
77241056
MM		 11514 ppd->cntrs = NULL;
11515 ppd->scntrs = NULL;
4eb06882
DD		 11516 ppd->ibport_data.rvp.rc_acks = NULL;
11517 ppd->ibport_data.rvp.rc_qacks = NULL;
11518 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
77241056
MM		 11519 }
11520 kfree(dd->portcntrnames);
11521 dd->portcntrnames = NULL;
11522 kfree(dd->cntrs);
11523 dd->cntrs = NULL;
11524 kfree(dd->scntrs);
11525 dd->scntrs = NULL;
11526 kfree(dd->cntrnames);
11527 dd->cntrnames = NULL;
11528}
11529
11530#define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
11531#define CNTR_32BIT_MAX 0x00000000FFFFFFFF
11532
11533static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
11534 u64 *psval, void *context, int vl)
11535{
11536 u64 val;
11537 u64 sval = *psval;
11538
11539 if (entry->flags & CNTR_DISABLED) {
11540 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11541 return 0;
11542 }
11543
11544 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11545
11546 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
11547
11548 /* If its a synthetic counter there is more work we need to do */
11549 if (entry->flags & CNTR_SYNTH) {
11550 if (sval == CNTR_MAX) {
11551 /* No need to read already saturated */
11552 return CNTR_MAX;
11553 }
11554
11555 if (entry->flags & CNTR_32BIT) {
11556 /* 32bit counters can wrap multiple times */
11557 u64 upper = sval >> 32;
11558 u64 lower = (sval << 32) >> 32;
11559
11560 if (lower > val) { /* hw wrapped */
11561 if (upper == CNTR_32BIT_MAX)
11562 val = CNTR_MAX;
11563 else
11564 upper++;
11565 }
11566
11567 if (val != CNTR_MAX)
11568 val = (upper << 32) | val;
11569
11570 } else {
11571 /* If we rolled we are saturated */
11572 if ((val < sval) || (val > CNTR_MAX))
11573 val = CNTR_MAX;
11574 }
11575 }
11576
11577 *psval = val;
11578
11579 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11580
11581 return val;
11582}
11583
11584static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
11585 struct cntr_entry *entry,
11586 u64 *psval, void *context, int vl, u64 data)
11587{
11588 u64 val;
11589
11590 if (entry->flags & CNTR_DISABLED) {
11591 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11592 return 0;
11593 }
11594
11595 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11596
11597 if (entry->flags & CNTR_SYNTH) {
11598 *psval = data;
11599 if (entry->flags & CNTR_32BIT) {
11600 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11601 (data << 32) >> 32);
11602 val = data; /* return the full 64bit value */
11603 } else {
11604 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11605 data);
11606 }
11607 } else {
11608 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
11609 }
11610
11611 *psval = val;
11612
11613 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11614
11615 return val;
11616}
11617
11618u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
11619{
11620 struct cntr_entry *entry;
11621 u64 *sval;
11622
11623 entry = &dev_cntrs[index];
11624 sval = dd->scntrs + entry->offset;
11625
11626 if (vl != CNTR_INVALID_VL)
11627 sval += vl;
11628
11629 return read_dev_port_cntr(dd, entry, sval, dd, vl);
11630}
11631
11632u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
11633{
11634 struct cntr_entry *entry;
11635 u64 *sval;
11636
11637 entry = &dev_cntrs[index];
11638 sval = dd->scntrs + entry->offset;
11639
11640 if (vl != CNTR_INVALID_VL)
11641 sval += vl;
11642
11643 return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
11644}
11645
11646u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
11647{
11648 struct cntr_entry *entry;
11649 u64 *sval;
11650
11651 entry = &port_cntrs[index];
11652 sval = ppd->scntrs + entry->offset;
11653
11654 if (vl != CNTR_INVALID_VL)
11655 sval += vl;
11656
11657 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11658 (index <= C_RCV_HDR_OVF_LAST)) {
11659 /* We do not want to bother for disabled contexts */
11660 return 0;
11661 }
11662
11663 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
11664}
11665
11666u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
11667{
11668 struct cntr_entry *entry;
11669 u64 *sval;
11670
11671 entry = &port_cntrs[index];
11672 sval = ppd->scntrs + entry->offset;
11673
11674 if (vl != CNTR_INVALID_VL)
11675 sval += vl;
11676
11677 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11678 (index <= C_RCV_HDR_OVF_LAST)) {
11679 /* We do not want to bother for disabled contexts */
11680 return 0;
11681 }
11682
11683 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
11684}
11685
11686static void update_synth_timer(unsigned long opaque)
11687{
11688 u64 cur_tx;
11689 u64 cur_rx;
11690 u64 total_flits;
11691 u8 update = 0;
11692 int i, j, vl;
11693 struct hfi1_pportdata *ppd;
11694 struct cntr_entry *entry;
11695
11696 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
11697
11698 /*
11699 * Rather than keep beating on the CSRs pick a minimal set that we can
11700 * check to watch for potential roll over. We can do this by looking at
11701 * the number of flits sent/recv. If the total flits exceeds 32bits then
11702 * we have to iterate all the counters and update.
11703 */
11704 entry = &dev_cntrs[C_DC_RCV_FLITS];
11705 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11706
11707 entry = &dev_cntrs[C_DC_XMIT_FLITS];
11708 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11709
11710 hfi1_cdbg(
11711 CNTR,
11712 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
11713 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
11714
11715 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
11716 /*
11717 * May not be strictly necessary to update but it won't hurt and
11718 * simplifies the logic here.
11719 */
11720 update = 1;
11721 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
11722 dd->unit);
11723 } else {
11724 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
11725 hfi1_cdbg(CNTR,
11726 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
11727 total_flits, (u64)CNTR_32BIT_MAX);
11728 if (total_flits >= CNTR_32BIT_MAX) {
11729 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
11730 dd->unit);
11731 update = 1;
11732 }
11733 }
11734
11735 if (update) {
11736 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
11737 for (i = 0; i < DEV_CNTR_LAST; i++) {
11738 entry = &dev_cntrs[i];
11739 if (entry->flags & CNTR_VL) {
11740 for (vl = 0; vl < C_VL_COUNT; vl++)
11741 read_dev_cntr(dd, i, vl);
11742 } else {
11743 read_dev_cntr(dd, i, CNTR_INVALID_VL);
11744 }
11745 }
11746 ppd = (struct hfi1_pportdata *)(dd + 1);
11747 for (i = 0; i < dd->num_pports; i++, ppd++) {
11748 for (j = 0; j < PORT_CNTR_LAST; j++) {
11749 entry = &port_cntrs[j];
11750 if (entry->flags & CNTR_VL) {
11751 for (vl = 0; vl < C_VL_COUNT; vl++)
11752 read_port_cntr(ppd, j, vl);
11753 } else {
11754 read_port_cntr(ppd, j, CNTR_INVALID_VL);
11755 }
11756 }
11757 }
11758
11759 /*
11760 * We want the value in the register. The goal is to keep track
11761 * of the number of "ticks" not the counter value. In other
11762 * words if the register rolls we want to notice it and go ahead
11763 * and force an update.
11764 */
11765 entry = &dev_cntrs[C_DC_XMIT_FLITS];
11766 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
11767 CNTR_MODE_R, 0);
11768
11769 entry = &dev_cntrs[C_DC_RCV_FLITS];
11770 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
11771 CNTR_MODE_R, 0);
11772
11773 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
11774 dd->unit, dd->last_tx, dd->last_rx);
11775
11776 } else {
11777 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
11778 }
11779
11780mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
11781}
11782
11783#define C_MAX_NAME 13 /* 12 chars + one for /0 */
11784static int init_cntrs(struct hfi1_devdata *dd)
11785{
c024c554 11786 int i, rcv_ctxts, j;
77241056
MM		 11787 size_t sz;
11788 char *p;
11789 char name[C_MAX_NAME];
11790 struct hfi1_pportdata *ppd;
11d2b114
SS		 11791 const char *bit_type_32 = ",32";
11792 const int bit_type_32_sz = strlen(bit_type_32);
77241056
MM		 11793
11794 /* set up the stats timer; the add_timer is done at the end */
24523a94
MFW		 11795 setup_timer(&dd->synth_stats_timer, update_synth_timer,
11796 (unsigned long)dd);
77241056
MM		 11797
11798 /***********************/
11799 /* per device counters */
11800 /***********************/
11801
11802 /* size names and determine how many we have*/
11803 dd->ndevcntrs = 0;
11804 sz = 0;
77241056
MM		 11805
11806 for (i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 11807 if (dev_cntrs[i].flags & CNTR_DISABLED) {
11808 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
11809 continue;
11810 }
11811
11812 if (dev_cntrs[i].flags & CNTR_VL) {
c024c554 11813 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 11814 for (j = 0; j < C_VL_COUNT; j++) {
77241056 11815 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 11816 dev_cntrs[i].name, vl_from_idx(j));
77241056 11817 sz += strlen(name);
11d2b114
SS		 11818 /* Add ",32" for 32-bit counters */
11819 if (dev_cntrs[i].flags & CNTR_32BIT)
11820 sz += bit_type_32_sz;
77241056 11821 sz++;
77241056 11822 dd->ndevcntrs++;
77241056 11823 }
a699c6c2 11824 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
c024c554 11825 dev_cntrs[i].offset = dd->ndevcntrs;
a699c6c2 11826 for (j = 0; j < dd->chip_sdma_engines; j++) {
a699c6c2
VM		 11827 snprintf(name, C_MAX_NAME, "%s%d",
11828 dev_cntrs[i].name, j);
77241056 11829 sz += strlen(name);
11d2b114
SS		 11830 /* Add ",32" for 32-bit counters */
11831 if (dev_cntrs[i].flags & CNTR_32BIT)
11832 sz += bit_type_32_sz;
77241056 11833 sz++;
77241056 11834 dd->ndevcntrs++;
77241056
MM		 11835 }
11836 } else {
11d2b114 11837 /* +1 for newline. */
77241056 11838 sz += strlen(dev_cntrs[i].name) + 1;
11d2b114
SS		 11839 /* Add ",32" for 32-bit counters */
11840 if (dev_cntrs[i].flags & CNTR_32BIT)
11841 sz += bit_type_32_sz;
c024c554 11842 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 11843 dd->ndevcntrs++;
77241056
MM		 11844 }
11845 }
11846
11847 /* allocate space for the counter values */
c024c554 11848 dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 11849 if (!dd->cntrs)
11850 goto bail;
11851
c024c554 11852 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 11853 if (!dd->scntrs)
11854 goto bail;
11855
77241056
MM		 11856 /* allocate space for the counter names */
11857 dd->cntrnameslen = sz;
11858 dd->cntrnames = kmalloc(sz, GFP_KERNEL);
11859 if (!dd->cntrnames)
11860 goto bail;
11861
11862 /* fill in the names */
c024c554 11863 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 11864 if (dev_cntrs[i].flags & CNTR_DISABLED) {
11865 /* Nothing */
11d2b114
SS		 11866 } else if (dev_cntrs[i].flags & CNTR_VL) {
11867 for (j = 0; j < C_VL_COUNT; j++) {
11d2b114
SS		 11868 snprintf(name, C_MAX_NAME, "%s%d",
11869 dev_cntrs[i].name,
11870 vl_from_idx(j));
11871 memcpy(p, name, strlen(name));
11872 p += strlen(name);
11873
11874 /* Counter is 32 bits */
11875 if (dev_cntrs[i].flags & CNTR_32BIT) {
11876 memcpy(p, bit_type_32, bit_type_32_sz);
11877 p += bit_type_32_sz;
77241056 11878 }
11d2b114
SS		 11879
11880 *p++ = '\n';
11881 }
11882 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
11883 for (j = 0; j < dd->chip_sdma_engines; j++) {
11d2b114
SS		 11884 snprintf(name, C_MAX_NAME, "%s%d",
11885 dev_cntrs[i].name, j);
11886 memcpy(p, name, strlen(name));
11887 p += strlen(name);
11888
11889 /* Counter is 32 bits */
11890 if (dev_cntrs[i].flags & CNTR_32BIT) {
11891 memcpy(p, bit_type_32, bit_type_32_sz);
11892 p += bit_type_32_sz;
a699c6c2 11893 }
11d2b114 11894
77241056
MM		 11895 *p++ = '\n';
11896 }
11d2b114
SS		 11897 } else {
11898 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
11899 p += strlen(dev_cntrs[i].name);
11900
11901 /* Counter is 32 bits */
11902 if (dev_cntrs[i].flags & CNTR_32BIT) {
11903 memcpy(p, bit_type_32, bit_type_32_sz);
11904 p += bit_type_32_sz;
11905 }
11906
11907 *p++ = '\n';
77241056
MM		 11908 }
11909 }
11910
11911 /*********************/
11912 /* per port counters */
11913 /*********************/
11914
11915 /*
11916 * Go through the counters for the overflows and disable the ones we
11917 * don't need. This varies based on platform so we need to do it
11918 * dynamically here.
11919 */
11920 rcv_ctxts = dd->num_rcv_contexts;
11921 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
11922 i <= C_RCV_HDR_OVF_LAST; i++) {
11923 port_cntrs[i].flags |= CNTR_DISABLED;
11924 }
11925
11926 /* size port counter names and determine how many we have*/
11927 sz = 0;
11928 dd->nportcntrs = 0;
11929 for (i = 0; i < PORT_CNTR_LAST; i++) {
77241056
MM		 11930 if (port_cntrs[i].flags & CNTR_DISABLED) {
11931 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
11932 continue;
11933 }
11934
11935 if (port_cntrs[i].flags & CNTR_VL) {
77241056
MM		 11936 port_cntrs[i].offset = dd->nportcntrs;
11937 for (j = 0; j < C_VL_COUNT; j++) {
77241056 11938 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 11939 port_cntrs[i].name, vl_from_idx(j));
77241056 11940 sz += strlen(name);
11d2b114
SS		 11941 /* Add ",32" for 32-bit counters */
11942 if (port_cntrs[i].flags & CNTR_32BIT)
11943 sz += bit_type_32_sz;
77241056 11944 sz++;
77241056
MM		 11945 dd->nportcntrs++;
11946 }
11947 } else {
11d2b114 11948 /* +1 for newline */
77241056 11949 sz += strlen(port_cntrs[i].name) + 1;
11d2b114
SS		 11950 /* Add ",32" for 32-bit counters */
11951 if (port_cntrs[i].flags & CNTR_32BIT)
11952 sz += bit_type_32_sz;
77241056
MM		 11953 port_cntrs[i].offset = dd->nportcntrs;
11954 dd->nportcntrs++;
77241056
MM		 11955 }
11956 }
11957
11958 /* allocate space for the counter names */
11959 dd->portcntrnameslen = sz;
11960 dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
11961 if (!dd->portcntrnames)
11962 goto bail;
11963
11964 /* fill in port cntr names */
11965 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
11966 if (port_cntrs[i].flags & CNTR_DISABLED)
11967 continue;
11968
11969 if (port_cntrs[i].flags & CNTR_VL) {
11970 for (j = 0; j < C_VL_COUNT; j++) {
77241056 11971 snprintf(name, C_MAX_NAME, "%s%d",
17fb4f29 11972 port_cntrs[i].name, vl_from_idx(j));
77241056
MM		 11973 memcpy(p, name, strlen(name));
11974 p += strlen(name);
11d2b114
SS		 11975
11976 /* Counter is 32 bits */
11977 if (port_cntrs[i].flags & CNTR_32BIT) {
11978 memcpy(p, bit_type_32, bit_type_32_sz);
11979 p += bit_type_32_sz;
11980 }
11981
77241056
MM		 11982 *p++ = '\n';
11983 }
11984 } else {
11985 memcpy(p, port_cntrs[i].name,
11986 strlen(port_cntrs[i].name));
11987 p += strlen(port_cntrs[i].name);
11d2b114
SS		 11988
11989 /* Counter is 32 bits */
11990 if (port_cntrs[i].flags & CNTR_32BIT) {
11991 memcpy(p, bit_type_32, bit_type_32_sz);
11992 p += bit_type_32_sz;
11993 }
11994
77241056
MM		 11995 *p++ = '\n';
11996 }
11997 }
11998
11999 /* allocate per port storage for counter values */
12000 ppd = (struct hfi1_pportdata *)(dd + 1);
12001 for (i = 0; i < dd->num_pports; i++, ppd++) {
12002 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12003 if (!ppd->cntrs)
12004 goto bail;
12005
12006 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12007 if (!ppd->scntrs)
12008 goto bail;
12009 }
12010
12011 /* CPU counters need to be allocated and zeroed */
12012 if (init_cpu_counters(dd))
12013 goto bail;
12014
12015 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12016 return 0;
12017bail:
12018 free_cntrs(dd);
12019 return -ENOMEM;
12020}
12021
77241056
MM		 12022static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12023{
12024 switch (chip_lstate) {
12025 default:
12026 dd_dev_err(dd,
17fb4f29
JJ		 12027 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12028 chip_lstate);
77241056
MM		 12029 /* fall through */
12030 case LSTATE_DOWN:
12031 return IB_PORT_DOWN;
12032 case LSTATE_INIT:
12033 return IB_PORT_INIT;
12034 case LSTATE_ARMED:
12035 return IB_PORT_ARMED;
12036 case LSTATE_ACTIVE:
12037 return IB_PORT_ACTIVE;
12038 }
12039}
12040
12041u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12042{
12043 /* look at the HFI meta-states only */
12044 switch (chip_pstate & 0xf0) {
12045 default:
12046 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
17fb4f29 12047 chip_pstate);
77241056
MM		 12048 /* fall through */
12049 case PLS_DISABLED:
12050 return IB_PORTPHYSSTATE_DISABLED;
12051 case PLS_OFFLINE:
12052 return OPA_PORTPHYSSTATE_OFFLINE;
12053 case PLS_POLLING:
12054 return IB_PORTPHYSSTATE_POLLING;
12055 case PLS_CONFIGPHY:
12056 return IB_PORTPHYSSTATE_TRAINING;
12057 case PLS_LINKUP:
12058 return IB_PORTPHYSSTATE_LINKUP;
12059 case PLS_PHYTEST:
12060 return IB_PORTPHYSSTATE_PHY_TEST;
12061 }
12062}
12063
12064/* return the OPA port logical state name */
12065const char *opa_lstate_name(u32 lstate)
12066{
12067 static const char * const port_logical_names[] = {
12068 "PORT_NOP",
12069 "PORT_DOWN",
12070 "PORT_INIT",
12071 "PORT_ARMED",
12072 "PORT_ACTIVE",
12073 "PORT_ACTIVE_DEFER",
12074 };
12075 if (lstate < ARRAY_SIZE(port_logical_names))
12076 return port_logical_names[lstate];
12077 return "unknown";
12078}
12079
12080/* return the OPA port physical state name */
12081const char *opa_pstate_name(u32 pstate)
12082{
12083 static const char * const port_physical_names[] = {
12084 "PHYS_NOP",
12085 "reserved1",
12086 "PHYS_POLL",
12087 "PHYS_DISABLED",
12088 "PHYS_TRAINING",
12089 "PHYS_LINKUP",
12090 "PHYS_LINK_ERR_RECOVER",
12091 "PHYS_PHY_TEST",
12092 "reserved8",
12093 "PHYS_OFFLINE",
12094 "PHYS_GANGED",
12095 "PHYS_TEST",
12096 };
12097 if (pstate < ARRAY_SIZE(port_physical_names))
12098 return port_physical_names[pstate];
12099 return "unknown";
12100}
12101
12102/*
12103 * Read the hardware link state and set the driver's cached value of it.
12104 * Return the (new) current value.
12105 */
12106u32 get_logical_state(struct hfi1_pportdata *ppd)
12107{
12108 u32 new_state;
12109
12110 new_state = chip_to_opa_lstate(ppd->dd, read_logical_state(ppd->dd));
12111 if (new_state != ppd->lstate) {
12112 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
17fb4f29 12113 opa_lstate_name(new_state), new_state);
77241056
MM		 12114 ppd->lstate = new_state;
12115 }
12116 /*
12117 * Set port status flags in the page mapped into userspace
12118 * memory. Do it here to ensure a reliable state - this is
12119 * the only function called by all state handling code.
12120 * Always set the flags due to the fact that the cache value
12121 * might have been changed explicitly outside of this
12122 * function.
12123 */
12124 if (ppd->statusp) {
12125 switch (ppd->lstate) {
12126 case IB_PORT_DOWN:
12127 case IB_PORT_INIT:
12128 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12129 HFI1_STATUS_IB_READY);
12130 break;
12131 case IB_PORT_ARMED:
12132 *ppd->statusp |= HFI1_STATUS_IB_CONF;
12133 break;
12134 case IB_PORT_ACTIVE:
12135 *ppd->statusp |= HFI1_STATUS_IB_READY;
12136 break;
12137 }
12138 }
12139 return ppd->lstate;
12140}
12141
12142/**
12143 * wait_logical_linkstate - wait for an IB link state change to occur
12144 * @ppd: port device
12145 * @state: the state to wait for
12146 * @msecs: the number of milliseconds to wait
12147 *
12148 * Wait up to msecs milliseconds for IB link state change to occur.
12149 * For now, take the easy polling route.
12150 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12151 */
12152static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12153 int msecs)
12154{
12155 unsigned long timeout;
12156
12157 timeout = jiffies + msecs_to_jiffies(msecs);
12158 while (1) {
12159 if (get_logical_state(ppd) == state)
12160 return 0;
12161 if (time_after(jiffies, timeout))
12162 break;
12163 msleep(20);
12164 }
12165 dd_dev_err(ppd->dd, "timeout waiting for link state 0x%x\n", state);
12166
12167 return -ETIMEDOUT;
12168}
12169
12170u8 hfi1_ibphys_portstate(struct hfi1_pportdata *ppd)
12171{
77241056
MM		 12172 u32 pstate;
12173 u32 ib_pstate;
12174
12175 pstate = read_physical_state(ppd->dd);
12176 ib_pstate = chip_to_opa_pstate(ppd->dd, pstate);
f45c8dc8 12177 if (ppd->last_pstate != ib_pstate) {
77241056 12178 dd_dev_info(ppd->dd,
17fb4f29
JJ		 12179 "%s: physical state changed to %s (0x%x), phy 0x%x\n",
12180 __func__, opa_pstate_name(ib_pstate), ib_pstate,
12181 pstate);
f45c8dc8 12182 ppd->last_pstate = ib_pstate;
77241056
MM		 12183 }
12184 return ib_pstate;
12185}
12186
12187/*
12188 * Read/modify/write ASIC_QSFP register bits as selected by mask
12189 * data: 0 or 1 in the positions depending on what needs to be written
12190 * dir: 0 for read, 1 for write
12191 * mask: select by setting
12192 * I2CCLK (bit 0)
12193 * I2CDATA (bit 1)
12194 */
12195u64 hfi1_gpio_mod(struct hfi1_devdata *dd, u32 target, u32 data, u32 dir,
12196 u32 mask)
12197{
12198 u64 qsfp_oe, target_oe;
12199
12200 target_oe = target ? ASIC_QSFP2_OE : ASIC_QSFP1_OE;
12201 if (mask) {
12202 /* We are writing register bits, so lock access */
12203 dir &= mask;
12204 data &= mask;
12205
12206 qsfp_oe = read_csr(dd, target_oe);
12207 qsfp_oe = (qsfp_oe & ~(u64)mask) | (u64)dir;
12208 write_csr(dd, target_oe, qsfp_oe);
12209 }
12210 /* We are exclusively reading bits here, but it is unlikely
12211 * we'll get valid data when we set the direction of the pin
12212 * in the same call, so read should call this function again
12213 * to get valid data
12214 */
12215 return read_csr(dd, target ? ASIC_QSFP2_IN : ASIC_QSFP1_IN);
12216}
12217
12218#define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12219(r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12220
12221#define SET_STATIC_RATE_CONTROL_SMASK(r) \
12222(r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12223
12224int hfi1_init_ctxt(struct send_context *sc)
12225{
d125a6c6 12226 if (sc) {
77241056
MM		 12227 struct hfi1_devdata *dd = sc->dd;
12228 u64 reg;
12229 u8 set = (sc->type == SC_USER ?
12230 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
12231 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
12232 reg = read_kctxt_csr(dd, sc->hw_context,
12233 SEND_CTXT_CHECK_ENABLE);
12234 if (set)
12235 CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
12236 else
12237 SET_STATIC_RATE_CONTROL_SMASK(reg);
12238 write_kctxt_csr(dd, sc->hw_context,
12239 SEND_CTXT_CHECK_ENABLE, reg);
12240 }
12241 return 0;
12242}
12243
12244int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12245{
12246 int ret = 0;
12247 u64 reg;
12248
12249 if (dd->icode != ICODE_RTL_SILICON) {
12250 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
12251 dd_dev_info(dd, "%s: tempsense not supported by HW\n",
12252 __func__);
12253 return -EINVAL;
12254 }
12255 reg = read_csr(dd, ASIC_STS_THERM);
12256 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
12257 ASIC_STS_THERM_CURR_TEMP_MASK);
12258 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
12259 ASIC_STS_THERM_LO_TEMP_MASK);
12260 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
12261 ASIC_STS_THERM_HI_TEMP_MASK);
12262 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
12263 ASIC_STS_THERM_CRIT_TEMP_MASK);
12264 /* triggers is a 3-bit value - 1 bit per trigger. */
12265 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
12266
12267 return ret;
12268}
12269
12270/* ========================================================================= */
12271
12272/*
12273 * Enable/disable chip from delivering interrupts.
12274 */
12275void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12276{
12277 int i;
12278
12279 /*
12280 * In HFI, the mask needs to be 1 to allow interrupts.
12281 */
12282 if (enable) {
77241056
MM		 12283 /* enable all interrupts */
12284 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12285 write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0);
77241056 12286
8ebd4cf1 12287 init_qsfp_int(dd);
77241056
MM		 12288 } else {
12289 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12290 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 12291 }
12292}
12293
12294/*
12295 * Clear all interrupt sources on the chip.
12296 */
12297static void clear_all_interrupts(struct hfi1_devdata *dd)
12298{
12299 int i;
12300
12301 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12302 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
77241056
MM		 12303
12304 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
12305 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
12306 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
12307 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
12308 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
12309 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
12310 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
12311 for (i = 0; i < dd->chip_send_contexts; i++)
12312 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
12313 for (i = 0; i < dd->chip_sdma_engines; i++)
12314 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
12315
12316 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
12317 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
12318 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
12319}
12320
12321/* Move to pcie.c? */
12322static void disable_intx(struct pci_dev *pdev)
12323{
12324 pci_intx(pdev, 0);
12325}
12326
12327static void clean_up_interrupts(struct hfi1_devdata *dd)
12328{
12329 int i;
12330
12331 /* remove irqs - must happen before disabling/turning off */
12332 if (dd->num_msix_entries) {
12333 /* MSI-X */
12334 struct hfi1_msix_entry *me = dd->msix_entries;
12335
12336 for (i = 0; i < dd->num_msix_entries; i++, me++) {
d125a6c6 12337 if (!me->arg) /* => no irq, no affinity */
957558c9
MH		 12338 continue;
12339 hfi1_put_irq_affinity(dd, &dd->msix_entries[i]);
77241056
MM		 12340 free_irq(me->msix.vector, me->arg);
12341 }
12342 } else {
12343 /* INTx */
12344 if (dd->requested_intx_irq) {
12345 free_irq(dd->pcidev->irq, dd);
12346 dd->requested_intx_irq = 0;
12347 }
12348 }
12349
12350 /* turn off interrupts */
12351 if (dd->num_msix_entries) {
12352 /* MSI-X */
6e5b6131 12353 pci_disable_msix(dd->pcidev);
77241056
MM		 12354 } else {
12355 /* INTx */
12356 disable_intx(dd->pcidev);
12357 }
12358
12359 /* clean structures */
77241056
MM		 12360 kfree(dd->msix_entries);
12361 dd->msix_entries = NULL;
12362 dd->num_msix_entries = 0;
12363}
12364
12365/*
12366 * Remap the interrupt source from the general handler to the given MSI-X
12367 * interrupt.
12368 */
12369static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
12370{
12371 u64 reg;
12372 int m, n;
12373
12374 /* clear from the handled mask of the general interrupt */
12375 m = isrc / 64;
12376 n = isrc % 64;
12377 dd->gi_mask[m] &= ~((u64)1 << n);
12378
12379 /* direct the chip source to the given MSI-X interrupt */
12380 m = isrc / 8;
12381 n = isrc % 8;
8638b77f
JJ		 12382 reg = read_csr(dd, CCE_INT_MAP + (8 * m));
12383 reg &= ~((u64)0xff << (8 * n));
12384 reg |= ((u64)msix_intr & 0xff) << (8 * n);
12385 write_csr(dd, CCE_INT_MAP + (8 * m), reg);
77241056
MM		 12386}
12387
12388static void remap_sdma_interrupts(struct hfi1_devdata *dd,
12389 int engine, int msix_intr)
12390{
12391 /*
12392 * SDMA engine interrupt sources grouped by type, rather than
12393 * engine. Per-engine interrupts are as follows:
12394 * SDMA
12395 * SDMAProgress
12396 * SDMAIdle
12397 */
8638b77f 12398 remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12399 msix_intr);
8638b77f 12400 remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12401 msix_intr);
8638b77f 12402 remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine,
17fb4f29 12403 msix_intr);
77241056
MM		 12404}
12405
77241056
MM		 12406static int request_intx_irq(struct hfi1_devdata *dd)
12407{
12408 int ret;
12409
9805071e
JJ		 12410 snprintf(dd->intx_name, sizeof(dd->intx_name), DRIVER_NAME "_%d",
12411 dd->unit);
77241056 12412 ret = request_irq(dd->pcidev->irq, general_interrupt,
17fb4f29 12413 IRQF_SHARED, dd->intx_name, dd);
77241056
MM		 12414 if (ret)
12415 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
17fb4f29 12416 ret);
77241056
MM		 12417 else
12418 dd->requested_intx_irq = 1;
12419 return ret;
12420}
12421
12422static int request_msix_irqs(struct hfi1_devdata *dd)
12423{
77241056
MM		 12424 int first_general, last_general;
12425 int first_sdma, last_sdma;
12426 int first_rx, last_rx;
957558c9 12427 int i, ret = 0;
77241056
MM		 12428
12429 /* calculate the ranges we are going to use */
12430 first_general = 0;
f3ff8189
JJ		 12431 last_general = first_general + 1;
12432 first_sdma = last_general;
12433 last_sdma = first_sdma + dd->num_sdma;
12434 first_rx = last_sdma;
77241056
MM		 12435 last_rx = first_rx + dd->n_krcv_queues;
12436
77241056
MM		 12437 /*
12438 * Sanity check - the code expects all SDMA chip source
12439 * interrupts to be in the same CSR, starting at bit 0. Verify
12440 * that this is true by checking the bit location of the start.
12441 */
12442 BUILD_BUG_ON(IS_SDMA_START % 64);
12443
12444 for (i = 0; i < dd->num_msix_entries; i++) {
12445 struct hfi1_msix_entry *me = &dd->msix_entries[i];
12446 const char *err_info;
12447 irq_handler_t handler;
f4f30031 12448 irq_handler_t thread = NULL;
77241056
MM		 12449 void *arg;
12450 int idx;
12451 struct hfi1_ctxtdata *rcd = NULL;
12452 struct sdma_engine *sde = NULL;
12453
12454 /* obtain the arguments to request_irq */
12455 if (first_general <= i && i < last_general) {
12456 idx = i - first_general;
12457 handler = general_interrupt;
12458 arg = dd;
12459 snprintf(me->name, sizeof(me->name),
9805071e 12460 DRIVER_NAME "_%d", dd->unit);
77241056 12461 err_info = "general";
957558c9 12462 me->type = IRQ_GENERAL;
77241056
MM		 12463 } else if (first_sdma <= i && i < last_sdma) {
12464 idx = i - first_sdma;
12465 sde = &dd->per_sdma[idx];
12466 handler = sdma_interrupt;
12467 arg = sde;
12468 snprintf(me->name, sizeof(me->name),
9805071e 12469 DRIVER_NAME "_%d sdma%d", dd->unit, idx);
77241056
MM		 12470 err_info = "sdma";
12471 remap_sdma_interrupts(dd, idx, i);
957558c9 12472 me->type = IRQ_SDMA;
77241056
MM		 12473 } else if (first_rx <= i && i < last_rx) {
12474 idx = i - first_rx;
12475 rcd = dd->rcd[idx];
12476 /* no interrupt if no rcd */
12477 if (!rcd)
12478 continue;
12479 /*
12480 * Set the interrupt register and mask for this
12481 * context's interrupt.
12482 */
8638b77f 12483 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
77241056 12484 rcd->imask = ((u64)1) <<
8638b77f 12485 ((IS_RCVAVAIL_START + idx) % 64);
77241056 12486 handler = receive_context_interrupt;
f4f30031 12487 thread = receive_context_thread;
77241056
MM		 12488 arg = rcd;
12489 snprintf(me->name, sizeof(me->name),
9805071e 12490 DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
77241056 12491 err_info = "receive context";
66c0933b 12492 remap_intr(dd, IS_RCVAVAIL_START + idx, i);
957558c9 12493 me->type = IRQ_RCVCTXT;
77241056
MM		 12494 } else {
12495 /* not in our expected range - complain, then
4d114fdd
JJ		 12496 * ignore it
12497 */
77241056 12498 dd_dev_err(dd,
17fb4f29 12499 "Unexpected extra MSI-X interrupt %d\n", i);
77241056
MM		 12500 continue;
12501 }
12502 /* no argument, no interrupt */
d125a6c6 12503 if (!arg)
77241056
MM		 12504 continue;
12505 /* make sure the name is terminated */
8638b77f 12506 me->name[sizeof(me->name) - 1] = 0;
77241056 12507
f4f30031 12508 ret = request_threaded_irq(me->msix.vector, handler, thread, 0,
17fb4f29 12509 me->name, arg);
77241056
MM		 12510 if (ret) {
12511 dd_dev_err(dd,
17fb4f29
JJ		 12512 "unable to allocate %s interrupt, vector %d, index %d, err %d\n",
12513 err_info, me->msix.vector, idx, ret);
77241056
MM		 12514 return ret;
12515 }
12516 /*
12517 * assign arg after request_irq call, so it will be
12518 * cleaned up
12519 */
12520 me->arg = arg;
12521
957558c9
MH		 12522 ret = hfi1_get_irq_affinity(dd, me);
12523 if (ret)
12524 dd_dev_err(dd,
12525 "unable to pin IRQ %d\n", ret);
77241056
MM		 12526 }
12527
77241056 12528 return ret;
77241056
MM		 12529}
12530
12531/*
12532 * Set the general handler to accept all interrupts, remap all
12533 * chip interrupts back to MSI-X 0.
12534 */
12535static void reset_interrupts(struct hfi1_devdata *dd)
12536{
12537 int i;
12538
12539 /* all interrupts handled by the general handler */
12540 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12541 dd->gi_mask[i] = ~(u64)0;
12542
12543 /* all chip interrupts map to MSI-X 0 */
12544 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 12545 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 12546}
12547
12548static int set_up_interrupts(struct hfi1_devdata *dd)
12549{
12550 struct hfi1_msix_entry *entries;
12551 u32 total, request;
12552 int i, ret;
12553 int single_interrupt = 0; /* we expect to have all the interrupts */
12554
12555 /*
12556 * Interrupt count:
12557 * 1 general, "slow path" interrupt (includes the SDMA engines
12558 * slow source, SDMACleanupDone)
12559 * N interrupts - one per used SDMA engine
12560 * M interrupt - one per kernel receive context
12561 */
12562 total = 1 + dd->num_sdma + dd->n_krcv_queues;
12563
12564 entries = kcalloc(total, sizeof(*entries), GFP_KERNEL);
12565 if (!entries) {
77241056
MM		 12566 ret = -ENOMEM;
12567 goto fail;
12568 }
12569 /* 1-1 MSI-X entry assignment */
12570 for (i = 0; i < total; i++)
12571 entries[i].msix.entry = i;
12572
12573 /* ask for MSI-X interrupts */
12574 request = total;
12575 request_msix(dd, &request, entries);
12576
12577 if (request == 0) {
12578 /* using INTx */
12579 /* dd->num_msix_entries already zero */
12580 kfree(entries);
12581 single_interrupt = 1;
12582 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n");
12583 } else {
12584 /* using MSI-X */
12585 dd->num_msix_entries = request;
12586 dd->msix_entries = entries;
12587
12588 if (request != total) {
12589 /* using MSI-X, with reduced interrupts */
12590 dd_dev_err(
12591 dd,
12592 "cannot handle reduced interrupt case, want %u, got %u\n",
12593 total, request);
12594 ret = -EINVAL;
12595 goto fail;
12596 }
12597 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
12598 }
12599
12600 /* mask all interrupts */
12601 set_intr_state(dd, 0);
12602 /* clear all pending interrupts */
12603 clear_all_interrupts(dd);
12604
12605 /* reset general handler mask, chip MSI-X mappings */
12606 reset_interrupts(dd);
12607
12608 if (single_interrupt)
12609 ret = request_intx_irq(dd);
12610 else
12611 ret = request_msix_irqs(dd);
12612 if (ret)
12613 goto fail;
12614
12615 return 0;
12616
12617fail:
12618 clean_up_interrupts(dd);
12619 return ret;
12620}
12621
12622/*
12623 * Set up context values in dd. Sets:
12624 *
12625 * num_rcv_contexts - number of contexts being used
12626 * n_krcv_queues - number of kernel contexts
12627 * first_user_ctxt - first non-kernel context in array of contexts
12628 * freectxts - number of free user contexts
12629 * num_send_contexts - number of PIO send contexts being used
12630 */
12631static int set_up_context_variables(struct hfi1_devdata *dd)
12632{
12633 int num_kernel_contexts;
77241056
MM		 12634 int total_contexts;
12635 int ret;
12636 unsigned ngroups;
8f000f7f
DL		 12637 int qos_rmt_count;
12638 int user_rmt_reduced;
77241056
MM		 12639
12640 /*
33a9eb52
DL		 12641 * Kernel receive contexts:
12642 * - min of 2 or 1 context/numa (excluding control context)
82c2611d 12643 * - Context 0 - control context (VL15/multicast/error)
33a9eb52
DL		 12644 * - Context 1 - first kernel context
12645 * - Context 2 - second kernel context
12646 * ...
77241056
MM		 12647 */
12648 if (n_krcvqs)
82c2611d 12649 /*
33a9eb52
DL		 12650 * n_krcvqs is the sum of module parameter kernel receive
12651 * contexts, krcvqs[]. It does not include the control
12652 * context, so add that.
82c2611d 12653 */
33a9eb52 12654 num_kernel_contexts = n_krcvqs + 1;
77241056 12655 else
0edf80ea 12656 num_kernel_contexts = num_online_nodes() + 1;
77241056
MM		 12657 num_kernel_contexts =
12658 max_t(int, MIN_KERNEL_KCTXTS, num_kernel_contexts);
12659 /*
12660 * Every kernel receive context needs an ACK send context.
12661 * one send context is allocated for each VL{0-7} and VL15
12662 */
12663 if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) {
12664 dd_dev_err(dd,
12665 "Reducing # kernel rcv contexts to: %d, from %d\n",
12666 (int)(dd->chip_send_contexts - num_vls - 1),
12667 (int)num_kernel_contexts);
12668 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
12669 }
12670 /*
0852d241
JJ		 12671 * User contexts:
12672 * - default to 1 user context per real (non-HT) CPU core if
12673 * num_user_contexts is negative
77241056 12674 */
2ce6bf22 12675 if (num_user_contexts < 0)
0852d241
JJ		 12676 num_user_contexts =
12677 cpumask_weight(&dd->affinity->real_cpu_mask);
77241056
MM		 12678
12679 total_contexts = num_kernel_contexts + num_user_contexts;
12680
12681 /*
12682 * Adjust the counts given a global max.
12683 */
12684 if (total_contexts > dd->chip_rcv_contexts) {
12685 dd_dev_err(dd,
12686 "Reducing # user receive contexts to: %d, from %d\n",
12687 (int)(dd->chip_rcv_contexts - num_kernel_contexts),
12688 (int)num_user_contexts);
12689 num_user_contexts = dd->chip_rcv_contexts - num_kernel_contexts;
12690 /* recalculate */
12691 total_contexts = num_kernel_contexts + num_user_contexts;
12692 }
12693
8f000f7f
DL		 12694 /* each user context requires an entry in the RMT */
12695 qos_rmt_count = qos_rmt_entries(dd, NULL, NULL);
12696 if (qos_rmt_count + num_user_contexts > NUM_MAP_ENTRIES) {
12697 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count;
12698 dd_dev_err(dd,
12699 "RMT size is reducing the number of user receive contexts from %d to %d\n",
12700 (int)num_user_contexts,
12701 user_rmt_reduced);
12702 /* recalculate */
12703 num_user_contexts = user_rmt_reduced;
12704 total_contexts = num_kernel_contexts + num_user_contexts;
12705 }
12706
77241056
MM		 12707 /* the first N are kernel contexts, the rest are user contexts */
12708 dd->num_rcv_contexts = total_contexts;
12709 dd->n_krcv_queues = num_kernel_contexts;
12710 dd->first_user_ctxt = num_kernel_contexts;
affa48de 12711 dd->num_user_contexts = num_user_contexts;
77241056
MM		 12712 dd->freectxts = num_user_contexts;
12713 dd_dev_info(dd,
17fb4f29
JJ		 12714 "rcv contexts: chip %d, used %d (kernel %d, user %d)\n",
12715 (int)dd->chip_rcv_contexts,
12716 (int)dd->num_rcv_contexts,
12717 (int)dd->n_krcv_queues,
12718 (int)dd->num_rcv_contexts - dd->n_krcv_queues);
77241056
MM		 12719
12720 /*
12721 * Receive array allocation:
12722 * All RcvArray entries are divided into groups of 8. This
12723 * is required by the hardware and will speed up writes to
12724 * consecutive entries by using write-combining of the entire
12725 * cacheline.
12726 *
12727 * The number of groups are evenly divided among all contexts.
12728 * any left over groups will be given to the first N user
12729 * contexts.
12730 */
12731 dd->rcv_entries.group_size = RCV_INCREMENT;
12732 ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size;
12733 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
12734 dd->rcv_entries.nctxt_extra = ngroups -
12735 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
12736 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
12737 dd->rcv_entries.ngroups,
12738 dd->rcv_entries.nctxt_extra);
12739 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
12740 MAX_EAGER_ENTRIES * 2) {
12741 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
12742 dd->rcv_entries.group_size;
12743 dd_dev_info(dd,
17fb4f29
JJ		 12744 "RcvArray group count too high, change to %u\n",
12745 dd->rcv_entries.ngroups);
77241056
MM		 12746 dd->rcv_entries.nctxt_extra = 0;
12747 }
12748 /*
12749 * PIO send contexts
12750 */
12751 ret = init_sc_pools_and_sizes(dd);
12752 if (ret >= 0) { /* success */
12753 dd->num_send_contexts = ret;
12754 dd_dev_info(
12755 dd,
44306f15 12756 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
77241056
MM		 12757 dd->chip_send_contexts,
12758 dd->num_send_contexts,
12759 dd->sc_sizes[SC_KERNEL].count,
12760 dd->sc_sizes[SC_ACK].count,
44306f15
JX		 12761 dd->sc_sizes[SC_USER].count,
12762 dd->sc_sizes[SC_VL15].count);
77241056
MM		 12763 ret = 0; /* success */
12764 }
12765
12766 return ret;
12767}
12768
12769/*
12770 * Set the device/port partition key table. The MAD code
12771 * will ensure that, at least, the partial management
12772 * partition key is present in the table.
12773 */
12774static void set_partition_keys(struct hfi1_pportdata *ppd)
12775{
12776 struct hfi1_devdata *dd = ppd->dd;
12777 u64 reg = 0;
12778 int i;
12779
12780 dd_dev_info(dd, "Setting partition keys\n");
12781 for (i = 0; i < hfi1_get_npkeys(dd); i++) {
12782 reg |= (ppd->pkeys[i] &
12783 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
12784 ((i % 4) *
12785 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
12786 /* Each register holds 4 PKey values. */
12787 if ((i % 4) == 3) {
12788 write_csr(dd, RCV_PARTITION_KEY +
12789 ((i - 3) * 2), reg);
12790 reg = 0;
12791 }
12792 }
12793
12794 /* Always enable HW pkeys check when pkeys table is set */
12795 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
12796}
12797
12798/*
12799 * These CSRs and memories are uninitialized on reset and must be
12800 * written before reading to set the ECC/parity bits.
12801 *
12802 * NOTE: All user context CSRs that are not mmaped write-only
12803 * (e.g. the TID flows) must be initialized even if the driver never
12804 * reads them.
12805 */
12806static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
12807{
12808 int i, j;
12809
12810 /* CceIntMap */
12811 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 12812 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 12813
12814 /* SendCtxtCreditReturnAddr */
12815 for (i = 0; i < dd->chip_send_contexts; i++)
12816 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
12817
12818 /* PIO Send buffers */
12819 /* SDMA Send buffers */
4d114fdd
JJ		 12820 /*
12821 * These are not normally read, and (presently) have no method
12822 * to be read, so are not pre-initialized
12823 */
77241056
MM		 12824
12825 /* RcvHdrAddr */
12826 /* RcvHdrTailAddr */
12827 /* RcvTidFlowTable */
12828 for (i = 0; i < dd->chip_rcv_contexts; i++) {
12829 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
12830 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
12831 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
8638b77f 12832 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
77241056
MM		 12833 }
12834
12835 /* RcvArray */
12836 for (i = 0; i < dd->chip_rcv_array_count; i++)
8638b77f 12837 write_csr(dd, RCV_ARRAY + (8 * i),
17fb4f29 12838 RCV_ARRAY_RT_WRITE_ENABLE_SMASK);
77241056
MM		 12839
12840 /* RcvQPMapTable */
12841 for (i = 0; i < 32; i++)
12842 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
12843}
12844
12845/*
12846 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
12847 */
12848static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
12849 u64 ctrl_bits)
12850{
12851 unsigned long timeout;
12852 u64 reg;
12853
12854 /* is the condition present? */
12855 reg = read_csr(dd, CCE_STATUS);
12856 if ((reg & status_bits) == 0)
12857 return;
12858
12859 /* clear the condition */
12860 write_csr(dd, CCE_CTRL, ctrl_bits);
12861
12862 /* wait for the condition to clear */
12863 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
12864 while (1) {
12865 reg = read_csr(dd, CCE_STATUS);
12866 if ((reg & status_bits) == 0)
12867 return;
12868 if (time_after(jiffies, timeout)) {
12869 dd_dev_err(dd,
17fb4f29
JJ		 12870 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
12871 status_bits, reg & status_bits);
77241056
MM		 12872 return;
12873 }
12874 udelay(1);
12875 }
12876}
12877
12878/* set CCE CSRs to chip reset defaults */
12879static void reset_cce_csrs(struct hfi1_devdata *dd)
12880{
12881 int i;
12882
12883 /* CCE_REVISION read-only */
12884 /* CCE_REVISION2 read-only */
12885 /* CCE_CTRL - bits clear automatically */
12886 /* CCE_STATUS read-only, use CceCtrl to clear */
12887 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
12888 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
12889 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
12890 for (i = 0; i < CCE_NUM_SCRATCH; i++)
12891 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
12892 /* CCE_ERR_STATUS read-only */
12893 write_csr(dd, CCE_ERR_MASK, 0);
12894 write_csr(dd, CCE_ERR_CLEAR, ~0ull);
12895 /* CCE_ERR_FORCE leave alone */
12896 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
12897 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
12898 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
12899 /* CCE_PCIE_CTRL leave alone */
12900 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
12901 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
12902 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
17fb4f29 12903 CCE_MSIX_TABLE_UPPER_RESETCSR);
77241056
MM		 12904 }
12905 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
12906 /* CCE_MSIX_PBA read-only */
12907 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
12908 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
12909 }
12910 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
12911 write_csr(dd, CCE_INT_MAP, 0);
12912 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
12913 /* CCE_INT_STATUS read-only */
12914 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
12915 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
12916 /* CCE_INT_FORCE leave alone */
12917 /* CCE_INT_BLOCKED read-only */
12918 }
12919 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
12920 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
12921}
12922
77241056
MM		 12923/* set MISC CSRs to chip reset defaults */
12924static void reset_misc_csrs(struct hfi1_devdata *dd)
12925{
12926 int i;
12927
12928 for (i = 0; i < 32; i++) {
12929 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
12930 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
12931 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
12932 }
4d114fdd
JJ		 12933 /*
12934 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
12935 * only be written 128-byte chunks
12936 */
77241056
MM		 12937 /* init RSA engine to clear lingering errors */
12938 write_csr(dd, MISC_CFG_RSA_CMD, 1);
12939 write_csr(dd, MISC_CFG_RSA_MU, 0);
12940 write_csr(dd, MISC_CFG_FW_CTRL, 0);
12941 /* MISC_STS_8051_DIGEST read-only */
12942 /* MISC_STS_SBM_DIGEST read-only */
12943 /* MISC_STS_PCIE_DIGEST read-only */
12944 /* MISC_STS_FAB_DIGEST read-only */
12945 /* MISC_ERR_STATUS read-only */
12946 write_csr(dd, MISC_ERR_MASK, 0);
12947 write_csr(dd, MISC_ERR_CLEAR, ~0ull);
12948 /* MISC_ERR_FORCE leave alone */
12949}
12950
12951/* set TXE CSRs to chip reset defaults */
12952static void reset_txe_csrs(struct hfi1_devdata *dd)
12953{
12954 int i;
12955
12956 /*
12957 * TXE Kernel CSRs
12958 */
12959 write_csr(dd, SEND_CTRL, 0);
12960 __cm_reset(dd, 0); /* reset CM internal state */
12961 /* SEND_CONTEXTS read-only */
12962 /* SEND_DMA_ENGINES read-only */
12963 /* SEND_PIO_MEM_SIZE read-only */
12964 /* SEND_DMA_MEM_SIZE read-only */
12965 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
12966 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */
12967 /* SEND_PIO_ERR_STATUS read-only */
12968 write_csr(dd, SEND_PIO_ERR_MASK, 0);
12969 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
12970 /* SEND_PIO_ERR_FORCE leave alone */
12971 /* SEND_DMA_ERR_STATUS read-only */
12972 write_csr(dd, SEND_DMA_ERR_MASK, 0);
12973 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
12974 /* SEND_DMA_ERR_FORCE leave alone */
12975 /* SEND_EGRESS_ERR_STATUS read-only */
12976 write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
12977 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
12978 /* SEND_EGRESS_ERR_FORCE leave alone */
12979 write_csr(dd, SEND_BTH_QP, 0);
12980 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
12981 write_csr(dd, SEND_SC2VLT0, 0);
12982 write_csr(dd, SEND_SC2VLT1, 0);
12983 write_csr(dd, SEND_SC2VLT2, 0);
12984 write_csr(dd, SEND_SC2VLT3, 0);
12985 write_csr(dd, SEND_LEN_CHECK0, 0);
12986 write_csr(dd, SEND_LEN_CHECK1, 0);
12987 /* SEND_ERR_STATUS read-only */
12988 write_csr(dd, SEND_ERR_MASK, 0);
12989 write_csr(dd, SEND_ERR_CLEAR, ~0ull);
12990 /* SEND_ERR_FORCE read-only */
12991 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
8638b77f 12992 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
77241056 12993 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
8638b77f
JJ		 12994 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
12995 for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++)
12996 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
77241056 12997 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
8638b77f 12998 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
77241056 12999 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
8638b77f 13000 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
77241056 13001 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
17fb4f29 13002 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
77241056
MM		 13003 /* SEND_CM_CREDIT_USED_STATUS read-only */
13004 write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13005 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13006 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13007 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13008 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13009 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 13010 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056
MM		 13011 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13012 /* SEND_CM_CREDIT_USED_VL read-only */
13013 /* SEND_CM_CREDIT_USED_VL15 read-only */
13014 /* SEND_EGRESS_CTXT_STATUS read-only */
13015 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13016 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13017 /* SEND_EGRESS_ERR_INFO read-only */
13018 /* SEND_EGRESS_ERR_SOURCE read-only */
13019
13020 /*
13021 * TXE Per-Context CSRs
13022 */
13023 for (i = 0; i < dd->chip_send_contexts; i++) {
13024 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13025 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13026 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13027 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13028 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13029 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13030 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13031 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13032 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13033 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13034 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13035 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13036 }
13037
13038 /*
13039 * TXE Per-SDMA CSRs
13040 */
13041 for (i = 0; i < dd->chip_sdma_engines; i++) {
13042 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13043 /* SEND_DMA_STATUS read-only */
13044 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13045 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13046 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13047 /* SEND_DMA_HEAD read-only */
13048 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13049 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13050 /* SEND_DMA_IDLE_CNT read-only */
13051 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13052 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13053 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13054 /* SEND_DMA_ENG_ERR_STATUS read-only */
13055 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13056 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13057 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13058 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13059 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13060 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13061 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13062 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13063 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13064 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13065 }
13066}
13067
13068/*
13069 * Expect on entry:
13070 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13071 */
13072static void init_rbufs(struct hfi1_devdata *dd)
13073{
13074 u64 reg;
13075 int count;
13076
13077 /*
13078 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13079 * clear.
13080 */
13081 count = 0;
13082 while (1) {
13083 reg = read_csr(dd, RCV_STATUS);
13084 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13085 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13086 break;
13087 /*
13088 * Give up after 1ms - maximum wait time.
13089 *
13090 * RBuf size is 148KiB. Slowest possible is PCIe Gen1 x1 at
13091 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
13092 * 148 KB / (66% * 250MB/s) = 920us
13093 */
13094 if (count++ > 500) {
13095 dd_dev_err(dd,
17fb4f29
JJ		 13096 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13097 __func__, reg);
77241056
MM		 13098 break;
13099 }
13100 udelay(2); /* do not busy-wait the CSR */
13101 }
13102
13103 /* start the init - expect RcvCtrl to be 0 */
13104 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13105
13106 /*
13107 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13108 * period after the write before RcvStatus.RxRbufInitDone is valid.
13109 * The delay in the first run through the loop below is sufficient and
13110 * required before the first read of RcvStatus.RxRbufInintDone.
13111 */
13112 read_csr(dd, RCV_CTRL);
13113
13114 /* wait for the init to finish */
13115 count = 0;
13116 while (1) {
13117 /* delay is required first time through - see above */
13118 udelay(2); /* do not busy-wait the CSR */
13119 reg = read_csr(dd, RCV_STATUS);
13120 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13121 break;
13122
13123 /* give up after 100us - slowest possible at 33MHz is 73us */
13124 if (count++ > 50) {
13125 dd_dev_err(dd,
17fb4f29
JJ		 13126 "%s: RcvStatus.RxRbufInit not set, continuing\n",
13127 __func__);
77241056
MM		 13128 break;
13129 }
13130 }
13131}
13132
13133/* set RXE CSRs to chip reset defaults */
13134static void reset_rxe_csrs(struct hfi1_devdata *dd)
13135{
13136 int i, j;
13137
13138 /*
13139 * RXE Kernel CSRs
13140 */
13141 write_csr(dd, RCV_CTRL, 0);
13142 init_rbufs(dd);
13143 /* RCV_STATUS read-only */
13144 /* RCV_CONTEXTS read-only */
13145 /* RCV_ARRAY_CNT read-only */
13146 /* RCV_BUF_SIZE read-only */
13147 write_csr(dd, RCV_BTH_QP, 0);
13148 write_csr(dd, RCV_MULTICAST, 0);
13149 write_csr(dd, RCV_BYPASS, 0);
13150 write_csr(dd, RCV_VL15, 0);
13151 /* this is a clear-down */
13152 write_csr(dd, RCV_ERR_INFO,
17fb4f29 13153 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
77241056
MM		 13154 /* RCV_ERR_STATUS read-only */
13155 write_csr(dd, RCV_ERR_MASK, 0);
13156 write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13157 /* RCV_ERR_FORCE leave alone */
13158 for (i = 0; i < 32; i++)
13159 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13160 for (i = 0; i < 4; i++)
13161 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13162 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13163 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13164 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13165 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13166 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) {
13167 write_csr(dd, RCV_RSM_CFG + (8 * i), 0);
13168 write_csr(dd, RCV_RSM_SELECT + (8 * i), 0);
13169 write_csr(dd, RCV_RSM_MATCH + (8 * i), 0);
13170 }
13171 for (i = 0; i < 32; i++)
13172 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13173
13174 /*
13175 * RXE Kernel and User Per-Context CSRs
13176 */
13177 for (i = 0; i < dd->chip_rcv_contexts; i++) {
13178 /* kernel */
13179 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13180 /* RCV_CTXT_STATUS read-only */
13181 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13182 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13183 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13184 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13185 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13186 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13187 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13188 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13189 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13190 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13191
13192 /* user */
13193 /* RCV_HDR_TAIL read-only */
13194 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13195 /* RCV_EGR_INDEX_TAIL read-only */
13196 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13197 /* RCV_EGR_OFFSET_TAIL read-only */
13198 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
17fb4f29
JJ		 13199 write_uctxt_csr(dd, i,
13200 RCV_TID_FLOW_TABLE + (8 * j), 0);
77241056
MM		 13201 }
13202 }
13203}
13204
13205/*
13206 * Set sc2vl tables.
13207 *
13208 * They power on to zeros, so to avoid send context errors
13209 * they need to be set:
13210 *
13211 * SC 0-7 -> VL 0-7 (respectively)
13212 * SC 15 -> VL 15
13213 * otherwise
13214 * -> VL 0
13215 */
13216static void init_sc2vl_tables(struct hfi1_devdata *dd)
13217{
13218 int i;
13219 /* init per architecture spec, constrained by hardware capability */
13220
13221 /* HFI maps sent packets */
13222 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13223 0,
13224 0, 0, 1, 1,
13225 2, 2, 3, 3,
13226 4, 4, 5, 5,
13227 6, 6, 7, 7));
13228 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13229 1,
13230 8, 0, 9, 0,
13231 10, 0, 11, 0,
13232 12, 0, 13, 0,
13233 14, 0, 15, 15));
13234 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
13235 2,
13236 16, 0, 17, 0,
13237 18, 0, 19, 0,
13238 20, 0, 21, 0,
13239 22, 0, 23, 0));
13240 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
13241 3,
13242 24, 0, 25, 0,
13243 26, 0, 27, 0,
13244 28, 0, 29, 0,
13245 30, 0, 31, 0));
13246
13247 /* DC maps received packets */
13248 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
13249 15_0,
13250 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
13251 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
13252 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
13253 31_16,
13254 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
13255 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
13256
13257 /* initialize the cached sc2vl values consistently with h/w */
13258 for (i = 0; i < 32; i++) {
13259 if (i < 8 || i == 15)
13260 *((u8 *)(dd->sc2vl) + i) = (u8)i;
13261 else
13262 *((u8 *)(dd->sc2vl) + i) = 0;
13263 }
13264}
13265
13266/*
13267 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
13268 * depend on the chip going through a power-on reset - a driver may be loaded
13269 * and unloaded many times.
13270 *
13271 * Do not write any CSR values to the chip in this routine - there may be
13272 * a reset following the (possible) FLR in this routine.
13273 *
13274 */
13275static void init_chip(struct hfi1_devdata *dd)
13276{
13277 int i;
13278
13279 /*
13280 * Put the HFI CSRs in a known state.
13281 * Combine this with a DC reset.
13282 *
13283 * Stop the device from doing anything while we do a
13284 * reset. We know there are no other active users of
13285 * the device since we are now in charge. Turn off
13286 * off all outbound and inbound traffic and make sure
13287 * the device does not generate any interrupts.
13288 */
13289
13290 /* disable send contexts and SDMA engines */
13291 write_csr(dd, SEND_CTRL, 0);
13292 for (i = 0; i < dd->chip_send_contexts; i++)
13293 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13294 for (i = 0; i < dd->chip_sdma_engines; i++)
13295 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13296 /* disable port (turn off RXE inbound traffic) and contexts */
13297 write_csr(dd, RCV_CTRL, 0);
13298 for (i = 0; i < dd->chip_rcv_contexts; i++)
13299 write_csr(dd, RCV_CTXT_CTRL, 0);
13300 /* mask all interrupt sources */
13301 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 13302 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 13303
13304 /*
13305 * DC Reset: do a full DC reset before the register clear.
13306 * A recommended length of time to hold is one CSR read,
13307 * so reread the CceDcCtrl. Then, hold the DC in reset
13308 * across the clear.
13309 */
13310 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
50e5dcbe 13311 (void)read_csr(dd, CCE_DC_CTRL);
77241056
MM		 13312
13313 if (use_flr) {
13314 /*
13315 * A FLR will reset the SPC core and part of the PCIe.
13316 * The parts that need to be restored have already been
13317 * saved.
13318 */
13319 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13320
13321 /* do the FLR, the DC reset will remain */
13322 hfi1_pcie_flr(dd);
13323
13324 /* restore command and BARs */
13325 restore_pci_variables(dd);
13326
995deafa 13327 if (is_ax(dd)) {
77241056
MM		 13328 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13329 hfi1_pcie_flr(dd);
13330 restore_pci_variables(dd);
13331 }
77241056
MM		 13332 } else {
13333 dd_dev_info(dd, "Resetting CSRs with writes\n");
13334 reset_cce_csrs(dd);
13335 reset_txe_csrs(dd);
13336 reset_rxe_csrs(dd);
77241056
MM		 13337 reset_misc_csrs(dd);
13338 }
13339 /* clear the DC reset */
13340 write_csr(dd, CCE_DC_CTRL, 0);
7c03ed85 13341
77241056 13342 /* Set the LED off */
773d0451
SS		 13343 setextled(dd, 0);
13344
77241056
MM		 13345 /*
13346 * Clear the QSFP reset.
72a67ba2 13347 * An FLR enforces a 0 on all out pins. The driver does not touch
77241056 13348 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
72a67ba2 13349 * anything plugged constantly in reset, if it pays attention
77241056 13350 * to RESET_N.
72a67ba2 13351 * Prime examples of this are optical cables. Set all pins high.
77241056
MM		 13352 * I2CCLK and I2CDAT will change per direction, and INT_N and
13353 * MODPRS_N are input only and their value is ignored.
13354 */
72a67ba2
EH		 13355 write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
13356 write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
a2ee27a4 13357 init_chip_resources(dd);
77241056
MM		 13358}
13359
13360static void init_early_variables(struct hfi1_devdata *dd)
13361{
13362 int i;
13363
13364 /* assign link credit variables */
13365 dd->vau = CM_VAU;
13366 dd->link_credits = CM_GLOBAL_CREDITS;
995deafa 13367 if (is_ax(dd))
77241056
MM		 13368 dd->link_credits--;
13369 dd->vcu = cu_to_vcu(hfi1_cu);
13370 /* enough room for 8 MAD packets plus header - 17K */
13371 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
13372 if (dd->vl15_init > dd->link_credits)
13373 dd->vl15_init = dd->link_credits;
13374
13375 write_uninitialized_csrs_and_memories(dd);
13376
13377 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
13378 for (i = 0; i < dd->num_pports; i++) {
13379 struct hfi1_pportdata *ppd = &dd->pport[i];
13380
13381 set_partition_keys(ppd);
13382 }
13383 init_sc2vl_tables(dd);
13384}
13385
13386static void init_kdeth_qp(struct hfi1_devdata *dd)
13387{
13388 /* user changed the KDETH_QP */
13389 if (kdeth_qp != 0 && kdeth_qp >= 0xff) {
13390 /* out of range or illegal value */
13391 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring");
13392 kdeth_qp = 0;
13393 }
13394 if (kdeth_qp == 0) /* not set, or failed range check */
13395 kdeth_qp = DEFAULT_KDETH_QP;
13396
13397 write_csr(dd, SEND_BTH_QP,
17fb4f29
JJ		 13398 (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) <<
13399 SEND_BTH_QP_KDETH_QP_SHIFT);
77241056
MM		 13400
13401 write_csr(dd, RCV_BTH_QP,
17fb4f29
JJ		 13402 (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) <<
13403 RCV_BTH_QP_KDETH_QP_SHIFT);
77241056
MM		 13404}
13405
13406/**
13407 * init_qpmap_table
13408 * @dd - device data
13409 * @first_ctxt - first context
13410 * @last_ctxt - first context
13411 *
13412 * This return sets the qpn mapping table that
13413 * is indexed by qpn[8:1].
13414 *
13415 * The routine will round robin the 256 settings
13416 * from first_ctxt to last_ctxt.
13417 *
13418 * The first/last looks ahead to having specialized
13419 * receive contexts for mgmt and bypass. Normal
13420 * verbs traffic will assumed to be on a range
13421 * of receive contexts.
13422 */
13423static void init_qpmap_table(struct hfi1_devdata *dd,
13424 u32 first_ctxt,
13425 u32 last_ctxt)
13426{
13427 u64 reg = 0;
13428 u64 regno = RCV_QP_MAP_TABLE;
13429 int i;
13430 u64 ctxt = first_ctxt;
13431
60d585ad 13432 for (i = 0; i < 256; i++) {
77241056 13433 reg |= ctxt << (8 * (i % 8));
77241056
MM		 13434 ctxt++;
13435 if (ctxt > last_ctxt)
13436 ctxt = first_ctxt;
60d585ad 13437 if (i % 8 == 7) {
77241056
MM		 13438 write_csr(dd, regno, reg);
13439 reg = 0;
13440 regno += 8;
13441 }
13442 }
77241056
MM		 13443
13444 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
13445 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
13446}
13447
372cc85a
DL		 13448struct rsm_map_table {
13449 u64 map[NUM_MAP_REGS];
13450 unsigned int used;
13451};
13452
b12349ae
DL		 13453struct rsm_rule_data {
13454 u8 offset;
13455 u8 pkt_type;
13456 u32 field1_off;
13457 u32 field2_off;
13458 u32 index1_off;
13459 u32 index1_width;
13460 u32 index2_off;
13461 u32 index2_width;
13462 u32 mask1;
13463 u32 value1;
13464 u32 mask2;
13465 u32 value2;
13466};
13467
372cc85a
DL		 13468/*
13469 * Return an initialized RMT map table for users to fill in. OK if it
13470 * returns NULL, indicating no table.
13471 */
13472static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd)
13473{
13474 struct rsm_map_table *rmt;
13475 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */
13476
13477 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL);
13478 if (rmt) {
13479 memset(rmt->map, rxcontext, sizeof(rmt->map));
13480 rmt->used = 0;
13481 }
13482
13483 return rmt;
13484}
13485
13486/*
13487 * Write the final RMT map table to the chip and free the table. OK if
13488 * table is NULL.
13489 */
13490static void complete_rsm_map_table(struct hfi1_devdata *dd,
13491 struct rsm_map_table *rmt)
13492{
13493 int i;
13494
13495 if (rmt) {
13496 /* write table to chip */
13497 for (i = 0; i < NUM_MAP_REGS; i++)
13498 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
13499
13500 /* enable RSM */
13501 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
13502 }
13503}
13504
b12349ae
DL		 13505/*
13506 * Add a receive side mapping rule.
13507 */
13508static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index,
13509 struct rsm_rule_data *rrd)
13510{
13511 write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
13512 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT |
13513 1ull << rule_index | /* enable bit */
13514 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
13515 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
13516 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
13517 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
13518 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
13519 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
13520 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
13521 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
13522 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
13523 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT |
13524 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT |
13525 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT |
13526 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT);
13527}
13528
4a818bed
DL		 13529/* return the number of RSM map table entries that will be used for QOS */
13530static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
13531 unsigned int *np)
13532{
13533 int i;
13534 unsigned int m, n;
13535 u8 max_by_vl = 0;
13536
13537 /* is QOS active at all? */
13538 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
13539 num_vls == 1 ||
13540 krcvqsset <= 1)
13541 goto no_qos;
13542
13543 /* determine bits for qpn */
13544 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++)
13545 if (krcvqs[i] > max_by_vl)
13546 max_by_vl = krcvqs[i];
13547 if (max_by_vl > 32)
13548 goto no_qos;
13549 m = ilog2(__roundup_pow_of_two(max_by_vl));
13550
13551 /* determine bits for vl */
13552 n = ilog2(__roundup_pow_of_two(num_vls));
13553
13554 /* reject if too much is used */
13555 if ((m + n) > 7)
13556 goto no_qos;
13557
13558 if (mp)
13559 *mp = m;
13560 if (np)
13561 *np = n;
13562
13563 return 1 << (m + n);
13564
13565no_qos:
13566 if (mp)
13567 *mp = 0;
13568 if (np)
13569 *np = 0;
13570 return 0;
13571}
13572
77241056
MM		 13573/**
13574 * init_qos - init RX qos
13575 * @dd - device data
372cc85a 13576 * @rmt - RSM map table
77241056 13577 *
33a9eb52
DL		 13578 * This routine initializes Rule 0 and the RSM map table to implement
13579 * quality of service (qos).
77241056 13580 *
33a9eb52
DL		 13581 * If all of the limit tests succeed, qos is applied based on the array
13582 * interpretation of krcvqs where entry 0 is VL0.
77241056 13583 *
33a9eb52
DL		 13584 * The number of vl bits (n) and the number of qpn bits (m) are computed to
13585 * feed both the RSM map table and the single rule.
77241056 13586 */
372cc85a 13587static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt)
77241056 13588{
b12349ae 13589 struct rsm_rule_data rrd;
77241056 13590 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
372cc85a 13591 unsigned int rmt_entries;
77241056 13592 u64 reg;
77241056 13593
4a818bed 13594 if (!rmt)
77241056 13595 goto bail;
4a818bed
DL		 13596 rmt_entries = qos_rmt_entries(dd, &m, &n);
13597 if (rmt_entries == 0)
77241056 13598 goto bail;
4a818bed
DL		 13599 qpns_per_vl = 1 << m;
13600
372cc85a
DL		 13601 /* enough room in the map table? */
13602 rmt_entries = 1 << (m + n);
13603 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES)
859bcad9 13604 goto bail;
4a818bed 13605
372cc85a 13606 /* add qos entries to the the RSM map table */
33a9eb52 13607 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
77241056
MM		 13608 unsigned tctxt;
13609
13610 for (qpn = 0, tctxt = ctxt;
13611 krcvqs[i] && qpn < qpns_per_vl; qpn++) {
13612 unsigned idx, regoff, regidx;
13613
372cc85a
DL		 13614 /* generate the index the hardware will produce */
13615 idx = rmt->used + ((qpn << n) ^ i);
77241056
MM		 13616 regoff = (idx % 8) * 8;
13617 regidx = idx / 8;
372cc85a
DL		 13618 /* replace default with context number */
13619 reg = rmt->map[regidx];
77241056
MM		 13620 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
13621 << regoff);
13622 reg |= (u64)(tctxt++) << regoff;
372cc85a 13623 rmt->map[regidx] = reg;
77241056
MM		 13624 if (tctxt == ctxt + krcvqs[i])
13625 tctxt = ctxt;
13626 }
13627 ctxt += krcvqs[i];
13628 }
b12349ae
DL		 13629
13630 rrd.offset = rmt->used;
13631 rrd.pkt_type = 2;
13632 rrd.field1_off = LRH_BTH_MATCH_OFFSET;
13633 rrd.field2_off = LRH_SC_MATCH_OFFSET;
13634 rrd.index1_off = LRH_SC_SELECT_OFFSET;
13635 rrd.index1_width = n;
13636 rrd.index2_off = QPN_SELECT_OFFSET;
13637 rrd.index2_width = m + n;
13638 rrd.mask1 = LRH_BTH_MASK;
13639 rrd.value1 = LRH_BTH_VALUE;
13640 rrd.mask2 = LRH_SC_MASK;
13641 rrd.value2 = LRH_SC_VALUE;
13642
13643 /* add rule 0 */
13644 add_rsm_rule(dd, 0, &rrd);
13645
372cc85a
DL		 13646 /* mark RSM map entries as used */
13647 rmt->used += rmt_entries;
33a9eb52
DL		 13648 /* map everything else to the mcast/err/vl15 context */
13649 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT);
77241056
MM		 13650 dd->qos_shift = n + 1;
13651 return;
13652bail:
13653 dd->qos_shift = 1;
82c2611d 13654 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
77241056
MM		 13655}
13656
8f000f7f
DL		 13657static void init_user_fecn_handling(struct hfi1_devdata *dd,
13658 struct rsm_map_table *rmt)
13659{
13660 struct rsm_rule_data rrd;
13661 u64 reg;
13662 int i, idx, regoff, regidx;
13663 u8 offset;
13664
13665 /* there needs to be enough room in the map table */
13666 if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) {
13667 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n");
13668 return;
13669 }
13670
13671 /*
13672 * RSM will extract the destination context as an index into the
13673 * map table. The destination contexts are a sequential block
13674 * in the range first_user_ctxt...num_rcv_contexts-1 (inclusive).
13675 * Map entries are accessed as offset + extracted value. Adjust
13676 * the added offset so this sequence can be placed anywhere in
13677 * the table - as long as the entries themselves do not wrap.
13678 * There are only enough bits in offset for the table size, so
13679 * start with that to allow for a "negative" offset.
13680 */
13681 offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used -
13682 (int)dd->first_user_ctxt);
13683
13684 for (i = dd->first_user_ctxt, idx = rmt->used;
13685 i < dd->num_rcv_contexts; i++, idx++) {
13686 /* replace with identity mapping */
13687 regoff = (idx % 8) * 8;
13688 regidx = idx / 8;
13689 reg = rmt->map[regidx];
13690 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff);
13691 reg |= (u64)i << regoff;
13692 rmt->map[regidx] = reg;
13693 }
13694
13695 /*
13696 * For RSM intercept of Expected FECN packets:
13697 * o packet type 0 - expected
13698 * o match on F (bit 95), using select/match 1, and
13699 * o match on SH (bit 133), using select/match 2.
13700 *
13701 * Use index 1 to extract the 8-bit receive context from DestQP
13702 * (start at bit 64). Use that as the RSM map table index.
13703 */
13704 rrd.offset = offset;
13705 rrd.pkt_type = 0;
13706 rrd.field1_off = 95;
13707 rrd.field2_off = 133;
13708 rrd.index1_off = 64;
13709 rrd.index1_width = 8;
13710 rrd.index2_off = 0;
13711 rrd.index2_width = 0;
13712 rrd.mask1 = 1;
13713 rrd.value1 = 1;
13714 rrd.mask2 = 1;
13715 rrd.value2 = 1;
13716
13717 /* add rule 1 */
13718 add_rsm_rule(dd, 1, &rrd);
13719
13720 rmt->used += dd->num_user_contexts;
13721}
13722
77241056
MM		 13723static void init_rxe(struct hfi1_devdata *dd)
13724{
372cc85a
DL		 13725 struct rsm_map_table *rmt;
13726
77241056
MM		 13727 /* enable all receive errors */
13728 write_csr(dd, RCV_ERR_MASK, ~0ull);
372cc85a
DL		 13729
13730 rmt = alloc_rsm_map_table(dd);
13731 /* set up QOS, including the QPN map table */
13732 init_qos(dd, rmt);
8f000f7f 13733 init_user_fecn_handling(dd, rmt);
372cc85a
DL		 13734 complete_rsm_map_table(dd, rmt);
13735 kfree(rmt);
13736
77241056
MM		 13737 /*
13738 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
13739 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
13740 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
13741 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
13742 * Max_PayLoad_Size set to its minimum of 128.
13743 *
13744 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
13745 * (64 bytes). Max_Payload_Size is possibly modified upward in
13746 * tune_pcie_caps() which is called after this routine.
13747 */
13748}
13749
13750static void init_other(struct hfi1_devdata *dd)
13751{
13752 /* enable all CCE errors */
13753 write_csr(dd, CCE_ERR_MASK, ~0ull);
13754 /* enable *some* Misc errors */
13755 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
13756 /* enable all DC errors, except LCB */
13757 write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
13758 write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
13759}
13760
13761/*
13762 * Fill out the given AU table using the given CU. A CU is defined in terms
13763 * AUs. The table is a an encoding: given the index, how many AUs does that
13764 * represent?
13765 *
13766 * NOTE: Assumes that the register layout is the same for the
13767 * local and remote tables.
13768 */
13769static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
13770 u32 csr0to3, u32 csr4to7)
13771{
13772 write_csr(dd, csr0to3,
17fb4f29
JJ		 13773 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT |
13774 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT |
13775 2ull * cu <<
13776 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
13777 4ull * cu <<
13778 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
77241056 13779 write_csr(dd, csr4to7,
17fb4f29
JJ		 13780 8ull * cu <<
13781 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
13782 16ull * cu <<
13783 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
13784 32ull * cu <<
13785 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
13786 64ull * cu <<
13787 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
77241056
MM		 13788}
13789
13790static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
13791{
13792 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
17fb4f29 13793 SEND_CM_LOCAL_AU_TABLE4_TO7);
77241056
MM		 13794}
13795
13796void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
13797{
13798 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
17fb4f29 13799 SEND_CM_REMOTE_AU_TABLE4_TO7);
77241056
MM		 13800}
13801
13802static void init_txe(struct hfi1_devdata *dd)
13803{
13804 int i;
13805
13806 /* enable all PIO, SDMA, general, and Egress errors */
13807 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
13808 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
13809 write_csr(dd, SEND_ERR_MASK, ~0ull);
13810 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
13811
13812 /* enable all per-context and per-SDMA engine errors */
13813 for (i = 0; i < dd->chip_send_contexts; i++)
13814 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
13815 for (i = 0; i < dd->chip_sdma_engines; i++)
13816 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
13817
13818 /* set the local CU to AU mapping */
13819 assign_local_cm_au_table(dd, dd->vcu);
13820
13821 /*
13822 * Set reasonable default for Credit Return Timer
13823 * Don't set on Simulator - causes it to choke.
13824 */
13825 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
13826 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
13827}
13828
13829int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey)
13830{
13831 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
13832 unsigned sctxt;
13833 int ret = 0;
13834 u64 reg;
13835
13836 if (!rcd || !rcd->sc) {
13837 ret = -EINVAL;
13838 goto done;
13839 }
13840 sctxt = rcd->sc->hw_context;
13841 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
13842 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
13843 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
13844 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
13845 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
13846 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
13847 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
13848 /*
13849 * Enable send-side J_KEY integrity check, unless this is A0 h/w
77241056 13850 */
995deafa 13851 if (!is_ax(dd)) {
77241056
MM		 13852 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13853 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
13854 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13855 }
13856
13857 /* Enable J_KEY check on receive context. */
13858 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
13859 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
13860 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
13861 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, reg);
13862done:
13863 return ret;
13864}
13865
13866int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt)
13867{
13868 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
13869 unsigned sctxt;
13870 int ret = 0;
13871 u64 reg;
13872
13873 if (!rcd || !rcd->sc) {
13874 ret = -EINVAL;
13875 goto done;
13876 }
13877 sctxt = rcd->sc->hw_context;
13878 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
13879 /*
13880 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
13881 * This check would not have been enabled for A0 h/w, see
13882 * set_ctxt_jkey().
13883 */
995deafa 13884 if (!is_ax(dd)) {
77241056
MM		 13885 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13886 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
13887 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13888 }
13889 /* Turn off the J_KEY on the receive side */
13890 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, 0);
13891done:
13892 return ret;
13893}
13894
13895int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey)
13896{
13897 struct hfi1_ctxtdata *rcd;
13898 unsigned sctxt;
13899 int ret = 0;
13900 u64 reg;
13901
e490974e 13902 if (ctxt < dd->num_rcv_contexts) {
77241056 13903 rcd = dd->rcd[ctxt];
e490974e 13904 } else {
77241056
MM		 13905 ret = -EINVAL;
13906 goto done;
13907 }
13908 if (!rcd || !rcd->sc) {
13909 ret = -EINVAL;
13910 goto done;
13911 }
13912 sctxt = rcd->sc->hw_context;
13913 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
13914 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
13915 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
13916 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13917 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
e38d1e4f 13918 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK;
77241056
MM		 13919 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13920done:
13921 return ret;
13922}
13923
13924int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt)
13925{
13926 struct hfi1_ctxtdata *rcd;
13927 unsigned sctxt;
13928 int ret = 0;
13929 u64 reg;
13930
e490974e 13931 if (ctxt < dd->num_rcv_contexts) {
77241056 13932 rcd = dd->rcd[ctxt];
e490974e 13933 } else {
77241056
MM		 13934 ret = -EINVAL;
13935 goto done;
13936 }
13937 if (!rcd || !rcd->sc) {
13938 ret = -EINVAL;
13939 goto done;
13940 }
13941 sctxt = rcd->sc->hw_context;
13942 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13943 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
13944 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13945 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13946done:
13947 return ret;
13948}
13949
13950/*
13951 * Start doing the clean up the the chip. Our clean up happens in multiple
13952 * stages and this is just the first.
13953 */
13954void hfi1_start_cleanup(struct hfi1_devdata *dd)
13955{
affa48de 13956 aspm_exit(dd);
77241056
MM		 13957 free_cntrs(dd);
13958 free_rcverr(dd);
13959 clean_up_interrupts(dd);
a2ee27a4 13960 finish_chip_resources(dd);
77241056
MM		 13961}
13962
13963#define HFI_BASE_GUID(dev) \
13964 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
13965
13966/*
78eb129d
DL		 13967 * Information can be shared between the two HFIs on the same ASIC
13968 * in the same OS. This function finds the peer device and sets
13969 * up a shared structure.
77241056 13970 */
78eb129d 13971static int init_asic_data(struct hfi1_devdata *dd)
77241056
MM		 13972{
13973 unsigned long flags;
13974 struct hfi1_devdata *tmp, *peer = NULL;
78eb129d 13975 int ret = 0;
77241056
MM		 13976
13977 spin_lock_irqsave(&hfi1_devs_lock, flags);
13978 /* Find our peer device */
13979 list_for_each_entry(tmp, &hfi1_dev_list, list) {
13980 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) &&
13981 dd->unit != tmp->unit) {
13982 peer = tmp;
13983 break;
13984 }
13985 }
13986
78eb129d
DL		 13987 if (peer) {
13988 dd->asic_data = peer->asic_data;
13989 } else {
13990 dd->asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL);
13991 if (!dd->asic_data) {
13992 ret = -ENOMEM;
13993 goto done;
13994 }
13995 mutex_init(&dd->asic_data->asic_resource_mutex);
13996 }
13997 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */
13998
13999done:
77241056 14000 spin_unlock_irqrestore(&hfi1_devs_lock, flags);
78eb129d 14001 return ret;
77241056
MM		 14002}
14003
5d9157aa
DL		 14004/*
14005 * Set dd->boardname. Use a generic name if a name is not returned from
14006 * EFI variable space.
14007 *
14008 * Return 0 on success, -ENOMEM if space could not be allocated.
14009 */
14010static int obtain_boardname(struct hfi1_devdata *dd)
14011{
14012 /* generic board description */
14013 const char generic[] =
14014 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
14015 unsigned long size;
14016 int ret;
14017
14018 ret = read_hfi1_efi_var(dd, "description", &size,
14019 (void **)&dd->boardname);
14020 if (ret) {
845f876d 14021 dd_dev_info(dd, "Board description not found\n");
5d9157aa
DL		 14022 /* use generic description */
14023 dd->boardname = kstrdup(generic, GFP_KERNEL);
14024 if (!dd->boardname)
14025 return -ENOMEM;
14026 }
14027 return 0;
14028}
14029
24487dd3
KW		 14030/*
14031 * Check the interrupt registers to make sure that they are mapped correctly.
14032 * It is intended to help user identify any mismapping by VMM when the driver
14033 * is running in a VM. This function should only be called before interrupt
14034 * is set up properly.
14035 *
14036 * Return 0 on success, -EINVAL on failure.
14037 */
14038static int check_int_registers(struct hfi1_devdata *dd)
14039{
14040 u64 reg;
14041 u64 all_bits = ~(u64)0;
14042 u64 mask;
14043
14044 /* Clear CceIntMask[0] to avoid raising any interrupts */
14045 mask = read_csr(dd, CCE_INT_MASK);
14046 write_csr(dd, CCE_INT_MASK, 0ull);
14047 reg = read_csr(dd, CCE_INT_MASK);
14048 if (reg)
14049 goto err_exit;
14050
14051 /* Clear all interrupt status bits */
14052 write_csr(dd, CCE_INT_CLEAR, all_bits);
14053 reg = read_csr(dd, CCE_INT_STATUS);
14054 if (reg)
14055 goto err_exit;
14056
14057 /* Set all interrupt status bits */
14058 write_csr(dd, CCE_INT_FORCE, all_bits);
14059 reg = read_csr(dd, CCE_INT_STATUS);
14060 if (reg != all_bits)
14061 goto err_exit;
14062
14063 /* Restore the interrupt mask */
14064 write_csr(dd, CCE_INT_CLEAR, all_bits);
14065 write_csr(dd, CCE_INT_MASK, mask);
14066
14067 return 0;
14068err_exit:
14069 write_csr(dd, CCE_INT_MASK, mask);
14070 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n");
14071 return -EINVAL;
14072}
14073
77241056 14074/**
7c03ed85 14075 * Allocate and initialize the device structure for the hfi.
77241056
MM		 14076 * @dev: the pci_dev for hfi1_ib device
14077 * @ent: pci_device_id struct for this dev
14078 *
14079 * Also allocates, initializes, and returns the devdata struct for this
14080 * device instance
14081 *
14082 * This is global, and is called directly at init to set up the
14083 * chip-specific function pointers for later use.
14084 */
14085struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
14086 const struct pci_device_id *ent)
14087{
14088 struct hfi1_devdata *dd;
14089 struct hfi1_pportdata *ppd;
14090 u64 reg;
14091 int i, ret;
14092 static const char * const inames[] = { /* implementation names */
14093 "RTL silicon",
14094 "RTL VCS simulation",
14095 "RTL FPGA emulation",
14096 "Functional simulator"
14097 };
24487dd3 14098 struct pci_dev *parent = pdev->bus->self;
77241056 14099
17fb4f29
JJ		 14100 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
14101 sizeof(struct hfi1_pportdata));
77241056
MM		 14102 if (IS_ERR(dd))
14103 goto bail;
14104 ppd = dd->pport;
14105 for (i = 0; i < dd->num_pports; i++, ppd++) {
14106 int vl;
14107 /* init common fields */
14108 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
14109 /* DC supports 4 link widths */
14110 ppd->link_width_supported =
14111 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
14112 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
14113 ppd->link_width_downgrade_supported =
14114 ppd->link_width_supported;
14115 /* start out enabling only 4X */
14116 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
14117 ppd->link_width_downgrade_enabled =
14118 ppd->link_width_downgrade_supported;
14119 /* link width active is 0 when link is down */
14120 /* link width downgrade active is 0 when link is down */
14121
d0d236ea
JJ		 14122 if (num_vls < HFI1_MIN_VLS_SUPPORTED ||
14123 num_vls > HFI1_MAX_VLS_SUPPORTED) {
77241056
MM		 14124 hfi1_early_err(&pdev->dev,
14125 "Invalid num_vls %u, using %u VLs\n",
14126 num_vls, HFI1_MAX_VLS_SUPPORTED);
14127 num_vls = HFI1_MAX_VLS_SUPPORTED;
14128 }
14129 ppd->vls_supported = num_vls;
14130 ppd->vls_operational = ppd->vls_supported;
8a4d3444 14131 ppd->actual_vls_operational = ppd->vls_supported;
77241056
MM		 14132 /* Set the default MTU. */
14133 for (vl = 0; vl < num_vls; vl++)
14134 dd->vld[vl].mtu = hfi1_max_mtu;
14135 dd->vld[15].mtu = MAX_MAD_PACKET;
14136 /*
14137 * Set the initial values to reasonable default, will be set
14138 * for real when link is up.
14139 */
14140 ppd->lstate = IB_PORT_DOWN;
14141 ppd->overrun_threshold = 0x4;
14142 ppd->phy_error_threshold = 0xf;
14143 ppd->port_crc_mode_enabled = link_crc_mask;
14144 /* initialize supported LTP CRC mode */
14145 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
14146 /* initialize enabled LTP CRC mode */
14147 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
14148 /* start in offline */
14149 ppd->host_link_state = HLS_DN_OFFLINE;
14150 init_vl_arb_caches(ppd);
f45c8dc8 14151 ppd->last_pstate = 0xff; /* invalid value */
77241056
MM		 14152 }
14153
14154 dd->link_default = HLS_DN_POLL;
14155
14156 /*
14157 * Do remaining PCIe setup and save PCIe values in dd.
14158 * Any error printing is already done by the init code.
14159 * On return, we have the chip mapped.
14160 */
14161 ret = hfi1_pcie_ddinit(dd, pdev, ent);
14162 if (ret < 0)
14163 goto bail_free;
14164
14165 /* verify that reads actually work, save revision for reset check */
14166 dd->revision = read_csr(dd, CCE_REVISION);
14167 if (dd->revision == ~(u64)0) {
14168 dd_dev_err(dd, "cannot read chip CSRs\n");
14169 ret = -EINVAL;
14170 goto bail_cleanup;
14171 }
14172 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
14173 & CCE_REVISION_CHIP_REV_MAJOR_MASK;
14174 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
14175 & CCE_REVISION_CHIP_REV_MINOR_MASK;
14176
24487dd3
KW		 14177 /*
14178 * Check interrupt registers mapping if the driver has no access to
14179 * the upstream component. In this case, it is likely that the driver
14180 * is running in a VM.
14181 */
14182 if (!parent) {
14183 ret = check_int_registers(dd);
14184 if (ret)
14185 goto bail_cleanup;
14186 }
14187
4d114fdd
JJ		 14188 /*
14189 * obtain the hardware ID - NOT related to unit, which is a
14190 * software enumeration
14191 */
77241056
MM		 14192 reg = read_csr(dd, CCE_REVISION2);
14193 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
14194 & CCE_REVISION2_HFI_ID_MASK;
14195 /* the variable size will remove unwanted bits */
14196 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
14197 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
14198 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
17fb4f29
JJ		 14199 dd->icode < ARRAY_SIZE(inames) ?
14200 inames[dd->icode] : "unknown", (int)dd->irev);
77241056
MM		 14201
14202 /* speeds the hardware can support */
14203 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
14204 /* speeds allowed to run at */
14205 dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
14206 /* give a reasonable active value, will be set on link up */
14207 dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
14208
14209 dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);
14210 dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);
14211 dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);
14212 dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);
14213 dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);
14214 /* fix up link widths for emulation _p */
14215 ppd = dd->pport;
14216 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
14217 ppd->link_width_supported =
14218 ppd->link_width_enabled =
14219 ppd->link_width_downgrade_supported =
14220 ppd->link_width_downgrade_enabled =
14221 OPA_LINK_WIDTH_1X;
14222 }
14223 /* insure num_vls isn't larger than number of sdma engines */
14224 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
14225 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
11a5909b
DL		 14226 num_vls, dd->chip_sdma_engines);
14227 num_vls = dd->chip_sdma_engines;
14228 ppd->vls_supported = dd->chip_sdma_engines;
8a4d3444 14229 ppd->vls_operational = ppd->vls_supported;
77241056
MM		 14230 }
14231
14232 /*
14233 * Convert the ns parameter to the 64 * cclocks used in the CSR.
14234 * Limit the max if larger than the field holds. If timeout is
14235 * non-zero, then the calculated field will be at least 1.
14236 *
14237 * Must be after icode is set up - the cclock rate depends
14238 * on knowing the hardware being used.
14239 */
14240 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
14241 if (dd->rcv_intr_timeout_csr >
14242 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
14243 dd->rcv_intr_timeout_csr =
14244 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
14245 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
14246 dd->rcv_intr_timeout_csr = 1;
14247
7c03ed85
EH		 14248 /* needs to be done before we look for the peer device */
14249 read_guid(dd);
14250
78eb129d
DL		 14251 /* set up shared ASIC data with peer device */
14252 ret = init_asic_data(dd);
14253 if (ret)
14254 goto bail_cleanup;
7c03ed85 14255
77241056
MM		 14256 /* obtain chip sizes, reset chip CSRs */
14257 init_chip(dd);
14258
14259 /* read in the PCIe link speed information */
14260 ret = pcie_speeds(dd);
14261 if (ret)
14262 goto bail_cleanup;
14263
c3838b39
EH		 14264 /* Needs to be called before hfi1_firmware_init */
14265 get_platform_config(dd);
14266
77241056
MM		 14267 /* read in firmware */
14268 ret = hfi1_firmware_init(dd);
14269 if (ret)
14270 goto bail_cleanup;
14271
14272 /*
14273 * In general, the PCIe Gen3 transition must occur after the
14274 * chip has been idled (so it won't initiate any PCIe transactions
14275 * e.g. an interrupt) and before the driver changes any registers
14276 * (the transition will reset the registers).
14277 *
14278 * In particular, place this call after:
14279 * - init_chip() - the chip will not initiate any PCIe transactions
14280 * - pcie_speeds() - reads the current link speed
14281 * - hfi1_firmware_init() - the needed firmware is ready to be
14282 * downloaded
14283 */
14284 ret = do_pcie_gen3_transition(dd);
14285 if (ret)
14286 goto bail_cleanup;
14287
14288 /* start setting dd values and adjusting CSRs */
14289 init_early_variables(dd);
14290
14291 parse_platform_config(dd);
14292
5d9157aa
DL		 14293 ret = obtain_boardname(dd);
14294 if (ret)
77241056 14295 goto bail_cleanup;
77241056
MM		 14296
14297 snprintf(dd->boardversion, BOARD_VERS_MAX,
5d9157aa 14298 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
77241056 14299 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
77241056
MM		 14300 (u32)dd->majrev,
14301 (u32)dd->minrev,
14302 (dd->revision >> CCE_REVISION_SW_SHIFT)
14303 & CCE_REVISION_SW_MASK);
14304
0852d241
JJ		 14305 /*
14306 * The real cpu mask is part of the affinity struct but has to be
14307 * initialized earlier than the rest of the affinity struct because it
14308 * is needed to calculate the number of user contexts in
14309 * set_up_context_variables(). However, hfi1_dev_affinity_init(),
14310 * which initializes the rest of the affinity struct members,
14311 * depends on set_up_context_variables() for the number of kernel
14312 * contexts, so it cannot be called before set_up_context_variables().
14313 */
14314 ret = init_real_cpu_mask(dd);
14315 if (ret)
14316 goto bail_cleanup;
14317
77241056
MM		 14318 ret = set_up_context_variables(dd);
14319 if (ret)
14320 goto bail_cleanup;
14321
14322 /* set initial RXE CSRs */
14323 init_rxe(dd);
14324 /* set initial TXE CSRs */
14325 init_txe(dd);
14326 /* set initial non-RXE, non-TXE CSRs */
14327 init_other(dd);
14328 /* set up KDETH QP prefix in both RX and TX CSRs */
14329 init_kdeth_qp(dd);
14330
0852d241 14331 hfi1_dev_affinity_init(dd);
957558c9 14332
77241056
MM		 14333 /* send contexts must be set up before receive contexts */
14334 ret = init_send_contexts(dd);
14335 if (ret)
14336 goto bail_cleanup;
14337
14338 ret = hfi1_create_ctxts(dd);
14339 if (ret)
14340 goto bail_cleanup;
14341
14342 dd->rcvhdrsize = DEFAULT_RCVHDRSIZE;
14343 /*
14344 * rcd[0] is guaranteed to be valid by this point. Also, all
14345 * context are using the same value, as per the module parameter.
14346 */
14347 dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
14348
14349 ret = init_pervl_scs(dd);
14350 if (ret)
14351 goto bail_cleanup;
14352
14353 /* sdma init */
14354 for (i = 0; i < dd->num_pports; ++i) {
14355 ret = sdma_init(dd, i);
14356 if (ret)
14357 goto bail_cleanup;
14358 }
14359
14360 /* use contexts created by hfi1_create_ctxts */
14361 ret = set_up_interrupts(dd);
14362 if (ret)
14363 goto bail_cleanup;
14364
14365 /* set up LCB access - must be after set_up_interrupts() */
14366 init_lcb_access(dd);
14367
14368 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
14369 dd->base_guid & 0xFFFFFF);
14370
14371 dd->oui1 = dd->base_guid >> 56 & 0xFF;
14372 dd->oui2 = dd->base_guid >> 48 & 0xFF;
14373 dd->oui3 = dd->base_guid >> 40 & 0xFF;
14374
14375 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
14376 if (ret)
14377 goto bail_clear_intr;
14378 check_fabric_firmware_versions(dd);
14379
14380 thermal_init(dd);
14381
14382 ret = init_cntrs(dd);
14383 if (ret)
14384 goto bail_clear_intr;
14385
14386 ret = init_rcverr(dd);
14387 if (ret)
14388 goto bail_free_cntrs;
14389
14390 ret = eprom_init(dd);
14391 if (ret)
14392 goto bail_free_rcverr;
14393
14394 goto bail;
14395
14396bail_free_rcverr:
14397 free_rcverr(dd);
14398bail_free_cntrs:
14399 free_cntrs(dd);
14400bail_clear_intr:
14401 clean_up_interrupts(dd);
14402bail_cleanup:
14403 hfi1_pcie_ddcleanup(dd);
14404bail_free:
14405 hfi1_free_devdata(dd);
14406 dd = ERR_PTR(ret);
14407bail:
14408 return dd;
14409}
14410
14411static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
14412 u32 dw_len)
14413{
14414 u32 delta_cycles;
14415 u32 current_egress_rate = ppd->current_egress_rate;
14416 /* rates here are in units of 10^6 bits/sec */
14417
14418 if (desired_egress_rate == -1)
14419 return 0; /* shouldn't happen */
14420
14421 if (desired_egress_rate >= current_egress_rate)
14422 return 0; /* we can't help go faster, only slower */
14423
14424 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
14425 egress_cycles(dw_len * 4, current_egress_rate);
14426
14427 return (u16)delta_cycles;
14428}
14429
77241056
MM		 14430/**
14431 * create_pbc - build a pbc for transmission
14432 * @flags: special case flags or-ed in built pbc
14433 * @srate: static rate
14434 * @vl: vl
14435 * @dwlen: dword length (header words + data words + pbc words)
14436 *
14437 * Create a PBC with the given flags, rate, VL, and length.
14438 *
14439 * NOTE: The PBC created will not insert any HCRC - all callers but one are
14440 * for verbs, which does not use this PSM feature. The lone other caller
14441 * is for the diagnostic interface which calls this if the user does not
14442 * supply their own PBC.
14443 */
14444u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
14445 u32 dw_len)
14446{
14447 u64 pbc, delay = 0;
14448
14449 if (unlikely(srate_mbs))
14450 delay = delay_cycles(ppd, srate_mbs, dw_len);
14451
14452 pbc = flags
14453 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
14454 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
14455 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
14456 | (dw_len & PBC_LENGTH_DWS_MASK)
14457 << PBC_LENGTH_DWS_SHIFT;
14458
14459 return pbc;
14460}
14461
14462#define SBUS_THERMAL 0x4f
14463#define SBUS_THERM_MONITOR_MODE 0x1
14464
14465#define THERM_FAILURE(dev, ret, reason) \
14466 dd_dev_err((dd), \
14467 "Thermal sensor initialization failed: %s (%d)\n", \
14468 (reason), (ret))
14469
14470/*
14471 * Initialize the Avago Thermal sensor.
14472 *
14473 * After initialization, enable polling of thermal sensor through
14474 * SBus interface. In order for this to work, the SBus Master
14475 * firmware has to be loaded due to the fact that the HW polling
14476 * logic uses SBus interrupts, which are not supported with
14477 * default firmware. Otherwise, no data will be returned through
14478 * the ASIC_STS_THERM CSR.
14479 */
14480static int thermal_init(struct hfi1_devdata *dd)
14481{
14482 int ret = 0;
14483
14484 if (dd->icode != ICODE_RTL_SILICON ||
a453698b 14485 check_chip_resource(dd, CR_THERM_INIT, NULL))
77241056
MM		 14486 return ret;
14487
576531fd
DL		 14488 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
14489 if (ret) {
14490 THERM_FAILURE(dd, ret, "Acquire SBus");
14491 return ret;
14492 }
14493
77241056 14494 dd_dev_info(dd, "Initializing thermal sensor\n");
4ef98989
JAQ		 14495 /* Disable polling of thermal readings */
14496 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
14497 msleep(100);
77241056
MM		 14498 /* Thermal Sensor Initialization */
14499 /* Step 1: Reset the Thermal SBus Receiver */
14500 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14501 RESET_SBUS_RECEIVER, 0);
14502 if (ret) {
14503 THERM_FAILURE(dd, ret, "Bus Reset");
14504 goto done;
14505 }
14506 /* Step 2: Set Reset bit in Thermal block */
14507 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14508 WRITE_SBUS_RECEIVER, 0x1);
14509 if (ret) {
14510 THERM_FAILURE(dd, ret, "Therm Block Reset");
14511 goto done;
14512 }
14513 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
14514 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
14515 WRITE_SBUS_RECEIVER, 0x32);
14516 if (ret) {
14517 THERM_FAILURE(dd, ret, "Write Clock Div");
14518 goto done;
14519 }
14520 /* Step 4: Select temperature mode */
14521 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
14522 WRITE_SBUS_RECEIVER,
14523 SBUS_THERM_MONITOR_MODE);
14524 if (ret) {
14525 THERM_FAILURE(dd, ret, "Write Mode Sel");
14526 goto done;
14527 }
14528 /* Step 5: De-assert block reset and start conversion */
14529 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14530 WRITE_SBUS_RECEIVER, 0x2);
14531 if (ret) {
14532 THERM_FAILURE(dd, ret, "Write Reset Deassert");
14533 goto done;
14534 }
14535 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
14536 msleep(22);
14537
14538 /* Enable polling of thermal readings */
14539 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
a453698b
DL		 14540
14541 /* Set initialized flag */
14542 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0);
14543 if (ret)
14544 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");
14545
77241056 14546done:
576531fd 14547 release_chip_resource(dd, CR_SBUS);
77241056
MM		 14548 return ret;
14549}
14550
14551static void handle_temp_err(struct hfi1_devdata *dd)
14552{
14553 struct hfi1_pportdata *ppd = &dd->pport[0];
14554 /*
14555 * Thermal Critical Interrupt
14556 * Put the device into forced freeze mode, take link down to
14557 * offline, and put DC into reset.
14558 */
14559 dd_dev_emerg(dd,
14560 "Critical temperature reached! Forcing device into freeze mode!\n");
14561 dd->flags |= HFI1_FORCED_FREEZE;
8638b77f 14562 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
77241056
MM		 14563 /*
14564 * Shut DC down as much and as quickly as possible.
14565 *
14566 * Step 1: Take the link down to OFFLINE. This will cause the
14567 * 8051 to put the Serdes in reset. However, we don't want to
14568 * go through the entire link state machine since we want to
14569 * shutdown ASAP. Furthermore, this is not a graceful shutdown
14570 * but rather an attempt to save the chip.
14571 * Code below is almost the same as quiet_serdes() but avoids
14572 * all the extra work and the sleeps.
14573 */
14574 ppd->driver_link_ready = 0;
14575 ppd->link_enabled = 0;
bf640096
HC		 14576 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) |
14577 PLS_OFFLINE);
77241056
MM		 14578 /*
14579 * Step 2: Shutdown LCB and 8051
14580 * After shutdown, do not restore DC_CFG_RESET value.
14581 */
14582 dc_shutdown(dd);
14583}
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