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77241056
MM		 1/*
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2015 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2015 Intel Corporation.
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 *
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
32 * distribution.
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 */
50
51#include <linux/spinlock.h>
52#include <linux/seqlock.h>
53#include <linux/netdevice.h>
54#include <linux/moduleparam.h>
55#include <linux/bitops.h>
56#include <linux/timer.h>
57#include <linux/vmalloc.h>
f4d26d81 58#include <linux/highmem.h>
77241056
MM		 59
60#include "hfi.h"
61#include "common.h"
62#include "qp.h"
63#include "sdma.h"
64#include "iowait.h"
65#include "trace.h"
66
67/* must be a power of 2 >= 64 <= 32768 */
028d7254 68#define SDMA_DESCQ_CNT 2048
ee947859 69#define SDMA_DESC_INTR 64
77241056
MM		 70#define INVALID_TAIL 0xffff
71
72static uint sdma_descq_cnt = SDMA_DESCQ_CNT;
73module_param(sdma_descq_cnt, uint, S_IRUGO);
74MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries");
75
76static uint sdma_idle_cnt = 250;
77module_param(sdma_idle_cnt, uint, S_IRUGO);
78MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)");
79
80uint mod_num_sdma;
81module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO);
82MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");
83
ee947859
MH		 84static uint sdma_desct_intr = SDMA_DESC_INTR;
85module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR);
86MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");
87
77241056
MM		 88#define SDMA_WAIT_BATCH_SIZE 20
89/* max wait time for a SDMA engine to indicate it has halted */
90#define SDMA_ERR_HALT_TIMEOUT 10 /* ms */
91/* all SDMA engine errors that cause a halt */
92
93#define SD(name) SEND_DMA_##name
94#define ALL_SDMA_ENG_HALT_ERRS \
95 (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \
96 | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \
97 | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \
98 | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \
99 | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \
100 | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \
101 | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \
102 | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \
103 | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \
104 | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \
105 | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \
106 | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \
107 | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \
108 | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \
109 | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \
110 | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \
111 | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \
112 | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK))
113
114/* sdma_sendctrl operations */
349ac71f 115#define SDMA_SENDCTRL_OP_ENABLE BIT(0)
116#define SDMA_SENDCTRL_OP_INTENABLE BIT(1)
117#define SDMA_SENDCTRL_OP_HALT BIT(2)
118#define SDMA_SENDCTRL_OP_CLEANUP BIT(3)
77241056
MM		 119
120/* handle long defines */
121#define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \
122SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK
123#define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \
124SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT
125
126static const char * const sdma_state_names[] = {
127 [sdma_state_s00_hw_down] = "s00_HwDown",
128 [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait",
129 [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait",
130 [sdma_state_s20_idle] = "s20_Idle",
131 [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait",
132 [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait",
133 [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait",
134 [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait",
135 [sdma_state_s80_hw_freeze] = "s80_HwFreeze",
136 [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean",
137 [sdma_state_s99_running] = "s99_Running",
138};
139
140static const char * const sdma_event_names[] = {
141 [sdma_event_e00_go_hw_down] = "e00_GoHwDown",
142 [sdma_event_e10_go_hw_start] = "e10_GoHwStart",
143 [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone",
144 [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone",
145 [sdma_event_e30_go_running] = "e30_GoRunning",
146 [sdma_event_e40_sw_cleaned] = "e40_SwCleaned",
147 [sdma_event_e50_hw_cleaned] = "e50_HwCleaned",
148 [sdma_event_e60_hw_halted] = "e60_HwHalted",
149 [sdma_event_e70_go_idle] = "e70_GoIdle",
150 [sdma_event_e80_hw_freeze] = "e80_HwFreeze",
151 [sdma_event_e81_hw_frozen] = "e81_HwFrozen",
152 [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze",
153 [sdma_event_e85_link_down] = "e85_LinkDown",
154 [sdma_event_e90_sw_halted] = "e90_SwHalted",
155};
156
157static const struct sdma_set_state_action sdma_action_table[] = {
158 [sdma_state_s00_hw_down] = {
159 .go_s99_running_tofalse = 1,
160 .op_enable = 0,
161 .op_intenable = 0,
162 .op_halt = 0,
163 .op_cleanup = 0,
164 },
165 [sdma_state_s10_hw_start_up_halt_wait] = {
166 .op_enable = 0,
167 .op_intenable = 0,
168 .op_halt = 1,
169 .op_cleanup = 0,
170 },
171 [sdma_state_s15_hw_start_up_clean_wait] = {
172 .op_enable = 0,
173 .op_intenable = 1,
174 .op_halt = 0,
175 .op_cleanup = 1,
176 },
177 [sdma_state_s20_idle] = {
178 .op_enable = 0,
179 .op_intenable = 1,
180 .op_halt = 0,
181 .op_cleanup = 0,
182 },
183 [sdma_state_s30_sw_clean_up_wait] = {
184 .op_enable = 0,
185 .op_intenable = 0,
186 .op_halt = 0,
187 .op_cleanup = 0,
188 },
189 [sdma_state_s40_hw_clean_up_wait] = {
190 .op_enable = 0,
191 .op_intenable = 0,
192 .op_halt = 0,
193 .op_cleanup = 1,
194 },
195 [sdma_state_s50_hw_halt_wait] = {
196 .op_enable = 0,
197 .op_intenable = 0,
198 .op_halt = 0,
199 .op_cleanup = 0,
200 },
201 [sdma_state_s60_idle_halt_wait] = {
202 .go_s99_running_tofalse = 1,
203 .op_enable = 0,
204 .op_intenable = 0,
205 .op_halt = 1,
206 .op_cleanup = 0,
207 },
208 [sdma_state_s80_hw_freeze] = {
209 .op_enable = 0,
210 .op_intenable = 0,
211 .op_halt = 0,
212 .op_cleanup = 0,
213 },
214 [sdma_state_s82_freeze_sw_clean] = {
215 .op_enable = 0,
216 .op_intenable = 0,
217 .op_halt = 0,
218 .op_cleanup = 0,
219 },
220 [sdma_state_s99_running] = {
221 .op_enable = 1,
222 .op_intenable = 1,
223 .op_halt = 0,
224 .op_cleanup = 0,
225 .go_s99_running_totrue = 1,
226 },
227};
228
229#define SDMA_TAIL_UPDATE_THRESH 0x1F
230
231/* declare all statics here rather than keep sorting */
232static void sdma_complete(struct kref *);
233static void sdma_finalput(struct sdma_state *);
234static void sdma_get(struct sdma_state *);
235static void sdma_hw_clean_up_task(unsigned long);
236static void sdma_put(struct sdma_state *);
237static void sdma_set_state(struct sdma_engine *, enum sdma_states);
238static void sdma_start_hw_clean_up(struct sdma_engine *);
77241056
MM		 239static void sdma_sw_clean_up_task(unsigned long);
240static void sdma_sendctrl(struct sdma_engine *, unsigned);
241static void init_sdma_regs(struct sdma_engine *, u32, uint);
242static void sdma_process_event(
243 struct sdma_engine *sde,
244 enum sdma_events event);
245static void __sdma_process_event(
246 struct sdma_engine *sde,
247 enum sdma_events event);
248static void dump_sdma_state(struct sdma_engine *sde);
249static void sdma_make_progress(struct sdma_engine *sde, u64 status);
250static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail);
251static void sdma_flush_descq(struct sdma_engine *sde);
252
253/**
254 * sdma_state_name() - return state string from enum
255 * @state: state
256 */
257static const char *sdma_state_name(enum sdma_states state)
258{
259 return sdma_state_names[state];
260}
261
262static void sdma_get(struct sdma_state *ss)
263{
264 kref_get(&ss->kref);
265}
266
267static void sdma_complete(struct kref *kref)
268{
269 struct sdma_state *ss =
270 container_of(kref, struct sdma_state, kref);
271
272 complete(&ss->comp);
273}
274
275static void sdma_put(struct sdma_state *ss)
276{
277 kref_put(&ss->kref, sdma_complete);
278}
279
280static void sdma_finalput(struct sdma_state *ss)
281{
282 sdma_put(ss);
283 wait_for_completion(&ss->comp);
284}
285
286static inline void write_sde_csr(
287 struct sdma_engine *sde,
288 u32 offset0,
289 u64 value)
290{
291 write_kctxt_csr(sde->dd, sde->this_idx, offset0, value);
292}
293
294static inline u64 read_sde_csr(
295 struct sdma_engine *sde,
296 u32 offset0)
297{
298 return read_kctxt_csr(sde->dd, sde->this_idx, offset0);
299}
300
301/*
302 * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for
303 * sdma engine 'sde' to drop to 0.
304 */
305static void sdma_wait_for_packet_egress(struct sdma_engine *sde,
306 int pause)
307{
308 u64 off = 8 * sde->this_idx;
309 struct hfi1_devdata *dd = sde->dd;
310 int lcnt = 0;
25d97dd5
VM		 311 u64 reg_prev;
312 u64 reg = 0;
77241056
MM		 313
314 while (1) {
25d97dd5
VM		 315 reg_prev = reg;
316 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS);
77241056
MM		 317
318 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK;
319 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT;
320 if (reg == 0)
321 break;
25d97dd5
VM		 322 /* counter is reest if accupancy count changes */
323 if (reg != reg_prev)
324 lcnt = 0;
325 if (lcnt++ > 500) {
326 /* timed out - bounce the link */
327 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n",
77241056 328 __func__, sde->this_idx, (u32)reg);
25d97dd5
VM		 329 queue_work(dd->pport->hfi1_wq,
330 &dd->pport->link_bounce_work);
77241056
MM		 331 break;
332 }
333 udelay(1);
334 }
335}
336
337/*
338 * sdma_wait() - wait for packet egress to complete for all SDMA engines,
339 * and pause for credit return.
340 */
341void sdma_wait(struct hfi1_devdata *dd)
342{
343 int i;
344
345 for (i = 0; i < dd->num_sdma; i++) {
346 struct sdma_engine *sde = &dd->per_sdma[i];
347
348 sdma_wait_for_packet_egress(sde, 0);
349 }
350}
351
352static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt)
353{
354 u64 reg;
355
356 if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT))
357 return;
358 reg = cnt;
359 reg &= SD(DESC_CNT_CNT_MASK);
360 reg <<= SD(DESC_CNT_CNT_SHIFT);
361 write_sde_csr(sde, SD(DESC_CNT), reg);
362}
363
a545f530
MM		 364static inline void complete_tx(struct sdma_engine *sde,
365 struct sdma_txreq *tx,
366 int res)
367{
368 /* protect against complete modifying */
369 struct iowait *wait = tx->wait;
370 callback_t complete = tx->complete;
371
372#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
373 trace_hfi1_sdma_out_sn(sde, txp->sn);
374 if (WARN_ON_ONCE(sde->head_sn != txp->sn))
375 dd_dev_err(sde->dd, "expected %llu got %llu\n",
376 sde->head_sn, txp->sn);
377 sde->head_sn++;
378#endif
379 sdma_txclean(sde->dd, tx);
380 if (complete)
381 (*complete)(tx, res);
382 if (iowait_sdma_dec(wait) && wait)
383 iowait_drain_wakeup(wait);
384}
385
77241056
MM		 386/*
387 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status
388 *
389 * Depending on timing there can be txreqs in two places:
390 * - in the descq ring
391 * - in the flush list
392 *
393 * To avoid ordering issues the descq ring needs to be flushed
394 * first followed by the flush list.
395 *
396 * This routine is called from two places
397 * - From a work queue item
398 * - Directly from the state machine just before setting the
399 * state to running
400 *
401 * Must be called with head_lock held
402 *
403 */
404static void sdma_flush(struct sdma_engine *sde)
405{
406 struct sdma_txreq *txp, *txp_next;
407 LIST_HEAD(flushlist);
b77d713a 408 unsigned long flags;
77241056
MM		 409
410 /* flush from head to tail */
411 sdma_flush_descq(sde);
b77d713a 412 spin_lock_irqsave(&sde->flushlist_lock, flags);
77241056
MM		 413 /* copy flush list */
414 list_for_each_entry_safe(txp, txp_next, &sde->flushlist, list) {
415 list_del_init(&txp->list);
416 list_add_tail(&txp->list, &flushlist);
417 }
b77d713a 418 spin_unlock_irqrestore(&sde->flushlist_lock, flags);
77241056 419 /* flush from flush list */
a545f530
MM		 420 list_for_each_entry_safe(txp, txp_next, &flushlist, list)
421 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
77241056
MM		 422}
423
424/*
425 * Fields a work request for flushing the descq ring
426 * and the flush list
427 *
428 * If the engine has been brought to running during
429 * the scheduling delay, the flush is ignored, assuming
430 * that the process of bringing the engine to running
431 * would have done this flush prior to going to running.
432 *
433 */
434static void sdma_field_flush(struct work_struct *work)
435{
436 unsigned long flags;
437 struct sdma_engine *sde =
438 container_of(work, struct sdma_engine, flush_worker);
439
440 write_seqlock_irqsave(&sde->head_lock, flags);
441 if (!__sdma_running(sde))
442 sdma_flush(sde);
443 write_sequnlock_irqrestore(&sde->head_lock, flags);
444}
445
446static void sdma_err_halt_wait(struct work_struct *work)
447{
448 struct sdma_engine *sde = container_of(work, struct sdma_engine,
449 err_halt_worker);
450 u64 statuscsr;
451 unsigned long timeout;
452
453 timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT);
454 while (1) {
455 statuscsr = read_sde_csr(sde, SD(STATUS));
456 statuscsr &= SD(STATUS_ENG_HALTED_SMASK);
457 if (statuscsr)
458 break;
459 if (time_after(jiffies, timeout)) {
460 dd_dev_err(sde->dd,
461 "SDMA engine %d - timeout waiting for engine to halt\n",
462 sde->this_idx);
463 /*
464 * Continue anyway. This could happen if there was
465 * an uncorrectable error in the wrong spot.
466 */
467 break;
468 }
469 usleep_range(80, 120);
470 }
471
472 sdma_process_event(sde, sdma_event_e15_hw_halt_done);
473}
474
77241056
MM		 475static void sdma_err_progress_check_schedule(struct sdma_engine *sde)
476{
477 if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) {
77241056
MM		 478 unsigned index;
479 struct hfi1_devdata *dd = sde->dd;
480
481 for (index = 0; index < dd->num_sdma; index++) {
482 struct sdma_engine *curr_sdma = &dd->per_sdma[index];
483
484 if (curr_sdma != sde)
485 curr_sdma->progress_check_head =
486 curr_sdma->descq_head;
487 }
488 dd_dev_err(sde->dd,
489 "SDMA engine %d - check scheduled\n",
490 sde->this_idx);
491 mod_timer(&sde->err_progress_check_timer, jiffies + 10);
492 }
493}
494
495static void sdma_err_progress_check(unsigned long data)
496{
497 unsigned index;
498 struct sdma_engine *sde = (struct sdma_engine *)data;
499
500 dd_dev_err(sde->dd, "SDE progress check event\n");
501 for (index = 0; index < sde->dd->num_sdma; index++) {
502 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index];
503 unsigned long flags;
504
505 /* check progress on each engine except the current one */
506 if (curr_sde == sde)
507 continue;
508 /*
509 * We must lock interrupts when acquiring sde->lock,
510 * to avoid a deadlock if interrupt triggers and spins on
511 * the same lock on same CPU
512 */
513 spin_lock_irqsave(&curr_sde->tail_lock, flags);
514 write_seqlock(&curr_sde->head_lock);
515
516 /* skip non-running queues */
517 if (curr_sde->state.current_state != sdma_state_s99_running) {
518 write_sequnlock(&curr_sde->head_lock);
519 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
520 continue;
521 }
522
523 if ((curr_sde->descq_head != curr_sde->descq_tail) &&
524 (curr_sde->descq_head ==
525 curr_sde->progress_check_head))
526 __sdma_process_event(curr_sde,
527 sdma_event_e90_sw_halted);
528 write_sequnlock(&curr_sde->head_lock);
529 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
530 }
531 schedule_work(&sde->err_halt_worker);
532}
533
534static void sdma_hw_clean_up_task(unsigned long opaque)
535{
50e5dcbe 536 struct sdma_engine *sde = (struct sdma_engine *)opaque;
77241056
MM		 537 u64 statuscsr;
538
539 while (1) {
540#ifdef CONFIG_SDMA_VERBOSITY
541 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
542 sde->this_idx, slashstrip(__FILE__), __LINE__,
543 __func__);
544#endif
545 statuscsr = read_sde_csr(sde, SD(STATUS));
546 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK);
547 if (statuscsr)
548 break;
549 udelay(10);
550 }
551
552 sdma_process_event(sde, sdma_event_e25_hw_clean_up_done);
553}
554
555static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde)
556{
557 smp_read_barrier_depends(); /* see sdma_update_tail() */
558 return sde->tx_ring[sde->tx_head & sde->sdma_mask];
559}
560
561/*
562 * flush ring for recovery
563 */
564static void sdma_flush_descq(struct sdma_engine *sde)
565{
566 u16 head, tail;
567 int progress = 0;
568 struct sdma_txreq *txp = get_txhead(sde);
569
570 /* The reason for some of the complexity of this code is that
571 * not all descriptors have corresponding txps. So, we have to
572 * be able to skip over descs until we wander into the range of
573 * the next txp on the list.
574 */
575 head = sde->descq_head & sde->sdma_mask;
576 tail = sde->descq_tail & sde->sdma_mask;
577 while (head != tail) {
578 /* advance head, wrap if needed */
579 head = ++sde->descq_head & sde->sdma_mask;
580 /* if now past this txp's descs, do the callback */
581 if (txp && txp->next_descq_idx == head) {
77241056
MM		 582 /* remove from list */
583 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
a545f530 584 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
77241056 585 trace_hfi1_sdma_progress(sde, head, tail, txp);
77241056
MM		 586 txp = get_txhead(sde);
587 }
588 progress++;
589 }
590 if (progress)
591 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
592}
593
594static void sdma_sw_clean_up_task(unsigned long opaque)
595{
50e5dcbe 596 struct sdma_engine *sde = (struct sdma_engine *)opaque;
77241056
MM		 597 unsigned long flags;
598
599 spin_lock_irqsave(&sde->tail_lock, flags);
600 write_seqlock(&sde->head_lock);
601
602 /*
603 * At this point, the following should always be true:
604 * - We are halted, so no more descriptors are getting retired.
605 * - We are not running, so no one is submitting new work.
606 * - Only we can send the e40_sw_cleaned, so we can't start
607 * running again until we say so. So, the active list and
608 * descq are ours to play with.
609 */
610
77241056
MM		 611 /*
612 * In the error clean up sequence, software clean must be called
613 * before the hardware clean so we can use the hardware head in
614 * the progress routine. A hardware clean or SPC unfreeze will
615 * reset the hardware head.
616 *
617 * Process all retired requests. The progress routine will use the
618 * latest physical hardware head - we are not running so speed does
619 * not matter.
620 */
621 sdma_make_progress(sde, 0);
622
623 sdma_flush(sde);
624
625 /*
626 * Reset our notion of head and tail.
627 * Note that the HW registers have been reset via an earlier
628 * clean up.
629 */
630 sde->descq_tail = 0;
631 sde->descq_head = 0;
632 sde->desc_avail = sdma_descq_freecnt(sde);
633 *sde->head_dma = 0;
634
635 __sdma_process_event(sde, sdma_event_e40_sw_cleaned);
636
637 write_sequnlock(&sde->head_lock);
638 spin_unlock_irqrestore(&sde->tail_lock, flags);
639}
640
641static void sdma_sw_tear_down(struct sdma_engine *sde)
642{
643 struct sdma_state *ss = &sde->state;
644
645 /* Releasing this reference means the state machine has stopped. */
646 sdma_put(ss);
647
648 /* stop waiting for all unfreeze events to complete */
649 atomic_set(&sde->dd->sdma_unfreeze_count, -1);
650 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
651}
652
653static void sdma_start_hw_clean_up(struct sdma_engine *sde)
654{
655 tasklet_hi_schedule(&sde->sdma_hw_clean_up_task);
656}
657
77241056
MM		 658static void sdma_set_state(struct sdma_engine *sde,
659 enum sdma_states next_state)
660{
661 struct sdma_state *ss = &sde->state;
662 const struct sdma_set_state_action *action = sdma_action_table;
663 unsigned op = 0;
664
665 trace_hfi1_sdma_state(
666 sde,
667 sdma_state_names[ss->current_state],
668 sdma_state_names[next_state]);
669
670 /* debugging bookkeeping */
671 ss->previous_state = ss->current_state;
672 ss->previous_op = ss->current_op;
673 ss->current_state = next_state;
674
675 if (ss->previous_state != sdma_state_s99_running
676 && next_state == sdma_state_s99_running)
677 sdma_flush(sde);
678
679 if (action[next_state].op_enable)
680 op |= SDMA_SENDCTRL_OP_ENABLE;
681
682 if (action[next_state].op_intenable)
683 op |= SDMA_SENDCTRL_OP_INTENABLE;
684
685 if (action[next_state].op_halt)
686 op |= SDMA_SENDCTRL_OP_HALT;
687
688 if (action[next_state].op_cleanup)
689 op |= SDMA_SENDCTRL_OP_CLEANUP;
690
691 if (action[next_state].go_s99_running_tofalse)
692 ss->go_s99_running = 0;
693
694 if (action[next_state].go_s99_running_totrue)
695 ss->go_s99_running = 1;
696
697 ss->current_op = op;
698 sdma_sendctrl(sde, ss->current_op);
699}
700
701/**
702 * sdma_get_descq_cnt() - called when device probed
703 *
704 * Return a validated descq count.
705 *
706 * This is currently only used in the verbs initialization to build the tx
707 * list.
708 *
709 * This will probably be deleted in favor of a more scalable approach to
710 * alloc tx's.
711 *
712 */
713u16 sdma_get_descq_cnt(void)
714{
715 u16 count = sdma_descq_cnt;
716
717 if (!count)
718 return SDMA_DESCQ_CNT;
719 /* count must be a power of 2 greater than 64 and less than
720 * 32768. Otherwise return default.
721 */
722 if (!is_power_of_2(count))
723 return SDMA_DESCQ_CNT;
aeef010a 724 if (count < 64 || count > 32768)
77241056
MM		 725 return SDMA_DESCQ_CNT;
726 return count;
727}
b91cc573 728
77241056
MM		 729/**
730 * sdma_select_engine_vl() - select sdma engine
731 * @dd: devdata
732 * @selector: a spreading factor
733 * @vl: this vl
734 *
735 *
736 * This function returns an engine based on the selector and a vl. The
737 * mapping fields are protected by RCU.
738 */
739struct sdma_engine *sdma_select_engine_vl(
740 struct hfi1_devdata *dd,
741 u32 selector,
742 u8 vl)
743{
744 struct sdma_vl_map *m;
745 struct sdma_map_elem *e;
746 struct sdma_engine *rval;
747
4be81991
IW		 748 /* NOTE This should only happen if SC->VL changed after the initial
749 * checks on the QP/AH
750 * Default will return engine 0 below
751 */
752 if (vl >= num_vls) {
753 rval = NULL;
754 goto done;
755 }
77241056
MM		 756
757 rcu_read_lock();
758 m = rcu_dereference(dd->sdma_map);
759 if (unlikely(!m)) {
760 rcu_read_unlock();
0a226edd 761 return &dd->per_sdma[0];
77241056
MM		 762 }
763 e = m->map[vl & m->mask];
764 rval = e->sde[selector & e->mask];
765 rcu_read_unlock();
766
4be81991 767done:
0a226edd 768 rval = !rval ? &dd->per_sdma[0] : rval;
77241056
MM		 769 trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx);
770 return rval;
771}
772
773/**
774 * sdma_select_engine_sc() - select sdma engine
775 * @dd: devdata
776 * @selector: a spreading factor
777 * @sc5: the 5 bit sc
778 *
779 *
780 * This function returns an engine based on the selector and an sc.
781 */
782struct sdma_engine *sdma_select_engine_sc(
783 struct hfi1_devdata *dd,
784 u32 selector,
785 u8 sc5)
786{
787 u8 vl = sc_to_vlt(dd, sc5);
788
789 return sdma_select_engine_vl(dd, selector, vl);
790}
791
792/*
793 * Free the indicated map struct
794 */
795static void sdma_map_free(struct sdma_vl_map *m)
796{
797 int i;
798
799 for (i = 0; m && i < m->actual_vls; i++)
800 kfree(m->map[i]);
801 kfree(m);
802}
803
804/*
805 * Handle RCU callback
806 */
807static void sdma_map_rcu_callback(struct rcu_head *list)
808{
809 struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list);
810
811 sdma_map_free(m);
812}
813
814/**
815 * sdma_map_init - called when # vls change
816 * @dd: hfi1_devdata
817 * @port: port number
818 * @num_vls: number of vls
819 * @vl_engines: per vl engine mapping (optional)
820 *
821 * This routine changes the mapping based on the number of vls.
822 *
823 * vl_engines is used to specify a non-uniform vl/engine loading. NULL
824 * implies auto computing the loading and giving each VLs a uniform
825 * distribution of engines per VL.
826 *
827 * The auto algorithm computes the sde_per_vl and the number of extra
828 * engines. Any extra engines are added from the last VL on down.
829 *
830 * rcu locking is used here to control access to the mapping fields.
831 *
832 * If either the num_vls or num_sdma are non-power of 2, the array sizes
833 * in the struct sdma_vl_map and the struct sdma_map_elem are rounded
834 * up to the next highest power of 2 and the first entry is reused
835 * in a round robin fashion.
836 *
837 * If an error occurs the map change is not done and the mapping is
838 * not changed.
839 *
840 */
841int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines)
842{
843 int i, j;
844 int extra, sde_per_vl;
845 int engine = 0;
846 u8 lvl_engines[OPA_MAX_VLS];
847 struct sdma_vl_map *oldmap, *newmap;
848
849 if (!(dd->flags & HFI1_HAS_SEND_DMA))
850 return 0;
851
852 if (!vl_engines) {
853 /* truncate divide */
854 sde_per_vl = dd->num_sdma / num_vls;
855 /* extras */
856 extra = dd->num_sdma % num_vls;
857 vl_engines = lvl_engines;
858 /* add extras from last vl down */
859 for (i = num_vls - 1; i >= 0; i--, extra--)
860 vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0);
861 }
862 /* build new map */
863 newmap = kzalloc(
864 sizeof(struct sdma_vl_map) +
865 roundup_pow_of_two(num_vls) *
866 sizeof(struct sdma_map_elem *),
867 GFP_KERNEL);
868 if (!newmap)
869 goto bail;
870 newmap->actual_vls = num_vls;
871 newmap->vls = roundup_pow_of_two(num_vls);
872 newmap->mask = (1 << ilog2(newmap->vls)) - 1;
69a00b8e
MM		 873 /* initialize back-map */
874 for (i = 0; i < TXE_NUM_SDMA_ENGINES; i++)
875 newmap->engine_to_vl[i] = -1;
77241056
MM		 876 for (i = 0; i < newmap->vls; i++) {
877 /* save for wrap around */
878 int first_engine = engine;
879
880 if (i < newmap->actual_vls) {
881 int sz = roundup_pow_of_two(vl_engines[i]);
882
883 /* only allocate once */
884 newmap->map[i] = kzalloc(
885 sizeof(struct sdma_map_elem) +
886 sz * sizeof(struct sdma_engine *),
887 GFP_KERNEL);
888 if (!newmap->map[i])
889 goto bail;
890 newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
891 /* assign engines */
892 for (j = 0; j < sz; j++) {
893 newmap->map[i]->sde[j] =
894 &dd->per_sdma[engine];
895 if (++engine >= first_engine + vl_engines[i])
896 /* wrap back to first engine */
897 engine = first_engine;
898 }
69a00b8e
MM		 899 /* assign back-map */
900 for (j = 0; j < vl_engines[i]; j++)
901 newmap->engine_to_vl[first_engine + j] = i;
77241056
MM		 902 } else {
903 /* just re-use entry without allocating */
904 newmap->map[i] = newmap->map[i % num_vls];
905 }
906 engine = first_engine + vl_engines[i];
907 }
908 /* newmap in hand, save old map */
909 spin_lock_irq(&dd->sde_map_lock);
910 oldmap = rcu_dereference_protected(dd->sdma_map,
911 lockdep_is_held(&dd->sde_map_lock));
912
913 /* publish newmap */
914 rcu_assign_pointer(dd->sdma_map, newmap);
915
916 spin_unlock_irq(&dd->sde_map_lock);
917 /* success, free any old map after grace period */
918 if (oldmap)
919 call_rcu(&oldmap->list, sdma_map_rcu_callback);
920 return 0;
921bail:
922 /* free any partial allocation */
923 sdma_map_free(newmap);
924 return -ENOMEM;
925}
926
927/*
928 * Clean up allocated memory.
929 *
930 * This routine is can be called regardless of the success of sdma_init()
931 *
932 */
933static void sdma_clean(struct hfi1_devdata *dd, size_t num_engines)
934{
935 size_t i;
936 struct sdma_engine *sde;
937
938 if (dd->sdma_pad_dma) {
939 dma_free_coherent(&dd->pcidev->dev, 4,
940 (void *)dd->sdma_pad_dma,
941 dd->sdma_pad_phys);
942 dd->sdma_pad_dma = NULL;
943 dd->sdma_pad_phys = 0;
944 }
945 if (dd->sdma_heads_dma) {
946 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size,
947 (void *)dd->sdma_heads_dma,
948 dd->sdma_heads_phys);
949 dd->sdma_heads_dma = NULL;
950 dd->sdma_heads_phys = 0;
951 }
952 for (i = 0; dd->per_sdma && i < num_engines; ++i) {
953 sde = &dd->per_sdma[i];
954
955 sde->head_dma = NULL;
956 sde->head_phys = 0;
957
958 if (sde->descq) {
959 dma_free_coherent(
960 &dd->pcidev->dev,
961 sde->descq_cnt * sizeof(u64[2]),
962 sde->descq,
963 sde->descq_phys
964 );
965 sde->descq = NULL;
966 sde->descq_phys = 0;
967 }
60f57ec2 968 kvfree(sde->tx_ring);
77241056
MM		 969 sde->tx_ring = NULL;
970 }
971 spin_lock_irq(&dd->sde_map_lock);
972 kfree(rcu_access_pointer(dd->sdma_map));
973 RCU_INIT_POINTER(dd->sdma_map, NULL);
974 spin_unlock_irq(&dd->sde_map_lock);
975 synchronize_rcu();
976 kfree(dd->per_sdma);
977 dd->per_sdma = NULL;
978}
979
980/**
981 * sdma_init() - called when device probed
982 * @dd: hfi1_devdata
983 * @port: port number (currently only zero)
984 *
985 * sdma_init initializes the specified number of engines.
986 *
987 * The code initializes each sde, its csrs. Interrupts
988 * are not required to be enabled.
989 *
990 * Returns:
991 * 0 - success, -errno on failure
992 */
993int sdma_init(struct hfi1_devdata *dd, u8 port)
994{
995 unsigned this_idx;
996 struct sdma_engine *sde;
997 u16 descq_cnt;
998 void *curr_head;
999 struct hfi1_pportdata *ppd = dd->pport + port;
1000 u32 per_sdma_credits;
1001 uint idle_cnt = sdma_idle_cnt;
1002 size_t num_engines = dd->chip_sdma_engines;
1003
1004 if (!HFI1_CAP_IS_KSET(SDMA)) {
1005 HFI1_CAP_CLEAR(SDMA_AHG);
1006 return 0;
1007 }
1008 if (mod_num_sdma &&
1009 /* can't exceed chip support */
1010 mod_num_sdma <= dd->chip_sdma_engines &&
1011 /* count must be >= vls */
1012 mod_num_sdma >= num_vls)
1013 num_engines = mod_num_sdma;
1014
1015 dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma);
1016 dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", dd->chip_sdma_engines);
1017 dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n",
1018 dd->chip_sdma_mem_size);
1019
1020 per_sdma_credits =
8638b77f 1021 dd->chip_sdma_mem_size / (num_engines * SDMA_BLOCK_SIZE);
77241056
MM		 1022
1023 /* set up freeze waitqueue */
1024 init_waitqueue_head(&dd->sdma_unfreeze_wq);
1025 atomic_set(&dd->sdma_unfreeze_count, 0);
1026
1027 descq_cnt = sdma_get_descq_cnt();
1028 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n",
1029 num_engines, descq_cnt);
1030
1031 /* alloc memory for array of send engines */
1032 dd->per_sdma = kcalloc(num_engines, sizeof(*dd->per_sdma), GFP_KERNEL);
1033 if (!dd->per_sdma)
1034 return -ENOMEM;
1035
1036 idle_cnt = ns_to_cclock(dd, idle_cnt);
ee947859
MH		 1037 if (!sdma_desct_intr)
1038 sdma_desct_intr = SDMA_DESC_INTR;
1039
77241056
MM		 1040 /* Allocate memory for SendDMA descriptor FIFOs */
1041 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1042 sde = &dd->per_sdma[this_idx];
1043 sde->dd = dd;
1044 sde->ppd = ppd;
1045 sde->this_idx = this_idx;
1046 sde->descq_cnt = descq_cnt;
1047 sde->desc_avail = sdma_descq_freecnt(sde);
1048 sde->sdma_shift = ilog2(descq_cnt);
1049 sde->sdma_mask = (1 << sde->sdma_shift) - 1;
a699c6c2
VM		 1050
1051 /* Create a mask specifically for each interrupt source */
1052 sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES +
1053 this_idx);
1054 sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES +
1055 this_idx);
1056 sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES +
1057 this_idx);
1058 /* Create a combined mask to cover all 3 interrupt sources */
1059 sde->imask = sde->int_mask | sde->progress_mask |
1060 sde->idle_mask;
1061
77241056
MM		 1062 spin_lock_init(&sde->tail_lock);
1063 seqlock_init(&sde->head_lock);
1064 spin_lock_init(&sde->senddmactrl_lock);
1065 spin_lock_init(&sde->flushlist_lock);
1066 /* insure there is always a zero bit */
1067 sde->ahg_bits = 0xfffffffe00000000ULL;
1068
1069 sdma_set_state(sde, sdma_state_s00_hw_down);
1070
1071 /* set up reference counting */
1072 kref_init(&sde->state.kref);
1073 init_completion(&sde->state.comp);
1074
1075 INIT_LIST_HEAD(&sde->flushlist);
1076 INIT_LIST_HEAD(&sde->dmawait);
1077
1078 sde->tail_csr =
1079 get_kctxt_csr_addr(dd, this_idx, SD(TAIL));
1080
1081 if (idle_cnt)
1082 dd->default_desc1 =
1083 SDMA_DESC1_HEAD_TO_HOST_FLAG;
1084 else
1085 dd->default_desc1 =
1086 SDMA_DESC1_INT_REQ_FLAG;
1087
1088 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task,
1089 (unsigned long)sde);
1090
1091 tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task,
1092 (unsigned long)sde);
1093 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait);
1094 INIT_WORK(&sde->flush_worker, sdma_field_flush);
1095
1096 sde->progress_check_head = 0;
1097
daac731b
MFW		 1098 setup_timer(&sde->err_progress_check_timer,
1099 sdma_err_progress_check, (unsigned long)sde);
77241056
MM		 1100
1101 sde->descq = dma_zalloc_coherent(
1102 &dd->pcidev->dev,
1103 descq_cnt * sizeof(u64[2]),
1104 &sde->descq_phys,
1105 GFP_KERNEL
1106 );
1107 if (!sde->descq)
1108 goto bail;
1109 sde->tx_ring =
1110 kcalloc(descq_cnt, sizeof(struct sdma_txreq *),
1111 GFP_KERNEL);
1112 if (!sde->tx_ring)
1113 sde->tx_ring =
1114 vzalloc(
1115 sizeof(struct sdma_txreq *) *
1116 descq_cnt);
1117 if (!sde->tx_ring)
1118 goto bail;
1119 }
1120
1121 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines;
1122 /* Allocate memory for DMA of head registers to memory */
1123 dd->sdma_heads_dma = dma_zalloc_coherent(
1124 &dd->pcidev->dev,
1125 dd->sdma_heads_size,
1126 &dd->sdma_heads_phys,
1127 GFP_KERNEL
1128 );
1129 if (!dd->sdma_heads_dma) {
1130 dd_dev_err(dd, "failed to allocate SendDMA head memory\n");
1131 goto bail;
1132 }
1133
1134 /* Allocate memory for pad */
1135 dd->sdma_pad_dma = dma_zalloc_coherent(
1136 &dd->pcidev->dev,
1137 sizeof(u32),
1138 &dd->sdma_pad_phys,
1139 GFP_KERNEL
1140 );
1141 if (!dd->sdma_pad_dma) {
1142 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n");
1143 goto bail;
1144 }
1145
1146 /* assign each engine to different cacheline and init registers */
1147 curr_head = (void *)dd->sdma_heads_dma;
1148 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1149 unsigned long phys_offset;
1150
1151 sde = &dd->per_sdma[this_idx];
1152
1153 sde->head_dma = curr_head;
1154 curr_head += L1_CACHE_BYTES;
1155 phys_offset = (unsigned long)sde->head_dma -
1156 (unsigned long)dd->sdma_heads_dma;
1157 sde->head_phys = dd->sdma_heads_phys + phys_offset;
1158 init_sdma_regs(sde, per_sdma_credits, idle_cnt);
1159 }
1160 dd->flags |= HFI1_HAS_SEND_DMA;
1161 dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0;
1162 dd->num_sdma = num_engines;
1163 if (sdma_map_init(dd, port, ppd->vls_operational, NULL))
1164 goto bail;
1165 dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma);
1166 return 0;
1167
1168bail:
1169 sdma_clean(dd, num_engines);
1170 return -ENOMEM;
1171}
1172
1173/**
1174 * sdma_all_running() - called when the link goes up
1175 * @dd: hfi1_devdata
1176 *
1177 * This routine moves all engines to the running state.
1178 */
1179void sdma_all_running(struct hfi1_devdata *dd)
1180{
1181 struct sdma_engine *sde;
1182 unsigned int i;
1183
1184 /* move all engines to running */
1185 for (i = 0; i < dd->num_sdma; ++i) {
1186 sde = &dd->per_sdma[i];
1187 sdma_process_event(sde, sdma_event_e30_go_running);
1188 }
1189}
1190
1191/**
1192 * sdma_all_idle() - called when the link goes down
1193 * @dd: hfi1_devdata
1194 *
1195 * This routine moves all engines to the idle state.
1196 */
1197void sdma_all_idle(struct hfi1_devdata *dd)
1198{
1199 struct sdma_engine *sde;
1200 unsigned int i;
1201
1202 /* idle all engines */
1203 for (i = 0; i < dd->num_sdma; ++i) {
1204 sde = &dd->per_sdma[i];
1205 sdma_process_event(sde, sdma_event_e70_go_idle);
1206 }
1207}
1208
1209/**
1210 * sdma_start() - called to kick off state processing for all engines
1211 * @dd: hfi1_devdata
1212 *
1213 * This routine is for kicking off the state processing for all required
1214 * sdma engines. Interrupts need to be working at this point.
1215 *
1216 */
1217void sdma_start(struct hfi1_devdata *dd)
1218{
1219 unsigned i;
1220 struct sdma_engine *sde;
1221
1222 /* kick off the engines state processing */
1223 for (i = 0; i < dd->num_sdma; ++i) {
1224 sde = &dd->per_sdma[i];
1225 sdma_process_event(sde, sdma_event_e10_go_hw_start);
1226 }
1227}
1228
1229/**
1230 * sdma_exit() - used when module is removed
1231 * @dd: hfi1_devdata
1232 */
1233void sdma_exit(struct hfi1_devdata *dd)
1234{
1235 unsigned this_idx;
1236 struct sdma_engine *sde;
1237
1238 for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma;
1239 ++this_idx) {
77241056
MM		 1240 sde = &dd->per_sdma[this_idx];
1241 if (!list_empty(&sde->dmawait))
1242 dd_dev_err(dd, "sde %u: dmawait list not empty!\n",
1243 sde->this_idx);
1244 sdma_process_event(sde, sdma_event_e00_go_hw_down);
1245
1246 del_timer_sync(&sde->err_progress_check_timer);
1247
1248 /*
1249 * This waits for the state machine to exit so it is not
1250 * necessary to kill the sdma_sw_clean_up_task to make sure
1251 * it is not running.
1252 */
1253 sdma_finalput(&sde->state);
1254 }
1255 sdma_clean(dd, dd->num_sdma);
1256}
1257
1258/*
1259 * unmap the indicated descriptor
1260 */
1261static inline void sdma_unmap_desc(
1262 struct hfi1_devdata *dd,
1263 struct sdma_desc *descp)
1264{
1265 switch (sdma_mapping_type(descp)) {
1266 case SDMA_MAP_SINGLE:
1267 dma_unmap_single(
1268 &dd->pcidev->dev,
1269 sdma_mapping_addr(descp),
1270 sdma_mapping_len(descp),
1271 DMA_TO_DEVICE);
1272 break;
1273 case SDMA_MAP_PAGE:
1274 dma_unmap_page(
1275 &dd->pcidev->dev,
1276 sdma_mapping_addr(descp),
1277 sdma_mapping_len(descp),
1278 DMA_TO_DEVICE);
1279 break;
1280 }
1281}
1282
1283/*
1284 * return the mode as indicated by the first
1285 * descriptor in the tx.
1286 */
1287static inline u8 ahg_mode(struct sdma_txreq *tx)
1288{
1289 return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1290 >> SDMA_DESC1_HEADER_MODE_SHIFT;
1291}
1292
1293/**
1294 * sdma_txclean() - clean tx of mappings, descp *kmalloc's
1295 * @dd: hfi1_devdata for unmapping
1296 * @tx: tx request to clean
1297 *
1298 * This is used in the progress routine to clean the tx or
1299 * by the ULP to toss an in-process tx build.
1300 *
1301 * The code can be called multiple times without issue.
1302 *
1303 */
1304void sdma_txclean(
1305 struct hfi1_devdata *dd,
1306 struct sdma_txreq *tx)
1307{
1308 u16 i;
1309
1310 if (tx->num_desc) {
1311 u8 skip = 0, mode = ahg_mode(tx);
1312
1313 /* unmap first */
1314 sdma_unmap_desc(dd, &tx->descp[0]);
1315 /* determine number of AHG descriptors to skip */
1316 if (mode > SDMA_AHG_APPLY_UPDATE1)
1317 skip = mode >> 1;
1318 for (i = 1 + skip; i < tx->num_desc; i++)
1319 sdma_unmap_desc(dd, &tx->descp[i]);
1320 tx->num_desc = 0;
1321 }
1322 kfree(tx->coalesce_buf);
1323 tx->coalesce_buf = NULL;
1324 /* kmalloc'ed descp */
1325 if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) {
1326 tx->desc_limit = ARRAY_SIZE(tx->descs);
1327 kfree(tx->descp);
1328 }
1329}
1330
1331static inline u16 sdma_gethead(struct sdma_engine *sde)
1332{
1333 struct hfi1_devdata *dd = sde->dd;
1334 int use_dmahead;
1335 u16 hwhead;
1336
1337#ifdef CONFIG_SDMA_VERBOSITY
1338 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1339 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1340#endif
1341
1342retry:
1343 use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) &&
1344 (dd->flags & HFI1_HAS_SDMA_TIMEOUT);
1345 hwhead = use_dmahead ?
50e5dcbe
JJ		 1346 (u16)le64_to_cpu(*sde->head_dma) :
1347 (u16)read_sde_csr(sde, SD(HEAD));
77241056
MM		 1348
1349 if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) {
1350 u16 cnt;
1351 u16 swtail;
1352 u16 swhead;
1353 int sane;
1354
1355 swhead = sde->descq_head & sde->sdma_mask;
1356 /* this code is really bad for cache line trading */
1357 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1358 cnt = sde->descq_cnt;
1359
1360 if (swhead < swtail)
1361 /* not wrapped */
1362 sane = (hwhead >= swhead) & (hwhead <= swtail);
1363 else if (swhead > swtail)
1364 /* wrapped around */
1365 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
1366 (hwhead <= swtail);
1367 else
1368 /* empty */
1369 sane = (hwhead == swhead);
1370
1371 if (unlikely(!sane)) {
1372 dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n",
1373 sde->this_idx,
1374 use_dmahead ? "dma" : "kreg",
1375 hwhead, swhead, swtail, cnt);
1376 if (use_dmahead) {
1377 /* try one more time, using csr */
1378 use_dmahead = 0;
1379 goto retry;
1380 }
1381 /* proceed as if no progress */
1382 hwhead = swhead;
1383 }
1384 }
1385 return hwhead;
1386}
1387
1388/*
1389 * This is called when there are send DMA descriptors that might be
1390 * available.
1391 *
1392 * This is called with head_lock held.
1393 */
1394static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail)
1395{
1396 struct iowait *wait, *nw;
1397 struct iowait *waits[SDMA_WAIT_BATCH_SIZE];
1398 unsigned i, n = 0, seq;
1399 struct sdma_txreq *stx;
1400 struct hfi1_ibdev *dev = &sde->dd->verbs_dev;
1401
1402#ifdef CONFIG_SDMA_VERBOSITY
1403 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
1404 slashstrip(__FILE__), __LINE__, __func__);
1405 dd_dev_err(sde->dd, "avail: %u\n", avail);
1406#endif
1407
1408 do {
1409 seq = read_seqbegin(&dev->iowait_lock);
1410 if (!list_empty(&sde->dmawait)) {
1411 /* at least one item */
1412 write_seqlock(&dev->iowait_lock);
1413 /* Harvest waiters wanting DMA descriptors */
1414 list_for_each_entry_safe(
1415 wait,
1416 nw,
1417 &sde->dmawait,
1418 list) {
1419 u16 num_desc = 0;
1420
1421 if (!wait->wakeup)
1422 continue;
1423 if (n == ARRAY_SIZE(waits))
1424 break;
1425 if (!list_empty(&wait->tx_head)) {
1426 stx = list_first_entry(
1427 &wait->tx_head,
1428 struct sdma_txreq,
1429 list);
1430 num_desc = stx->num_desc;
1431 }
1432 if (num_desc > avail)
1433 break;
1434 avail -= num_desc;
1435 list_del_init(&wait->list);
1436 waits[n++] = wait;
1437 }
1438 write_sequnlock(&dev->iowait_lock);
1439 break;
1440 }
1441 } while (read_seqretry(&dev->iowait_lock, seq));
1442
1443 for (i = 0; i < n; i++)
1444 waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON);
1445}
1446
1447/* head_lock must be held */
1448static void sdma_make_progress(struct sdma_engine *sde, u64 status)
1449{
1450 struct sdma_txreq *txp = NULL;
1451 int progress = 0;
a545f530 1452 u16 hwhead, swhead;
77241056
MM		 1453 int idle_check_done = 0;
1454
1455 hwhead = sdma_gethead(sde);
1456
1457 /* The reason for some of the complexity of this code is that
1458 * not all descriptors have corresponding txps. So, we have to
1459 * be able to skip over descs until we wander into the range of
1460 * the next txp on the list.
1461 */
1462
1463retry:
1464 txp = get_txhead(sde);
1465 swhead = sde->descq_head & sde->sdma_mask;
1466 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1467 while (swhead != hwhead) {
1468 /* advance head, wrap if needed */
1469 swhead = ++sde->descq_head & sde->sdma_mask;
1470
1471 /* if now past this txp's descs, do the callback */
1472 if (txp && txp->next_descq_idx == swhead) {
77241056
MM		 1473 /* remove from list */
1474 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
a545f530 1475 complete_tx(sde, txp, SDMA_TXREQ_S_OK);
77241056
MM		 1476 /* see if there is another txp */
1477 txp = get_txhead(sde);
1478 }
1479 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1480 progress++;
1481 }
1482
1483 /*
1484 * The SDMA idle interrupt is not guaranteed to be ordered with respect
1485 * to updates to the the dma_head location in host memory. The head
1486 * value read might not be fully up to date. If there are pending
1487 * descriptors and the SDMA idle interrupt fired then read from the
1488 * CSR SDMA head instead to get the latest value from the hardware.
1489 * The hardware SDMA head should be read at most once in this invocation
1490 * of sdma_make_progress(..) which is ensured by idle_check_done flag
1491 */
1492 if ((status & sde->idle_mask) && !idle_check_done) {
a545f530
MM		 1493 u16 swtail;
1494
77241056
MM		 1495 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1496 if (swtail != hwhead) {
1497 hwhead = (u16)read_sde_csr(sde, SD(HEAD));
1498 idle_check_done = 1;
1499 goto retry;
1500 }
1501 }
1502
1503 sde->last_status = status;
1504 if (progress)
1505 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
1506}
1507
1508/*
1509 * sdma_engine_interrupt() - interrupt handler for engine
1510 * @sde: sdma engine
1511 * @status: sdma interrupt reason
1512 *
1513 * Status is a mask of the 3 possible interrupts for this engine. It will
1514 * contain bits _only_ for this SDMA engine. It will contain at least one
1515 * bit, it may contain more.
1516 */
1517void sdma_engine_interrupt(struct sdma_engine *sde, u64 status)
1518{
1519 trace_hfi1_sdma_engine_interrupt(sde, status);
1520 write_seqlock(&sde->head_lock);
ee947859 1521 sdma_set_desc_cnt(sde, sdma_desct_intr);
a699c6c2
VM		 1522 if (status & sde->idle_mask)
1523 sde->idle_int_cnt++;
1524 else if (status & sde->progress_mask)
1525 sde->progress_int_cnt++;
1526 else if (status & sde->int_mask)
1527 sde->sdma_int_cnt++;
77241056
MM		 1528 sdma_make_progress(sde, status);
1529 write_sequnlock(&sde->head_lock);
1530}
1531
1532/**
1533 * sdma_engine_error() - error handler for engine
1534 * @sde: sdma engine
1535 * @status: sdma interrupt reason
1536 */
1537void sdma_engine_error(struct sdma_engine *sde, u64 status)
1538{
1539 unsigned long flags;
1540
1541#ifdef CONFIG_SDMA_VERBOSITY
1542 dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n",
1543 sde->this_idx,
1544 (unsigned long long)status,
1545 sdma_state_names[sde->state.current_state]);
1546#endif
1547 spin_lock_irqsave(&sde->tail_lock, flags);
1548 write_seqlock(&sde->head_lock);
1549 if (status & ALL_SDMA_ENG_HALT_ERRS)
1550 __sdma_process_event(sde, sdma_event_e60_hw_halted);
1551 if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) {
1552 dd_dev_err(sde->dd,
1553 "SDMA (%u) engine error: 0x%llx state %s\n",
1554 sde->this_idx,
1555 (unsigned long long)status,
1556 sdma_state_names[sde->state.current_state]);
1557 dump_sdma_state(sde);
1558 }
1559 write_sequnlock(&sde->head_lock);
1560 spin_unlock_irqrestore(&sde->tail_lock, flags);
1561}
1562
1563static void sdma_sendctrl(struct sdma_engine *sde, unsigned op)
1564{
1565 u64 set_senddmactrl = 0;
1566 u64 clr_senddmactrl = 0;
1567 unsigned long flags;
1568
1569#ifdef CONFIG_SDMA_VERBOSITY
1570 dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n",
1571 sde->this_idx,
1572 (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0,
1573 (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0,
1574 (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0,
1575 (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0);
1576#endif
1577
1578 if (op & SDMA_SENDCTRL_OP_ENABLE)
1579 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1580 else
1581 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1582
1583 if (op & SDMA_SENDCTRL_OP_INTENABLE)
1584 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1585 else
1586 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1587
1588 if (op & SDMA_SENDCTRL_OP_HALT)
1589 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1590 else
1591 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1592
1593 spin_lock_irqsave(&sde->senddmactrl_lock, flags);
1594
1595 sde->p_senddmactrl |= set_senddmactrl;
1596 sde->p_senddmactrl &= ~clr_senddmactrl;
1597
1598 if (op & SDMA_SENDCTRL_OP_CLEANUP)
1599 write_sde_csr(sde, SD(CTRL),
1600 sde->p_senddmactrl |
1601 SD(CTRL_SDMA_CLEANUP_SMASK));
1602 else
1603 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl);
1604
1605 spin_unlock_irqrestore(&sde->senddmactrl_lock, flags);
1606
1607#ifdef CONFIG_SDMA_VERBOSITY
1608 sdma_dumpstate(sde);
1609#endif
1610}
1611
1612static void sdma_setlengen(struct sdma_engine *sde)
1613{
1614#ifdef CONFIG_SDMA_VERBOSITY
1615 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1616 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1617#endif
1618
1619 /*
1620 * Set SendDmaLenGen and clear-then-set the MSB of the generation
1621 * count to enable generation checking and load the internal
1622 * generation counter.
1623 */
1624 write_sde_csr(sde, SD(LEN_GEN),
8638b77f 1625 (sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)
77241056
MM		 1626 );
1627 write_sde_csr(sde, SD(LEN_GEN),
8638b77f 1628 ((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT))
77241056
MM		 1629 | (4ULL << SD(LEN_GEN_GENERATION_SHIFT))
1630 );
1631}
1632
1633static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail)
1634{
1635 /* Commit writes to memory and advance the tail on the chip */
1636 smp_wmb(); /* see get_txhead() */
1637 writeq(tail, sde->tail_csr);
1638}
1639
1640/*
1641 * This is called when changing to state s10_hw_start_up_halt_wait as
1642 * a result of send buffer errors or send DMA descriptor errors.
1643 */
1644static void sdma_hw_start_up(struct sdma_engine *sde)
1645{
1646 u64 reg;
1647
1648#ifdef CONFIG_SDMA_VERBOSITY
1649 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1650 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1651#endif
1652
1653 sdma_setlengen(sde);
1654 sdma_update_tail(sde, 0); /* Set SendDmaTail */
1655 *sde->head_dma = 0;
1656
1657 reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) <<
1658 SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT);
1659 write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg);
1660}
1661
1662#define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
1663(r &= ~SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
1664
1665#define SET_STATIC_RATE_CONTROL_SMASK(r) \
1666(r |= SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
1667/*
1668 * set_sdma_integrity
1669 *
1670 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'.
1671 */
1672static void set_sdma_integrity(struct sdma_engine *sde)
1673{
1674 struct hfi1_devdata *dd = sde->dd;
1675 u64 reg;
1676
1677 if (unlikely(HFI1_CAP_IS_KSET(NO_INTEGRITY)))
1678 return;
1679
1680 reg = hfi1_pkt_base_sdma_integrity(dd);
1681
1682 if (HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
1683 CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
1684 else
1685 SET_STATIC_RATE_CONTROL_SMASK(reg);
1686
1687 write_sde_csr(sde, SD(CHECK_ENABLE), reg);
1688}
1689
77241056
MM		 1690static void init_sdma_regs(
1691 struct sdma_engine *sde,
1692 u32 credits,
1693 uint idle_cnt)
1694{
1695 u8 opval, opmask;
1696#ifdef CONFIG_SDMA_VERBOSITY
1697 struct hfi1_devdata *dd = sde->dd;
1698
1699 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1700 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1701#endif
1702
1703 write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys);
1704 sdma_setlengen(sde);
1705 sdma_update_tail(sde, 0); /* Set SendDmaTail */
1706 write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt);
1707 write_sde_csr(sde, SD(DESC_CNT), 0);
1708 write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys);
1709 write_sde_csr(sde, SD(MEMORY),
1710 ((u64)credits <<
1711 SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) |
1712 ((u64)(credits * sde->this_idx) <<
1713 SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT)));
1714 write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull);
1715 set_sdma_integrity(sde);
1716 opmask = OPCODE_CHECK_MASK_DISABLED;
1717 opval = OPCODE_CHECK_VAL_DISABLED;
1718 write_sde_csr(sde, SD(CHECK_OPCODE),
1719 (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) |
1720 (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT));
1721}
1722
1723#ifdef CONFIG_SDMA_VERBOSITY
1724
1725#define sdma_dumpstate_helper0(reg) do { \
1726 csr = read_csr(sde->dd, reg); \
1727 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \
1728 } while (0)
1729
1730#define sdma_dumpstate_helper(reg) do { \
1731 csr = read_sde_csr(sde, reg); \
1732 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \
1733 #reg, sde->this_idx, csr); \
1734 } while (0)
1735
1736#define sdma_dumpstate_helper2(reg) do { \
1737 csr = read_csr(sde->dd, reg + (8 * i)); \
1738 dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \
1739 #reg, i, csr); \
1740 } while (0)
1741
1742void sdma_dumpstate(struct sdma_engine *sde)
1743{
1744 u64 csr;
1745 unsigned i;
1746
1747 sdma_dumpstate_helper(SD(CTRL));
1748 sdma_dumpstate_helper(SD(STATUS));
1749 sdma_dumpstate_helper0(SD(ERR_STATUS));
1750 sdma_dumpstate_helper0(SD(ERR_MASK));
1751 sdma_dumpstate_helper(SD(ENG_ERR_STATUS));
1752 sdma_dumpstate_helper(SD(ENG_ERR_MASK));
1753
1754 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) {
6fd8edab 1755 sdma_dumpstate_helper2(CCE_INT_STATUS);
77241056
MM		 1756 sdma_dumpstate_helper2(CCE_INT_MASK);
1757 sdma_dumpstate_helper2(CCE_INT_BLOCKED);
1758 }
1759
1760 sdma_dumpstate_helper(SD(TAIL));
1761 sdma_dumpstate_helper(SD(HEAD));
1762 sdma_dumpstate_helper(SD(PRIORITY_THLD));
6fd8edab 1763 sdma_dumpstate_helper(SD(IDLE_CNT));
77241056
MM		 1764 sdma_dumpstate_helper(SD(RELOAD_CNT));
1765 sdma_dumpstate_helper(SD(DESC_CNT));
1766 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT));
1767 sdma_dumpstate_helper(SD(MEMORY));
1768 sdma_dumpstate_helper0(SD(ENGINES));
1769 sdma_dumpstate_helper0(SD(MEM_SIZE));
1770 /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */
1771 sdma_dumpstate_helper(SD(BASE_ADDR));
1772 sdma_dumpstate_helper(SD(LEN_GEN));
1773 sdma_dumpstate_helper(SD(HEAD_ADDR));
1774 sdma_dumpstate_helper(SD(CHECK_ENABLE));
1775 sdma_dumpstate_helper(SD(CHECK_VL));
1776 sdma_dumpstate_helper(SD(CHECK_JOB_KEY));
1777 sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY));
1778 sdma_dumpstate_helper(SD(CHECK_SLID));
1779 sdma_dumpstate_helper(SD(CHECK_OPCODE));
1780}
1781#endif
1782
1783static void dump_sdma_state(struct sdma_engine *sde)
1784{
1785 struct hw_sdma_desc *descq;
1786 struct hw_sdma_desc *descqp;
1787 u64 desc[2];
1788 u64 addr;
1789 u8 gen;
1790 u16 len;
1791 u16 head, tail, cnt;
1792
1793 head = sde->descq_head & sde->sdma_mask;
1794 tail = sde->descq_tail & sde->sdma_mask;
1795 cnt = sdma_descq_freecnt(sde);
1796 descq = sde->descq;
1797
1798 dd_dev_err(sde->dd,
1799 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
1800 sde->this_idx,
1801 head,
1802 tail,
1803 cnt,
1804 !list_empty(&sde->flushlist));
1805
1806 /* print info for each entry in the descriptor queue */
1807 while (head != tail) {
1808 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
1809
1810 descqp = &sde->descq[head];
1811 desc[0] = le64_to_cpu(descqp->qw[0]);
1812 desc[1] = le64_to_cpu(descqp->qw[1]);
1813 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
1814 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
1815 'H' : '-';
1816 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
1817 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
1818 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
1819 & SDMA_DESC0_PHY_ADDR_MASK;
1820 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
1821 & SDMA_DESC1_GENERATION_MASK;
1822 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
1823 & SDMA_DESC0_BYTE_COUNT_MASK;
1824 dd_dev_err(sde->dd,
1825 "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
1826 head, flags, addr, gen, len);
1827 dd_dev_err(sde->dd,
1828 "\tdesc0:0x%016llx desc1 0x%016llx\n",
1829 desc[0], desc[1]);
1830 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
1831 dd_dev_err(sde->dd,
1832 "\taidx: %u amode: %u alen: %u\n",
1833 (u8)((desc[1] & SDMA_DESC1_HEADER_INDEX_SMASK)
7d630467 1834 >> SDMA_DESC1_HEADER_INDEX_SHIFT),
77241056
MM		 1835 (u8)((desc[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1836 >> SDMA_DESC1_HEADER_MODE_SHIFT),
1837 (u8)((desc[1] & SDMA_DESC1_HEADER_DWS_SMASK)
1838 >> SDMA_DESC1_HEADER_DWS_SHIFT));
1839 head++;
1840 head &= sde->sdma_mask;
1841 }
1842}
1843
1844#define SDE_FMT \
0a226edd 1845 "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n"
77241056
MM		 1846/**
1847 * sdma_seqfile_dump_sde() - debugfs dump of sde
1848 * @s: seq file
1849 * @sde: send dma engine to dump
1850 *
1851 * This routine dumps the sde to the indicated seq file.
1852 */
1853void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde)
1854{
1855 u16 head, tail;
1856 struct hw_sdma_desc *descqp;
1857 u64 desc[2];
1858 u64 addr;
1859 u8 gen;
1860 u16 len;
1861
1862 head = sde->descq_head & sde->sdma_mask;
1863 tail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1864 seq_printf(s, SDE_FMT, sde->this_idx,
0a226edd 1865 sde->cpu,
77241056
MM		 1866 sdma_state_name(sde->state.current_state),
1867 (unsigned long long)read_sde_csr(sde, SD(CTRL)),
1868 (unsigned long long)read_sde_csr(sde, SD(STATUS)),
1869 (unsigned long long)read_sde_csr(sde,
1870 SD(ENG_ERR_STATUS)),
1871 (unsigned long long)read_sde_csr(sde, SD(TAIL)),
1872 tail,
1873 (unsigned long long)read_sde_csr(sde, SD(HEAD)),
1874 head,
1875 (unsigned long long)le64_to_cpu(*sde->head_dma),
1876 (unsigned long long)read_sde_csr(sde, SD(MEMORY)),
1877 (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)),
1878 (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)),
1879 (unsigned long long)sde->last_status,
1880 (unsigned long long)sde->ahg_bits,
1881 sde->tx_tail,
1882 sde->tx_head,
1883 sde->descq_tail,
1884 sde->descq_head,
1885 !list_empty(&sde->flushlist),
1886 sde->descq_full_count,
1887 (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID));
1888
1889 /* print info for each entry in the descriptor queue */
1890 while (head != tail) {
1891 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
1892
1893 descqp = &sde->descq[head];
1894 desc[0] = le64_to_cpu(descqp->qw[0]);
1895 desc[1] = le64_to_cpu(descqp->qw[1]);
1896 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
1897 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
1898 'H' : '-';
1899 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
1900 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
1901 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
1902 & SDMA_DESC0_PHY_ADDR_MASK;
1903 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
1904 & SDMA_DESC1_GENERATION_MASK;
1905 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
1906 & SDMA_DESC0_BYTE_COUNT_MASK;
1907 seq_printf(s,
1908 "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
1909 head, flags, addr, gen, len);
1910 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
1911 seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n",
1912 (u8)((desc[1] & SDMA_DESC1_HEADER_INDEX_SMASK)
7d630467 1913 >> SDMA_DESC1_HEADER_INDEX_SHIFT),
77241056
MM		 1914 (u8)((desc[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1915 >> SDMA_DESC1_HEADER_MODE_SHIFT));
1916 head = (head + 1) & sde->sdma_mask;
1917 }
1918}
1919
1920/*
1921 * add the generation number into
1922 * the qw1 and return
1923 */
1924static inline u64 add_gen(struct sdma_engine *sde, u64 qw1)
1925{
1926 u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3;
1927
1928 qw1 &= ~SDMA_DESC1_GENERATION_SMASK;
1929 qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK)
1930 << SDMA_DESC1_GENERATION_SHIFT;
1931 return qw1;
1932}
1933
1934/*
1935 * This routine submits the indicated tx
1936 *
1937 * Space has already been guaranteed and
1938 * tail side of ring is locked.
1939 *
1940 * The hardware tail update is done
1941 * in the caller and that is facilitated
1942 * by returning the new tail.
1943 *
1944 * There is special case logic for ahg
1945 * to not add the generation number for
1946 * up to 2 descriptors that follow the
1947 * first descriptor.
1948 *
1949 */
1950static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx)
1951{
1952 int i;
1953 u16 tail;
1954 struct sdma_desc *descp = tx->descp;
1955 u8 skip = 0, mode = ahg_mode(tx);
1956
1957 tail = sde->descq_tail & sde->sdma_mask;
1958 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
1959 sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1]));
1960 trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1],
1961 tail, &sde->descq[tail]);
1962 tail = ++sde->descq_tail & sde->sdma_mask;
1963 descp++;
1964 if (mode > SDMA_AHG_APPLY_UPDATE1)
1965 skip = mode >> 1;
1966 for (i = 1; i < tx->num_desc; i++, descp++) {
1967 u64 qw1;
1968
1969 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
1970 if (skip) {
1971 /* edits don't have generation */
1972 qw1 = descp->qw[1];
1973 skip--;
1974 } else {
1975 /* replace generation with real one for non-edits */
1976 qw1 = add_gen(sde, descp->qw[1]);
1977 }
1978 sde->descq[tail].qw[1] = cpu_to_le64(qw1);
1979 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1,
1980 tail, &sde->descq[tail]);
1981 tail = ++sde->descq_tail & sde->sdma_mask;
1982 }
1983 tx->next_descq_idx = tail;
1984#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
1985 tx->sn = sde->tail_sn++;
1986 trace_hfi1_sdma_in_sn(sde, tx->sn);
1987 WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]);
1988#endif
1989 sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx;
1990 sde->desc_avail -= tx->num_desc;
1991 return tail;
1992}
1993
1994/*
1995 * Check for progress
1996 */
1997static int sdma_check_progress(
1998 struct sdma_engine *sde,
1999 struct iowait *wait,
2000 struct sdma_txreq *tx)
2001{
2002 int ret;
2003
2004 sde->desc_avail = sdma_descq_freecnt(sde);
2005 if (tx->num_desc <= sde->desc_avail)
2006 return -EAGAIN;
2007 /* pulse the head_lock */
2008 if (wait && wait->sleep) {
2009 unsigned seq;
2010
2011 seq = raw_seqcount_begin(
2012 (const seqcount_t *)&sde->head_lock.seqcount);
2013 ret = wait->sleep(sde, wait, tx, seq);
2014 if (ret == -EAGAIN)
2015 sde->desc_avail = sdma_descq_freecnt(sde);
2016 } else
2017 ret = -EBUSY;
2018 return ret;
2019}
2020
2021/**
2022 * sdma_send_txreq() - submit a tx req to ring
2023 * @sde: sdma engine to use
2024 * @wait: wait structure to use when full (may be NULL)
2025 * @tx: sdma_txreq to submit
2026 *
2027 * The call submits the tx into the ring. If a iowait structure is non-NULL
2028 * the packet will be queued to the list in wait.
2029 *
2030 * Return:
2031 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in
2032 * ring (wait == NULL)
2033 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2034 */
2035int sdma_send_txreq(struct sdma_engine *sde,
2036 struct iowait *wait,
2037 struct sdma_txreq *tx)
2038{
2039 int ret = 0;
2040 u16 tail;
2041 unsigned long flags;
2042
2043 /* user should have supplied entire packet */
2044 if (unlikely(tx->tlen))
2045 return -EINVAL;
2046 tx->wait = wait;
2047 spin_lock_irqsave(&sde->tail_lock, flags);
2048retry:
2049 if (unlikely(!__sdma_running(sde)))
2050 goto unlock_noconn;
2051 if (unlikely(tx->num_desc > sde->desc_avail))
2052 goto nodesc;
2053 tail = submit_tx(sde, tx);
2054 if (wait)
14553ca1 2055 iowait_sdma_inc(wait);
77241056
MM		 2056 sdma_update_tail(sde, tail);
2057unlock:
2058 spin_unlock_irqrestore(&sde->tail_lock, flags);
2059 return ret;
2060unlock_noconn:
2061 if (wait)
14553ca1 2062 iowait_sdma_inc(wait);
77241056
MM		 2063 tx->next_descq_idx = 0;
2064#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2065 tx->sn = sde->tail_sn++;
2066 trace_hfi1_sdma_in_sn(sde, tx->sn);
2067#endif
f4f30031 2068 spin_lock(&sde->flushlist_lock);
77241056 2069 list_add_tail(&tx->list, &sde->flushlist);
f4f30031 2070 spin_unlock(&sde->flushlist_lock);
77241056
MM		 2071 if (wait) {
2072 wait->tx_count++;
2073 wait->count += tx->num_desc;
2074 }
2075 schedule_work(&sde->flush_worker);
2076 ret = -ECOMM;
2077 goto unlock;
2078nodesc:
2079 ret = sdma_check_progress(sde, wait, tx);
2080 if (ret == -EAGAIN) {
2081 ret = 0;
2082 goto retry;
2083 }
2084 sde->descq_full_count++;
2085 goto unlock;
2086}
2087
2088/**
2089 * sdma_send_txlist() - submit a list of tx req to ring
2090 * @sde: sdma engine to use
2091 * @wait: wait structure to use when full (may be NULL)
2092 * @tx_list: list of sdma_txreqs to submit
2093 *
2094 * The call submits the list into the ring.
2095 *
2096 * If the iowait structure is non-NULL and not equal to the iowait list
2097 * the unprocessed part of the list will be appended to the list in wait.
2098 *
2099 * In all cases, the tx_list will be updated so the head of the tx_list is
2100 * the list of descriptors that have yet to be transmitted.
2101 *
2102 * The intent of this call is to provide a more efficient
2103 * way of submitting multiple packets to SDMA while holding the tail
2104 * side locking.
2105 *
2106 * Return:
c7cbf2fa
MH		 2107 * > 0 - Success (value is number of sdma_txreq's submitted),
2108 * -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL)
77241056
MM		 2109 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2110 */
2111int sdma_send_txlist(struct sdma_engine *sde,
2112 struct iowait *wait,
2113 struct list_head *tx_list)
2114{
2115 struct sdma_txreq *tx, *tx_next;
2116 int ret = 0;
2117 unsigned long flags;
2118 u16 tail = INVALID_TAIL;
2119 int count = 0;
2120
2121 spin_lock_irqsave(&sde->tail_lock, flags);
2122retry:
2123 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2124 tx->wait = wait;
2125 if (unlikely(!__sdma_running(sde)))
2126 goto unlock_noconn;
2127 if (unlikely(tx->num_desc > sde->desc_avail))
2128 goto nodesc;
2129 if (unlikely(tx->tlen)) {
2130 ret = -EINVAL;
2131 goto update_tail;
2132 }
2133 list_del_init(&tx->list);
2134 tail = submit_tx(sde, tx);
2135 count++;
2136 if (tail != INVALID_TAIL &&
2137 (count & SDMA_TAIL_UPDATE_THRESH) == 0) {
2138 sdma_update_tail(sde, tail);
2139 tail = INVALID_TAIL;
2140 }
2141 }
2142update_tail:
2143 if (wait)
14553ca1 2144 iowait_sdma_add(wait, count);
77241056
MM		 2145 if (tail != INVALID_TAIL)
2146 sdma_update_tail(sde, tail);
2147 spin_unlock_irqrestore(&sde->tail_lock, flags);
c7cbf2fa 2148 return ret == 0 ? count : ret;
77241056
MM		 2149unlock_noconn:
2150 spin_lock(&sde->flushlist_lock);
2151 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2152 tx->wait = wait;
2153 list_del_init(&tx->list);
2154 if (wait)
14553ca1 2155 iowait_sdma_inc(wait);
77241056
MM		 2156 tx->next_descq_idx = 0;
2157#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2158 tx->sn = sde->tail_sn++;
2159 trace_hfi1_sdma_in_sn(sde, tx->sn);
2160#endif
2161 list_add_tail(&tx->list, &sde->flushlist);
2162 if (wait) {
2163 wait->tx_count++;
2164 wait->count += tx->num_desc;
2165 }
2166 }
2167 spin_unlock(&sde->flushlist_lock);
2168 schedule_work(&sde->flush_worker);
2169 ret = -ECOMM;
2170 goto update_tail;
2171nodesc:
2172 ret = sdma_check_progress(sde, wait, tx);
2173 if (ret == -EAGAIN) {
2174 ret = 0;
2175 goto retry;
2176 }
2177 sde->descq_full_count++;
2178 goto update_tail;
2179}
2180
2181static void sdma_process_event(struct sdma_engine *sde,
2182 enum sdma_events event)
2183{
2184 unsigned long flags;
2185
2186 spin_lock_irqsave(&sde->tail_lock, flags);
2187 write_seqlock(&sde->head_lock);
2188
2189 __sdma_process_event(sde, event);
2190
2191 if (sde->state.current_state == sdma_state_s99_running)
2192 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
2193
2194 write_sequnlock(&sde->head_lock);
2195 spin_unlock_irqrestore(&sde->tail_lock, flags);
2196}
2197
2198static void __sdma_process_event(struct sdma_engine *sde,
2199 enum sdma_events event)
2200{
2201 struct sdma_state *ss = &sde->state;
2202 int need_progress = 0;
2203
2204 /* CONFIG SDMA temporary */
2205#ifdef CONFIG_SDMA_VERBOSITY
2206 dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx,
2207 sdma_state_names[ss->current_state],
2208 sdma_event_names[event]);
2209#endif
2210
2211 switch (ss->current_state) {
2212 case sdma_state_s00_hw_down:
2213 switch (event) {
2214 case sdma_event_e00_go_hw_down:
2215 break;
2216 case sdma_event_e30_go_running:
2217 /*
2218 * If down, but running requested (usually result
2219 * of link up, then we need to start up.
2220 * This can happen when hw down is requested while
2221 * bringing the link up with traffic active on
2222 * 7220, e.g. */
2223 ss->go_s99_running = 1;
2224 /* fall through and start dma engine */
2225 case sdma_event_e10_go_hw_start:
2226 /* This reference means the state machine is started */
2227 sdma_get(&sde->state);
2228 sdma_set_state(sde,
2229 sdma_state_s10_hw_start_up_halt_wait);
2230 break;
2231 case sdma_event_e15_hw_halt_done:
2232 break;
2233 case sdma_event_e25_hw_clean_up_done:
2234 break;
2235 case sdma_event_e40_sw_cleaned:
2236 sdma_sw_tear_down(sde);
2237 break;
2238 case sdma_event_e50_hw_cleaned:
2239 break;
2240 case sdma_event_e60_hw_halted:
2241 break;
2242 case sdma_event_e70_go_idle:
2243 break;
2244 case sdma_event_e80_hw_freeze:
2245 break;
2246 case sdma_event_e81_hw_frozen:
2247 break;
2248 case sdma_event_e82_hw_unfreeze:
2249 break;
2250 case sdma_event_e85_link_down:
2251 break;
2252 case sdma_event_e90_sw_halted:
2253 break;
2254 }
2255 break;
2256
2257 case sdma_state_s10_hw_start_up_halt_wait:
2258 switch (event) {
2259 case sdma_event_e00_go_hw_down:
2260 sdma_set_state(sde, sdma_state_s00_hw_down);
2261 sdma_sw_tear_down(sde);
2262 break;
2263 case sdma_event_e10_go_hw_start:
2264 break;
2265 case sdma_event_e15_hw_halt_done:
2266 sdma_set_state(sde,
2267 sdma_state_s15_hw_start_up_clean_wait);
2268 sdma_start_hw_clean_up(sde);
2269 break;
2270 case sdma_event_e25_hw_clean_up_done:
2271 break;
2272 case sdma_event_e30_go_running:
2273 ss->go_s99_running = 1;
2274 break;
2275 case sdma_event_e40_sw_cleaned:
2276 break;
2277 case sdma_event_e50_hw_cleaned:
2278 break;
2279 case sdma_event_e60_hw_halted:
8edf7502 2280 schedule_work(&sde->err_halt_worker);
77241056
MM		 2281 break;
2282 case sdma_event_e70_go_idle:
2283 ss->go_s99_running = 0;
2284 break;
2285 case sdma_event_e80_hw_freeze:
2286 break;
2287 case sdma_event_e81_hw_frozen:
2288 break;
2289 case sdma_event_e82_hw_unfreeze:
2290 break;
2291 case sdma_event_e85_link_down:
2292 break;
2293 case sdma_event_e90_sw_halted:
2294 break;
2295 }
2296 break;
2297
2298 case sdma_state_s15_hw_start_up_clean_wait:
2299 switch (event) {
2300 case sdma_event_e00_go_hw_down:
2301 sdma_set_state(sde, sdma_state_s00_hw_down);
2302 sdma_sw_tear_down(sde);
2303 break;
2304 case sdma_event_e10_go_hw_start:
2305 break;
2306 case sdma_event_e15_hw_halt_done:
2307 break;
2308 case sdma_event_e25_hw_clean_up_done:
2309 sdma_hw_start_up(sde);
2310 sdma_set_state(sde, ss->go_s99_running ?
2311 sdma_state_s99_running :
2312 sdma_state_s20_idle);
2313 break;
2314 case sdma_event_e30_go_running:
2315 ss->go_s99_running = 1;
2316 break;
2317 case sdma_event_e40_sw_cleaned:
2318 break;
2319 case sdma_event_e50_hw_cleaned:
2320 break;
2321 case sdma_event_e60_hw_halted:
2322 break;
2323 case sdma_event_e70_go_idle:
2324 ss->go_s99_running = 0;
2325 break;
2326 case sdma_event_e80_hw_freeze:
2327 break;
2328 case sdma_event_e81_hw_frozen:
2329 break;
2330 case sdma_event_e82_hw_unfreeze:
2331 break;
2332 case sdma_event_e85_link_down:
2333 break;
2334 case sdma_event_e90_sw_halted:
2335 break;
2336 }
2337 break;
2338
2339 case sdma_state_s20_idle:
2340 switch (event) {
2341 case sdma_event_e00_go_hw_down:
2342 sdma_set_state(sde, sdma_state_s00_hw_down);
2343 sdma_sw_tear_down(sde);
2344 break;
2345 case sdma_event_e10_go_hw_start:
2346 break;
2347 case sdma_event_e15_hw_halt_done:
2348 break;
2349 case sdma_event_e25_hw_clean_up_done:
2350 break;
2351 case sdma_event_e30_go_running:
2352 sdma_set_state(sde, sdma_state_s99_running);
2353 ss->go_s99_running = 1;
2354 break;
2355 case sdma_event_e40_sw_cleaned:
2356 break;
2357 case sdma_event_e50_hw_cleaned:
2358 break;
2359 case sdma_event_e60_hw_halted:
2360 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
8edf7502 2361 schedule_work(&sde->err_halt_worker);
77241056
MM		 2362 break;
2363 case sdma_event_e70_go_idle:
2364 break;
2365 case sdma_event_e85_link_down:
2366 /* fall through */
2367 case sdma_event_e80_hw_freeze:
2368 sdma_set_state(sde, sdma_state_s80_hw_freeze);
2369 atomic_dec(&sde->dd->sdma_unfreeze_count);
2370 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2371 break;
2372 case sdma_event_e81_hw_frozen:
2373 break;
2374 case sdma_event_e82_hw_unfreeze:
2375 break;
2376 case sdma_event_e90_sw_halted:
2377 break;
2378 }
2379 break;
2380
2381 case sdma_state_s30_sw_clean_up_wait:
2382 switch (event) {
2383 case sdma_event_e00_go_hw_down:
2384 sdma_set_state(sde, sdma_state_s00_hw_down);
2385 break;
2386 case sdma_event_e10_go_hw_start:
2387 break;
2388 case sdma_event_e15_hw_halt_done:
2389 break;
2390 case sdma_event_e25_hw_clean_up_done:
2391 break;
2392 case sdma_event_e30_go_running:
2393 ss->go_s99_running = 1;
2394 break;
2395 case sdma_event_e40_sw_cleaned:
2396 sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait);
2397 sdma_start_hw_clean_up(sde);
2398 break;
2399 case sdma_event_e50_hw_cleaned:
2400 break;
2401 case sdma_event_e60_hw_halted:
2402 break;
2403 case sdma_event_e70_go_idle:
2404 ss->go_s99_running = 0;
2405 break;
2406 case sdma_event_e80_hw_freeze:
2407 break;
2408 case sdma_event_e81_hw_frozen:
2409 break;
2410 case sdma_event_e82_hw_unfreeze:
2411 break;
2412 case sdma_event_e85_link_down:
2413 ss->go_s99_running = 0;
2414 break;
2415 case sdma_event_e90_sw_halted:
2416 break;
2417 }
2418 break;
2419
2420 case sdma_state_s40_hw_clean_up_wait:
2421 switch (event) {
2422 case sdma_event_e00_go_hw_down:
2423 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2424 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2425 break;
2426 case sdma_event_e10_go_hw_start:
2427 break;
2428 case sdma_event_e15_hw_halt_done:
2429 break;
2430 case sdma_event_e25_hw_clean_up_done:
2431 sdma_hw_start_up(sde);
2432 sdma_set_state(sde, ss->go_s99_running ?
2433 sdma_state_s99_running :
2434 sdma_state_s20_idle);
2435 break;
2436 case sdma_event_e30_go_running:
2437 ss->go_s99_running = 1;
2438 break;
2439 case sdma_event_e40_sw_cleaned:
2440 break;
2441 case sdma_event_e50_hw_cleaned:
2442 break;
2443 case sdma_event_e60_hw_halted:
2444 break;
2445 case sdma_event_e70_go_idle:
2446 ss->go_s99_running = 0;
2447 break;
2448 case sdma_event_e80_hw_freeze:
2449 break;
2450 case sdma_event_e81_hw_frozen:
2451 break;
2452 case sdma_event_e82_hw_unfreeze:
2453 break;
2454 case sdma_event_e85_link_down:
2455 ss->go_s99_running = 0;
2456 break;
2457 case sdma_event_e90_sw_halted:
2458 break;
2459 }
2460 break;
2461
2462 case sdma_state_s50_hw_halt_wait:
2463 switch (event) {
2464 case sdma_event_e00_go_hw_down:
2465 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2466 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2467 break;
2468 case sdma_event_e10_go_hw_start:
2469 break;
2470 case sdma_event_e15_hw_halt_done:
2471 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
8edf7502 2472 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2473 break;
2474 case sdma_event_e25_hw_clean_up_done:
2475 break;
2476 case sdma_event_e30_go_running:
2477 ss->go_s99_running = 1;
2478 break;
2479 case sdma_event_e40_sw_cleaned:
2480 break;
2481 case sdma_event_e50_hw_cleaned:
2482 break;
2483 case sdma_event_e60_hw_halted:
8edf7502 2484 schedule_work(&sde->err_halt_worker);
77241056
MM		 2485 break;
2486 case sdma_event_e70_go_idle:
2487 ss->go_s99_running = 0;
2488 break;
2489 case sdma_event_e80_hw_freeze:
2490 break;
2491 case sdma_event_e81_hw_frozen:
2492 break;
2493 case sdma_event_e82_hw_unfreeze:
2494 break;
2495 case sdma_event_e85_link_down:
2496 ss->go_s99_running = 0;
2497 break;
2498 case sdma_event_e90_sw_halted:
2499 break;
2500 }
2501 break;
2502
2503 case sdma_state_s60_idle_halt_wait:
2504 switch (event) {
2505 case sdma_event_e00_go_hw_down:
2506 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2507 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2508 break;
2509 case sdma_event_e10_go_hw_start:
2510 break;
2511 case sdma_event_e15_hw_halt_done:
2512 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
8edf7502 2513 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2514 break;
2515 case sdma_event_e25_hw_clean_up_done:
2516 break;
2517 case sdma_event_e30_go_running:
2518 ss->go_s99_running = 1;
2519 break;
2520 case sdma_event_e40_sw_cleaned:
2521 break;
2522 case sdma_event_e50_hw_cleaned:
2523 break;
2524 case sdma_event_e60_hw_halted:
8edf7502 2525 schedule_work(&sde->err_halt_worker);
77241056
MM		 2526 break;
2527 case sdma_event_e70_go_idle:
2528 ss->go_s99_running = 0;
2529 break;
2530 case sdma_event_e80_hw_freeze:
2531 break;
2532 case sdma_event_e81_hw_frozen:
2533 break;
2534 case sdma_event_e82_hw_unfreeze:
2535 break;
2536 case sdma_event_e85_link_down:
2537 break;
2538 case sdma_event_e90_sw_halted:
2539 break;
2540 }
2541 break;
2542
2543 case sdma_state_s80_hw_freeze:
2544 switch (event) {
2545 case sdma_event_e00_go_hw_down:
2546 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2547 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2548 break;
2549 case sdma_event_e10_go_hw_start:
2550 break;
2551 case sdma_event_e15_hw_halt_done:
2552 break;
2553 case sdma_event_e25_hw_clean_up_done:
2554 break;
2555 case sdma_event_e30_go_running:
2556 ss->go_s99_running = 1;
2557 break;
2558 case sdma_event_e40_sw_cleaned:
2559 break;
2560 case sdma_event_e50_hw_cleaned:
2561 break;
2562 case sdma_event_e60_hw_halted:
2563 break;
2564 case sdma_event_e70_go_idle:
2565 ss->go_s99_running = 0;
2566 break;
2567 case sdma_event_e80_hw_freeze:
2568 break;
2569 case sdma_event_e81_hw_frozen:
2570 sdma_set_state(sde, sdma_state_s82_freeze_sw_clean);
8edf7502 2571 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2572 break;
2573 case sdma_event_e82_hw_unfreeze:
2574 break;
2575 case sdma_event_e85_link_down:
2576 break;
2577 case sdma_event_e90_sw_halted:
2578 break;
2579 }
2580 break;
2581
2582 case sdma_state_s82_freeze_sw_clean:
2583 switch (event) {
2584 case sdma_event_e00_go_hw_down:
2585 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2586 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2587 break;
2588 case sdma_event_e10_go_hw_start:
2589 break;
2590 case sdma_event_e15_hw_halt_done:
2591 break;
2592 case sdma_event_e25_hw_clean_up_done:
2593 break;
2594 case sdma_event_e30_go_running:
2595 ss->go_s99_running = 1;
2596 break;
2597 case sdma_event_e40_sw_cleaned:
2598 /* notify caller this engine is done cleaning */
2599 atomic_dec(&sde->dd->sdma_unfreeze_count);
2600 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2601 break;
2602 case sdma_event_e50_hw_cleaned:
2603 break;
2604 case sdma_event_e60_hw_halted:
2605 break;
2606 case sdma_event_e70_go_idle:
2607 ss->go_s99_running = 0;
2608 break;
2609 case sdma_event_e80_hw_freeze:
2610 break;
2611 case sdma_event_e81_hw_frozen:
2612 break;
2613 case sdma_event_e82_hw_unfreeze:
2614 sdma_hw_start_up(sde);
2615 sdma_set_state(sde, ss->go_s99_running ?
2616 sdma_state_s99_running :
2617 sdma_state_s20_idle);
2618 break;
2619 case sdma_event_e85_link_down:
2620 break;
2621 case sdma_event_e90_sw_halted:
2622 break;
2623 }
2624 break;
2625
2626 case sdma_state_s99_running:
2627 switch (event) {
2628 case sdma_event_e00_go_hw_down:
2629 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2630 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2631 break;
2632 case sdma_event_e10_go_hw_start:
2633 break;
2634 case sdma_event_e15_hw_halt_done:
2635 break;
2636 case sdma_event_e25_hw_clean_up_done:
2637 break;
2638 case sdma_event_e30_go_running:
2639 break;
2640 case sdma_event_e40_sw_cleaned:
2641 break;
2642 case sdma_event_e50_hw_cleaned:
2643 break;
2644 case sdma_event_e60_hw_halted:
2645 need_progress = 1;
2646 sdma_err_progress_check_schedule(sde);
2647 case sdma_event_e90_sw_halted:
2648 /*
2649 * SW initiated halt does not perform engines
2650 * progress check
2651 */
2652 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
8edf7502 2653 schedule_work(&sde->err_halt_worker);
77241056
MM		 2654 break;
2655 case sdma_event_e70_go_idle:
2656 sdma_set_state(sde, sdma_state_s60_idle_halt_wait);
2657 break;
2658 case sdma_event_e85_link_down:
2659 ss->go_s99_running = 0;
2660 /* fall through */
2661 case sdma_event_e80_hw_freeze:
2662 sdma_set_state(sde, sdma_state_s80_hw_freeze);
2663 atomic_dec(&sde->dd->sdma_unfreeze_count);
2664 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2665 break;
2666 case sdma_event_e81_hw_frozen:
2667 break;
2668 case sdma_event_e82_hw_unfreeze:
2669 break;
2670 }
2671 break;
2672 }
2673
2674 ss->last_event = event;
2675 if (need_progress)
2676 sdma_make_progress(sde, 0);
2677}
2678
2679/*
2680 * _extend_sdma_tx_descs() - helper to extend txreq
2681 *
2682 * This is called once the initial nominal allocation
2683 * of descriptors in the sdma_txreq is exhausted.
2684 *
2685 * The code will bump the allocation up to the max
f4d26d81
NV		 2686 * of MAX_DESC (64) descriptors. There doesn't seem
2687 * much point in an interim step. The last descriptor
2688 * is reserved for coalesce buffer in order to support
2689 * cases where input packet has >MAX_DESC iovecs.
77241056
MM		 2690 *
2691 */
f4d26d81 2692static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
77241056
MM		 2693{
2694 int i;
2695
f4d26d81
NV		 2696 /* Handle last descriptor */
2697 if (unlikely((tx->num_desc == (MAX_DESC - 1)))) {
2698 /* if tlen is 0, it is for padding, release last descriptor */
2699 if (!tx->tlen) {
2700 tx->desc_limit = MAX_DESC;
2701 } else if (!tx->coalesce_buf) {
2702 /* allocate coalesce buffer with space for padding */
2703 tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32),
2704 GFP_ATOMIC);
2705 if (!tx->coalesce_buf)
a5a9e8cc 2706 goto enomem;
f4d26d81
NV		 2707 tx->coalesce_idx = 0;
2708 }
2709 return 0;
2710 }
2711
2712 if (unlikely(tx->num_desc == MAX_DESC))
a5a9e8cc 2713 goto enomem;
f4d26d81 2714
77241056
MM		 2715 tx->descp = kmalloc_array(
2716 MAX_DESC,
2717 sizeof(struct sdma_desc),
2718 GFP_ATOMIC);
2719 if (!tx->descp)
a5a9e8cc 2720 goto enomem;
f4d26d81
NV		 2721
2722 /* reserve last descriptor for coalescing */
2723 tx->desc_limit = MAX_DESC - 1;
77241056
MM		 2724 /* copy ones already built */
2725 for (i = 0; i < tx->num_desc; i++)
2726 tx->descp[i] = tx->descs[i];
2727 return 0;
a5a9e8cc
MM		 2728enomem:
2729 sdma_txclean(dd, tx);
2730 return -ENOMEM;
77241056
MM		 2731}
2732
f4d26d81
NV		 2733/*
2734 * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors
2735 *
2736 * This is called once the initial nominal allocation of descriptors
2737 * in the sdma_txreq is exhausted.
2738 *
2739 * This function calls _extend_sdma_tx_descs to extend or allocate
2740 * coalesce buffer. If there is a allocated coalesce buffer, it will
2741 * copy the input packet data into the coalesce buffer. It also adds
2742 * coalesce buffer descriptor once whe whole packet is received.
2743 *
2744 * Return:
2745 * <0 - error
2746 * 0 - coalescing, don't populate descriptor
2747 * 1 - continue with populating descriptor
2748 */
2749int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
2750 int type, void *kvaddr, struct page *page,
2751 unsigned long offset, u16 len)
2752{
2753 int pad_len, rval;
2754 dma_addr_t addr;
2755
2756 rval = _extend_sdma_tx_descs(dd, tx);
2757 if (rval) {
2758 sdma_txclean(dd, tx);
2759 return rval;
2760 }
2761
2762 /* If coalesce buffer is allocated, copy data into it */
2763 if (tx->coalesce_buf) {
2764 if (type == SDMA_MAP_NONE) {
2765 sdma_txclean(dd, tx);
2766 return -EINVAL;
2767 }
2768
2769 if (type == SDMA_MAP_PAGE) {
2770 kvaddr = kmap(page);
2771 kvaddr += offset;
2772 } else if (WARN_ON(!kvaddr)) {
2773 sdma_txclean(dd, tx);
2774 return -EINVAL;
2775 }
2776
2777 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len);
2778 tx->coalesce_idx += len;
2779 if (type == SDMA_MAP_PAGE)
2780 kunmap(page);
2781
2782 /* If there is more data, return */
2783 if (tx->tlen - tx->coalesce_idx)
2784 return 0;
2785
2786 /* Whole packet is received; add any padding */
2787 pad_len = tx->packet_len & (sizeof(u32) - 1);
2788 if (pad_len) {
2789 pad_len = sizeof(u32) - pad_len;
2790 memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len);
2791 /* padding is taken care of for coalescing case */
2792 tx->packet_len += pad_len;
2793 tx->tlen += pad_len;
2794 }
2795
2796 /* dma map the coalesce buffer */
2797 addr = dma_map_single(&dd->pcidev->dev,
2798 tx->coalesce_buf,
2799 tx->tlen,
2800 DMA_TO_DEVICE);
2801
2802 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
2803 sdma_txclean(dd, tx);
2804 return -ENOSPC;
2805 }
2806
2807 /* Add descriptor for coalesce buffer */
2808 tx->desc_limit = MAX_DESC;
2809 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx,
2810 addr, tx->tlen);
2811 }
2812
2813 return 1;
2814}
2815
77241056
MM		 2816/* Update sdes when the lmc changes */
2817void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid)
2818{
2819 struct sdma_engine *sde;
2820 int i;
2821 u64 sreg;
2822
2823 sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) <<
2824 SD(CHECK_SLID_MASK_SHIFT)) |
2825 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) <<
2826 SD(CHECK_SLID_VALUE_SHIFT));
2827
2828 for (i = 0; i < dd->num_sdma; i++) {
2829 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x",
2830 i, (u32)sreg);
2831 sde = &dd->per_sdma[i];
2832 write_sde_csr(sde, SD(CHECK_SLID), sreg);
2833 }
2834}
2835
2836/* tx not dword sized - pad */
2837int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
2838{
2839 int rval = 0;
2840
f4d26d81 2841 tx->num_desc++;
77241056
MM		 2842 if ((unlikely(tx->num_desc == tx->desc_limit))) {
2843 rval = _extend_sdma_tx_descs(dd, tx);
f4d26d81
NV		 2844 if (rval) {
2845 sdma_txclean(dd, tx);
77241056 2846 return rval;
f4d26d81 2847 }
77241056 2848 }
f4d26d81 2849 /* finish the one just added */
77241056
MM		 2850 make_tx_sdma_desc(
2851 tx,
2852 SDMA_MAP_NONE,
2853 dd->sdma_pad_phys,
2854 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1)));
2855 _sdma_close_tx(dd, tx);
2856 return rval;
2857}
2858
2859/*
2860 * Add ahg to the sdma_txreq
2861 *
2862 * The logic will consume up to 3
2863 * descriptors at the beginning of
2864 * sdma_txreq.
2865 */
2866void _sdma_txreq_ahgadd(
2867 struct sdma_txreq *tx,
2868 u8 num_ahg,
2869 u8 ahg_entry,
2870 u32 *ahg,
2871 u8 ahg_hlen)
2872{
2873 u32 i, shift = 0, desc = 0;
2874 u8 mode;
2875
2876 WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4);
2877 /* compute mode */
2878 if (num_ahg == 1)
2879 mode = SDMA_AHG_APPLY_UPDATE1;
2880 else if (num_ahg <= 5)
2881 mode = SDMA_AHG_APPLY_UPDATE2;
2882 else
2883 mode = SDMA_AHG_APPLY_UPDATE3;
2884 tx->num_desc++;
2885 /* initialize to consumed descriptors to zero */
2886 switch (mode) {
2887 case SDMA_AHG_APPLY_UPDATE3:
2888 tx->num_desc++;
2889 tx->descs[2].qw[0] = 0;
2890 tx->descs[2].qw[1] = 0;
2891 /* FALLTHROUGH */
2892 case SDMA_AHG_APPLY_UPDATE2:
2893 tx->num_desc++;
2894 tx->descs[1].qw[0] = 0;
2895 tx->descs[1].qw[1] = 0;
2896 break;
2897 }
2898 ahg_hlen >>= 2;
2899 tx->descs[0].qw[1] |=
2900 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)
2901 << SDMA_DESC1_HEADER_INDEX_SHIFT) |
2902 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK)
2903 << SDMA_DESC1_HEADER_DWS_SHIFT) |
2904 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK)
2905 << SDMA_DESC1_HEADER_MODE_SHIFT) |
2906 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK)
2907 << SDMA_DESC1_HEADER_UPDATE1_SHIFT);
2908 for (i = 0; i < (num_ahg - 1); i++) {
2909 if (!shift && !(i & 2))
2910 desc++;
2911 tx->descs[desc].qw[!!(i & 2)] |=
2912 (((u64)ahg[i + 1])
2913 << shift);
2914 shift = (shift + 32) & 63;
2915 }
2916}
2917
2918/**
2919 * sdma_ahg_alloc - allocate an AHG entry
2920 * @sde: engine to allocate from
2921 *
2922 * Return:
2923 * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled,
2924 * -ENOSPC if an entry is not available
2925 */
2926int sdma_ahg_alloc(struct sdma_engine *sde)
2927{
2928 int nr;
2929 int oldbit;
2930
2931 if (!sde) {
2932 trace_hfi1_ahg_allocate(sde, -EINVAL);
2933 return -EINVAL;
2934 }
2935 while (1) {
2936 nr = ffz(ACCESS_ONCE(sde->ahg_bits));
2937 if (nr > 31) {
2938 trace_hfi1_ahg_allocate(sde, -ENOSPC);
2939 return -ENOSPC;
2940 }
2941 oldbit = test_and_set_bit(nr, &sde->ahg_bits);
2942 if (!oldbit)
2943 break;
2944 cpu_relax();
2945 }
2946 trace_hfi1_ahg_allocate(sde, nr);
2947 return nr;
2948}
2949
2950/**
2951 * sdma_ahg_free - free an AHG entry
2952 * @sde: engine to return AHG entry
2953 * @ahg_index: index to free
2954 *
2955 * This routine frees the indicate AHG entry.
2956 */
2957void sdma_ahg_free(struct sdma_engine *sde, int ahg_index)
2958{
2959 if (!sde)
2960 return;
2961 trace_hfi1_ahg_deallocate(sde, ahg_index);
2962 if (ahg_index < 0 || ahg_index > 31)
2963 return;
2964 clear_bit(ahg_index, &sde->ahg_bits);
2965}
2966
2967/*
2968 * SPC freeze handling for SDMA engines. Called when the driver knows
2969 * the SPC is going into a freeze but before the freeze is fully
2970 * settled. Generally an error interrupt.
2971 *
2972 * This event will pull the engine out of running so no more entries can be
2973 * added to the engine's queue.
2974 */
2975void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down)
2976{
2977 int i;
2978 enum sdma_events event = link_down ? sdma_event_e85_link_down :
2979 sdma_event_e80_hw_freeze;
2980
2981 /* set up the wait but do not wait here */
2982 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
2983
2984 /* tell all engines to stop running and wait */
2985 for (i = 0; i < dd->num_sdma; i++)
2986 sdma_process_event(&dd->per_sdma[i], event);
2987
2988 /* sdma_freeze() will wait for all engines to have stopped */
2989}
2990
2991/*
2992 * SPC freeze handling for SDMA engines. Called when the driver knows
2993 * the SPC is fully frozen.
2994 */
2995void sdma_freeze(struct hfi1_devdata *dd)
2996{
2997 int i;
2998 int ret;
2999
3000 /*
3001 * Make sure all engines have moved out of the running state before
3002 * continuing.
3003 */
3004 ret = wait_event_interruptible(dd->sdma_unfreeze_wq,
3005 atomic_read(&dd->sdma_unfreeze_count) <= 0);
3006 /* interrupted or count is negative, then unloading - just exit */
3007 if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0)
3008 return;
3009
3010 /* set up the count for the next wait */
3011 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3012
3013 /* tell all engines that the SPC is frozen, they can start cleaning */
3014 for (i = 0; i < dd->num_sdma; i++)
3015 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen);
3016
3017 /*
3018 * Wait for everyone to finish software clean before exiting. The
3019 * software clean will read engine CSRs, so must be completed before
3020 * the next step, which will clear the engine CSRs.
3021 */
50e5dcbe 3022 (void)wait_event_interruptible(dd->sdma_unfreeze_wq,
77241056
MM		 3023 atomic_read(&dd->sdma_unfreeze_count) <= 0);
3024 /* no need to check results - done no matter what */
3025}
3026
3027/*
3028 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen.
3029 *
3030 * The SPC freeze acts like a SDMA halt and a hardware clean combined. All
3031 * that is left is a software clean. We could do it after the SPC is fully
3032 * frozen, but then we'd have to add another state to wait for the unfreeze.
3033 * Instead, just defer the software clean until the unfreeze step.
3034 */
3035void sdma_unfreeze(struct hfi1_devdata *dd)
3036{
3037 int i;
3038
3039 /* tell all engines start freeze clean up */
3040 for (i = 0; i < dd->num_sdma; i++)
3041 sdma_process_event(&dd->per_sdma[i],
3042 sdma_event_e82_hw_unfreeze);
3043}
3044
3045/**
3046 * _sdma_engine_progress_schedule() - schedule progress on engine
3047 * @sde: sdma_engine to schedule progress
3048 *
3049 */
3050void _sdma_engine_progress_schedule(
3051 struct sdma_engine *sde)
3052{
3053 trace_hfi1_sdma_engine_progress(sde, sde->progress_mask);
3054 /* assume we have selected a good cpu */
3055 write_csr(sde->dd,
8638b77f 3056 CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)), sde->progress_mask);
77241056 3057}
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