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Commit | Line | Data |
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77241056 MM |
1 | /* |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
0840aea9 | 8 | * Copyright(c) 2015, 2016 Intel Corporation. |
77241056 MM |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * BSD LICENSE | |
20 | * | |
0840aea9 | 21 | * Copyright(c) 2015, 2016 Intel Corporation. |
77241056 MM |
22 | * |
23 | * Redistribution and use in source and binary forms, with or without | |
24 | * modification, are permitted provided that the following conditions | |
25 | * are met: | |
26 | * | |
27 | * - Redistributions of source code must retain the above copyright | |
28 | * notice, this list of conditions and the following disclaimer. | |
29 | * - Redistributions in binary form must reproduce the above copyright | |
30 | * notice, this list of conditions and the following disclaimer in | |
31 | * the documentation and/or other materials provided with the | |
32 | * distribution. | |
33 | * - Neither the name of Intel Corporation nor the names of its | |
34 | * contributors may be used to endorse or promote products derived | |
35 | * from this software without specific prior written permission. | |
36 | * | |
37 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
38 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
39 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
40 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
41 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
42 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
43 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
44 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
45 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
46 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
48 | * | |
49 | */ | |
50 | #include <linux/mm.h> | |
51 | #include <linux/types.h> | |
52 | #include <linux/device.h> | |
53 | #include <linux/dmapool.h> | |
54 | #include <linux/slab.h> | |
55 | #include <linux/list.h> | |
56 | #include <linux/highmem.h> | |
57 | #include <linux/io.h> | |
58 | #include <linux/uio.h> | |
59 | #include <linux/rbtree.h> | |
60 | #include <linux/spinlock.h> | |
61 | #include <linux/delay.h> | |
62 | #include <linux/kthread.h> | |
63 | #include <linux/mmu_context.h> | |
64 | #include <linux/module.h> | |
65 | #include <linux/vmalloc.h> | |
66 | ||
67 | #include "hfi.h" | |
68 | #include "sdma.h" | |
69 | #include "user_sdma.h" | |
70 | #include "sdma.h" | |
71 | #include "verbs.h" /* for the headers */ | |
72 | #include "common.h" /* for struct hfi1_tid_info */ | |
73 | #include "trace.h" | |
74 | ||
75 | static uint hfi1_sdma_comp_ring_size = 128; | |
76 | module_param_named(sdma_comp_size, hfi1_sdma_comp_ring_size, uint, S_IRUGO); | |
77 | MODULE_PARM_DESC(sdma_comp_size, "Size of User SDMA completion ring. Default: 128"); | |
78 | ||
79 | /* The maximum number of Data io vectors per message/request */ | |
80 | #define MAX_VECTORS_PER_REQ 8 | |
81 | /* | |
82 | * Maximum number of packet to send from each message/request | |
83 | * before moving to the next one. | |
84 | */ | |
85 | #define MAX_PKTS_PER_QUEUE 16 | |
86 | ||
87 | #define num_pages(x) (1 + ((((x) - 1) & PAGE_MASK) >> PAGE_SHIFT)) | |
88 | ||
89 | #define req_opcode(x) \ | |
90 | (((x) >> HFI1_SDMA_REQ_OPCODE_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK) | |
91 | #define req_version(x) \ | |
92 | (((x) >> HFI1_SDMA_REQ_VERSION_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK) | |
93 | #define req_iovcnt(x) \ | |
94 | (((x) >> HFI1_SDMA_REQ_IOVCNT_SHIFT) & HFI1_SDMA_REQ_IOVCNT_MASK) | |
95 | ||
96 | /* Number of BTH.PSN bits used for sequence number in expected rcvs */ | |
97 | #define BTH_SEQ_MASK 0x7ffull | |
98 | ||
99 | /* | |
100 | * Define fields in the KDETH header so we can update the header | |
101 | * template. | |
102 | */ | |
103 | #define KDETH_OFFSET_SHIFT 0 | |
104 | #define KDETH_OFFSET_MASK 0x7fff | |
105 | #define KDETH_OM_SHIFT 15 | |
106 | #define KDETH_OM_MASK 0x1 | |
107 | #define KDETH_TID_SHIFT 16 | |
108 | #define KDETH_TID_MASK 0x3ff | |
109 | #define KDETH_TIDCTRL_SHIFT 26 | |
110 | #define KDETH_TIDCTRL_MASK 0x3 | |
111 | #define KDETH_INTR_SHIFT 28 | |
112 | #define KDETH_INTR_MASK 0x1 | |
113 | #define KDETH_SH_SHIFT 29 | |
114 | #define KDETH_SH_MASK 0x1 | |
115 | #define KDETH_HCRC_UPPER_SHIFT 16 | |
116 | #define KDETH_HCRC_UPPER_MASK 0xff | |
117 | #define KDETH_HCRC_LOWER_SHIFT 24 | |
118 | #define KDETH_HCRC_LOWER_MASK 0xff | |
119 | ||
120 | #define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4) | |
121 | #define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff) | |
122 | ||
123 | #define KDETH_GET(val, field) \ | |
124 | (((le32_to_cpu((val))) >> KDETH_##field##_SHIFT) & KDETH_##field##_MASK) | |
125 | #define KDETH_SET(dw, field, val) do { \ | |
126 | u32 dwval = le32_to_cpu(dw); \ | |
127 | dwval &= ~(KDETH_##field##_MASK << KDETH_##field##_SHIFT); \ | |
128 | dwval |= (((val) & KDETH_##field##_MASK) << \ | |
129 | KDETH_##field##_SHIFT); \ | |
130 | dw = cpu_to_le32(dwval); \ | |
131 | } while (0) | |
132 | ||
133 | #define AHG_HEADER_SET(arr, idx, dw, bit, width, value) \ | |
134 | do { \ | |
135 | if ((idx) < ARRAY_SIZE((arr))) \ | |
136 | (arr)[(idx++)] = sdma_build_ahg_descriptor( \ | |
137 | (__force u16)(value), (dw), (bit), \ | |
138 | (width)); \ | |
139 | else \ | |
140 | return -ERANGE; \ | |
141 | } while (0) | |
142 | ||
143 | /* KDETH OM multipliers and switch over point */ | |
144 | #define KDETH_OM_SMALL 4 | |
145 | #define KDETH_OM_LARGE 64 | |
146 | #define KDETH_OM_MAX_SIZE (1 << ((KDETH_OM_LARGE / KDETH_OM_SMALL) + 1)) | |
147 | ||
148 | /* Last packet in the request */ | |
cb32649d | 149 | #define TXREQ_FLAGS_REQ_LAST_PKT BIT(0) |
0f2d87d2 MH |
150 | |
151 | /* Last packet that uses a particular io vector */ | |
cb32649d | 152 | #define TXREQ_FLAGS_IOVEC_LAST_PKT BIT(0) |
77241056 MM |
153 | |
154 | #define SDMA_REQ_IN_USE 0 | |
155 | #define SDMA_REQ_FOR_THREAD 1 | |
156 | #define SDMA_REQ_SEND_DONE 2 | |
157 | #define SDMA_REQ_HAVE_AHG 3 | |
158 | #define SDMA_REQ_HAS_ERROR 4 | |
159 | #define SDMA_REQ_DONE_ERROR 5 | |
160 | ||
cb32649d SK |
161 | #define SDMA_PKT_Q_INACTIVE BIT(0) |
162 | #define SDMA_PKT_Q_ACTIVE BIT(1) | |
163 | #define SDMA_PKT_Q_DEFERRED BIT(2) | |
77241056 MM |
164 | |
165 | /* | |
166 | * Maximum retry attempts to submit a TX request | |
167 | * before putting the process to sleep. | |
168 | */ | |
169 | #define MAX_DEFER_RETRY_COUNT 1 | |
170 | ||
171 | static unsigned initial_pkt_count = 8; | |
172 | ||
173 | #define SDMA_IOWAIT_TIMEOUT 1000 /* in milliseconds */ | |
174 | ||
175 | struct user_sdma_iovec { | |
0f2d87d2 | 176 | struct list_head list; |
77241056 MM |
177 | struct iovec iov; |
178 | /* number of pages in this vector */ | |
179 | unsigned npages; | |
180 | /* array of pinned pages for this vector */ | |
181 | struct page **pages; | |
182 | /* offset into the virtual address space of the vector at | |
183 | * which we last left off. */ | |
184 | u64 offset; | |
185 | }; | |
186 | ||
187 | struct user_sdma_request { | |
188 | struct sdma_req_info info; | |
189 | struct hfi1_user_sdma_pkt_q *pq; | |
190 | struct hfi1_user_sdma_comp_q *cq; | |
191 | /* This is the original header from user space */ | |
192 | struct hfi1_pkt_header hdr; | |
193 | /* | |
194 | * Pointer to the SDMA engine for this request. | |
195 | * Since different request could be on different VLs, | |
196 | * each request will need it's own engine pointer. | |
197 | */ | |
198 | struct sdma_engine *sde; | |
199 | u8 ahg_idx; | |
200 | u32 ahg[9]; | |
201 | /* | |
202 | * KDETH.Offset (Eager) field | |
203 | * We need to remember the initial value so the headers | |
204 | * can be updated properly. | |
205 | */ | |
206 | u32 koffset; | |
207 | /* | |
208 | * KDETH.OFFSET (TID) field | |
209 | * The offset can cover multiple packets, depending on the | |
210 | * size of the TID entry. | |
211 | */ | |
212 | u32 tidoffset; | |
213 | /* | |
214 | * KDETH.OM | |
215 | * Remember this because the header template always sets it | |
216 | * to 0. | |
217 | */ | |
218 | u8 omfactor; | |
77241056 MM |
219 | /* |
220 | * We copy the iovs for this request (based on | |
221 | * info.iovcnt). These are only the data vectors | |
222 | */ | |
223 | unsigned data_iovs; | |
224 | /* total length of the data in the request */ | |
225 | u32 data_len; | |
226 | /* progress index moving along the iovs array */ | |
227 | unsigned iov_idx; | |
228 | struct user_sdma_iovec iovs[MAX_VECTORS_PER_REQ]; | |
229 | /* number of elements copied to the tids array */ | |
230 | u16 n_tids; | |
231 | /* TID array values copied from the tid_iov vector */ | |
232 | u32 *tids; | |
233 | u16 tididx; | |
234 | u32 sent; | |
235 | u64 seqnum; | |
0f2d87d2 | 236 | u64 seqcomp; |
c7cbf2fa | 237 | u64 seqsubmitted; |
77241056 MM |
238 | struct list_head txps; |
239 | unsigned long flags; | |
a0d40693 MH |
240 | /* status of the last txreq completed */ |
241 | int status; | |
77241056 MM |
242 | }; |
243 | ||
b9fb6318 MH |
244 | /* |
245 | * A single txreq could span up to 3 physical pages when the MTU | |
246 | * is sufficiently large (> 4K). Each of the IOV pointers also | |
247 | * needs it's own set of flags so the vector has been handled | |
248 | * independently of each other. | |
249 | */ | |
77241056 MM |
250 | struct user_sdma_txreq { |
251 | /* Packet header for the txreq */ | |
252 | struct hfi1_pkt_header hdr; | |
253 | struct sdma_txreq txreq; | |
a0d40693 | 254 | struct list_head list; |
77241056 | 255 | struct user_sdma_request *req; |
b9fb6318 MH |
256 | struct { |
257 | struct user_sdma_iovec *vec; | |
258 | u8 flags; | |
259 | } iovecs[3]; | |
260 | int idx; | |
77241056 MM |
261 | u16 flags; |
262 | unsigned busycount; | |
263 | u64 seqnum; | |
264 | }; | |
265 | ||
266 | #define SDMA_DBG(req, fmt, ...) \ | |
267 | hfi1_cdbg(SDMA, "[%u:%u:%u:%u] " fmt, (req)->pq->dd->unit, \ | |
268 | (req)->pq->ctxt, (req)->pq->subctxt, (req)->info.comp_idx, \ | |
269 | ##__VA_ARGS__) | |
270 | #define SDMA_Q_DBG(pq, fmt, ...) \ | |
271 | hfi1_cdbg(SDMA, "[%u:%u:%u] " fmt, (pq)->dd->unit, (pq)->ctxt, \ | |
272 | (pq)->subctxt, ##__VA_ARGS__) | |
273 | ||
274 | static int user_sdma_send_pkts(struct user_sdma_request *, unsigned); | |
275 | static int num_user_pages(const struct iovec *); | |
a545f530 | 276 | static void user_sdma_txreq_cb(struct sdma_txreq *, int); |
0f2d87d2 MH |
277 | static inline void pq_update(struct hfi1_user_sdma_pkt_q *); |
278 | static void user_sdma_free_request(struct user_sdma_request *, bool); | |
77241056 MM |
279 | static int pin_vector_pages(struct user_sdma_request *, |
280 | struct user_sdma_iovec *); | |
0f2d87d2 | 281 | static void unpin_vector_pages(struct user_sdma_iovec *); |
77241056 MM |
282 | static int check_header_template(struct user_sdma_request *, |
283 | struct hfi1_pkt_header *, u32, u32); | |
284 | static int set_txreq_header(struct user_sdma_request *, | |
285 | struct user_sdma_txreq *, u32); | |
286 | static int set_txreq_header_ahg(struct user_sdma_request *, | |
287 | struct user_sdma_txreq *, u32); | |
0f2d87d2 MH |
288 | static inline void set_comp_state(struct hfi1_user_sdma_pkt_q *, |
289 | struct hfi1_user_sdma_comp_q *, | |
290 | u16, enum hfi1_sdma_comp_state, int); | |
77241056 MM |
291 | static inline u32 set_pkt_bth_psn(__be32, u8, u32); |
292 | static inline u32 get_lrh_len(struct hfi1_pkt_header, u32 len); | |
293 | ||
294 | static int defer_packet_queue( | |
295 | struct sdma_engine *, | |
296 | struct iowait *, | |
297 | struct sdma_txreq *, | |
298 | unsigned seq); | |
299 | static void activate_packet_queue(struct iowait *, int); | |
300 | ||
77241056 MM |
301 | static int defer_packet_queue( |
302 | struct sdma_engine *sde, | |
303 | struct iowait *wait, | |
304 | struct sdma_txreq *txreq, | |
305 | unsigned seq) | |
306 | { | |
307 | struct hfi1_user_sdma_pkt_q *pq = | |
308 | container_of(wait, struct hfi1_user_sdma_pkt_q, busy); | |
309 | struct hfi1_ibdev *dev = &pq->dd->verbs_dev; | |
310 | struct user_sdma_txreq *tx = | |
311 | container_of(txreq, struct user_sdma_txreq, txreq); | |
312 | ||
313 | if (sdma_progress(sde, seq, txreq)) { | |
314 | if (tx->busycount++ < MAX_DEFER_RETRY_COUNT) | |
315 | goto eagain; | |
316 | } | |
317 | /* | |
318 | * We are assuming that if the list is enqueued somewhere, it | |
319 | * is to the dmawait list since that is the only place where | |
320 | * it is supposed to be enqueued. | |
321 | */ | |
322 | xchg(&pq->state, SDMA_PKT_Q_DEFERRED); | |
323 | write_seqlock(&dev->iowait_lock); | |
324 | if (list_empty(&pq->busy.list)) | |
325 | list_add_tail(&pq->busy.list, &sde->dmawait); | |
326 | write_sequnlock(&dev->iowait_lock); | |
327 | return -EBUSY; | |
328 | eagain: | |
329 | return -EAGAIN; | |
330 | } | |
331 | ||
332 | static void activate_packet_queue(struct iowait *wait, int reason) | |
333 | { | |
334 | struct hfi1_user_sdma_pkt_q *pq = | |
335 | container_of(wait, struct hfi1_user_sdma_pkt_q, busy); | |
336 | xchg(&pq->state, SDMA_PKT_Q_ACTIVE); | |
337 | wake_up(&wait->wait_dma); | |
338 | }; | |
339 | ||
340 | static void sdma_kmem_cache_ctor(void *obj) | |
341 | { | |
342 | struct user_sdma_txreq *tx = (struct user_sdma_txreq *)obj; | |
343 | ||
344 | memset(tx, 0, sizeof(*tx)); | |
345 | } | |
346 | ||
347 | int hfi1_user_sdma_alloc_queues(struct hfi1_ctxtdata *uctxt, struct file *fp) | |
348 | { | |
9e10af47 | 349 | struct hfi1_filedata *fd; |
77241056 MM |
350 | int ret = 0; |
351 | unsigned memsize; | |
352 | char buf[64]; | |
353 | struct hfi1_devdata *dd; | |
354 | struct hfi1_user_sdma_comp_q *cq; | |
355 | struct hfi1_user_sdma_pkt_q *pq; | |
356 | unsigned long flags; | |
357 | ||
358 | if (!uctxt || !fp) { | |
359 | ret = -EBADF; | |
360 | goto done; | |
361 | } | |
362 | ||
9e10af47 IW |
363 | fd = fp->private_data; |
364 | ||
77241056 MM |
365 | if (!hfi1_sdma_comp_ring_size) { |
366 | ret = -EINVAL; | |
367 | goto done; | |
368 | } | |
369 | ||
370 | dd = uctxt->dd; | |
371 | ||
372 | pq = kzalloc(sizeof(*pq), GFP_KERNEL); | |
806e6e1b | 373 | if (!pq) |
77241056 | 374 | goto pq_nomem; |
806e6e1b | 375 | |
77241056 | 376 | memsize = sizeof(*pq->reqs) * hfi1_sdma_comp_ring_size; |
0f2d87d2 | 377 | pq->reqs = kzalloc(memsize, GFP_KERNEL); |
806e6e1b | 378 | if (!pq->reqs) |
77241056 | 379 | goto pq_reqs_nomem; |
806e6e1b | 380 | |
77241056 MM |
381 | INIT_LIST_HEAD(&pq->list); |
382 | pq->dd = dd; | |
383 | pq->ctxt = uctxt->ctxt; | |
9e10af47 | 384 | pq->subctxt = fd->subctxt; |
77241056 MM |
385 | pq->n_max_reqs = hfi1_sdma_comp_ring_size; |
386 | pq->state = SDMA_PKT_Q_INACTIVE; | |
387 | atomic_set(&pq->n_reqs, 0); | |
a0d40693 | 388 | init_waitqueue_head(&pq->wait); |
77241056 MM |
389 | |
390 | iowait_init(&pq->busy, 0, NULL, defer_packet_queue, | |
a545f530 | 391 | activate_packet_queue, NULL); |
77241056 MM |
392 | pq->reqidx = 0; |
393 | snprintf(buf, 64, "txreq-kmem-cache-%u-%u-%u", dd->unit, uctxt->ctxt, | |
9e10af47 | 394 | fd->subctxt); |
77241056 MM |
395 | pq->txreq_cache = kmem_cache_create(buf, |
396 | sizeof(struct user_sdma_txreq), | |
397 | L1_CACHE_BYTES, | |
398 | SLAB_HWCACHE_ALIGN, | |
399 | sdma_kmem_cache_ctor); | |
400 | if (!pq->txreq_cache) { | |
401 | dd_dev_err(dd, "[%u] Failed to allocate TxReq cache\n", | |
402 | uctxt->ctxt); | |
403 | goto pq_txreq_nomem; | |
404 | } | |
9e10af47 | 405 | fd->pq = pq; |
77241056 | 406 | cq = kzalloc(sizeof(*cq), GFP_KERNEL); |
806e6e1b | 407 | if (!cq) |
77241056 | 408 | goto cq_nomem; |
77241056 MM |
409 | |
410 | memsize = ALIGN(sizeof(*cq->comps) * hfi1_sdma_comp_ring_size, | |
411 | PAGE_SIZE); | |
412 | cq->comps = vmalloc_user(memsize); | |
806e6e1b | 413 | if (!cq->comps) |
77241056 | 414 | goto cq_comps_nomem; |
806e6e1b | 415 | |
77241056 | 416 | cq->nentries = hfi1_sdma_comp_ring_size; |
9e10af47 | 417 | fd->cq = cq; |
77241056 MM |
418 | |
419 | spin_lock_irqsave(&uctxt->sdma_qlock, flags); | |
420 | list_add(&pq->list, &uctxt->sdma_queues); | |
421 | spin_unlock_irqrestore(&uctxt->sdma_qlock, flags); | |
422 | goto done; | |
423 | ||
424 | cq_comps_nomem: | |
425 | kfree(cq); | |
426 | cq_nomem: | |
427 | kmem_cache_destroy(pq->txreq_cache); | |
428 | pq_txreq_nomem: | |
429 | kfree(pq->reqs); | |
430 | pq_reqs_nomem: | |
431 | kfree(pq); | |
9e10af47 | 432 | fd->pq = NULL; |
77241056 MM |
433 | pq_nomem: |
434 | ret = -ENOMEM; | |
435 | done: | |
436 | return ret; | |
437 | } | |
438 | ||
439 | int hfi1_user_sdma_free_queues(struct hfi1_filedata *fd) | |
440 | { | |
441 | struct hfi1_ctxtdata *uctxt = fd->uctxt; | |
442 | struct hfi1_user_sdma_pkt_q *pq; | |
443 | unsigned long flags; | |
444 | ||
445 | hfi1_cdbg(SDMA, "[%u:%u:%u] Freeing user SDMA queues", uctxt->dd->unit, | |
446 | uctxt->ctxt, fd->subctxt); | |
447 | pq = fd->pq; | |
448 | if (pq) { | |
77241056 MM |
449 | spin_lock_irqsave(&uctxt->sdma_qlock, flags); |
450 | if (!list_empty(&pq->list)) | |
451 | list_del_init(&pq->list); | |
452 | spin_unlock_irqrestore(&uctxt->sdma_qlock, flags); | |
453 | iowait_sdma_drain(&pq->busy); | |
a0d40693 MH |
454 | /* Wait until all requests have been freed. */ |
455 | wait_event_interruptible( | |
456 | pq->wait, | |
457 | (ACCESS_ONCE(pq->state) == SDMA_PKT_Q_INACTIVE)); | |
458 | kfree(pq->reqs); | |
adad44d1 | 459 | kmem_cache_destroy(pq->txreq_cache); |
77241056 MM |
460 | kfree(pq); |
461 | fd->pq = NULL; | |
462 | } | |
463 | if (fd->cq) { | |
464 | if (fd->cq->comps) | |
465 | vfree(fd->cq->comps); | |
466 | kfree(fd->cq); | |
467 | fd->cq = NULL; | |
468 | } | |
469 | return 0; | |
470 | } | |
471 | ||
472 | int hfi1_user_sdma_process_request(struct file *fp, struct iovec *iovec, | |
473 | unsigned long dim, unsigned long *count) | |
474 | { | |
0f2d87d2 | 475 | int ret = 0, i = 0; |
9e10af47 IW |
476 | struct hfi1_filedata *fd = fp->private_data; |
477 | struct hfi1_ctxtdata *uctxt = fd->uctxt; | |
478 | struct hfi1_user_sdma_pkt_q *pq = fd->pq; | |
479 | struct hfi1_user_sdma_comp_q *cq = fd->cq; | |
77241056 | 480 | struct hfi1_devdata *dd = pq->dd; |
0840aea9 | 481 | unsigned long idx = 0, unpinned; |
77241056 MM |
482 | u8 pcount = initial_pkt_count; |
483 | struct sdma_req_info info; | |
484 | struct user_sdma_request *req; | |
485 | u8 opcode, sc, vl; | |
486 | ||
487 | if (iovec[idx].iov_len < sizeof(info) + sizeof(req->hdr)) { | |
488 | hfi1_cdbg( | |
489 | SDMA, | |
490 | "[%u:%u:%u] First vector not big enough for header %lu/%lu", | |
9e10af47 | 491 | dd->unit, uctxt->ctxt, fd->subctxt, |
77241056 | 492 | iovec[idx].iov_len, sizeof(info) + sizeof(req->hdr)); |
faa98b86 | 493 | return -EINVAL; |
77241056 MM |
494 | } |
495 | ret = copy_from_user(&info, iovec[idx].iov_base, sizeof(info)); | |
496 | if (ret) { | |
497 | hfi1_cdbg(SDMA, "[%u:%u:%u] Failed to copy info QW (%d)", | |
9e10af47 | 498 | dd->unit, uctxt->ctxt, fd->subctxt, ret); |
faa98b86 | 499 | return -EFAULT; |
77241056 | 500 | } |
0f2d87d2 MH |
501 | |
502 | /* Process any completed vectors */ | |
0840aea9 MH |
503 | unpinned = xchg(&pq->unpinned, 0); |
504 | if (unpinned) { | |
505 | down_write(¤t->mm->mmap_sem); | |
506 | current->mm->pinned_vm -= unpinned; | |
507 | up_write(¤t->mm->mmap_sem); | |
0f2d87d2 MH |
508 | } |
509 | ||
9e10af47 | 510 | trace_hfi1_sdma_user_reqinfo(dd, uctxt->ctxt, fd->subctxt, |
77241056 | 511 | (u16 *)&info); |
0f2d87d2 MH |
512 | if (cq->comps[info.comp_idx].status == QUEUED || |
513 | test_bit(SDMA_REQ_IN_USE, &pq->reqs[info.comp_idx].flags)) { | |
77241056 | 514 | hfi1_cdbg(SDMA, "[%u:%u:%u] Entry %u is in QUEUED state", |
9e10af47 | 515 | dd->unit, uctxt->ctxt, fd->subctxt, |
77241056 | 516 | info.comp_idx); |
faa98b86 | 517 | return -EBADSLT; |
77241056 MM |
518 | } |
519 | if (!info.fragsize) { | |
520 | hfi1_cdbg(SDMA, | |
521 | "[%u:%u:%u:%u] Request does not specify fragsize", | |
9e10af47 | 522 | dd->unit, uctxt->ctxt, fd->subctxt, info.comp_idx); |
faa98b86 | 523 | return -EINVAL; |
77241056 MM |
524 | } |
525 | /* | |
526 | * We've done all the safety checks that we can up to this point, | |
527 | * "allocate" the request entry. | |
528 | */ | |
529 | hfi1_cdbg(SDMA, "[%u:%u:%u] Using req/comp entry %u\n", dd->unit, | |
9e10af47 | 530 | uctxt->ctxt, fd->subctxt, info.comp_idx); |
77241056 MM |
531 | req = pq->reqs + info.comp_idx; |
532 | memset(req, 0, sizeof(*req)); | |
533 | /* Mark the request as IN_USE before we start filling it in. */ | |
534 | set_bit(SDMA_REQ_IN_USE, &req->flags); | |
535 | req->data_iovs = req_iovcnt(info.ctrl) - 1; | |
536 | req->pq = pq; | |
537 | req->cq = cq; | |
a0d40693 | 538 | req->status = -1; |
77241056 | 539 | INIT_LIST_HEAD(&req->txps); |
a0d40693 | 540 | |
77241056 MM |
541 | memcpy(&req->info, &info, sizeof(info)); |
542 | ||
543 | if (req_opcode(info.ctrl) == EXPECTED) | |
544 | req->data_iovs--; | |
545 | ||
546 | if (!info.npkts || req->data_iovs > MAX_VECTORS_PER_REQ) { | |
547 | SDMA_DBG(req, "Too many vectors (%u/%u)", req->data_iovs, | |
548 | MAX_VECTORS_PER_REQ); | |
faa98b86 | 549 | return -EINVAL; |
77241056 MM |
550 | } |
551 | /* Copy the header from the user buffer */ | |
552 | ret = copy_from_user(&req->hdr, iovec[idx].iov_base + sizeof(info), | |
553 | sizeof(req->hdr)); | |
554 | if (ret) { | |
555 | SDMA_DBG(req, "Failed to copy header template (%d)", ret); | |
556 | ret = -EFAULT; | |
557 | goto free_req; | |
558 | } | |
559 | ||
560 | /* If Static rate control is not enabled, sanitize the header. */ | |
561 | if (!HFI1_CAP_IS_USET(STATIC_RATE_CTRL)) | |
562 | req->hdr.pbc[2] = 0; | |
563 | ||
564 | /* Validate the opcode. Do not trust packets from user space blindly. */ | |
565 | opcode = (be32_to_cpu(req->hdr.bth[0]) >> 24) & 0xff; | |
566 | if ((opcode & USER_OPCODE_CHECK_MASK) != | |
567 | USER_OPCODE_CHECK_VAL) { | |
568 | SDMA_DBG(req, "Invalid opcode (%d)", opcode); | |
569 | ret = -EINVAL; | |
570 | goto free_req; | |
571 | } | |
572 | /* | |
573 | * Validate the vl. Do not trust packets from user space blindly. | |
574 | * VL comes from PBC, SC comes from LRH, and the VL needs to | |
575 | * match the SC look up. | |
576 | */ | |
577 | vl = (le16_to_cpu(req->hdr.pbc[0]) >> 12) & 0xF; | |
578 | sc = (((be16_to_cpu(req->hdr.lrh[0]) >> 12) & 0xF) | | |
579 | (((le16_to_cpu(req->hdr.pbc[1]) >> 14) & 0x1) << 4)); | |
580 | if (vl >= dd->pport->vls_operational || | |
581 | vl != sc_to_vlt(dd, sc)) { | |
582 | SDMA_DBG(req, "Invalid SC(%u)/VL(%u)", sc, vl); | |
583 | ret = -EINVAL; | |
584 | goto free_req; | |
585 | } | |
586 | ||
587 | /* | |
588 | * Also should check the BTH.lnh. If it says the next header is GRH then | |
589 | * the RXE parsing will be off and will land in the middle of the KDETH | |
590 | * or miss it entirely. | |
591 | */ | |
592 | if ((be16_to_cpu(req->hdr.lrh[0]) & 0x3) == HFI1_LRH_GRH) { | |
593 | SDMA_DBG(req, "User tried to pass in a GRH"); | |
594 | ret = -EINVAL; | |
595 | goto free_req; | |
596 | } | |
597 | ||
598 | req->koffset = le32_to_cpu(req->hdr.kdeth.swdata[6]); | |
599 | /* Calculate the initial TID offset based on the values of | |
600 | KDETH.OFFSET and KDETH.OM that are passed in. */ | |
601 | req->tidoffset = KDETH_GET(req->hdr.kdeth.ver_tid_offset, OFFSET) * | |
602 | (KDETH_GET(req->hdr.kdeth.ver_tid_offset, OM) ? | |
603 | KDETH_OM_LARGE : KDETH_OM_SMALL); | |
604 | SDMA_DBG(req, "Initial TID offset %u", req->tidoffset); | |
605 | idx++; | |
606 | ||
607 | /* Save all the IO vector structures */ | |
608 | while (i < req->data_iovs) { | |
0f2d87d2 | 609 | INIT_LIST_HEAD(&req->iovs[i].list); |
77241056 MM |
610 | memcpy(&req->iovs[i].iov, iovec + idx++, sizeof(struct iovec)); |
611 | req->iovs[i].offset = 0; | |
612 | req->data_len += req->iovs[i++].iov.iov_len; | |
613 | } | |
614 | SDMA_DBG(req, "total data length %u", req->data_len); | |
615 | ||
616 | if (pcount > req->info.npkts) | |
617 | pcount = req->info.npkts; | |
618 | /* | |
619 | * Copy any TID info | |
620 | * User space will provide the TID info only when the | |
621 | * request type is EXPECTED. This is true even if there is | |
622 | * only one packet in the request and the header is already | |
623 | * setup. The reason for the singular TID case is that the | |
624 | * driver needs to perform safety checks. | |
625 | */ | |
626 | if (req_opcode(req->info.ctrl) == EXPECTED) { | |
627 | u16 ntids = iovec[idx].iov_len / sizeof(*req->tids); | |
628 | ||
629 | if (!ntids || ntids > MAX_TID_PAIR_ENTRIES) { | |
630 | ret = -EINVAL; | |
631 | goto free_req; | |
632 | } | |
633 | req->tids = kcalloc(ntids, sizeof(*req->tids), GFP_KERNEL); | |
634 | if (!req->tids) { | |
635 | ret = -ENOMEM; | |
636 | goto free_req; | |
637 | } | |
638 | /* | |
639 | * We have to copy all of the tids because they may vary | |
640 | * in size and, therefore, the TID count might not be | |
641 | * equal to the pkt count. However, there is no way to | |
642 | * tell at this point. | |
643 | */ | |
644 | ret = copy_from_user(req->tids, iovec[idx].iov_base, | |
645 | ntids * sizeof(*req->tids)); | |
646 | if (ret) { | |
647 | SDMA_DBG(req, "Failed to copy %d TIDs (%d)", | |
648 | ntids, ret); | |
649 | ret = -EFAULT; | |
650 | goto free_req; | |
651 | } | |
652 | req->n_tids = ntids; | |
653 | idx++; | |
654 | } | |
655 | ||
656 | /* Have to select the engine */ | |
657 | req->sde = sdma_select_engine_vl(dd, | |
9e10af47 | 658 | (u32)(uctxt->ctxt + fd->subctxt), |
77241056 MM |
659 | vl); |
660 | if (!req->sde || !sdma_running(req->sde)) { | |
661 | ret = -ECOMM; | |
662 | goto free_req; | |
663 | } | |
664 | ||
665 | /* We don't need an AHG entry if the request contains only one packet */ | |
666 | if (req->info.npkts > 1 && HFI1_CAP_IS_USET(SDMA_AHG)) { | |
667 | int ahg = sdma_ahg_alloc(req->sde); | |
668 | ||
669 | if (likely(ahg >= 0)) { | |
670 | req->ahg_idx = (u8)ahg; | |
671 | set_bit(SDMA_REQ_HAVE_AHG, &req->flags); | |
672 | } | |
673 | } | |
674 | ||
0f2d87d2 MH |
675 | set_comp_state(pq, cq, info.comp_idx, QUEUED, 0); |
676 | atomic_inc(&pq->n_reqs); | |
77241056 | 677 | /* Send the first N packets in the request to buy us some time */ |
0f2d87d2 MH |
678 | ret = user_sdma_send_pkts(req, pcount); |
679 | if (unlikely(ret < 0 && ret != -EBUSY)) { | |
680 | req->status = ret; | |
0f2d87d2 | 681 | goto free_req; |
77241056 | 682 | } |
77241056 | 683 | |
0f2d87d2 MH |
684 | /* |
685 | * It is possible that the SDMA engine would have processed all the | |
686 | * submitted packets by the time we get here. Therefore, only set | |
687 | * packet queue state to ACTIVE if there are still uncompleted | |
688 | * requests. | |
689 | */ | |
690 | if (atomic_read(&pq->n_reqs)) | |
691 | xchg(&pq->state, SDMA_PKT_Q_ACTIVE); | |
692 | ||
693 | /* | |
694 | * This is a somewhat blocking send implementation. | |
695 | * The driver will block the caller until all packets of the | |
696 | * request have been submitted to the SDMA engine. However, it | |
697 | * will not wait for send completions. | |
698 | */ | |
699 | while (!test_bit(SDMA_REQ_SEND_DONE, &req->flags)) { | |
700 | ret = user_sdma_send_pkts(req, pcount); | |
701 | if (ret < 0) { | |
702 | if (ret != -EBUSY) { | |
703 | req->status = ret; | |
704 | set_bit(SDMA_REQ_DONE_ERROR, &req->flags); | |
a402d6ab MH |
705 | if (ACCESS_ONCE(req->seqcomp) == |
706 | req->seqsubmitted - 1) | |
707 | goto free_req; | |
0f2d87d2 | 708 | return ret; |
77241056 | 709 | } |
0f2d87d2 MH |
710 | wait_event_interruptible_timeout( |
711 | pq->busy.wait_dma, | |
712 | (pq->state == SDMA_PKT_Q_ACTIVE), | |
713 | msecs_to_jiffies( | |
714 | SDMA_IOWAIT_TIMEOUT)); | |
77241056 | 715 | } |
77241056 | 716 | } |
77241056 | 717 | *count += idx; |
a0d40693 | 718 | return 0; |
77241056 | 719 | free_req: |
0f2d87d2 | 720 | user_sdma_free_request(req, true); |
a402d6ab | 721 | pq_update(pq); |
0f2d87d2 | 722 | set_comp_state(pq, cq, info.comp_idx, ERROR, req->status); |
77241056 MM |
723 | return ret; |
724 | } | |
725 | ||
726 | static inline u32 compute_data_length(struct user_sdma_request *req, | |
727 | struct user_sdma_txreq *tx) | |
728 | { | |
729 | /* | |
730 | * Determine the proper size of the packet data. | |
731 | * The size of the data of the first packet is in the header | |
732 | * template. However, it includes the header and ICRC, which need | |
733 | * to be subtracted. | |
734 | * The size of the remaining packets is the minimum of the frag | |
735 | * size (MTU) or remaining data in the request. | |
736 | */ | |
737 | u32 len; | |
738 | ||
739 | if (!req->seqnum) { | |
740 | len = ((be16_to_cpu(req->hdr.lrh[2]) << 2) - | |
741 | (sizeof(tx->hdr) - 4)); | |
742 | } else if (req_opcode(req->info.ctrl) == EXPECTED) { | |
743 | u32 tidlen = EXP_TID_GET(req->tids[req->tididx], LEN) * | |
744 | PAGE_SIZE; | |
745 | /* Get the data length based on the remaining space in the | |
746 | * TID pair. */ | |
747 | len = min(tidlen - req->tidoffset, (u32)req->info.fragsize); | |
748 | /* If we've filled up the TID pair, move to the next one. */ | |
749 | if (unlikely(!len) && ++req->tididx < req->n_tids && | |
750 | req->tids[req->tididx]) { | |
751 | tidlen = EXP_TID_GET(req->tids[req->tididx], | |
752 | LEN) * PAGE_SIZE; | |
753 | req->tidoffset = 0; | |
754 | len = min_t(u32, tidlen, req->info.fragsize); | |
755 | } | |
756 | /* Since the TID pairs map entire pages, make sure that we | |
757 | * are not going to try to send more data that we have | |
758 | * remaining. */ | |
759 | len = min(len, req->data_len - req->sent); | |
760 | } else | |
761 | len = min(req->data_len - req->sent, (u32)req->info.fragsize); | |
762 | SDMA_DBG(req, "Data Length = %u", len); | |
763 | return len; | |
764 | } | |
765 | ||
766 | static inline u32 get_lrh_len(struct hfi1_pkt_header hdr, u32 len) | |
767 | { | |
768 | /* (Size of complete header - size of PBC) + 4B ICRC + data length */ | |
769 | return ((sizeof(hdr) - sizeof(hdr.pbc)) + 4 + len); | |
770 | } | |
771 | ||
772 | static int user_sdma_send_pkts(struct user_sdma_request *req, unsigned maxpkts) | |
773 | { | |
774 | int ret = 0; | |
775 | unsigned npkts = 0; | |
776 | struct user_sdma_txreq *tx = NULL; | |
777 | struct hfi1_user_sdma_pkt_q *pq = NULL; | |
778 | struct user_sdma_iovec *iovec = NULL; | |
779 | ||
faa98b86 MH |
780 | if (!req->pq) |
781 | return -EINVAL; | |
77241056 MM |
782 | |
783 | pq = req->pq; | |
784 | ||
6a5464f2 MH |
785 | /* If tx completion has reported an error, we are done. */ |
786 | if (test_bit(SDMA_REQ_HAS_ERROR, &req->flags)) { | |
787 | set_bit(SDMA_REQ_DONE_ERROR, &req->flags); | |
788 | return -EFAULT; | |
789 | } | |
790 | ||
77241056 MM |
791 | /* |
792 | * Check if we might have sent the entire request already | |
793 | */ | |
794 | if (unlikely(req->seqnum == req->info.npkts)) { | |
795 | if (!list_empty(&req->txps)) | |
796 | goto dosend; | |
faa98b86 | 797 | return ret; |
77241056 MM |
798 | } |
799 | ||
800 | if (!maxpkts || maxpkts > req->info.npkts - req->seqnum) | |
801 | maxpkts = req->info.npkts - req->seqnum; | |
802 | ||
803 | while (npkts < maxpkts) { | |
804 | u32 datalen = 0, queued = 0, data_sent = 0; | |
805 | u64 iov_offset = 0; | |
806 | ||
807 | /* | |
808 | * Check whether any of the completions have come back | |
809 | * with errors. If so, we are not going to process any | |
810 | * more packets from this request. | |
811 | */ | |
812 | if (test_bit(SDMA_REQ_HAS_ERROR, &req->flags)) { | |
813 | set_bit(SDMA_REQ_DONE_ERROR, &req->flags); | |
faa98b86 | 814 | return -EFAULT; |
77241056 MM |
815 | } |
816 | ||
817 | tx = kmem_cache_alloc(pq->txreq_cache, GFP_KERNEL); | |
faa98b86 MH |
818 | if (!tx) |
819 | return -ENOMEM; | |
820 | ||
77241056 MM |
821 | tx->flags = 0; |
822 | tx->req = req; | |
823 | tx->busycount = 0; | |
b9fb6318 | 824 | tx->idx = -1; |
a0d40693 | 825 | INIT_LIST_HEAD(&tx->list); |
b9fb6318 | 826 | memset(tx->iovecs, 0, sizeof(tx->iovecs)); |
77241056 MM |
827 | |
828 | if (req->seqnum == req->info.npkts - 1) | |
b9fb6318 | 829 | tx->flags |= TXREQ_FLAGS_REQ_LAST_PKT; |
77241056 MM |
830 | |
831 | /* | |
832 | * Calculate the payload size - this is min of the fragment | |
833 | * (MTU) size or the remaining bytes in the request but only | |
834 | * if we have payload data. | |
835 | */ | |
836 | if (req->data_len) { | |
837 | iovec = &req->iovs[req->iov_idx]; | |
838 | if (ACCESS_ONCE(iovec->offset) == iovec->iov.iov_len) { | |
839 | if (++req->iov_idx == req->data_iovs) { | |
840 | ret = -EFAULT; | |
841 | goto free_txreq; | |
842 | } | |
843 | iovec = &req->iovs[req->iov_idx]; | |
844 | WARN_ON(iovec->offset); | |
845 | } | |
846 | ||
847 | /* | |
848 | * This request might include only a header and no user | |
849 | * data, so pin pages only if there is data and it the | |
850 | * pages have not been pinned already. | |
851 | */ | |
852 | if (unlikely(!iovec->pages && iovec->iov.iov_len)) { | |
853 | ret = pin_vector_pages(req, iovec); | |
854 | if (ret) | |
855 | goto free_tx; | |
856 | } | |
857 | ||
b9fb6318 | 858 | tx->iovecs[++tx->idx].vec = iovec; |
77241056 MM |
859 | datalen = compute_data_length(req, tx); |
860 | if (!datalen) { | |
861 | SDMA_DBG(req, | |
862 | "Request has data but pkt len is 0"); | |
863 | ret = -EFAULT; | |
864 | goto free_tx; | |
865 | } | |
866 | } | |
867 | ||
868 | if (test_bit(SDMA_REQ_HAVE_AHG, &req->flags)) { | |
869 | if (!req->seqnum) { | |
870 | u16 pbclen = le16_to_cpu(req->hdr.pbc[0]); | |
871 | u32 lrhlen = get_lrh_len(req->hdr, datalen); | |
872 | /* | |
873 | * Copy the request header into the tx header | |
874 | * because the HW needs a cacheline-aligned | |
875 | * address. | |
876 | * This copy can be optimized out if the hdr | |
877 | * member of user_sdma_request were also | |
878 | * cacheline aligned. | |
879 | */ | |
880 | memcpy(&tx->hdr, &req->hdr, sizeof(tx->hdr)); | |
881 | if (PBC2LRH(pbclen) != lrhlen) { | |
882 | pbclen = (pbclen & 0xf000) | | |
883 | LRH2PBC(lrhlen); | |
884 | tx->hdr.pbc[0] = cpu_to_le16(pbclen); | |
885 | } | |
886 | ret = sdma_txinit_ahg(&tx->txreq, | |
887 | SDMA_TXREQ_F_AHG_COPY, | |
888 | sizeof(tx->hdr) + datalen, | |
889 | req->ahg_idx, 0, NULL, 0, | |
890 | user_sdma_txreq_cb); | |
891 | if (ret) | |
892 | goto free_tx; | |
893 | ret = sdma_txadd_kvaddr(pq->dd, &tx->txreq, | |
894 | &tx->hdr, | |
895 | sizeof(tx->hdr)); | |
896 | if (ret) | |
897 | goto free_txreq; | |
898 | } else { | |
899 | int changes; | |
900 | ||
901 | changes = set_txreq_header_ahg(req, tx, | |
902 | datalen); | |
903 | if (changes < 0) | |
904 | goto free_tx; | |
905 | sdma_txinit_ahg(&tx->txreq, | |
906 | SDMA_TXREQ_F_USE_AHG, | |
907 | datalen, req->ahg_idx, changes, | |
908 | req->ahg, sizeof(req->hdr), | |
909 | user_sdma_txreq_cb); | |
910 | } | |
911 | } else { | |
912 | ret = sdma_txinit(&tx->txreq, 0, sizeof(req->hdr) + | |
913 | datalen, user_sdma_txreq_cb); | |
914 | if (ret) | |
915 | goto free_tx; | |
916 | /* | |
917 | * Modify the header for this packet. This only needs | |
918 | * to be done if we are not going to use AHG. Otherwise, | |
919 | * the HW will do it based on the changes we gave it | |
920 | * during sdma_txinit_ahg(). | |
921 | */ | |
922 | ret = set_txreq_header(req, tx, datalen); | |
923 | if (ret) | |
924 | goto free_txreq; | |
925 | } | |
926 | ||
927 | /* | |
928 | * If the request contains any data vectors, add up to | |
929 | * fragsize bytes to the descriptor. | |
930 | */ | |
931 | while (queued < datalen && | |
932 | (req->sent + data_sent) < req->data_len) { | |
933 | unsigned long base, offset; | |
934 | unsigned pageidx, len; | |
935 | ||
936 | base = (unsigned long)iovec->iov.iov_base; | |
937 | offset = ((base + iovec->offset + iov_offset) & | |
938 | ~PAGE_MASK); | |
939 | pageidx = (((iovec->offset + iov_offset + | |
940 | base) - (base & PAGE_MASK)) >> PAGE_SHIFT); | |
941 | len = offset + req->info.fragsize > PAGE_SIZE ? | |
942 | PAGE_SIZE - offset : req->info.fragsize; | |
943 | len = min((datalen - queued), len); | |
944 | ret = sdma_txadd_page(pq->dd, &tx->txreq, | |
945 | iovec->pages[pageidx], | |
946 | offset, len); | |
947 | if (ret) { | |
a0d40693 MH |
948 | SDMA_DBG(req, "SDMA txreq add page failed %d\n", |
949 | ret); | |
77241056 MM |
950 | goto free_txreq; |
951 | } | |
952 | iov_offset += len; | |
953 | queued += len; | |
954 | data_sent += len; | |
955 | if (unlikely(queued < datalen && | |
956 | pageidx == iovec->npages && | |
b9fb6318 MH |
957 | req->iov_idx < req->data_iovs - 1 && |
958 | tx->idx < ARRAY_SIZE(tx->iovecs))) { | |
77241056 | 959 | iovec->offset += iov_offset; |
b9fb6318 MH |
960 | tx->iovecs[tx->idx].flags |= |
961 | TXREQ_FLAGS_IOVEC_LAST_PKT; | |
77241056 MM |
962 | iovec = &req->iovs[++req->iov_idx]; |
963 | if (!iovec->pages) { | |
964 | ret = pin_vector_pages(req, iovec); | |
965 | if (ret) | |
966 | goto free_txreq; | |
967 | } | |
968 | iov_offset = 0; | |
b9fb6318 | 969 | tx->iovecs[++tx->idx].vec = iovec; |
77241056 MM |
970 | } |
971 | } | |
972 | /* | |
973 | * The txreq was submitted successfully so we can update | |
974 | * the counters. | |
975 | */ | |
976 | req->koffset += datalen; | |
977 | if (req_opcode(req->info.ctrl) == EXPECTED) | |
978 | req->tidoffset += datalen; | |
979 | req->sent += data_sent; | |
980 | if (req->data_len) { | |
b9fb6318 MH |
981 | tx->iovecs[tx->idx].vec->offset += iov_offset; |
982 | /* If we've reached the end of the io vector, mark it | |
983 | * so the callback can unpin the pages and free it. */ | |
984 | if (tx->iovecs[tx->idx].vec->offset == | |
985 | tx->iovecs[tx->idx].vec->iov.iov_len) | |
986 | tx->iovecs[tx->idx].flags |= | |
987 | TXREQ_FLAGS_IOVEC_LAST_PKT; | |
77241056 | 988 | } |
b9fb6318 | 989 | |
c7cbf2fa | 990 | list_add_tail(&tx->txreq.list, &req->txps); |
77241056 MM |
991 | /* |
992 | * It is important to increment this here as it is used to | |
993 | * generate the BTH.PSN and, therefore, can't be bulk-updated | |
994 | * outside of the loop. | |
995 | */ | |
996 | tx->seqnum = req->seqnum++; | |
77241056 MM |
997 | npkts++; |
998 | } | |
999 | dosend: | |
1000 | ret = sdma_send_txlist(req->sde, &pq->busy, &req->txps); | |
c7cbf2fa MH |
1001 | if (list_empty(&req->txps)) { |
1002 | req->seqsubmitted = req->seqnum; | |
77241056 MM |
1003 | if (req->seqnum == req->info.npkts) { |
1004 | set_bit(SDMA_REQ_SEND_DONE, &req->flags); | |
1005 | /* | |
1006 | * The txreq has already been submitted to the HW queue | |
1007 | * so we can free the AHG entry now. Corruption will not | |
1008 | * happen due to the sequential manner in which | |
1009 | * descriptors are processed. | |
1010 | */ | |
1011 | if (test_bit(SDMA_REQ_HAVE_AHG, &req->flags)) | |
1012 | sdma_ahg_free(req->sde, req->ahg_idx); | |
1013 | } | |
c7cbf2fa MH |
1014 | } else if (ret > 0) { |
1015 | req->seqsubmitted += ret; | |
1016 | ret = 0; | |
1017 | } | |
faa98b86 MH |
1018 | return ret; |
1019 | ||
77241056 MM |
1020 | free_txreq: |
1021 | sdma_txclean(pq->dd, &tx->txreq); | |
1022 | free_tx: | |
1023 | kmem_cache_free(pq->txreq_cache, tx); | |
77241056 MM |
1024 | return ret; |
1025 | } | |
1026 | ||
1027 | /* | |
1028 | * How many pages in this iovec element? | |
1029 | */ | |
1030 | static inline int num_user_pages(const struct iovec *iov) | |
1031 | { | |
50e5dcbe | 1032 | const unsigned long addr = (unsigned long)iov->iov_base; |
77241056 MM |
1033 | const unsigned long len = iov->iov_len; |
1034 | const unsigned long spage = addr & PAGE_MASK; | |
1035 | const unsigned long epage = (addr + len - 1) & PAGE_MASK; | |
1036 | ||
1037 | return 1 + ((epage - spage) >> PAGE_SHIFT); | |
1038 | } | |
1039 | ||
1040 | static int pin_vector_pages(struct user_sdma_request *req, | |
1041 | struct user_sdma_iovec *iovec) { | |
a0d40693 | 1042 | int pinned, npages; |
77241056 | 1043 | |
a0d40693 MH |
1044 | npages = num_user_pages(&iovec->iov); |
1045 | iovec->pages = kcalloc(npages, sizeof(*iovec->pages), GFP_KERNEL); | |
77241056 MM |
1046 | if (!iovec->pages) { |
1047 | SDMA_DBG(req, "Failed page array alloc"); | |
a0d40693 | 1048 | return -ENOMEM; |
77241056 | 1049 | } |
a0d40693 | 1050 | |
a0d40693 MH |
1051 | pinned = hfi1_acquire_user_pages((unsigned long)iovec->iov.iov_base, |
1052 | npages, 0, iovec->pages); | |
1053 | ||
1054 | if (pinned < 0) | |
1055 | return pinned; | |
1056 | ||
1057 | iovec->npages = pinned; | |
1058 | if (pinned != npages) { | |
1059 | SDMA_DBG(req, "Failed to pin pages (%d/%u)", pinned, npages); | |
0f2d87d2 | 1060 | unpin_vector_pages(iovec); |
a0d40693 | 1061 | return -EFAULT; |
77241056 | 1062 | } |
a0d40693 | 1063 | return 0; |
77241056 MM |
1064 | } |
1065 | ||
0f2d87d2 | 1066 | static void unpin_vector_pages(struct user_sdma_iovec *iovec) |
77241056 | 1067 | { |
a0d40693 MH |
1068 | hfi1_release_user_pages(iovec->pages, iovec->npages, 0); |
1069 | ||
77241056 MM |
1070 | kfree(iovec->pages); |
1071 | iovec->pages = NULL; | |
1072 | iovec->npages = 0; | |
1073 | iovec->offset = 0; | |
1074 | } | |
1075 | ||
1076 | static int check_header_template(struct user_sdma_request *req, | |
1077 | struct hfi1_pkt_header *hdr, u32 lrhlen, | |
1078 | u32 datalen) | |
1079 | { | |
1080 | /* | |
1081 | * Perform safety checks for any type of packet: | |
1082 | * - transfer size is multiple of 64bytes | |
1083 | * - packet length is multiple of 4bytes | |
1084 | * - entire request length is multiple of 4bytes | |
1085 | * - packet length is not larger than MTU size | |
1086 | * | |
1087 | * These checks are only done for the first packet of the | |
1088 | * transfer since the header is "given" to us by user space. | |
1089 | * For the remainder of the packets we compute the values. | |
1090 | */ | |
1091 | if (req->info.fragsize % PIO_BLOCK_SIZE || | |
1092 | lrhlen & 0x3 || req->data_len & 0x3 || | |
1093 | lrhlen > get_lrh_len(*hdr, req->info.fragsize)) | |
1094 | return -EINVAL; | |
1095 | ||
1096 | if (req_opcode(req->info.ctrl) == EXPECTED) { | |
1097 | /* | |
1098 | * The header is checked only on the first packet. Furthermore, | |
1099 | * we ensure that at least one TID entry is copied when the | |
1100 | * request is submitted. Therefore, we don't have to verify that | |
1101 | * tididx points to something sane. | |
1102 | */ | |
1103 | u32 tidval = req->tids[req->tididx], | |
1104 | tidlen = EXP_TID_GET(tidval, LEN) * PAGE_SIZE, | |
1105 | tididx = EXP_TID_GET(tidval, IDX), | |
1106 | tidctrl = EXP_TID_GET(tidval, CTRL), | |
1107 | tidoff; | |
1108 | __le32 kval = hdr->kdeth.ver_tid_offset; | |
1109 | ||
1110 | tidoff = KDETH_GET(kval, OFFSET) * | |
1111 | (KDETH_GET(req->hdr.kdeth.ver_tid_offset, OM) ? | |
1112 | KDETH_OM_LARGE : KDETH_OM_SMALL); | |
1113 | /* | |
1114 | * Expected receive packets have the following | |
1115 | * additional checks: | |
1116 | * - offset is not larger than the TID size | |
1117 | * - TIDCtrl values match between header and TID array | |
1118 | * - TID indexes match between header and TID array | |
1119 | */ | |
1120 | if ((tidoff + datalen > tidlen) || | |
1121 | KDETH_GET(kval, TIDCTRL) != tidctrl || | |
1122 | KDETH_GET(kval, TID) != tididx) | |
1123 | return -EINVAL; | |
1124 | } | |
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | /* | |
1129 | * Correctly set the BTH.PSN field based on type of | |
1130 | * transfer - eager packets can just increment the PSN but | |
1131 | * expected packets encode generation and sequence in the | |
1132 | * BTH.PSN field so just incrementing will result in errors. | |
1133 | */ | |
1134 | static inline u32 set_pkt_bth_psn(__be32 bthpsn, u8 expct, u32 frags) | |
1135 | { | |
1136 | u32 val = be32_to_cpu(bthpsn), | |
1137 | mask = (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffffull : | |
1138 | 0xffffffull), | |
1139 | psn = val & mask; | |
1140 | if (expct) | |
1141 | psn = (psn & ~BTH_SEQ_MASK) | ((psn + frags) & BTH_SEQ_MASK); | |
1142 | else | |
1143 | psn = psn + frags; | |
1144 | return psn & mask; | |
1145 | } | |
1146 | ||
1147 | static int set_txreq_header(struct user_sdma_request *req, | |
1148 | struct user_sdma_txreq *tx, u32 datalen) | |
1149 | { | |
1150 | struct hfi1_user_sdma_pkt_q *pq = req->pq; | |
1151 | struct hfi1_pkt_header *hdr = &tx->hdr; | |
1152 | u16 pbclen; | |
1153 | int ret; | |
1154 | u32 tidval = 0, lrhlen = get_lrh_len(*hdr, datalen); | |
1155 | ||
1156 | /* Copy the header template to the request before modification */ | |
1157 | memcpy(hdr, &req->hdr, sizeof(*hdr)); | |
1158 | ||
1159 | /* | |
1160 | * Check if the PBC and LRH length are mismatched. If so | |
1161 | * adjust both in the header. | |
1162 | */ | |
1163 | pbclen = le16_to_cpu(hdr->pbc[0]); | |
1164 | if (PBC2LRH(pbclen) != lrhlen) { | |
1165 | pbclen = (pbclen & 0xf000) | LRH2PBC(lrhlen); | |
1166 | hdr->pbc[0] = cpu_to_le16(pbclen); | |
1167 | hdr->lrh[2] = cpu_to_be16(lrhlen >> 2); | |
1168 | /* | |
1169 | * Third packet | |
1170 | * This is the first packet in the sequence that has | |
1171 | * a "static" size that can be used for the rest of | |
1172 | * the packets (besides the last one). | |
1173 | */ | |
1174 | if (unlikely(req->seqnum == 2)) { | |
1175 | /* | |
1176 | * From this point on the lengths in both the | |
1177 | * PBC and LRH are the same until the last | |
1178 | * packet. | |
1179 | * Adjust the template so we don't have to update | |
1180 | * every packet | |
1181 | */ | |
1182 | req->hdr.pbc[0] = hdr->pbc[0]; | |
1183 | req->hdr.lrh[2] = hdr->lrh[2]; | |
1184 | } | |
1185 | } | |
1186 | /* | |
1187 | * We only have to modify the header if this is not the | |
1188 | * first packet in the request. Otherwise, we use the | |
1189 | * header given to us. | |
1190 | */ | |
1191 | if (unlikely(!req->seqnum)) { | |
1192 | ret = check_header_template(req, hdr, lrhlen, datalen); | |
1193 | if (ret) | |
1194 | return ret; | |
1195 | goto done; | |
77241056 MM |
1196 | } |
1197 | ||
1198 | hdr->bth[2] = cpu_to_be32( | |
1199 | set_pkt_bth_psn(hdr->bth[2], | |
1200 | (req_opcode(req->info.ctrl) == EXPECTED), | |
1201 | req->seqnum)); | |
1202 | ||
1203 | /* Set ACK request on last packet */ | |
b9fb6318 | 1204 | if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) |
8638b77f | 1205 | hdr->bth[2] |= cpu_to_be32(1UL << 31); |
77241056 MM |
1206 | |
1207 | /* Set the new offset */ | |
1208 | hdr->kdeth.swdata[6] = cpu_to_le32(req->koffset); | |
1209 | /* Expected packets have to fill in the new TID information */ | |
1210 | if (req_opcode(req->info.ctrl) == EXPECTED) { | |
1211 | tidval = req->tids[req->tididx]; | |
1212 | /* | |
1213 | * If the offset puts us at the end of the current TID, | |
1214 | * advance everything. | |
1215 | */ | |
1216 | if ((req->tidoffset) == (EXP_TID_GET(tidval, LEN) * | |
1217 | PAGE_SIZE)) { | |
1218 | req->tidoffset = 0; | |
1219 | /* Since we don't copy all the TIDs, all at once, | |
1220 | * we have to check again. */ | |
1221 | if (++req->tididx > req->n_tids - 1 || | |
1222 | !req->tids[req->tididx]) { | |
1223 | return -EINVAL; | |
1224 | } | |
1225 | tidval = req->tids[req->tididx]; | |
1226 | } | |
1227 | req->omfactor = EXP_TID_GET(tidval, LEN) * PAGE_SIZE >= | |
1228 | KDETH_OM_MAX_SIZE ? KDETH_OM_LARGE : KDETH_OM_SMALL; | |
1229 | /* Set KDETH.TIDCtrl based on value for this TID. */ | |
1230 | KDETH_SET(hdr->kdeth.ver_tid_offset, TIDCTRL, | |
1231 | EXP_TID_GET(tidval, CTRL)); | |
1232 | /* Set KDETH.TID based on value for this TID */ | |
1233 | KDETH_SET(hdr->kdeth.ver_tid_offset, TID, | |
1234 | EXP_TID_GET(tidval, IDX)); | |
1235 | /* Clear KDETH.SH only on the last packet */ | |
b9fb6318 | 1236 | if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) |
77241056 MM |
1237 | KDETH_SET(hdr->kdeth.ver_tid_offset, SH, 0); |
1238 | /* | |
1239 | * Set the KDETH.OFFSET and KDETH.OM based on size of | |
1240 | * transfer. | |
1241 | */ | |
1242 | SDMA_DBG(req, "TID offset %ubytes %uunits om%u", | |
1243 | req->tidoffset, req->tidoffset / req->omfactor, | |
1244 | !!(req->omfactor - KDETH_OM_SMALL)); | |
1245 | KDETH_SET(hdr->kdeth.ver_tid_offset, OFFSET, | |
1246 | req->tidoffset / req->omfactor); | |
1247 | KDETH_SET(hdr->kdeth.ver_tid_offset, OM, | |
1248 | !!(req->omfactor - KDETH_OM_SMALL)); | |
1249 | } | |
1250 | done: | |
1251 | trace_hfi1_sdma_user_header(pq->dd, pq->ctxt, pq->subctxt, | |
1252 | req->info.comp_idx, hdr, tidval); | |
1253 | return sdma_txadd_kvaddr(pq->dd, &tx->txreq, hdr, sizeof(*hdr)); | |
1254 | } | |
1255 | ||
1256 | static int set_txreq_header_ahg(struct user_sdma_request *req, | |
1257 | struct user_sdma_txreq *tx, u32 len) | |
1258 | { | |
1259 | int diff = 0; | |
1260 | struct hfi1_user_sdma_pkt_q *pq = req->pq; | |
1261 | struct hfi1_pkt_header *hdr = &req->hdr; | |
1262 | u16 pbclen = le16_to_cpu(hdr->pbc[0]); | |
1263 | u32 val32, tidval = 0, lrhlen = get_lrh_len(*hdr, len); | |
1264 | ||
1265 | if (PBC2LRH(pbclen) != lrhlen) { | |
1266 | /* PBC.PbcLengthDWs */ | |
1267 | AHG_HEADER_SET(req->ahg, diff, 0, 0, 12, | |
1268 | cpu_to_le16(LRH2PBC(lrhlen))); | |
1269 | /* LRH.PktLen (we need the full 16 bits due to byte swap) */ | |
1270 | AHG_HEADER_SET(req->ahg, diff, 3, 0, 16, | |
1271 | cpu_to_be16(lrhlen >> 2)); | |
1272 | } | |
1273 | ||
1274 | /* | |
1275 | * Do the common updates | |
1276 | */ | |
1277 | /* BTH.PSN and BTH.A */ | |
1278 | val32 = (be32_to_cpu(hdr->bth[2]) + req->seqnum) & | |
1279 | (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffff : 0xffffff); | |
b9fb6318 | 1280 | if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) |
77241056 MM |
1281 | val32 |= 1UL << 31; |
1282 | AHG_HEADER_SET(req->ahg, diff, 6, 0, 16, cpu_to_be16(val32 >> 16)); | |
1283 | AHG_HEADER_SET(req->ahg, diff, 6, 16, 16, cpu_to_be16(val32 & 0xffff)); | |
1284 | /* KDETH.Offset */ | |
1285 | AHG_HEADER_SET(req->ahg, diff, 15, 0, 16, | |
1286 | cpu_to_le16(req->koffset & 0xffff)); | |
1287 | AHG_HEADER_SET(req->ahg, diff, 15, 16, 16, | |
1288 | cpu_to_le16(req->koffset >> 16)); | |
1289 | if (req_opcode(req->info.ctrl) == EXPECTED) { | |
1290 | __le16 val; | |
1291 | ||
1292 | tidval = req->tids[req->tididx]; | |
1293 | ||
1294 | /* | |
1295 | * If the offset puts us at the end of the current TID, | |
1296 | * advance everything. | |
1297 | */ | |
1298 | if ((req->tidoffset) == (EXP_TID_GET(tidval, LEN) * | |
1299 | PAGE_SIZE)) { | |
1300 | req->tidoffset = 0; | |
1301 | /* Since we don't copy all the TIDs, all at once, | |
1302 | * we have to check again. */ | |
1303 | if (++req->tididx > req->n_tids - 1 || | |
1304 | !req->tids[req->tididx]) { | |
1305 | return -EINVAL; | |
1306 | } | |
1307 | tidval = req->tids[req->tididx]; | |
1308 | } | |
1309 | req->omfactor = ((EXP_TID_GET(tidval, LEN) * | |
1310 | PAGE_SIZE) >= | |
1311 | KDETH_OM_MAX_SIZE) ? KDETH_OM_LARGE : | |
1312 | KDETH_OM_SMALL; | |
1313 | /* KDETH.OM and KDETH.OFFSET (TID) */ | |
1314 | AHG_HEADER_SET(req->ahg, diff, 7, 0, 16, | |
1315 | ((!!(req->omfactor - KDETH_OM_SMALL)) << 15 | | |
1316 | ((req->tidoffset / req->omfactor) & 0x7fff))); | |
1317 | /* KDETH.TIDCtrl, KDETH.TID */ | |
1318 | val = cpu_to_le16(((EXP_TID_GET(tidval, CTRL) & 0x3) << 10) | | |
1319 | (EXP_TID_GET(tidval, IDX) & 0x3ff)); | |
1320 | /* Clear KDETH.SH on last packet */ | |
b9fb6318 | 1321 | if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) { |
77241056 MM |
1322 | val |= cpu_to_le16(KDETH_GET(hdr->kdeth.ver_tid_offset, |
1323 | INTR) >> 16); | |
1324 | val &= cpu_to_le16(~(1U << 13)); | |
1325 | AHG_HEADER_SET(req->ahg, diff, 7, 16, 14, val); | |
1326 | } else | |
1327 | AHG_HEADER_SET(req->ahg, diff, 7, 16, 12, val); | |
1328 | } | |
1329 | ||
1330 | trace_hfi1_sdma_user_header_ahg(pq->dd, pq->ctxt, pq->subctxt, | |
1331 | req->info.comp_idx, req->sde->this_idx, | |
1332 | req->ahg_idx, req->ahg, diff, tidval); | |
1333 | return diff; | |
1334 | } | |
1335 | ||
a0d40693 MH |
1336 | /* |
1337 | * SDMA tx request completion callback. Called when the SDMA progress | |
1338 | * state machine gets notification that the SDMA descriptors for this | |
1339 | * tx request have been processed by the DMA engine. Called in | |
1340 | * interrupt context. | |
1341 | */ | |
a545f530 | 1342 | static void user_sdma_txreq_cb(struct sdma_txreq *txreq, int status) |
77241056 MM |
1343 | { |
1344 | struct user_sdma_txreq *tx = | |
1345 | container_of(txreq, struct user_sdma_txreq, txreq); | |
a0d40693 | 1346 | struct user_sdma_request *req; |
0f2d87d2 MH |
1347 | struct hfi1_user_sdma_pkt_q *pq; |
1348 | struct hfi1_user_sdma_comp_q *cq; | |
1349 | u16 idx; | |
0840aea9 | 1350 | int i, j; |
77241056 | 1351 | |
a0d40693 | 1352 | if (!tx->req) |
77241056 MM |
1353 | return; |
1354 | ||
a0d40693 | 1355 | req = tx->req; |
0f2d87d2 MH |
1356 | pq = req->pq; |
1357 | cq = req->cq; | |
b9fb6318 | 1358 | |
a0d40693 MH |
1359 | /* |
1360 | * If we have any io vectors associated with this txreq, | |
0840aea9 | 1361 | * check whether they need to be 'freed'. |
a0d40693 MH |
1362 | */ |
1363 | for (i = tx->idx; i >= 0; i--) { | |
1364 | if (tx->iovecs[i].flags & TXREQ_FLAGS_IOVEC_LAST_PKT) { | |
0840aea9 MH |
1365 | struct user_sdma_iovec *vec = |
1366 | tx->iovecs[i].vec; | |
1367 | ||
1368 | for (j = 0; j < vec->npages; j++) | |
1369 | put_page(vec->pages[j]); | |
1370 | xadd(&pq->unpinned, vec->npages); | |
1371 | kfree(vec->pages); | |
1372 | vec->pages = NULL; | |
1373 | vec->npages = 0; | |
b9fb6318 MH |
1374 | } |
1375 | } | |
77241056 | 1376 | |
77241056 | 1377 | if (status != SDMA_TXREQ_S_OK) { |
a0d40693 MH |
1378 | SDMA_DBG(req, "SDMA completion with error %d", |
1379 | status); | |
77241056 | 1380 | set_bit(SDMA_REQ_HAS_ERROR, &req->flags); |
a0d40693 MH |
1381 | } |
1382 | ||
0f2d87d2 MH |
1383 | req->seqcomp = tx->seqnum; |
1384 | kmem_cache_free(pq->txreq_cache, tx); | |
1385 | tx = NULL; | |
1386 | ||
1387 | idx = req->info.comp_idx; | |
1388 | if (req->status == -1 && status == SDMA_TXREQ_S_OK) { | |
1389 | if (req->seqcomp == req->info.npkts - 1) { | |
1390 | req->status = 0; | |
1391 | user_sdma_free_request(req, false); | |
1392 | pq_update(pq); | |
1393 | set_comp_state(pq, cq, idx, COMPLETE, 0); | |
1394 | } | |
77241056 | 1395 | } else { |
0f2d87d2 MH |
1396 | if (status != SDMA_TXREQ_S_OK) |
1397 | req->status = status; | |
c7cbf2fa MH |
1398 | if (req->seqcomp == (ACCESS_ONCE(req->seqsubmitted) - 1) && |
1399 | (test_bit(SDMA_REQ_SEND_DONE, &req->flags) || | |
1400 | test_bit(SDMA_REQ_DONE_ERROR, &req->flags))) { | |
0f2d87d2 MH |
1401 | user_sdma_free_request(req, false); |
1402 | pq_update(pq); | |
1403 | set_comp_state(pq, cq, idx, ERROR, req->status); | |
1404 | } | |
a0d40693 MH |
1405 | } |
1406 | } | |
1407 | ||
0f2d87d2 | 1408 | static inline void pq_update(struct hfi1_user_sdma_pkt_q *pq) |
a0d40693 | 1409 | { |
0f2d87d2 | 1410 | if (atomic_dec_and_test(&pq->n_reqs)) { |
77241056 | 1411 | xchg(&pq->state, SDMA_PKT_Q_INACTIVE); |
a0d40693 MH |
1412 | wake_up(&pq->wait); |
1413 | } | |
77241056 MM |
1414 | } |
1415 | ||
0f2d87d2 | 1416 | static void user_sdma_free_request(struct user_sdma_request *req, bool unpin) |
77241056 MM |
1417 | { |
1418 | if (!list_empty(&req->txps)) { | |
1419 | struct sdma_txreq *t, *p; | |
1420 | ||
1421 | list_for_each_entry_safe(t, p, &req->txps, list) { | |
1422 | struct user_sdma_txreq *tx = | |
1423 | container_of(t, struct user_sdma_txreq, txreq); | |
1424 | list_del_init(&t->list); | |
1425 | sdma_txclean(req->pq->dd, t); | |
1426 | kmem_cache_free(req->pq->txreq_cache, tx); | |
1427 | } | |
1428 | } | |
0f2d87d2 | 1429 | if (req->data_iovs && unpin) { |
77241056 MM |
1430 | int i; |
1431 | ||
1432 | for (i = 0; i < req->data_iovs; i++) | |
1433 | if (req->iovs[i].npages && req->iovs[i].pages) | |
0f2d87d2 | 1434 | unpin_vector_pages(&req->iovs[i]); |
77241056 | 1435 | } |
77241056 MM |
1436 | kfree(req->tids); |
1437 | clear_bit(SDMA_REQ_IN_USE, &req->flags); | |
1438 | } | |
1439 | ||
0f2d87d2 MH |
1440 | static inline void set_comp_state(struct hfi1_user_sdma_pkt_q *pq, |
1441 | struct hfi1_user_sdma_comp_q *cq, | |
1442 | u16 idx, enum hfi1_sdma_comp_state state, | |
1443 | int ret) | |
77241056 | 1444 | { |
0f2d87d2 MH |
1445 | hfi1_cdbg(SDMA, "[%u:%u:%u:%u] Setting completion status %u %d", |
1446 | pq->dd->unit, pq->ctxt, pq->subctxt, idx, state, ret); | |
1447 | cq->comps[idx].status = state; | |
77241056 | 1448 | if (state == ERROR) |
0f2d87d2 MH |
1449 | cq->comps[idx].errcode = -ret; |
1450 | trace_hfi1_sdma_user_completion(pq->dd, pq->ctxt, pq->subctxt, | |
1451 | idx, state, ret); | |
77241056 | 1452 | } |