]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/staging/rdma/hfi1/user_sdma.c
staging: rdma: hfi1: Remove unnecessary parantheses
[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / rdma / hfi1 / user_sdma.c
CommitLineData
77241056
MM
1/*
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2015 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2015 Intel Corporation.
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 *
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
32 * distribution.
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 */
50#include <linux/mm.h>
51#include <linux/types.h>
52#include <linux/device.h>
53#include <linux/dmapool.h>
54#include <linux/slab.h>
55#include <linux/list.h>
56#include <linux/highmem.h>
57#include <linux/io.h>
58#include <linux/uio.h>
59#include <linux/rbtree.h>
60#include <linux/spinlock.h>
61#include <linux/delay.h>
62#include <linux/kthread.h>
63#include <linux/mmu_context.h>
64#include <linux/module.h>
65#include <linux/vmalloc.h>
66
67#include "hfi.h"
68#include "sdma.h"
69#include "user_sdma.h"
77241056
MM
70#include "verbs.h" /* for the headers */
71#include "common.h" /* for struct hfi1_tid_info */
72#include "trace.h"
73
74static uint hfi1_sdma_comp_ring_size = 128;
75module_param_named(sdma_comp_size, hfi1_sdma_comp_ring_size, uint, S_IRUGO);
76MODULE_PARM_DESC(sdma_comp_size, "Size of User SDMA completion ring. Default: 128");
77
78/* The maximum number of Data io vectors per message/request */
79#define MAX_VECTORS_PER_REQ 8
80/*
81 * Maximum number of packet to send from each message/request
82 * before moving to the next one.
83 */
84#define MAX_PKTS_PER_QUEUE 16
85
86#define num_pages(x) (1 + ((((x) - 1) & PAGE_MASK) >> PAGE_SHIFT))
87
88#define req_opcode(x) \
89 (((x) >> HFI1_SDMA_REQ_OPCODE_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
90#define req_version(x) \
91 (((x) >> HFI1_SDMA_REQ_VERSION_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
92#define req_iovcnt(x) \
93 (((x) >> HFI1_SDMA_REQ_IOVCNT_SHIFT) & HFI1_SDMA_REQ_IOVCNT_MASK)
94
95/* Number of BTH.PSN bits used for sequence number in expected rcvs */
96#define BTH_SEQ_MASK 0x7ffull
97
98/*
99 * Define fields in the KDETH header so we can update the header
100 * template.
101 */
102#define KDETH_OFFSET_SHIFT 0
103#define KDETH_OFFSET_MASK 0x7fff
104#define KDETH_OM_SHIFT 15
105#define KDETH_OM_MASK 0x1
106#define KDETH_TID_SHIFT 16
107#define KDETH_TID_MASK 0x3ff
108#define KDETH_TIDCTRL_SHIFT 26
109#define KDETH_TIDCTRL_MASK 0x3
110#define KDETH_INTR_SHIFT 28
111#define KDETH_INTR_MASK 0x1
112#define KDETH_SH_SHIFT 29
113#define KDETH_SH_MASK 0x1
114#define KDETH_HCRC_UPPER_SHIFT 16
115#define KDETH_HCRC_UPPER_MASK 0xff
116#define KDETH_HCRC_LOWER_SHIFT 24
117#define KDETH_HCRC_LOWER_MASK 0xff
118
119#define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4)
120#define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff)
121
122#define KDETH_GET(val, field) \
123 (((le32_to_cpu((val))) >> KDETH_##field##_SHIFT) & KDETH_##field##_MASK)
124#define KDETH_SET(dw, field, val) do { \
125 u32 dwval = le32_to_cpu(dw); \
126 dwval &= ~(KDETH_##field##_MASK << KDETH_##field##_SHIFT); \
127 dwval |= (((val) & KDETH_##field##_MASK) << \
128 KDETH_##field##_SHIFT); \
129 dw = cpu_to_le32(dwval); \
130 } while (0)
131
132#define AHG_HEADER_SET(arr, idx, dw, bit, width, value) \
133 do { \
134 if ((idx) < ARRAY_SIZE((arr))) \
135 (arr)[(idx++)] = sdma_build_ahg_descriptor( \
136 (__force u16)(value), (dw), (bit), \
137 (width)); \
138 else \
139 return -ERANGE; \
140 } while (0)
141
142/* KDETH OM multipliers and switch over point */
143#define KDETH_OM_SMALL 4
144#define KDETH_OM_LARGE 64
145#define KDETH_OM_MAX_SIZE (1 << ((KDETH_OM_LARGE / KDETH_OM_SMALL) + 1))
146
147/* Last packet in the request */
cb32649d
SK
148#define TXREQ_FLAGS_REQ_LAST_PKT BIT(0)
149#define TXREQ_FLAGS_IOVEC_LAST_PKT BIT(0)
77241056
MM
150
151#define SDMA_REQ_IN_USE 0
152#define SDMA_REQ_FOR_THREAD 1
153#define SDMA_REQ_SEND_DONE 2
154#define SDMA_REQ_HAVE_AHG 3
155#define SDMA_REQ_HAS_ERROR 4
156#define SDMA_REQ_DONE_ERROR 5
157
cb32649d
SK
158#define SDMA_PKT_Q_INACTIVE BIT(0)
159#define SDMA_PKT_Q_ACTIVE BIT(1)
160#define SDMA_PKT_Q_DEFERRED BIT(2)
77241056
MM
161
162/*
163 * Maximum retry attempts to submit a TX request
164 * before putting the process to sleep.
165 */
166#define MAX_DEFER_RETRY_COUNT 1
167
168static unsigned initial_pkt_count = 8;
169
170#define SDMA_IOWAIT_TIMEOUT 1000 /* in milliseconds */
171
172struct user_sdma_iovec {
173 struct iovec iov;
174 /* number of pages in this vector */
175 unsigned npages;
176 /* array of pinned pages for this vector */
177 struct page **pages;
178 /* offset into the virtual address space of the vector at
179 * which we last left off. */
180 u64 offset;
181};
182
183struct user_sdma_request {
184 struct sdma_req_info info;
185 struct hfi1_user_sdma_pkt_q *pq;
186 struct hfi1_user_sdma_comp_q *cq;
187 /* This is the original header from user space */
188 struct hfi1_pkt_header hdr;
189 /*
190 * Pointer to the SDMA engine for this request.
191 * Since different request could be on different VLs,
192 * each request will need it's own engine pointer.
193 */
194 struct sdma_engine *sde;
195 u8 ahg_idx;
196 u32 ahg[9];
197 /*
198 * KDETH.Offset (Eager) field
199 * We need to remember the initial value so the headers
200 * can be updated properly.
201 */
202 u32 koffset;
203 /*
204 * KDETH.OFFSET (TID) field
205 * The offset can cover multiple packets, depending on the
206 * size of the TID entry.
207 */
208 u32 tidoffset;
209 /*
210 * KDETH.OM
211 * Remember this because the header template always sets it
212 * to 0.
213 */
214 u8 omfactor;
77241056
MM
215 /*
216 * pointer to the user's mm_struct. We are going to
217 * get a reference to it so it doesn't get freed
218 * since we might not be in process context when we
219 * are processing the iov's.
220 * Using this mm_struct, we can get vma based on the
221 * iov's address (find_vma()).
222 */
223 struct mm_struct *user_mm;
224 /*
225 * We copy the iovs for this request (based on
226 * info.iovcnt). These are only the data vectors
227 */
228 unsigned data_iovs;
229 /* total length of the data in the request */
230 u32 data_len;
231 /* progress index moving along the iovs array */
232 unsigned iov_idx;
233 struct user_sdma_iovec iovs[MAX_VECTORS_PER_REQ];
234 /* number of elements copied to the tids array */
235 u16 n_tids;
236 /* TID array values copied from the tid_iov vector */
237 u32 *tids;
238 u16 tididx;
239 u32 sent;
240 u64 seqnum;
77241056 241 struct list_head txps;
a0d40693
MH
242 spinlock_t txcmp_lock; /* protect txcmp list */
243 struct list_head txcmp;
77241056 244 unsigned long flags;
a0d40693
MH
245 /* status of the last txreq completed */
246 int status;
247 struct work_struct worker;
77241056
MM
248};
249
b9fb6318
MH
250/*
251 * A single txreq could span up to 3 physical pages when the MTU
252 * is sufficiently large (> 4K). Each of the IOV pointers also
253 * needs it's own set of flags so the vector has been handled
254 * independently of each other.
255 */
77241056
MM
256struct user_sdma_txreq {
257 /* Packet header for the txreq */
258 struct hfi1_pkt_header hdr;
259 struct sdma_txreq txreq;
a0d40693 260 struct list_head list;
77241056 261 struct user_sdma_request *req;
b9fb6318
MH
262 struct {
263 struct user_sdma_iovec *vec;
264 u8 flags;
265 } iovecs[3];
266 int idx;
77241056
MM
267 u16 flags;
268 unsigned busycount;
269 u64 seqnum;
270};
271
272#define SDMA_DBG(req, fmt, ...) \
273 hfi1_cdbg(SDMA, "[%u:%u:%u:%u] " fmt, (req)->pq->dd->unit, \
274 (req)->pq->ctxt, (req)->pq->subctxt, (req)->info.comp_idx, \
275 ##__VA_ARGS__)
276#define SDMA_Q_DBG(pq, fmt, ...) \
277 hfi1_cdbg(SDMA, "[%u:%u:%u] " fmt, (pq)->dd->unit, (pq)->ctxt, \
278 (pq)->subctxt, ##__VA_ARGS__)
279
280static int user_sdma_send_pkts(struct user_sdma_request *, unsigned);
281static int num_user_pages(const struct iovec *);
282static void user_sdma_txreq_cb(struct sdma_txreq *, int, int);
a0d40693 283static void user_sdma_delayed_completion(struct work_struct *);
77241056
MM
284static void user_sdma_free_request(struct user_sdma_request *);
285static int pin_vector_pages(struct user_sdma_request *,
286 struct user_sdma_iovec *);
a0d40693
MH
287static void unpin_vector_pages(struct user_sdma_request *,
288 struct user_sdma_iovec *);
77241056
MM
289static int check_header_template(struct user_sdma_request *,
290 struct hfi1_pkt_header *, u32, u32);
291static int set_txreq_header(struct user_sdma_request *,
292 struct user_sdma_txreq *, u32);
293static int set_txreq_header_ahg(struct user_sdma_request *,
294 struct user_sdma_txreq *, u32);
295static inline void set_comp_state(struct user_sdma_request *,
296 enum hfi1_sdma_comp_state, int);
297static inline u32 set_pkt_bth_psn(__be32, u8, u32);
298static inline u32 get_lrh_len(struct hfi1_pkt_header, u32 len);
299
300static int defer_packet_queue(
301 struct sdma_engine *,
302 struct iowait *,
303 struct sdma_txreq *,
304 unsigned seq);
305static void activate_packet_queue(struct iowait *, int);
306
77241056
MM
307static int defer_packet_queue(
308 struct sdma_engine *sde,
309 struct iowait *wait,
310 struct sdma_txreq *txreq,
311 unsigned seq)
312{
313 struct hfi1_user_sdma_pkt_q *pq =
314 container_of(wait, struct hfi1_user_sdma_pkt_q, busy);
315 struct hfi1_ibdev *dev = &pq->dd->verbs_dev;
316 struct user_sdma_txreq *tx =
317 container_of(txreq, struct user_sdma_txreq, txreq);
318
319 if (sdma_progress(sde, seq, txreq)) {
320 if (tx->busycount++ < MAX_DEFER_RETRY_COUNT)
321 goto eagain;
322 }
323 /*
324 * We are assuming that if the list is enqueued somewhere, it
325 * is to the dmawait list since that is the only place where
326 * it is supposed to be enqueued.
327 */
328 xchg(&pq->state, SDMA_PKT_Q_DEFERRED);
329 write_seqlock(&dev->iowait_lock);
330 if (list_empty(&pq->busy.list))
331 list_add_tail(&pq->busy.list, &sde->dmawait);
332 write_sequnlock(&dev->iowait_lock);
333 return -EBUSY;
334eagain:
335 return -EAGAIN;
336}
337
338static void activate_packet_queue(struct iowait *wait, int reason)
339{
340 struct hfi1_user_sdma_pkt_q *pq =
341 container_of(wait, struct hfi1_user_sdma_pkt_q, busy);
342 xchg(&pq->state, SDMA_PKT_Q_ACTIVE);
343 wake_up(&wait->wait_dma);
344};
345
346static void sdma_kmem_cache_ctor(void *obj)
347{
348 struct user_sdma_txreq *tx = (struct user_sdma_txreq *)obj;
349
350 memset(tx, 0, sizeof(*tx));
351}
352
353int hfi1_user_sdma_alloc_queues(struct hfi1_ctxtdata *uctxt, struct file *fp)
354{
9e10af47 355 struct hfi1_filedata *fd;
77241056
MM
356 int ret = 0;
357 unsigned memsize;
358 char buf[64];
359 struct hfi1_devdata *dd;
360 struct hfi1_user_sdma_comp_q *cq;
361 struct hfi1_user_sdma_pkt_q *pq;
362 unsigned long flags;
363
364 if (!uctxt || !fp) {
365 ret = -EBADF;
366 goto done;
367 }
368
9e10af47
IW
369 fd = fp->private_data;
370
77241056
MM
371 if (!hfi1_sdma_comp_ring_size) {
372 ret = -EINVAL;
373 goto done;
374 }
375
376 dd = uctxt->dd;
377
378 pq = kzalloc(sizeof(*pq), GFP_KERNEL);
806e6e1b 379 if (!pq)
77241056 380 goto pq_nomem;
806e6e1b 381
77241056
MM
382 memsize = sizeof(*pq->reqs) * hfi1_sdma_comp_ring_size;
383 pq->reqs = kmalloc(memsize, GFP_KERNEL);
806e6e1b 384 if (!pq->reqs)
77241056 385 goto pq_reqs_nomem;
806e6e1b 386
77241056
MM
387 INIT_LIST_HEAD(&pq->list);
388 pq->dd = dd;
389 pq->ctxt = uctxt->ctxt;
9e10af47 390 pq->subctxt = fd->subctxt;
77241056
MM
391 pq->n_max_reqs = hfi1_sdma_comp_ring_size;
392 pq->state = SDMA_PKT_Q_INACTIVE;
393 atomic_set(&pq->n_reqs, 0);
a0d40693 394 init_waitqueue_head(&pq->wait);
77241056
MM
395
396 iowait_init(&pq->busy, 0, NULL, defer_packet_queue,
397 activate_packet_queue);
398 pq->reqidx = 0;
399 snprintf(buf, 64, "txreq-kmem-cache-%u-%u-%u", dd->unit, uctxt->ctxt,
9e10af47 400 fd->subctxt);
77241056
MM
401 pq->txreq_cache = kmem_cache_create(buf,
402 sizeof(struct user_sdma_txreq),
403 L1_CACHE_BYTES,
404 SLAB_HWCACHE_ALIGN,
405 sdma_kmem_cache_ctor);
406 if (!pq->txreq_cache) {
407 dd_dev_err(dd, "[%u] Failed to allocate TxReq cache\n",
408 uctxt->ctxt);
409 goto pq_txreq_nomem;
410 }
9e10af47 411 fd->pq = pq;
77241056 412 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
806e6e1b 413 if (!cq)
77241056 414 goto cq_nomem;
77241056
MM
415
416 memsize = ALIGN(sizeof(*cq->comps) * hfi1_sdma_comp_ring_size,
417 PAGE_SIZE);
418 cq->comps = vmalloc_user(memsize);
806e6e1b 419 if (!cq->comps)
77241056 420 goto cq_comps_nomem;
806e6e1b 421
77241056 422 cq->nentries = hfi1_sdma_comp_ring_size;
9e10af47 423 fd->cq = cq;
77241056
MM
424
425 spin_lock_irqsave(&uctxt->sdma_qlock, flags);
426 list_add(&pq->list, &uctxt->sdma_queues);
427 spin_unlock_irqrestore(&uctxt->sdma_qlock, flags);
428 goto done;
429
430cq_comps_nomem:
431 kfree(cq);
432cq_nomem:
433 kmem_cache_destroy(pq->txreq_cache);
434pq_txreq_nomem:
435 kfree(pq->reqs);
436pq_reqs_nomem:
437 kfree(pq);
9e10af47 438 fd->pq = NULL;
77241056
MM
439pq_nomem:
440 ret = -ENOMEM;
441done:
442 return ret;
443}
444
445int hfi1_user_sdma_free_queues(struct hfi1_filedata *fd)
446{
447 struct hfi1_ctxtdata *uctxt = fd->uctxt;
448 struct hfi1_user_sdma_pkt_q *pq;
449 unsigned long flags;
450
451 hfi1_cdbg(SDMA, "[%u:%u:%u] Freeing user SDMA queues", uctxt->dd->unit,
452 uctxt->ctxt, fd->subctxt);
453 pq = fd->pq;
454 if (pq) {
77241056
MM
455 spin_lock_irqsave(&uctxt->sdma_qlock, flags);
456 if (!list_empty(&pq->list))
457 list_del_init(&pq->list);
458 spin_unlock_irqrestore(&uctxt->sdma_qlock, flags);
459 iowait_sdma_drain(&pq->busy);
a0d40693
MH
460 /* Wait until all requests have been freed. */
461 wait_event_interruptible(
462 pq->wait,
463 (ACCESS_ONCE(pq->state) == SDMA_PKT_Q_INACTIVE));
464 kfree(pq->reqs);
adad44d1 465 kmem_cache_destroy(pq->txreq_cache);
77241056
MM
466 kfree(pq);
467 fd->pq = NULL;
468 }
469 if (fd->cq) {
a4d7d05b 470 vfree(fd->cq->comps);
77241056
MM
471 kfree(fd->cq);
472 fd->cq = NULL;
473 }
474 return 0;
475}
476
477int hfi1_user_sdma_process_request(struct file *fp, struct iovec *iovec,
478 unsigned long dim, unsigned long *count)
479{
480 int ret = 0, i = 0, sent;
9e10af47
IW
481 struct hfi1_filedata *fd = fp->private_data;
482 struct hfi1_ctxtdata *uctxt = fd->uctxt;
483 struct hfi1_user_sdma_pkt_q *pq = fd->pq;
484 struct hfi1_user_sdma_comp_q *cq = fd->cq;
77241056
MM
485 struct hfi1_devdata *dd = pq->dd;
486 unsigned long idx = 0;
487 u8 pcount = initial_pkt_count;
488 struct sdma_req_info info;
489 struct user_sdma_request *req;
490 u8 opcode, sc, vl;
491
492 if (iovec[idx].iov_len < sizeof(info) + sizeof(req->hdr)) {
493 hfi1_cdbg(
494 SDMA,
495 "[%u:%u:%u] First vector not big enough for header %lu/%lu",
9e10af47 496 dd->unit, uctxt->ctxt, fd->subctxt,
77241056 497 iovec[idx].iov_len, sizeof(info) + sizeof(req->hdr));
faa98b86 498 return -EINVAL;
77241056
MM
499 }
500 ret = copy_from_user(&info, iovec[idx].iov_base, sizeof(info));
501 if (ret) {
502 hfi1_cdbg(SDMA, "[%u:%u:%u] Failed to copy info QW (%d)",
9e10af47 503 dd->unit, uctxt->ctxt, fd->subctxt, ret);
faa98b86 504 return -EFAULT;
77241056 505 }
9e10af47 506 trace_hfi1_sdma_user_reqinfo(dd, uctxt->ctxt, fd->subctxt,
77241056
MM
507 (u16 *)&info);
508 if (cq->comps[info.comp_idx].status == QUEUED) {
509 hfi1_cdbg(SDMA, "[%u:%u:%u] Entry %u is in QUEUED state",
9e10af47 510 dd->unit, uctxt->ctxt, fd->subctxt,
77241056 511 info.comp_idx);
faa98b86 512 return -EBADSLT;
77241056
MM
513 }
514 if (!info.fragsize) {
515 hfi1_cdbg(SDMA,
516 "[%u:%u:%u:%u] Request does not specify fragsize",
9e10af47 517 dd->unit, uctxt->ctxt, fd->subctxt, info.comp_idx);
faa98b86 518 return -EINVAL;
77241056
MM
519 }
520 /*
521 * We've done all the safety checks that we can up to this point,
522 * "allocate" the request entry.
523 */
524 hfi1_cdbg(SDMA, "[%u:%u:%u] Using req/comp entry %u\n", dd->unit,
9e10af47 525 uctxt->ctxt, fd->subctxt, info.comp_idx);
77241056
MM
526 req = pq->reqs + info.comp_idx;
527 memset(req, 0, sizeof(*req));
528 /* Mark the request as IN_USE before we start filling it in. */
529 set_bit(SDMA_REQ_IN_USE, &req->flags);
530 req->data_iovs = req_iovcnt(info.ctrl) - 1;
531 req->pq = pq;
532 req->cq = cq;
a0d40693 533 req->status = -1;
77241056 534 INIT_LIST_HEAD(&req->txps);
a0d40693
MH
535 INIT_LIST_HEAD(&req->txcmp);
536 INIT_WORK(&req->worker, user_sdma_delayed_completion);
537
538 spin_lock_init(&req->txcmp_lock);
77241056
MM
539 memcpy(&req->info, &info, sizeof(info));
540
541 if (req_opcode(info.ctrl) == EXPECTED)
542 req->data_iovs--;
543
544 if (!info.npkts || req->data_iovs > MAX_VECTORS_PER_REQ) {
545 SDMA_DBG(req, "Too many vectors (%u/%u)", req->data_iovs,
546 MAX_VECTORS_PER_REQ);
faa98b86 547 return -EINVAL;
77241056
MM
548 }
549 /* Copy the header from the user buffer */
550 ret = copy_from_user(&req->hdr, iovec[idx].iov_base + sizeof(info),
551 sizeof(req->hdr));
552 if (ret) {
553 SDMA_DBG(req, "Failed to copy header template (%d)", ret);
554 ret = -EFAULT;
555 goto free_req;
556 }
557
558 /* If Static rate control is not enabled, sanitize the header. */
559 if (!HFI1_CAP_IS_USET(STATIC_RATE_CTRL))
560 req->hdr.pbc[2] = 0;
561
562 /* Validate the opcode. Do not trust packets from user space blindly. */
563 opcode = (be32_to_cpu(req->hdr.bth[0]) >> 24) & 0xff;
564 if ((opcode & USER_OPCODE_CHECK_MASK) !=
565 USER_OPCODE_CHECK_VAL) {
566 SDMA_DBG(req, "Invalid opcode (%d)", opcode);
567 ret = -EINVAL;
568 goto free_req;
569 }
570 /*
571 * Validate the vl. Do not trust packets from user space blindly.
572 * VL comes from PBC, SC comes from LRH, and the VL needs to
573 * match the SC look up.
574 */
575 vl = (le16_to_cpu(req->hdr.pbc[0]) >> 12) & 0xF;
576 sc = (((be16_to_cpu(req->hdr.lrh[0]) >> 12) & 0xF) |
577 (((le16_to_cpu(req->hdr.pbc[1]) >> 14) & 0x1) << 4));
578 if (vl >= dd->pport->vls_operational ||
579 vl != sc_to_vlt(dd, sc)) {
580 SDMA_DBG(req, "Invalid SC(%u)/VL(%u)", sc, vl);
581 ret = -EINVAL;
582 goto free_req;
583 }
584
585 /*
586 * Also should check the BTH.lnh. If it says the next header is GRH then
587 * the RXE parsing will be off and will land in the middle of the KDETH
588 * or miss it entirely.
589 */
590 if ((be16_to_cpu(req->hdr.lrh[0]) & 0x3) == HFI1_LRH_GRH) {
591 SDMA_DBG(req, "User tried to pass in a GRH");
592 ret = -EINVAL;
593 goto free_req;
594 }
595
596 req->koffset = le32_to_cpu(req->hdr.kdeth.swdata[6]);
597 /* Calculate the initial TID offset based on the values of
598 KDETH.OFFSET and KDETH.OM that are passed in. */
599 req->tidoffset = KDETH_GET(req->hdr.kdeth.ver_tid_offset, OFFSET) *
600 (KDETH_GET(req->hdr.kdeth.ver_tid_offset, OM) ?
601 KDETH_OM_LARGE : KDETH_OM_SMALL);
602 SDMA_DBG(req, "Initial TID offset %u", req->tidoffset);
603 idx++;
604
605 /* Save all the IO vector structures */
606 while (i < req->data_iovs) {
607 memcpy(&req->iovs[i].iov, iovec + idx++, sizeof(struct iovec));
608 req->iovs[i].offset = 0;
609 req->data_len += req->iovs[i++].iov.iov_len;
610 }
611 SDMA_DBG(req, "total data length %u", req->data_len);
612
613 if (pcount > req->info.npkts)
614 pcount = req->info.npkts;
615 /*
616 * Copy any TID info
617 * User space will provide the TID info only when the
618 * request type is EXPECTED. This is true even if there is
619 * only one packet in the request and the header is already
620 * setup. The reason for the singular TID case is that the
621 * driver needs to perform safety checks.
622 */
623 if (req_opcode(req->info.ctrl) == EXPECTED) {
624 u16 ntids = iovec[idx].iov_len / sizeof(*req->tids);
625
626 if (!ntids || ntids > MAX_TID_PAIR_ENTRIES) {
627 ret = -EINVAL;
628 goto free_req;
629 }
630 req->tids = kcalloc(ntids, sizeof(*req->tids), GFP_KERNEL);
631 if (!req->tids) {
632 ret = -ENOMEM;
633 goto free_req;
634 }
635 /*
636 * We have to copy all of the tids because they may vary
637 * in size and, therefore, the TID count might not be
638 * equal to the pkt count. However, there is no way to
639 * tell at this point.
640 */
641 ret = copy_from_user(req->tids, iovec[idx].iov_base,
642 ntids * sizeof(*req->tids));
643 if (ret) {
644 SDMA_DBG(req, "Failed to copy %d TIDs (%d)",
645 ntids, ret);
646 ret = -EFAULT;
647 goto free_req;
648 }
649 req->n_tids = ntids;
650 idx++;
651 }
652
653 /* Have to select the engine */
654 req->sde = sdma_select_engine_vl(dd,
9e10af47 655 (u32)(uctxt->ctxt + fd->subctxt),
77241056
MM
656 vl);
657 if (!req->sde || !sdma_running(req->sde)) {
658 ret = -ECOMM;
659 goto free_req;
660 }
661
662 /* We don't need an AHG entry if the request contains only one packet */
663 if (req->info.npkts > 1 && HFI1_CAP_IS_USET(SDMA_AHG)) {
664 int ahg = sdma_ahg_alloc(req->sde);
665
666 if (likely(ahg >= 0)) {
667 req->ahg_idx = (u8)ahg;
668 set_bit(SDMA_REQ_HAVE_AHG, &req->flags);
669 }
670 }
671
672 set_comp_state(req, QUEUED, 0);
673 /* Send the first N packets in the request to buy us some time */
674 sent = user_sdma_send_pkts(req, pcount);
675 if (unlikely(sent < 0)) {
676 if (sent != -EBUSY) {
a0d40693
MH
677 req->status = sent;
678 set_comp_state(req, ERROR, req->status);
679 return sent;
77241056
MM
680 } else
681 sent = 0;
682 }
683 atomic_inc(&pq->n_reqs);
a0d40693 684 xchg(&pq->state, SDMA_PKT_Q_ACTIVE);
77241056
MM
685
686 if (sent < req->info.npkts) {
77241056
MM
687 /*
688 * This is a somewhat blocking send implementation.
689 * The driver will block the caller until all packets of the
690 * request have been submitted to the SDMA engine. However, it
691 * will not wait for send completions.
692 */
693 while (!test_bit(SDMA_REQ_SEND_DONE, &req->flags)) {
694 ret = user_sdma_send_pkts(req, pcount);
695 if (ret < 0) {
a0d40693
MH
696 if (ret != -EBUSY) {
697 req->status = ret;
698 return ret;
699 }
77241056
MM
700 wait_event_interruptible_timeout(
701 pq->busy.wait_dma,
702 (pq->state == SDMA_PKT_Q_ACTIVE),
703 msecs_to_jiffies(
704 SDMA_IOWAIT_TIMEOUT));
705 }
706 }
707
708 }
77241056 709 *count += idx;
a0d40693 710 return 0;
77241056
MM
711free_req:
712 user_sdma_free_request(req);
77241056
MM
713 return ret;
714}
715
716static inline u32 compute_data_length(struct user_sdma_request *req,
717 struct user_sdma_txreq *tx)
718{
719 /*
720 * Determine the proper size of the packet data.
721 * The size of the data of the first packet is in the header
722 * template. However, it includes the header and ICRC, which need
723 * to be subtracted.
724 * The size of the remaining packets is the minimum of the frag
725 * size (MTU) or remaining data in the request.
726 */
727 u32 len;
728
729 if (!req->seqnum) {
730 len = ((be16_to_cpu(req->hdr.lrh[2]) << 2) -
731 (sizeof(tx->hdr) - 4));
732 } else if (req_opcode(req->info.ctrl) == EXPECTED) {
733 u32 tidlen = EXP_TID_GET(req->tids[req->tididx], LEN) *
734 PAGE_SIZE;
735 /* Get the data length based on the remaining space in the
736 * TID pair. */
737 len = min(tidlen - req->tidoffset, (u32)req->info.fragsize);
738 /* If we've filled up the TID pair, move to the next one. */
739 if (unlikely(!len) && ++req->tididx < req->n_tids &&
740 req->tids[req->tididx]) {
741 tidlen = EXP_TID_GET(req->tids[req->tididx],
742 LEN) * PAGE_SIZE;
743 req->tidoffset = 0;
744 len = min_t(u32, tidlen, req->info.fragsize);
745 }
746 /* Since the TID pairs map entire pages, make sure that we
747 * are not going to try to send more data that we have
748 * remaining. */
749 len = min(len, req->data_len - req->sent);
750 } else
751 len = min(req->data_len - req->sent, (u32)req->info.fragsize);
752 SDMA_DBG(req, "Data Length = %u", len);
753 return len;
754}
755
756static inline u32 get_lrh_len(struct hfi1_pkt_header hdr, u32 len)
757{
758 /* (Size of complete header - size of PBC) + 4B ICRC + data length */
759 return ((sizeof(hdr) - sizeof(hdr.pbc)) + 4 + len);
760}
761
762static int user_sdma_send_pkts(struct user_sdma_request *req, unsigned maxpkts)
763{
764 int ret = 0;
765 unsigned npkts = 0;
766 struct user_sdma_txreq *tx = NULL;
767 struct hfi1_user_sdma_pkt_q *pq = NULL;
768 struct user_sdma_iovec *iovec = NULL;
769
faa98b86
MH
770 if (!req->pq)
771 return -EINVAL;
77241056
MM
772
773 pq = req->pq;
774
6a5464f2
MH
775 /* If tx completion has reported an error, we are done. */
776 if (test_bit(SDMA_REQ_HAS_ERROR, &req->flags)) {
777 set_bit(SDMA_REQ_DONE_ERROR, &req->flags);
778 return -EFAULT;
779 }
780
77241056
MM
781 /*
782 * Check if we might have sent the entire request already
783 */
784 if (unlikely(req->seqnum == req->info.npkts)) {
785 if (!list_empty(&req->txps))
786 goto dosend;
faa98b86 787 return ret;
77241056
MM
788 }
789
790 if (!maxpkts || maxpkts > req->info.npkts - req->seqnum)
791 maxpkts = req->info.npkts - req->seqnum;
792
793 while (npkts < maxpkts) {
794 u32 datalen = 0, queued = 0, data_sent = 0;
795 u64 iov_offset = 0;
796
797 /*
798 * Check whether any of the completions have come back
799 * with errors. If so, we are not going to process any
800 * more packets from this request.
801 */
802 if (test_bit(SDMA_REQ_HAS_ERROR, &req->flags)) {
803 set_bit(SDMA_REQ_DONE_ERROR, &req->flags);
faa98b86 804 return -EFAULT;
77241056
MM
805 }
806
807 tx = kmem_cache_alloc(pq->txreq_cache, GFP_KERNEL);
faa98b86
MH
808 if (!tx)
809 return -ENOMEM;
810
77241056
MM
811 tx->flags = 0;
812 tx->req = req;
813 tx->busycount = 0;
b9fb6318 814 tx->idx = -1;
a0d40693 815 INIT_LIST_HEAD(&tx->list);
b9fb6318 816 memset(tx->iovecs, 0, sizeof(tx->iovecs));
77241056
MM
817
818 if (req->seqnum == req->info.npkts - 1)
b9fb6318 819 tx->flags |= TXREQ_FLAGS_REQ_LAST_PKT;
77241056
MM
820
821 /*
822 * Calculate the payload size - this is min of the fragment
823 * (MTU) size or the remaining bytes in the request but only
824 * if we have payload data.
825 */
826 if (req->data_len) {
827 iovec = &req->iovs[req->iov_idx];
828 if (ACCESS_ONCE(iovec->offset) == iovec->iov.iov_len) {
829 if (++req->iov_idx == req->data_iovs) {
830 ret = -EFAULT;
831 goto free_txreq;
832 }
833 iovec = &req->iovs[req->iov_idx];
834 WARN_ON(iovec->offset);
835 }
836
837 /*
838 * This request might include only a header and no user
839 * data, so pin pages only if there is data and it the
840 * pages have not been pinned already.
841 */
842 if (unlikely(!iovec->pages && iovec->iov.iov_len)) {
843 ret = pin_vector_pages(req, iovec);
844 if (ret)
845 goto free_tx;
846 }
847
b9fb6318 848 tx->iovecs[++tx->idx].vec = iovec;
77241056
MM
849 datalen = compute_data_length(req, tx);
850 if (!datalen) {
851 SDMA_DBG(req,
852 "Request has data but pkt len is 0");
853 ret = -EFAULT;
854 goto free_tx;
855 }
856 }
857
858 if (test_bit(SDMA_REQ_HAVE_AHG, &req->flags)) {
859 if (!req->seqnum) {
860 u16 pbclen = le16_to_cpu(req->hdr.pbc[0]);
861 u32 lrhlen = get_lrh_len(req->hdr, datalen);
862 /*
863 * Copy the request header into the tx header
864 * because the HW needs a cacheline-aligned
865 * address.
866 * This copy can be optimized out if the hdr
867 * member of user_sdma_request were also
868 * cacheline aligned.
869 */
870 memcpy(&tx->hdr, &req->hdr, sizeof(tx->hdr));
871 if (PBC2LRH(pbclen) != lrhlen) {
872 pbclen = (pbclen & 0xf000) |
873 LRH2PBC(lrhlen);
874 tx->hdr.pbc[0] = cpu_to_le16(pbclen);
875 }
876 ret = sdma_txinit_ahg(&tx->txreq,
877 SDMA_TXREQ_F_AHG_COPY,
878 sizeof(tx->hdr) + datalen,
879 req->ahg_idx, 0, NULL, 0,
880 user_sdma_txreq_cb);
881 if (ret)
882 goto free_tx;
883 ret = sdma_txadd_kvaddr(pq->dd, &tx->txreq,
884 &tx->hdr,
885 sizeof(tx->hdr));
886 if (ret)
887 goto free_txreq;
888 } else {
889 int changes;
890
891 changes = set_txreq_header_ahg(req, tx,
892 datalen);
893 if (changes < 0)
894 goto free_tx;
895 sdma_txinit_ahg(&tx->txreq,
896 SDMA_TXREQ_F_USE_AHG,
897 datalen, req->ahg_idx, changes,
898 req->ahg, sizeof(req->hdr),
899 user_sdma_txreq_cb);
900 }
901 } else {
902 ret = sdma_txinit(&tx->txreq, 0, sizeof(req->hdr) +
903 datalen, user_sdma_txreq_cb);
904 if (ret)
905 goto free_tx;
906 /*
907 * Modify the header for this packet. This only needs
908 * to be done if we are not going to use AHG. Otherwise,
909 * the HW will do it based on the changes we gave it
910 * during sdma_txinit_ahg().
911 */
912 ret = set_txreq_header(req, tx, datalen);
913 if (ret)
914 goto free_txreq;
915 }
916
917 /*
918 * If the request contains any data vectors, add up to
919 * fragsize bytes to the descriptor.
920 */
921 while (queued < datalen &&
922 (req->sent + data_sent) < req->data_len) {
923 unsigned long base, offset;
924 unsigned pageidx, len;
925
926 base = (unsigned long)iovec->iov.iov_base;
72a5f6a8
AKC
927 offset = offset_in_page(base + iovec->offset +
928 iov_offset);
77241056
MM
929 pageidx = (((iovec->offset + iov_offset +
930 base) - (base & PAGE_MASK)) >> PAGE_SHIFT);
931 len = offset + req->info.fragsize > PAGE_SIZE ?
932 PAGE_SIZE - offset : req->info.fragsize;
933 len = min((datalen - queued), len);
934 ret = sdma_txadd_page(pq->dd, &tx->txreq,
935 iovec->pages[pageidx],
936 offset, len);
937 if (ret) {
b9fb6318
MH
938 int i;
939
a0d40693
MH
940 SDMA_DBG(req, "SDMA txreq add page failed %d\n",
941 ret);
b9fb6318
MH
942 /* Mark all assigned vectors as complete so they
943 * are unpinned in the callback. */
944 for (i = tx->idx; i >= 0; i--) {
945 tx->iovecs[i].flags |=
946 TXREQ_FLAGS_IOVEC_LAST_PKT;
947 }
77241056
MM
948 goto free_txreq;
949 }
950 iov_offset += len;
951 queued += len;
952 data_sent += len;
953 if (unlikely(queued < datalen &&
954 pageidx == iovec->npages &&
b9fb6318
MH
955 req->iov_idx < req->data_iovs - 1 &&
956 tx->idx < ARRAY_SIZE(tx->iovecs))) {
77241056 957 iovec->offset += iov_offset;
b9fb6318
MH
958 tx->iovecs[tx->idx].flags |=
959 TXREQ_FLAGS_IOVEC_LAST_PKT;
77241056
MM
960 iovec = &req->iovs[++req->iov_idx];
961 if (!iovec->pages) {
962 ret = pin_vector_pages(req, iovec);
963 if (ret)
964 goto free_txreq;
965 }
966 iov_offset = 0;
b9fb6318 967 tx->iovecs[++tx->idx].vec = iovec;
77241056
MM
968 }
969 }
970 /*
971 * The txreq was submitted successfully so we can update
972 * the counters.
973 */
974 req->koffset += datalen;
975 if (req_opcode(req->info.ctrl) == EXPECTED)
976 req->tidoffset += datalen;
977 req->sent += data_sent;
978 if (req->data_len) {
b9fb6318
MH
979 tx->iovecs[tx->idx].vec->offset += iov_offset;
980 /* If we've reached the end of the io vector, mark it
981 * so the callback can unpin the pages and free it. */
982 if (tx->iovecs[tx->idx].vec->offset ==
983 tx->iovecs[tx->idx].vec->iov.iov_len)
984 tx->iovecs[tx->idx].flags |=
985 TXREQ_FLAGS_IOVEC_LAST_PKT;
77241056 986 }
b9fb6318 987
77241056
MM
988 /*
989 * It is important to increment this here as it is used to
990 * generate the BTH.PSN and, therefore, can't be bulk-updated
991 * outside of the loop.
992 */
993 tx->seqnum = req->seqnum++;
994 list_add_tail(&tx->txreq.list, &req->txps);
995 npkts++;
996 }
997dosend:
998 ret = sdma_send_txlist(req->sde, &pq->busy, &req->txps);
999 if (list_empty(&req->txps))
1000 if (req->seqnum == req->info.npkts) {
1001 set_bit(SDMA_REQ_SEND_DONE, &req->flags);
1002 /*
1003 * The txreq has already been submitted to the HW queue
1004 * so we can free the AHG entry now. Corruption will not
1005 * happen due to the sequential manner in which
1006 * descriptors are processed.
1007 */
1008 if (test_bit(SDMA_REQ_HAVE_AHG, &req->flags))
1009 sdma_ahg_free(req->sde, req->ahg_idx);
1010 }
faa98b86
MH
1011 return ret;
1012
77241056
MM
1013free_txreq:
1014 sdma_txclean(pq->dd, &tx->txreq);
1015free_tx:
1016 kmem_cache_free(pq->txreq_cache, tx);
77241056
MM
1017 return ret;
1018}
1019
1020/*
1021 * How many pages in this iovec element?
1022 */
1023static inline int num_user_pages(const struct iovec *iov)
1024{
1025 const unsigned long addr = (unsigned long) iov->iov_base;
1026 const unsigned long len = iov->iov_len;
1027 const unsigned long spage = addr & PAGE_MASK;
1028 const unsigned long epage = (addr + len - 1) & PAGE_MASK;
1029
1030 return 1 + ((epage - spage) >> PAGE_SHIFT);
1031}
1032
1033static int pin_vector_pages(struct user_sdma_request *req,
1034 struct user_sdma_iovec *iovec) {
a0d40693 1035 int pinned, npages;
77241056 1036
a0d40693
MH
1037 npages = num_user_pages(&iovec->iov);
1038 iovec->pages = kcalloc(npages, sizeof(*iovec->pages), GFP_KERNEL);
77241056
MM
1039 if (!iovec->pages) {
1040 SDMA_DBG(req, "Failed page array alloc");
a0d40693 1041 return -ENOMEM;
77241056 1042 }
a0d40693
MH
1043
1044 /*
1045 * Get a reference to the process's mm so we can use it when
1046 * unpinning the io vectors.
1047 */
1048 req->pq->user_mm = get_task_mm(current);
1049
1050 pinned = hfi1_acquire_user_pages((unsigned long)iovec->iov.iov_base,
1051 npages, 0, iovec->pages);
1052
1053 if (pinned < 0)
1054 return pinned;
1055
1056 iovec->npages = pinned;
1057 if (pinned != npages) {
1058 SDMA_DBG(req, "Failed to pin pages (%d/%u)", pinned, npages);
1059 unpin_vector_pages(req, iovec);
1060 return -EFAULT;
77241056 1061 }
a0d40693 1062 return 0;
77241056
MM
1063}
1064
a0d40693
MH
1065static void unpin_vector_pages(struct user_sdma_request *req,
1066 struct user_sdma_iovec *iovec)
77241056 1067{
a0d40693
MH
1068 /*
1069 * Unpinning is done through the workqueue so use the
1070 * process's mm if we have a reference to it.
1071 */
1072 if ((current->flags & PF_KTHREAD) && req->pq->user_mm)
1073 use_mm(req->pq->user_mm);
77241056 1074
a0d40693
MH
1075 hfi1_release_user_pages(iovec->pages, iovec->npages, 0);
1076
1077 /*
1078 * Unuse the user's mm (see above) and release the
1079 * reference to it.
1080 */
1081 if (req->pq->user_mm) {
1082 if (current->flags & PF_KTHREAD)
1083 unuse_mm(req->pq->user_mm);
1084 mmput(req->pq->user_mm);
77241056 1085 }
a0d40693 1086
77241056
MM
1087 kfree(iovec->pages);
1088 iovec->pages = NULL;
1089 iovec->npages = 0;
1090 iovec->offset = 0;
1091}
1092
1093static int check_header_template(struct user_sdma_request *req,
1094 struct hfi1_pkt_header *hdr, u32 lrhlen,
1095 u32 datalen)
1096{
1097 /*
1098 * Perform safety checks for any type of packet:
1099 * - transfer size is multiple of 64bytes
1100 * - packet length is multiple of 4bytes
1101 * - entire request length is multiple of 4bytes
1102 * - packet length is not larger than MTU size
1103 *
1104 * These checks are only done for the first packet of the
1105 * transfer since the header is "given" to us by user space.
1106 * For the remainder of the packets we compute the values.
1107 */
1108 if (req->info.fragsize % PIO_BLOCK_SIZE ||
1109 lrhlen & 0x3 || req->data_len & 0x3 ||
1110 lrhlen > get_lrh_len(*hdr, req->info.fragsize))
1111 return -EINVAL;
1112
1113 if (req_opcode(req->info.ctrl) == EXPECTED) {
1114 /*
1115 * The header is checked only on the first packet. Furthermore,
1116 * we ensure that at least one TID entry is copied when the
1117 * request is submitted. Therefore, we don't have to verify that
1118 * tididx points to something sane.
1119 */
1120 u32 tidval = req->tids[req->tididx],
1121 tidlen = EXP_TID_GET(tidval, LEN) * PAGE_SIZE,
1122 tididx = EXP_TID_GET(tidval, IDX),
1123 tidctrl = EXP_TID_GET(tidval, CTRL),
1124 tidoff;
1125 __le32 kval = hdr->kdeth.ver_tid_offset;
1126
1127 tidoff = KDETH_GET(kval, OFFSET) *
1128 (KDETH_GET(req->hdr.kdeth.ver_tid_offset, OM) ?
1129 KDETH_OM_LARGE : KDETH_OM_SMALL);
1130 /*
1131 * Expected receive packets have the following
1132 * additional checks:
1133 * - offset is not larger than the TID size
1134 * - TIDCtrl values match between header and TID array
1135 * - TID indexes match between header and TID array
1136 */
1137 if ((tidoff + datalen > tidlen) ||
1138 KDETH_GET(kval, TIDCTRL) != tidctrl ||
1139 KDETH_GET(kval, TID) != tididx)
1140 return -EINVAL;
1141 }
1142 return 0;
1143}
1144
1145/*
1146 * Correctly set the BTH.PSN field based on type of
1147 * transfer - eager packets can just increment the PSN but
1148 * expected packets encode generation and sequence in the
1149 * BTH.PSN field so just incrementing will result in errors.
1150 */
1151static inline u32 set_pkt_bth_psn(__be32 bthpsn, u8 expct, u32 frags)
1152{
1153 u32 val = be32_to_cpu(bthpsn),
1154 mask = (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffffull :
1155 0xffffffull),
1156 psn = val & mask;
1157 if (expct)
1158 psn = (psn & ~BTH_SEQ_MASK) | ((psn + frags) & BTH_SEQ_MASK);
1159 else
1160 psn = psn + frags;
1161 return psn & mask;
1162}
1163
1164static int set_txreq_header(struct user_sdma_request *req,
1165 struct user_sdma_txreq *tx, u32 datalen)
1166{
1167 struct hfi1_user_sdma_pkt_q *pq = req->pq;
1168 struct hfi1_pkt_header *hdr = &tx->hdr;
1169 u16 pbclen;
1170 int ret;
1171 u32 tidval = 0, lrhlen = get_lrh_len(*hdr, datalen);
1172
1173 /* Copy the header template to the request before modification */
1174 memcpy(hdr, &req->hdr, sizeof(*hdr));
1175
1176 /*
1177 * Check if the PBC and LRH length are mismatched. If so
1178 * adjust both in the header.
1179 */
1180 pbclen = le16_to_cpu(hdr->pbc[0]);
1181 if (PBC2LRH(pbclen) != lrhlen) {
1182 pbclen = (pbclen & 0xf000) | LRH2PBC(lrhlen);
1183 hdr->pbc[0] = cpu_to_le16(pbclen);
1184 hdr->lrh[2] = cpu_to_be16(lrhlen >> 2);
1185 /*
1186 * Third packet
1187 * This is the first packet in the sequence that has
1188 * a "static" size that can be used for the rest of
1189 * the packets (besides the last one).
1190 */
1191 if (unlikely(req->seqnum == 2)) {
1192 /*
1193 * From this point on the lengths in both the
1194 * PBC and LRH are the same until the last
1195 * packet.
1196 * Adjust the template so we don't have to update
1197 * every packet
1198 */
1199 req->hdr.pbc[0] = hdr->pbc[0];
1200 req->hdr.lrh[2] = hdr->lrh[2];
1201 }
1202 }
1203 /*
1204 * We only have to modify the header if this is not the
1205 * first packet in the request. Otherwise, we use the
1206 * header given to us.
1207 */
1208 if (unlikely(!req->seqnum)) {
1209 ret = check_header_template(req, hdr, lrhlen, datalen);
1210 if (ret)
1211 return ret;
1212 goto done;
1213
1214 }
1215
1216 hdr->bth[2] = cpu_to_be32(
1217 set_pkt_bth_psn(hdr->bth[2],
1218 (req_opcode(req->info.ctrl) == EXPECTED),
1219 req->seqnum));
1220
1221 /* Set ACK request on last packet */
b9fb6318 1222 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT))
77241056
MM
1223 hdr->bth[2] |= cpu_to_be32(1UL<<31);
1224
1225 /* Set the new offset */
1226 hdr->kdeth.swdata[6] = cpu_to_le32(req->koffset);
1227 /* Expected packets have to fill in the new TID information */
1228 if (req_opcode(req->info.ctrl) == EXPECTED) {
1229 tidval = req->tids[req->tididx];
1230 /*
1231 * If the offset puts us at the end of the current TID,
1232 * advance everything.
1233 */
1234 if ((req->tidoffset) == (EXP_TID_GET(tidval, LEN) *
1235 PAGE_SIZE)) {
1236 req->tidoffset = 0;
1237 /* Since we don't copy all the TIDs, all at once,
1238 * we have to check again. */
1239 if (++req->tididx > req->n_tids - 1 ||
1240 !req->tids[req->tididx]) {
1241 return -EINVAL;
1242 }
1243 tidval = req->tids[req->tididx];
1244 }
1245 req->omfactor = EXP_TID_GET(tidval, LEN) * PAGE_SIZE >=
1246 KDETH_OM_MAX_SIZE ? KDETH_OM_LARGE : KDETH_OM_SMALL;
1247 /* Set KDETH.TIDCtrl based on value for this TID. */
1248 KDETH_SET(hdr->kdeth.ver_tid_offset, TIDCTRL,
1249 EXP_TID_GET(tidval, CTRL));
1250 /* Set KDETH.TID based on value for this TID */
1251 KDETH_SET(hdr->kdeth.ver_tid_offset, TID,
1252 EXP_TID_GET(tidval, IDX));
1253 /* Clear KDETH.SH only on the last packet */
b9fb6318 1254 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT))
77241056
MM
1255 KDETH_SET(hdr->kdeth.ver_tid_offset, SH, 0);
1256 /*
1257 * Set the KDETH.OFFSET and KDETH.OM based on size of
1258 * transfer.
1259 */
1260 SDMA_DBG(req, "TID offset %ubytes %uunits om%u",
1261 req->tidoffset, req->tidoffset / req->omfactor,
1262 !!(req->omfactor - KDETH_OM_SMALL));
1263 KDETH_SET(hdr->kdeth.ver_tid_offset, OFFSET,
1264 req->tidoffset / req->omfactor);
1265 KDETH_SET(hdr->kdeth.ver_tid_offset, OM,
1266 !!(req->omfactor - KDETH_OM_SMALL));
1267 }
1268done:
1269 trace_hfi1_sdma_user_header(pq->dd, pq->ctxt, pq->subctxt,
1270 req->info.comp_idx, hdr, tidval);
1271 return sdma_txadd_kvaddr(pq->dd, &tx->txreq, hdr, sizeof(*hdr));
1272}
1273
1274static int set_txreq_header_ahg(struct user_sdma_request *req,
1275 struct user_sdma_txreq *tx, u32 len)
1276{
1277 int diff = 0;
1278 struct hfi1_user_sdma_pkt_q *pq = req->pq;
1279 struct hfi1_pkt_header *hdr = &req->hdr;
1280 u16 pbclen = le16_to_cpu(hdr->pbc[0]);
1281 u32 val32, tidval = 0, lrhlen = get_lrh_len(*hdr, len);
1282
1283 if (PBC2LRH(pbclen) != lrhlen) {
1284 /* PBC.PbcLengthDWs */
1285 AHG_HEADER_SET(req->ahg, diff, 0, 0, 12,
1286 cpu_to_le16(LRH2PBC(lrhlen)));
1287 /* LRH.PktLen (we need the full 16 bits due to byte swap) */
1288 AHG_HEADER_SET(req->ahg, diff, 3, 0, 16,
1289 cpu_to_be16(lrhlen >> 2));
1290 }
1291
1292 /*
1293 * Do the common updates
1294 */
1295 /* BTH.PSN and BTH.A */
1296 val32 = (be32_to_cpu(hdr->bth[2]) + req->seqnum) &
1297 (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffff : 0xffffff);
b9fb6318 1298 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT))
77241056
MM
1299 val32 |= 1UL << 31;
1300 AHG_HEADER_SET(req->ahg, diff, 6, 0, 16, cpu_to_be16(val32 >> 16));
1301 AHG_HEADER_SET(req->ahg, diff, 6, 16, 16, cpu_to_be16(val32 & 0xffff));
1302 /* KDETH.Offset */
1303 AHG_HEADER_SET(req->ahg, diff, 15, 0, 16,
1304 cpu_to_le16(req->koffset & 0xffff));
1305 AHG_HEADER_SET(req->ahg, diff, 15, 16, 16,
1306 cpu_to_le16(req->koffset >> 16));
1307 if (req_opcode(req->info.ctrl) == EXPECTED) {
1308 __le16 val;
1309
1310 tidval = req->tids[req->tididx];
1311
1312 /*
1313 * If the offset puts us at the end of the current TID,
1314 * advance everything.
1315 */
1316 if ((req->tidoffset) == (EXP_TID_GET(tidval, LEN) *
1317 PAGE_SIZE)) {
1318 req->tidoffset = 0;
1319 /* Since we don't copy all the TIDs, all at once,
1320 * we have to check again. */
1321 if (++req->tididx > req->n_tids - 1 ||
1322 !req->tids[req->tididx]) {
1323 return -EINVAL;
1324 }
1325 tidval = req->tids[req->tididx];
1326 }
1327 req->omfactor = ((EXP_TID_GET(tidval, LEN) *
1328 PAGE_SIZE) >=
1329 KDETH_OM_MAX_SIZE) ? KDETH_OM_LARGE :
1330 KDETH_OM_SMALL;
1331 /* KDETH.OM and KDETH.OFFSET (TID) */
1332 AHG_HEADER_SET(req->ahg, diff, 7, 0, 16,
1333 ((!!(req->omfactor - KDETH_OM_SMALL)) << 15 |
1334 ((req->tidoffset / req->omfactor) & 0x7fff)));
1335 /* KDETH.TIDCtrl, KDETH.TID */
1336 val = cpu_to_le16(((EXP_TID_GET(tidval, CTRL) & 0x3) << 10) |
1337 (EXP_TID_GET(tidval, IDX) & 0x3ff));
1338 /* Clear KDETH.SH on last packet */
b9fb6318 1339 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) {
77241056
MM
1340 val |= cpu_to_le16(KDETH_GET(hdr->kdeth.ver_tid_offset,
1341 INTR) >> 16);
1342 val &= cpu_to_le16(~(1U << 13));
1343 AHG_HEADER_SET(req->ahg, diff, 7, 16, 14, val);
1344 } else
1345 AHG_HEADER_SET(req->ahg, diff, 7, 16, 12, val);
1346 }
1347
1348 trace_hfi1_sdma_user_header_ahg(pq->dd, pq->ctxt, pq->subctxt,
1349 req->info.comp_idx, req->sde->this_idx,
1350 req->ahg_idx, req->ahg, diff, tidval);
1351 return diff;
1352}
1353
a0d40693
MH
1354/*
1355 * SDMA tx request completion callback. Called when the SDMA progress
1356 * state machine gets notification that the SDMA descriptors for this
1357 * tx request have been processed by the DMA engine. Called in
1358 * interrupt context.
1359 */
77241056
MM
1360static void user_sdma_txreq_cb(struct sdma_txreq *txreq, int status,
1361 int drain)
1362{
1363 struct user_sdma_txreq *tx =
1364 container_of(txreq, struct user_sdma_txreq, txreq);
a0d40693
MH
1365 struct user_sdma_request *req;
1366 bool defer;
1367 int i;
77241056 1368
a0d40693 1369 if (!tx->req)
77241056
MM
1370 return;
1371
a0d40693
MH
1372 req = tx->req;
1373 /*
1374 * If this is the callback for the last packet of the request,
1375 * queue up the request for clean up.
1376 */
1377 defer = (tx->seqnum == req->info.npkts - 1);
b9fb6318 1378
a0d40693
MH
1379 /*
1380 * If we have any io vectors associated with this txreq,
1381 * check whether they need to be 'freed'. We can't free them
1382 * here because the unpin function needs to be able to sleep.
1383 */
1384 for (i = tx->idx; i >= 0; i--) {
1385 if (tx->iovecs[i].flags & TXREQ_FLAGS_IOVEC_LAST_PKT) {
1386 defer = true;
1387 break;
b9fb6318
MH
1388 }
1389 }
77241056 1390
a0d40693 1391 req->status = status;
77241056 1392 if (status != SDMA_TXREQ_S_OK) {
a0d40693
MH
1393 SDMA_DBG(req, "SDMA completion with error %d",
1394 status);
77241056 1395 set_bit(SDMA_REQ_HAS_ERROR, &req->flags);
a0d40693
MH
1396 defer = true;
1397 }
1398
1399 /*
1400 * Defer the clean up of the iovectors and the request until later
1401 * so it can be done outside of interrupt context.
1402 */
1403 if (defer) {
1404 spin_lock(&req->txcmp_lock);
1405 list_add_tail(&tx->list, &req->txcmp);
1406 spin_unlock(&req->txcmp_lock);
1407 schedule_work(&req->worker);
77241056 1408 } else {
a0d40693
MH
1409 kmem_cache_free(req->pq->txreq_cache, tx);
1410 }
1411}
1412
1413static void user_sdma_delayed_completion(struct work_struct *work)
1414{
1415 struct user_sdma_request *req =
1416 container_of(work, struct user_sdma_request, worker);
1417 struct hfi1_user_sdma_pkt_q *pq = req->pq;
1418 struct user_sdma_txreq *tx = NULL;
1419 unsigned long flags;
1420 u64 seqnum;
1421 int i;
1422
1423 while (1) {
1424 spin_lock_irqsave(&req->txcmp_lock, flags);
1425 if (!list_empty(&req->txcmp)) {
1426 tx = list_first_entry(&req->txcmp,
1427 struct user_sdma_txreq, list);
1428 list_del(&tx->list);
1429 }
1430 spin_unlock_irqrestore(&req->txcmp_lock, flags);
1431 if (!tx)
1432 break;
1433
1434 for (i = tx->idx; i >= 0; i--)
1435 if (tx->iovecs[i].flags & TXREQ_FLAGS_IOVEC_LAST_PKT)
1436 unpin_vector_pages(req, tx->iovecs[i].vec);
1437
1438 seqnum = tx->seqnum;
1439 kmem_cache_free(pq->txreq_cache, tx);
1440 tx = NULL;
1441
1442 if (req->status != SDMA_TXREQ_S_OK) {
1443 if (seqnum == ACCESS_ONCE(req->seqnum) &&
1444 test_bit(SDMA_REQ_DONE_ERROR, &req->flags)) {
1445 atomic_dec(&pq->n_reqs);
1446 set_comp_state(req, ERROR, req->status);
1447 user_sdma_free_request(req);
1448 break;
1449 }
1450 } else {
1451 if (seqnum == req->info.npkts - 1) {
1452 atomic_dec(&pq->n_reqs);
1453 set_comp_state(req, COMPLETE, 0);
1454 user_sdma_free_request(req);
1455 break;
1456 }
77241056
MM
1457 }
1458 }
a0d40693
MH
1459
1460 if (!atomic_read(&pq->n_reqs)) {
77241056 1461 xchg(&pq->state, SDMA_PKT_Q_INACTIVE);
a0d40693
MH
1462 wake_up(&pq->wait);
1463 }
77241056
MM
1464}
1465
1466static void user_sdma_free_request(struct user_sdma_request *req)
1467{
1468 if (!list_empty(&req->txps)) {
1469 struct sdma_txreq *t, *p;
1470
1471 list_for_each_entry_safe(t, p, &req->txps, list) {
1472 struct user_sdma_txreq *tx =
1473 container_of(t, struct user_sdma_txreq, txreq);
1474 list_del_init(&t->list);
1475 sdma_txclean(req->pq->dd, t);
1476 kmem_cache_free(req->pq->txreq_cache, tx);
1477 }
1478 }
1479 if (req->data_iovs) {
1480 int i;
1481
1482 for (i = 0; i < req->data_iovs; i++)
1483 if (req->iovs[i].npages && req->iovs[i].pages)
a0d40693 1484 unpin_vector_pages(req, &req->iovs[i]);
77241056 1485 }
77241056
MM
1486 kfree(req->tids);
1487 clear_bit(SDMA_REQ_IN_USE, &req->flags);
1488}
1489
1490static inline void set_comp_state(struct user_sdma_request *req,
1491 enum hfi1_sdma_comp_state state,
1492 int ret)
1493{
1494 SDMA_DBG(req, "Setting completion status %u %d", state, ret);
1495 req->cq->comps[req->info.comp_idx].status = state;
1496 if (state == ERROR)
1497 req->cq->comps[req->info.comp_idx].errcode = -ret;
1498 trace_hfi1_sdma_user_completion(req->pq->dd, req->pq->ctxt,
1499 req->pq->subctxt, req->info.comp_idx,
1500 state, ret);
1501}