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Staging:rtl888eu:include Fix CamelCase issue
[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / rtl8188eu / hal / odm.c
CommitLineData
18b0950e
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
18b0950e
LF		 14 ******************************************************************************/
15
16/* include files */
17
18#include "odm_precomp.h"
ecd1f9b3 19#include "phy.h"
18b0950e 20
6f1b7df4 21u32 GlobalDebugLevel;
18b0950e
LF		 22static const u16 dB_Invert_Table[8][12] = {
23 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
24 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
25 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
26 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
27 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
28 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
29 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
30 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
31};
32
33/* avoid to warn in FreeBSD ==> To DO modify */
34static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {
35 /* UL DL */
36 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
37 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */
38 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */
39 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */
40 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */
41 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */
42 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */
43 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */
44 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */
45 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */
46};
47
48/* Global var */
49u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
50 0x7f8001fe, /* 0, +6.0dB */
51 0x788001e2, /* 1, +5.5dB */
52 0x71c001c7, /* 2, +5.0dB */
53 0x6b8001ae, /* 3, +4.5dB */
54 0x65400195, /* 4, +4.0dB */
55 0x5fc0017f, /* 5, +3.5dB */
56 0x5a400169, /* 6, +3.0dB */
57 0x55400155, /* 7, +2.5dB */
58 0x50800142, /* 8, +2.0dB */
59 0x4c000130, /* 9, +1.5dB */
60 0x47c0011f, /* 10, +1.0dB */
61 0x43c0010f, /* 11, +0.5dB */
62 0x40000100, /* 12, +0dB */
63 0x3c8000f2, /* 13, -0.5dB */
64 0x390000e4, /* 14, -1.0dB */
65 0x35c000d7, /* 15, -1.5dB */
66 0x32c000cb, /* 16, -2.0dB */
67 0x300000c0, /* 17, -2.5dB */
68 0x2d4000b5, /* 18, -3.0dB */
69 0x2ac000ab, /* 19, -3.5dB */
70 0x288000a2, /* 20, -4.0dB */
71 0x26000098, /* 21, -4.5dB */
72 0x24000090, /* 22, -5.0dB */
73 0x22000088, /* 23, -5.5dB */
74 0x20000080, /* 24, -6.0dB */
75 0x1e400079, /* 25, -6.5dB */
76 0x1c800072, /* 26, -7.0dB */
77 0x1b00006c, /* 27. -7.5dB */
78 0x19800066, /* 28, -8.0dB */
79 0x18000060, /* 29, -8.5dB */
80 0x16c0005b, /* 30, -9.0dB */
81 0x15800056, /* 31, -9.5dB */
82 0x14400051, /* 32, -10.0dB */
83 0x1300004c, /* 33, -10.5dB */
84 0x12000048, /* 34, -11.0dB */
85 0x11000044, /* 35, -11.5dB */
86 0x10000040, /* 36, -12.0dB */
87 0x0f00003c,/* 37, -12.5dB */
88 0x0e400039,/* 38, -13.0dB */
89 0x0d800036,/* 39, -13.5dB */
90 0x0cc00033,/* 40, -14.0dB */
91 0x0c000030,/* 41, -14.5dB */
92 0x0b40002d,/* 42, -15.0dB */
93};
94
95u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
96 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
97 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
98 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
99 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
100 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
101 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
102 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
103 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
104 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
105 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
106 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
107 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
108 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
109 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
110 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
111 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
112 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
113 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
114 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
115 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
116 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
117 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
118 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
119 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
120 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
121 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
122 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
123 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
124 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
125 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
126 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
127 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
128 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
129};
130
131u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
132 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
133 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
134 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
135 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
136 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
137 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
138 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
139 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
140 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
141 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
142 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
143 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
144 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
145 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
146 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
147 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
148 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
149 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
150 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
151 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
152 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
153 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
154 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
155 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
156 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
157 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
158 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
159 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
160 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
161 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
162 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
163 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
164 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
165};
166
167
168#define RxDefaultAnt1 0x65a9
169#define RxDefaultAnt2 0x569a
170
6f1b7df4 171void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm)
172{
173 pDM_Odm->DebugLevel = ODM_DBG_TRACE;
174
175 pDM_Odm->DebugComponents = 0;
176}
177
18b0950e
LF		 178/* 3 Export Interface */
179
180/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */
181void ODM_DMInit(struct odm_dm_struct *pDM_Odm)
182{
183 /* 2012.05.03 Luke: For all IC series */
184 odm_CommonInfoSelfInit(pDM_Odm);
185 odm_CmnInfoInit_Debug(pDM_Odm);
186 odm_DIGInit(pDM_Odm);
187 odm_RateAdaptiveMaskInit(pDM_Odm);
188
6c0a555e
LF		 189 odm_DynamicTxPowerInit(pDM_Odm);
190 odm_TXPowerTrackingInit(pDM_Odm);
191 ODM_EdcaTurboInit(pDM_Odm);
192 ODM_RAInfo_Init_all(pDM_Odm);
193 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
194 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
195 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
196 odm_InitHybridAntDiv(pDM_Odm);
18b0950e
LF		 197}
198
199/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
200/* You can not add any dummy function here, be care, you can only use DM structure */
201/* to perform any new ODM_DM. */
202void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm)
203{
204 /* 2012.05.03 Luke: For all IC series */
18b0950e
LF		 205 odm_CmnInfoHook_Debug(pDM_Odm);
206 odm_CmnInfoUpdate_Debug(pDM_Odm);
207 odm_CommonInfoSelfUpdate(pDM_Odm);
208 odm_FalseAlarmCounterStatistics(pDM_Odm);
209 odm_RSSIMonitorCheck(pDM_Odm);
210
18b0950e 211 /* Fix Leave LPS issue */
f395036d 212 odm_DIG(pDM_Odm);
18b0950e
LF		 213 odm_CCKPacketDetectionThresh(pDM_Odm);
214
215 if (*(pDM_Odm->pbPowerSaving))
216 return;
217
218 odm_RefreshRateAdaptiveMask(pDM_Odm);
219
18b0950e
LF		 220 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
221 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
222 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
223 odm_HwAntDiv(pDM_Odm);
18b0950e 224
6c0a555e
LF		 225 ODM_TXPowerTrackingCheck(pDM_Odm);
226 odm_EdcaTurboCheck(pDM_Odm);
18b0950e
LF		 227}
228
18b0950e
LF		 229void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue)
230{
231 /* Hook call by reference pointer. */
232 switch (CmnInfo) {
233 /* Dynamic call by reference pointer. */
234 case ODM_CMNINFO_STA_STATUS:
235 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
236 break;
237 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
238 default:
239 /* do nothing */
240 break;
241 }
242}
243
18b0950e
LF		 244void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)
245{
25aacb2a
LF		 246 struct adapter *adapter = pDM_Odm->Adapter;
247
9c68ed09 248 pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT(9));
7be921a2 249 pDM_Odm->RFPathRxEnable = (u8)phy_query_bb_reg(adapter, 0xc04, 0x0F);
18b0950e
LF		 250
251 ODM_InitDebugSetting(pDM_Odm);
252}
253
254void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm)
255{
256 u8 EntryCnt = 0;
257 u8 i;
258 struct sta_info *pEntry;
259
260 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) {
261 if (*(pDM_Odm->pSecChOffset) == 1)
262 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2;
263 else if (*(pDM_Odm->pSecChOffset) == 2)
264 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2;
265 } else {
266 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
267 }
268
269 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
270 pEntry = pDM_Odm->pODM_StaInfo[i];
271 if (IS_STA_VALID(pEntry))
272 EntryCnt++;
273 }
274 if (EntryCnt == 1)
275 pDM_Odm->bOneEntryOnly = true;
276 else
277 pDM_Odm->bOneEntryOnly = false;
278}
279
280void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm)
281{
282 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n"));
283 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform));
284 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility));
285 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface));
286 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType));
287 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion));
18b0950e
LF		 288 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType));
289 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA));
290 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA));
291 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW));
292 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID));
293 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest));
294 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest));
295 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent));
296}
297
298void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm)
299{
300 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n"));
301 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast)));
302 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast)));
303 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode)));
304 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset)));
305 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity)));
306 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth)));
307 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel)));
308
309 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess)));
310 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving)));
18b0950e
LF		 311}
312
313void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm)
314{
315 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n"));
316 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct));
317 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display));
318 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked));
319 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min));
320}
321
18b0950e
LF		 322void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI)
323{
324 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
e690895a 325 struct adapter *adapter = pDM_Odm->Adapter;
18b0950e 326
18b0950e 327 if (pDM_DigTable->CurIGValue != CurrentIGI) {
9c6db651 328 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI);
18b0950e
LF		 329 pDM_DigTable->CurIGValue = CurrentIGI;
330 }
18b0950e
LF		 331}
332
18b0950e
LF		 333void odm_DIGInit(struct odm_dm_struct *pDM_Odm)
334{
25aacb2a 335 struct adapter *adapter = pDM_Odm->Adapter;
18b0950e
LF		 336 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
337
7be921a2 338 pDM_DigTable->CurIGValue = (u8)phy_query_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N);
18b0950e
LF		 339 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
340 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
341 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW;
342 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH;
3d272700
NMG		 343 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
344 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
18b0950e
LF		 345 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
346 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
347 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
348 pDM_DigTable->PreCCK_CCAThres = 0xFF;
349 pDM_DigTable->CurCCK_CCAThres = 0x83;
350 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
351 pDM_DigTable->LargeFAHit = 0;
352 pDM_DigTable->Recover_cnt = 0;
353 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
354 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
355 pDM_DigTable->bMediaConnect_0 = false;
356 pDM_DigTable->bMediaConnect_1 = false;
357
358 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */
359 pDM_Odm->bDMInitialGainEnable = true;
360}
361
362void odm_DIG(struct odm_dm_struct *pDM_Odm)
363{
364 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
365 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
366 u8 DIG_Dynamic_MIN;
367 u8 DIG_MaxOfMin;
368 bool FirstConnect, FirstDisConnect;
369 u8 dm_dig_max, dm_dig_min;
370 u8 CurrentIGI = pDM_DigTable->CurIGValue;
371
372 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
373 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
374 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
375 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
376 return;
377 }
378
379 if (*(pDM_Odm->pbScanInProcess)) {
380 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n"));
381 return;
382 }
383
384 /* add by Neil Chen to avoid PSD is processing */
f57329c6 385 if (!pDM_Odm->bDMInitialGainEnable) {
18b0950e
LF		 386 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n"));
387 return;
388 }
389
6c0a555e
LF		 390 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
391 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
392 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
18b0950e
LF		 393
394 /* 1 Boundary Decision */
6c0a555e
LF		 395 dm_dig_max = DM_DIG_MAX_NIC;
396 dm_dig_min = DM_DIG_MIN_NIC;
397 DIG_MaxOfMin = DM_DIG_MAX_AP;
398
18b0950e 399 if (pDM_Odm->bLinked) {
6c0a555e
LF		 400 /* 2 Modify DIG upper bound */
401 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
402 pDM_DigTable->rx_gain_range_max = dm_dig_max;
403 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
404 pDM_DigTable->rx_gain_range_max = dm_dig_min;
405 else
406 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
407 /* 2 Modify DIG lower bound */
408 if (pDM_Odm->bOneEntryOnly) {
409 if (pDM_Odm->RSSI_Min < dm_dig_min)
18b0950e 410 DIG_Dynamic_MIN = dm_dig_min;
6c0a555e
LF		 411 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
412 DIG_Dynamic_MIN = DIG_MaxOfMin;
413 else
414 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
415 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
416 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n",
417 DIG_Dynamic_MIN));
418 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
419 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",
420 pDM_Odm->RSSI_Min));
421 } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) {
422 /* 1 Lower Bound for 88E AntDiv */
423 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
7be921a2 424 DIG_Dynamic_MIN = (u8)pDM_DigTable->AntDiv_RSSI_max;
6c0a555e
LF		 425 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
426 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n",
427 pDM_DigTable->AntDiv_RSSI_max));
18b0950e 428 }
6c0a555e
LF		 429 } else {
430 DIG_Dynamic_MIN = dm_dig_min;
18b0950e
LF		 431 }
432 } else {
433 pDM_DigTable->rx_gain_range_max = dm_dig_max;
434 DIG_Dynamic_MIN = dm_dig_min;
435 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n"));
436 }
437
438 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
439 if (pFalseAlmCnt->Cnt_all > 10000) {
440 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n"));
441
442 if (pDM_DigTable->LargeFAHit != 3)
443 pDM_DigTable->LargeFAHit++;
444 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
445 pDM_DigTable->ForbiddenIGI = CurrentIGI;
446 pDM_DigTable->LargeFAHit = 1;
447 }
448
449 if (pDM_DigTable->LargeFAHit >= 3) {
450 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
451 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
452 else
453 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
454 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */
455 }
456
457 } else {
458 /* Recovery mechanism for IGI lower bound */
459 if (pDM_DigTable->Recover_cnt != 0) {
460 pDM_DigTable->Recover_cnt--;
461 } else {
462 if (pDM_DigTable->LargeFAHit < 3) {
463 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */
464 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
465 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
466 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n"));
467 } else {
468 pDM_DigTable->ForbiddenIGI--;
469 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
470 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n"));
471 }
472 } else {
473 pDM_DigTable->LargeFAHit = 0;
474 }
475 }
476 }
477 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
478 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",
479 pDM_DigTable->LargeFAHit));
480
481 /* 1 Adjust initial gain by false alarm */
482 if (pDM_Odm->bLinked) {
483 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n"));
484 if (FirstConnect) {
485 CurrentIGI = pDM_Odm->RSSI_Min;
486 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
487 } else {
6c0a555e
LF		 488 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
489 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
490 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
491 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
492 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
493 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
18b0950e
LF		 494 }
495 } else {
496 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n"));
497 if (FirstDisConnect) {
498 CurrentIGI = pDM_DigTable->rx_gain_range_min;
499 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n"));
500 } else {
501 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
502 if (pFalseAlmCnt->Cnt_all > 10000)
503 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
504 else if (pFalseAlmCnt->Cnt_all > 8000)
505 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
506 else if (pFalseAlmCnt->Cnt_all < 500)
507 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
508 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n"));
509 }
510 }
511 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n"));
512 /* 1 Check initial gain by upper/lower bound */
513 if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
514 CurrentIGI = pDM_DigTable->rx_gain_range_max;
515 if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
516 CurrentIGI = pDM_DigTable->rx_gain_range_min;
517
518 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
519 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
520 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
521 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all));
522 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI));
523
524 /* 2 High power RSSI threshold */
525
526 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
527 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
528 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
529}
530
531/* 3============================================================ */
532/* 3 FASLE ALARM CHECK */
533/* 3============================================================ */
534
535void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
536{
e690895a 537 struct adapter *adapter = pDM_Odm->Adapter;
18b0950e
LF		 538 u32 ret_value;
539 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
540
541 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
542 return;
543
6c0a555e 544 /* hold ofdm counter */
9c68ed09
AB		 545 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */
546 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */
6c0a555e 547
ecd1f9b3 548 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
6c0a555e 549 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
07add2d3 550 FalseAlmCnt->Cnt_SB_Search_fail = (ret_value & 0xffff0000)>>16;
ecd1f9b3 551 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
6c0a555e 552 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
07add2d3 553 FalseAlmCnt->Cnt_Parity_Fail = (ret_value & 0xffff0000)>>16;
ecd1f9b3 554 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
6c0a555e 555 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
07add2d3 556 FalseAlmCnt->Cnt_Crc8_fail = (ret_value & 0xffff0000)>>16;
ecd1f9b3 557 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
6c0a555e
LF		 558 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
559
560 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
561 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
562 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
563
ecd1f9b3 564 ret_value = phy_query_bb_reg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord);
6c0a555e 565 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
07add2d3 566 FalseAlmCnt->Cnt_BW_USC = (ret_value & 0xffff0000)>>16;
6c0a555e
LF		 567
568 /* hold cck counter */
9c68ed09
AB		 569 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
570 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
6c0a555e 571
ecd1f9b3 572 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
6c0a555e 573 FalseAlmCnt->Cnt_Cck_fail = ret_value;
ecd1f9b3 574 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
6c0a555e
LF		 575 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8;
576
ecd1f9b3 577 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
6c0a555e
LF		 578 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
579
580 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
581 FalseAlmCnt->Cnt_SB_Search_fail +
582 FalseAlmCnt->Cnt_Parity_Fail +
583 FalseAlmCnt->Cnt_Rate_Illegal +
584 FalseAlmCnt->Cnt_Crc8_fail +
585 FalseAlmCnt->Cnt_Mcs_fail +
586 FalseAlmCnt->Cnt_Cck_fail);
587
588 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
589
590 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
591 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
592 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
593 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
594 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
595 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
596 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
597 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
598 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
599 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
18b0950e
LF		 600 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail));
601 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
602 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all));
603}
604
605/* 3============================================================ */
606/* 3 CCK Packet Detect Threshold */
607/* 3============================================================ */
608
609void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm)
610{
611 u8 CurCCK_CCAThres;
612 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
613
614 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
615 return;
616 if (pDM_Odm->ExtLNA)
617 return;
618 if (pDM_Odm->bLinked) {
619 if (pDM_Odm->RSSI_Min > 25) {
620 CurCCK_CCAThres = 0xcd;
621 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
622 CurCCK_CCAThres = 0x83;
623 } else {
624 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
625 CurCCK_CCAThres = 0x83;
626 else
627 CurCCK_CCAThres = 0x40;
628 }
629 } else {
630 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
631 CurCCK_CCAThres = 0x83;
632 else
633 CurCCK_CCAThres = 0x40;
634 }
635 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
636}
637
638void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres)
639{
640 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
6348c232 641 struct adapter *adapt = pDM_Odm->Adapter;
18b0950e
LF		 642
643 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */
e76484d0 644 usb_write8(adapt, ODM_REG_CCK_CCA_11N, CurCCK_CCAThres);
18b0950e
LF		 645 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
646 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
647}
648
18b0950e
LF		 649void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
650{
e690895a 651 struct adapter *adapter = pDM_Odm->Adapter;
18b0950e
LF		 652 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
653 u8 Rssi_Up_bound = 30;
654 u8 Rssi_Low_bound = 25;
655
656 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
657 Rssi_Up_bound = 50;
658 Rssi_Low_bound = 45;
659 }
660 if (pDM_PSTable->initialize == 0) {
ecd1f9b3 661 pDM_PSTable->Reg874 = (phy_query_bb_reg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14;
9c68ed09 662 pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord) & BIT(3))>>3;
ecd1f9b3 663 pDM_PSTable->Reg85C = (phy_query_bb_reg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24;
664 pDM_PSTable->RegA74 = (phy_query_bb_reg(adapter, 0xa74, bMaskDWord)&0xF000)>>12;
18b0950e
LF		 665 pDM_PSTable->initialize = 1;
666 }
667
668 if (!bForceInNormal) {
669 if (pDM_Odm->RSSI_Min != 0xFF) {
670 if (pDM_PSTable->PreRFState == RF_Normal) {
671 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
672 pDM_PSTable->CurRFState = RF_Save;
673 else
674 pDM_PSTable->CurRFState = RF_Normal;
675 } else {
676 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
677 pDM_PSTable->CurRFState = RF_Normal;
678 else
679 pDM_PSTable->CurRFState = RF_Save;
680 }
681 } else {
682 pDM_PSTable->CurRFState = RF_MAX;
683 }
684 } else {
685 pDM_PSTable->CurRFState = RF_Normal;
686 }
687
688 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
689 if (pDM_PSTable->CurRFState == RF_Save) {
19fac3bb 690 phy_set_bb_reg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
9c68ed09 691 phy_set_bb_reg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */
9c6db651 692 phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
693 phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
694 phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
9c68ed09
AB		 695 phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
696 phy_set_bb_reg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
18b0950e 697 } else {
19fac3bb 698 phy_set_bb_reg(adapter, 0x874, 0x1CC000, pDM_PSTable->Reg874);
9c68ed09 699 phy_set_bb_reg(adapter, 0xc70, BIT(3), pDM_PSTable->RegC70);
9c6db651 700 phy_set_bb_reg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
701 phy_set_bb_reg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74);
9c68ed09 702 phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0);
18b0950e
LF		 703 }
704 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
705 }
706}
707
708/* 3============================================================ */
709/* 3 RATR MASK */
710/* 3============================================================ */
711/* 3============================================================ */
712/* 3 Rate Adaptive */
713/* 3============================================================ */
714
715void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm)
716{
717 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
718
719 pOdmRA->Type = DM_Type_ByDriver;
720 if (pOdmRA->Type == DM_Type_ByDriver)
721 pDM_Odm->bUseRAMask = true;
722 else
723 pDM_Odm->bUseRAMask = false;
724
725 pOdmRA->RATRState = DM_RATR_STA_INIT;
726 pOdmRA->HighRSSIThresh = 50;
727 pOdmRA->LowRSSIThresh = 20;
728}
729
730u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level)
731{
732 struct sta_info *pEntry;
733 u32 rate_bitmap = 0x0fffffff;
734 u8 WirelessMode;
735
736 pEntry = pDM_Odm->pODM_StaInfo[macid];
737 if (!IS_STA_VALID(pEntry))
738 return ra_mask;
739
740 WirelessMode = pEntry->wireless_mode;
741
742 switch (WirelessMode) {
743 case ODM_WM_B:
744 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */
745 rate_bitmap = 0x0000000d;
746 else
747 rate_bitmap = 0x0000000f;
748 break;
749 case (ODM_WM_A|ODM_WM_G):
750 if (rssi_level == DM_RATR_STA_HIGH)
751 rate_bitmap = 0x00000f00;
752 else
753 rate_bitmap = 0x00000ff0;
754 break;
755 case (ODM_WM_B|ODM_WM_G):
756 if (rssi_level == DM_RATR_STA_HIGH)
757 rate_bitmap = 0x00000f00;
758 else if (rssi_level == DM_RATR_STA_MIDDLE)
759 rate_bitmap = 0x00000ff0;
760 else
761 rate_bitmap = 0x00000ff5;
762 break;
763 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
764 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
2e414346
IS		 765 if (rssi_level == DM_RATR_STA_HIGH) {
766 rate_bitmap = 0x000f0000;
767 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
768 rate_bitmap = 0x000ff000;
18b0950e 769 } else {
2e414346
IS		 770 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
771 rate_bitmap = 0x000ff015;
772 else
773 rate_bitmap = 0x000ff005;
18b0950e
LF		 774 }
775 break;
776 default:
777 /* case WIRELESS_11_24N: */
778 /* case WIRELESS_11_5N: */
2e414346 779 rate_bitmap = 0x0fffffff;
18b0950e
LF		 780 break;
781 }
782
783 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
784 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n",
785 rssi_level, WirelessMode, rate_bitmap));
786
787 return rate_bitmap;
788}
789
790/*-----------------------------------------------------------------------------
791 * Function: odm_RefreshRateAdaptiveMask()
792 *
793 * Overview: Update rate table mask according to rssi
794 *
795 * Input: NONE
796 *
797 * Output: NONE
798 *
799 * Return: NONE
800 *
801 * Revised History:
802 * When Who Remark
803 * 05/27/2009 hpfan Create Version 0.
804 *
805 *---------------------------------------------------------------------------*/
806void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm)
807{
808 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
809 return;
810 /* */
811 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
812 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
813 /* HW dynamic mechanism. */
814 /* */
0735ea67 815 odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
18b0950e
LF		 816}
817
18b0950e
LF		 818void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm)
819{
820 u8 i;
821 struct adapter *pAdapter = pDM_Odm->Adapter;
822
823 if (pAdapter->bDriverStopped) {
824 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
825 return;
826 }
827
828 if (!pDM_Odm->bUseRAMask) {
829 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
830 return;
831 }
832
833 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
834 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
fc988e14 835
18b0950e 836 if (IS_STA_VALID(pstat)) {
19fac3bb 837 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
18b0950e
LF		 838 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
839 ("RSSI:%d, RSSI_LEVEL:%d\n",
840 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level));
841 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level);
842 }
843 }
844 }
845}
846
18b0950e
LF		 847/* Return Value: bool */
848/* - true: RATRState is changed. */
849bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState)
850{
851 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
852 const u8 GoUpGap = 5;
853 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
854 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
855 u8 RATRState;
856
857 /* Threshold Adjustment: */
858 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
859 /* Here GoUpGap is added to solve the boundary's level alternation issue. */
860 switch (*pRATRState) {
861 case DM_RATR_STA_INIT:
862 case DM_RATR_STA_HIGH:
863 break;
864 case DM_RATR_STA_MIDDLE:
865 HighRSSIThreshForRA += GoUpGap;
866 break;
867 case DM_RATR_STA_LOW:
868 HighRSSIThreshForRA += GoUpGap;
869 LowRSSIThreshForRA += GoUpGap;
870 break;
871 default:
872 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
873 break;
874 }
875
876 /* Decide RATRState by RSSI. */
877 if (RSSI > HighRSSIThreshForRA)
878 RATRState = DM_RATR_STA_HIGH;
879 else if (RSSI > LowRSSIThreshForRA)
880 RATRState = DM_RATR_STA_MIDDLE;
881 else
882 RATRState = DM_RATR_STA_LOW;
883
884 if (*pRATRState != RATRState || bForceUpdate) {
885 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
886 *pRATRState = RATRState;
887 return true;
888 }
889 return false;
890}
891
892/* 3============================================================ */
893/* 3 Dynamic Tx Power */
894/* 3============================================================ */
895
896void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm)
897{
898 struct adapter *Adapter = pDM_Odm->Adapter;
177aa53a 899 struct dm_priv *pdmpriv = &Adapter->HalData->dmpriv;
fc988e14 900
18b0950e
LF		 901 pdmpriv->bDynamicTxPowerEnable = false;
902 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
903 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
904}
905
18b0950e
LF		 906/* 3============================================================ */
907/* 3 RSSI Monitor */
908/* 3============================================================ */
909
910void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm)
911{
912 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
913 return;
914
915 /* */
916 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
917 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
918 /* HW dynamic mechanism. */
919 /* */
0735ea67 920 odm_RSSIMonitorCheckCE(pDM_Odm);
18b0950e
LF		 921} /* odm_RSSIMonitorCheck */
922
18b0950e
LF		 923static void FindMinimumRSSI(struct adapter *pAdapter)
924{
177aa53a 925 struct dm_priv *pdmpriv = &pAdapter->HalData->dmpriv;
e914024d
NMG		 926
927 /* 1 1.Unconditionally set RSSI */
928 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
18b0950e
LF		 929}
930
931void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm)
932{
933 struct adapter *Adapter = pDM_Odm->Adapter;
177aa53a 934 struct dm_priv *pdmpriv = &Adapter->HalData->dmpriv;
18b0950e
LF		 935 int i;
936 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
937 u8 sta_cnt = 0;
938 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
939 struct sta_info *psta;
940 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
941
942 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED))
943 return;
944
945 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
946 psta = pDM_Odm->pODM_StaInfo[i];
947 if (IS_STA_VALID(psta) &&
948 (psta->state & WIFI_ASOC_STATE) &&
f42f52aa
LF		 949 memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) &&
950 memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) {
18b0950e
LF		 951 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
952 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
953
954 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
955 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
956 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
957 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
958 }
959 }
960
961 for (i = 0; i < sta_cnt; i++) {
3abf4f98 962 if (PWDB_rssi[i] != 0) {
177aa53a 963 ODM_RA_SetRSSI_8188E(&Adapter->HalData->odmpriv,
3abf4f98
JS		 964 PWDB_rssi[i] & 0xFF,
965 (PWDB_rssi[i] >> 16) & 0xFF);
18b0950e
LF		 966 }
967 }
968
969 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */
970 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
971 else
972 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
973
974 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */
975 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
976 else
977 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
978
979 FindMinimumRSSI(Adapter);
177aa53a 980 Adapter->HalData->odmpriv.RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM;
18b0950e
LF		 981}
982
18b0950e
LF		 983/* 3============================================================ */
984/* 3 Tx Power Tracking */
985/* 3============================================================ */
986
987void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm)
988{
989 odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
990}
991
992void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm)
993{
994 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
995 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
18b0950e
LF		 996 if (*(pDM_Odm->mp_mode) != 1)
997 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
998 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
999
1000 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1001}
1002
1003void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm)
1004{
1005 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1006 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1007 /* HW dynamic mechanism. */
0735ea67 1008 odm_TXPowerTrackingCheckCE(pDM_Odm);
18b0950e
LF		 1009}
1010
1011void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm)
1012{
1013 struct adapter *Adapter = pDM_Odm->Adapter;
1014
1015 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
1016 return;
1017
1018 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */
9c68ed09 1019 phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
18b0950e
LF		 1020
1021 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
1022 return;
1023 } else {
05103ff0 1024 rtl88eu_dm_txpower_tracking_callback_thermalmeter(Adapter);
18b0950e
LF		 1025 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
1026 }
1027}
1028
18b0950e
LF		 1029/* 3============================================================ */
1030/* 3 SW Antenna Diversity */
1031/* 3============================================================ */
1032
1033void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
1034{
1035 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
1036 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n"));
1037 return;
1038 }
1039
db0ccdac 1040 rtl88eu_dm_antenna_div_init(pDM_Odm);
18b0950e
LF		 1041}
1042
18b0950e
LF		 1043void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
1044{
1045 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
1046 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n"));
1047 return;
1048 }
1049
8f4ece93 1050 rtl88eu_dm_antenna_diversity(pDM_Odm);
18b0950e
LF		 1051}
1052
1053/* EDCA Turbo */
1054void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm)
1055{
1056 struct adapter *Adapter = pDM_Odm->Adapter;
fc988e14 1057
18b0950e
LF		 1058 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1059 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1060 Adapter->recvpriv.bIsAnyNonBEPkts = false;
1061
99ecfb06 1062 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VO_PARAM)));
1063 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VI_PARAM)));
1064 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BE_PARAM)));
1065 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BK_PARAM)));
18b0950e
LF		 1066} /* ODM_InitEdcaTurbo */
1067
1068void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm)
1069{
1070 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1071 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1072 /* HW dynamic mechanism. */
1073 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n"));
1074
1075 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1076 return;
1077
0735ea67 1078 odm_EdcaTurboCheckCE(pDM_Odm);
18b0950e
LF		 1079 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n"));
1080} /* odm_CheckEdcaTurbo */
1081
1082void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm)
1083{
1084 struct adapter *Adapter = pDM_Odm->Adapter;
1085 u32 trafficIndex;
1086 u32 edca_param;
1087 u64 cur_tx_bytes = 0;
1088 u64 cur_rx_bytes = 0;
1089 u8 bbtchange = false;
18b0950e
LF		 1090 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
1091 struct recv_priv *precvpriv = &(Adapter->recvpriv);
1092 struct registry_priv *pregpriv = &Adapter->registrypriv;
1093 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv);
1094 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1095
1096 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */
1097 goto dm_CheckEdcaTurbo_EXIT;
1098
1099 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
1100 goto dm_CheckEdcaTurbo_EXIT;
1101
1102 /* Check if the status needs to be changed. */
1103 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1104 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1105 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1106
1107 /* traffic, TX or RX */
1108 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1109 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1110 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1111 /* Uplink TP is present. */
1112 trafficIndex = UP_LINK;
1113 } else {
1114 /* Balance TP is present. */
1115 trafficIndex = DOWN_LINK;
1116 }
1117 } else {
1118 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1119 /* Downlink TP is present. */
1120 trafficIndex = DOWN_LINK;
1121 } else {
1122 /* Balance TP is present. */
1123 trafficIndex = UP_LINK;
1124 }
1125 }
1126
1127 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1128 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1129 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1130 else
1131 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1132
fc158079 1133 usb_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
18b0950e
LF		 1134
1135 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1136 }
1137
1138 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1139 } else {
1140 /* Turn Off EDCA turbo here. */
1141 /* Restore original EDCA according to the declaration of AP. */
1142 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
177aa53a
IS		 1143 usb_write32(Adapter, REG_EDCA_BE_PARAM,
1144 Adapter->HalData->AcParam_BE);
18b0950e
LF		 1145 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1146 }
1147 }
1148
1149dm_CheckEdcaTurbo_EXIT:
1150 /* Set variables for next time. */
1151 precvpriv->bIsAnyNonBEPkts = false;
1152 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1153 precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1154}
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