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staging: r8188eu: Fix smatch warnings in core/rtw_xmit.c
[mirror_ubuntu-artful-kernel.git] / drivers / staging / rtl8188eu / hal / rtl8188e_hal_init.c
CommitLineData
615a4d12
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20#define _HAL_INIT_C_
21
22#include <drv_types.h>
23#include <rtw_efuse.h>
24
25#include <rtl8188e_hal.h>
26
27#include <rtw_iol.h>
28
29#include <usb_ops.h>
30
31static void iol_mode_enable(struct adapter *padapter, u8 enable)
32{
33 u8 reg_0xf0 = 0;
34
35 if (enable) {
36 /* Enable initial offload */
37 reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG);
38 rtw_write8(padapter, REG_SYS_CFG, reg_0xf0|SW_OFFLOAD_EN);
39
40 if (!padapter->bFWReady) {
41 DBG_88E("bFWReady == false call reset 8051...\n");
42 _8051Reset88E(padapter);
43 }
44
45 } else {
46 /* disable initial offload */
47 reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG);
48 rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN);
49 }
50}
51
52static s32 iol_execute(struct adapter *padapter, u8 control)
53{
54 s32 status = _FAIL;
55 u8 reg_0x88 = 0;
56 u32 start = 0, passing_time = 0;
57
58 control = control&0x0f;
59 reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0);
60 rtw_write8(padapter, REG_HMEBOX_E0, reg_0x88|control);
61
62 start = rtw_get_current_time();
63 while ((reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0)) & control &&
64 (passing_time = rtw_get_passing_time_ms(start)) < 1000) {
65 ;
66 }
67
68 reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0);
69 status = (reg_0x88 & control) ? _FAIL : _SUCCESS;
70 if (reg_0x88 & control<<4)
71 status = _FAIL;
72 return status;
73}
74
75static s32 iol_InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
76{
77 s32 rst = _SUCCESS;
78 iol_mode_enable(padapter, 1);
79 rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
80 rst = iol_execute(padapter, CMD_INIT_LLT);
81 iol_mode_enable(padapter, 0);
82 return rst;
83}
84
85static void
86efuse_phymap_to_logical(u8 *phymap, u16 _offset, u16 _size_byte, u8 *pbuf)
87{
88 u8 *efuseTbl = NULL;
89 u8 rtemp8;
90 u16 eFuse_Addr = 0;
91 u8 offset, wren;
92 u16 i, j;
93 u16 **eFuseWord = NULL;
94 u16 efuse_utilized = 0;
95 u8 u1temp = 0;
96
97 efuseTbl = (u8 *)rtw_zmalloc(EFUSE_MAP_LEN_88E);
98 if (efuseTbl == NULL) {
99 DBG_88E("%s: alloc efuseTbl fail!\n", __func__);
100 goto exit;
101 }
102
103 eFuseWord = (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
104 if (eFuseWord == NULL) {
105 DBG_88E("%s: alloc eFuseWord fail!\n", __func__);
106 goto exit;
107 }
108
109 /* 0. Refresh efuse init map as all oxFF. */
110 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
111 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
112 eFuseWord[i][j] = 0xFFFF;
113
114 /* */
115 /* 1. Read the first byte to check if efuse is empty!!! */
116 /* */
117 /* */
118 rtemp8 = *(phymap+eFuse_Addr);
119 if (rtemp8 != 0xFF) {
120 efuse_utilized++;
121 eFuse_Addr++;
122 } else {
123 DBG_88E("EFUSE is empty efuse_Addr-%d efuse_data =%x\n", eFuse_Addr, rtemp8);
124 goto exit;
125 }
126
127 /* */
128 /* 2. Read real efuse content. Filter PG header and every section data. */
129 /* */
130 while ((rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
131 /* Check PG header for section num. */
132 if ((rtemp8 & 0x1F) == 0x0F) { /* extended header */
133 u1temp = ((rtemp8 & 0xE0) >> 5);
134 rtemp8 = *(phymap+eFuse_Addr);
135 if ((rtemp8 & 0x0F) == 0x0F) {
136 eFuse_Addr++;
137 rtemp8 = *(phymap+eFuse_Addr);
138
139 if (rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
140 eFuse_Addr++;
141 continue;
142 } else {
143 offset = ((rtemp8 & 0xF0) >> 1) | u1temp;
144 wren = (rtemp8 & 0x0F);
145 eFuse_Addr++;
146 }
147 } else {
148 offset = ((rtemp8 >> 4) & 0x0f);
149 wren = (rtemp8 & 0x0f);
150 }
151
152 if (offset < EFUSE_MAX_SECTION_88E) {
153 /* Get word enable value from PG header */
154 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
155 /* Check word enable condition in the section */
156 if (!(wren & 0x01)) {
157 rtemp8 = *(phymap+eFuse_Addr);
158 eFuse_Addr++;
159 efuse_utilized++;
160 eFuseWord[offset][i] = (rtemp8 & 0xff);
161 if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
162 break;
163 rtemp8 = *(phymap+eFuse_Addr);
164 eFuse_Addr++;
165 efuse_utilized++;
166 eFuseWord[offset][i] |= (((u16)rtemp8 << 8) & 0xff00);
167
168 if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
169 break;
170 }
171 wren >>= 1;
172 }
173 }
174 /* Read next PG header */
175 rtemp8 = *(phymap+eFuse_Addr);
176
177 if (rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
178 efuse_utilized++;
179 eFuse_Addr++;
180 }
181 }
182
183 /* */
184 /* 3. Collect 16 sections and 4 word unit into Efuse map. */
185 /* */
186 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) {
187 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
188 efuseTbl[(i*8)+(j*2)] = (eFuseWord[i][j] & 0xff);
189 efuseTbl[(i*8)+((j*2)+1)] = ((eFuseWord[i][j] >> 8) & 0xff);
190 }
191 }
192
193 /* */
194 /* 4. Copy from Efuse map to output pointer memory!!! */
195 /* */
196 for (i = 0; i < _size_byte; i++)
197 pbuf[i] = efuseTbl[_offset+i];
198
199 /* */
200 /* 5. Calculate Efuse utilization. */
201 /* */
202
203exit:
204 kfree(efuseTbl);
205
206 if (eFuseWord)
207 rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
208}
209
210static void efuse_read_phymap_from_txpktbuf(
211 struct adapter *adapter,
212 int bcnhead, /* beacon head, where FW store len(2-byte) and efuse physical map. */
213 u8 *content, /* buffer to store efuse physical map */
214 u16 *size /* for efuse content: the max byte to read. will update to byte read */
215 )
216{
217 u16 dbg_addr = 0;
218 u32 start = 0, passing_time = 0;
219 u8 reg_0x143 = 0;
220 u32 lo32 = 0, hi32 = 0;
221 u16 len = 0, count = 0;
222 int i = 0;
223 u16 limit = *size;
224
225 u8 *pos = content;
226
227 if (bcnhead < 0) /* if not valid */
228 bcnhead = rtw_read8(adapter, REG_TDECTRL+1);
229
230 DBG_88E("%s bcnhead:%d\n", __func__, bcnhead);
231
232 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
233
234 dbg_addr = bcnhead*128/8; /* 8-bytes addressing */
235
236 while (1) {
237 rtw_write16(adapter, REG_PKTBUF_DBG_ADDR, dbg_addr+i);
238
239 rtw_write8(adapter, REG_TXPKTBUF_DBG, 0);
240 start = rtw_get_current_time();
241 while (!(reg_0x143 = rtw_read8(adapter, REG_TXPKTBUF_DBG)) &&
242 (passing_time = rtw_get_passing_time_ms(start)) < 1000) {
243 DBG_88E("%s polling reg_0x143:0x%02x, reg_0x106:0x%02x\n", __func__, reg_0x143, rtw_read8(adapter, 0x106));
244 rtw_usleep_os(100);
245 }
246
247 lo32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
248 hi32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
249
250 if (i == 0) {
251 u8 lenc[2];
252 u16 lenbak, aaabak;
253 u16 aaa;
254 lenc[0] = rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L);
255 lenc[1] = rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1);
256
257 aaabak = le16_to_cpup((__le16 *)lenc);
258 lenbak = le16_to_cpu(*((__le16 *)lenc));
259 aaa = le16_to_cpup((__le16 *)&lo32);
260 len = le16_to_cpu(*((__le16 *)&lo32));
261
262 limit = (len-2 < limit) ? len-2 : limit;
263
264 DBG_88E("%s len:%u, lenbak:%u, aaa:%u, aaabak:%u\n", __func__, len, lenbak, aaa, aaabak);
265
266 memcpy(pos, ((u8 *)&lo32)+2, (limit >= count+2) ? 2 : limit-count);
267 count += (limit >= count+2) ? 2 : limit-count;
268 pos = content+count;
269
270 } else {
271 memcpy(pos, ((u8 *)&lo32), (limit >= count+4) ? 4 : limit-count);
272 count += (limit >= count+4) ? 4 : limit-count;
273 pos = content+count;
274 }
275
276 if (limit > count && len-2 > count) {
277 memcpy(pos, (u8 *)&hi32, (limit >= count+4) ? 4 : limit-count);
278 count += (limit >= count+4) ? 4 : limit-count;
279 pos = content+count;
280 }
281
282 if (limit <= count || len-2 <= count)
283 break;
284 i++;
285 }
286 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS);
287 DBG_88E("%s read count:%u\n", __func__, count);
288 *size = count;
289}
290
291static s32 iol_read_efuse(struct adapter *padapter, u8 txpktbuf_bndy, u16 offset, u16 size_byte, u8 *logical_map)
292{
293 s32 status = _FAIL;
294 u8 physical_map[512];
295 u16 size = 512;
296
297 rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
298 _rtw_memset(physical_map, 0xFF, 512);
299 rtw_write8(padapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
300 status = iol_execute(padapter, CMD_READ_EFUSE_MAP);
301 if (status == _SUCCESS)
302 efuse_read_phymap_from_txpktbuf(padapter, txpktbuf_bndy, physical_map, &size);
303 efuse_phymap_to_logical(physical_map, offset, size_byte, logical_map);
304 return status;
305}
306
307s32 rtl8188e_iol_efuse_patch(struct adapter *padapter)
308{
309 s32 result = _SUCCESS;
310
311 DBG_88E("==> %s\n", __func__);
312 if (rtw_IOL_applied(padapter)) {
313 iol_mode_enable(padapter, 1);
314 result = iol_execute(padapter, CMD_READ_EFUSE_MAP);
315 if (result == _SUCCESS)
316 result = iol_execute(padapter, CMD_EFUSE_PATCH);
317
318 iol_mode_enable(padapter, 0);
319 }
320 return result;
321}
322
323static s32 iol_ioconfig(struct adapter *padapter, u8 iocfg_bndy)
324{
325 s32 rst = _SUCCESS;
326
327 rtw_write8(padapter, REG_TDECTRL+1, iocfg_bndy);
328 rst = iol_execute(padapter, CMD_IOCONFIG);
329 return rst;
330}
331
332static int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
333{
334 struct pkt_attrib *pattrib = &xmit_frame->attrib;
335 u8 i;
336 int ret = _FAIL;
337
338 if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
339 goto exit;
340 if (rtw_usb_bulk_size_boundary(adapter, TXDESC_SIZE+pattrib->last_txcmdsz)) {
341 if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
342 goto exit;
343 }
344
345 dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms);
346
347 iol_mode_enable(adapter, 1);
348 for (i = 0; i < bndy_cnt; i++) {
349 u8 page_no = 0;
350 page_no = i*2;
351 ret = iol_ioconfig(adapter, page_no);
352 if (ret != _SUCCESS)
353 break;
354 }
355 iol_mode_enable(adapter, 0);
356exit:
357 /* restore BCN_HEAD */
358 rtw_write8(adapter, REG_TDECTRL+1, 0);
359 return ret;
360}
361
362void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter, int data_len)
363{
364 u32 fifo_data, reg_140;
365 u32 addr, rstatus, loop = 0;
366 u16 data_cnts = (data_len/8)+1;
367 u8 *pbuf = rtw_zvmalloc(data_len+10);
368 DBG_88E("###### %s ######\n", __func__);
369
370 rtw_write8(Adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
371 if (pbuf) {
372 for (addr = 0; addr < data_cnts; addr++) {
373 rtw_write32(Adapter, 0x140, addr);
374 rtw_usleep_os(2);
375 loop = 0;
376 do {
377 rstatus = (reg_140 = rtw_read32(Adapter, REG_PKTBUF_DBG_CTRL)&BIT24);
378 if (rstatus) {
379 fifo_data = rtw_read32(Adapter, REG_PKTBUF_DBG_DATA_L);
380 memcpy(pbuf+(addr*8), &fifo_data, 4);
381
382 fifo_data = rtw_read32(Adapter, REG_PKTBUF_DBG_DATA_H);
383 memcpy(pbuf+(addr*8+4), &fifo_data, 4);
384 }
385 rtw_usleep_os(2);
386 } while (!rstatus && (loop++ < 10));
387 }
388 rtw_IOL_cmd_buf_dump(Adapter, data_len, pbuf);
389 rtw_vmfree(pbuf, data_len+10);
390 }
391 DBG_88E("###### %s ######\n", __func__);
392}
393
394static void _FWDownloadEnable(struct adapter *padapter, bool enable)
395{
396 u8 tmp;
397
398 if (enable) {
399 /* MCU firmware download enable. */
400 tmp = rtw_read8(padapter, REG_MCUFWDL);
401 rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
402
403 /* 8051 reset */
404 tmp = rtw_read8(padapter, REG_MCUFWDL+2);
405 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7);
406 } else {
407 /* MCU firmware download disable. */
408 tmp = rtw_read8(padapter, REG_MCUFWDL);
409 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe);
410
411 /* Reserved for fw extension. */
412 rtw_write8(padapter, REG_MCUFWDL+1, 0x00);
413 }
414}
415
416#define MAX_REG_BOLCK_SIZE 196
417
418static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize)
419{
420 int ret = _SUCCESS;
421 u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */
422 u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
423 u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */
424 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
425 u32 remainSize_p1 = 0, remainSize_p2 = 0;
426 u8 *bufferPtr = (u8 *)buffer;
427 u32 i = 0, offset = 0;
428
429 blockSize_p1 = MAX_REG_BOLCK_SIZE;
430
431 /* 3 Phase #1 */
432 blockCount_p1 = buffSize / blockSize_p1;
433 remainSize_p1 = buffSize % blockSize_p1;
434
435 if (blockCount_p1) {
436 RT_TRACE(_module_hal_init_c_, _drv_notice_,
437 ("_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n",
438 buffSize, blockSize_p1, blockCount_p1, remainSize_p1));
439 }
440
441 for (i = 0; i < blockCount_p1; i++) {
442 ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1));
443 if (ret == _FAIL)
444 goto exit;
445 }
446
447 /* 3 Phase #2 */
448 if (remainSize_p1) {
449 offset = blockCount_p1 * blockSize_p1;
450
451 blockCount_p2 = remainSize_p1/blockSize_p2;
452 remainSize_p2 = remainSize_p1%blockSize_p2;
453
454 if (blockCount_p2) {
455 RT_TRACE(_module_hal_init_c_, _drv_notice_,
456 ("_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n",
457 (buffSize-offset), blockSize_p2 , blockCount_p2, remainSize_p2));
458 }
459
460 for (i = 0; i < blockCount_p2; i++) {
461 ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + offset + i*blockSize_p2), blockSize_p2, (bufferPtr + offset + i*blockSize_p2));
462
463 if (ret == _FAIL)
464 goto exit;
465 }
466 }
467
468 /* 3 Phase #3 */
469 if (remainSize_p2) {
470 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
471
472 blockCount_p3 = remainSize_p2 / blockSize_p3;
473
474 RT_TRACE(_module_hal_init_c_, _drv_notice_,
475 ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n",
476 (buffSize-offset), blockSize_p3, blockCount_p3));
477
478 for (i = 0; i < blockCount_p3; i++) {
479 ret = rtw_write8(padapter, (FW_8188E_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
480
481 if (ret == _FAIL)
482 goto exit;
483 }
484 }
485
486exit:
487 return ret;
488}
489
490static int _PageWrite(struct adapter *padapter, u32 page, void *buffer, u32 size)
491{
492 u8 value8;
493 u8 u8Page = (u8)(page & 0x07);
494
495 value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page;
496 rtw_write8(padapter, REG_MCUFWDL+2, value8);
497
498 return _BlockWrite(padapter, buffer, size);
499}
500
501static int _WriteFW(struct adapter *padapter, void *buffer, u32 size)
502{
503 /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */
504 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
505 int ret = _SUCCESS;
506 u32 pageNums, remainSize;
507 u32 page, offset;
508 u8 *bufferPtr = (u8 *)buffer;
509
510 pageNums = size / MAX_PAGE_SIZE;
511 remainSize = size % MAX_PAGE_SIZE;
512
513 for (page = 0; page < pageNums; page++) {
514 offset = page * MAX_PAGE_SIZE;
515 ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_PAGE_SIZE);
516
517 if (ret == _FAIL)
518 goto exit;
519 }
520 if (remainSize) {
521 offset = pageNums * MAX_PAGE_SIZE;
522 page = pageNums;
523 ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize);
524
525 if (ret == _FAIL)
526 goto exit;
527 }
528 RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n"));
529exit:
530 return ret;
531}
532
533void _8051Reset88E(struct adapter *padapter)
534{
535 u8 u1bTmp;
536
537 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
538 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2));
539 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT2));
540 DBG_88E("=====> _8051Reset88E(): 8051 reset success .\n");
541}
542
543static s32 _FWFreeToGo(struct adapter *padapter)
544{
545 u32 counter = 0;
546 u32 value32;
547
548 /* polling CheckSum report */
549 do {
550 value32 = rtw_read32(padapter, REG_MCUFWDL);
551 if (value32 & FWDL_ChkSum_rpt)
552 break;
553 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
554
555 if (counter >= POLLING_READY_TIMEOUT_COUNT) {
556 DBG_88E("%s: chksum report fail! REG_MCUFWDL:0x%08x\n", __func__, value32);
557 return _FAIL;
558 }
559 DBG_88E("%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __func__, value32);
560
561 value32 = rtw_read32(padapter, REG_MCUFWDL);
562 value32 |= MCUFWDL_RDY;
563 value32 &= ~WINTINI_RDY;
564 rtw_write32(padapter, REG_MCUFWDL, value32);
565
566 _8051Reset88E(padapter);
567
568 /* polling for FW ready */
569 counter = 0;
570 do {
571 value32 = rtw_read32(padapter, REG_MCUFWDL);
572 if (value32 & WINTINI_RDY) {
573 DBG_88E("%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n", __func__, value32);
574 return _SUCCESS;
575 }
576 rtw_udelay_os(5);
577 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
578
579 DBG_88E("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __func__, value32);
580 return _FAIL;
581}
582
583#define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
584
585s32 rtl8188e_FirmwareDownload(struct adapter *padapter)
586{
587 s32 rtStatus = _SUCCESS;
588 u8 writeFW_retry = 0;
589 u32 fwdl_start_time;
590 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
591
592 u8 *FwImage;
593 u32 FwImageLen;
594 struct rt_firmware *pFirmware = NULL;
595 struct rt_firmware_hdr *pFwHdr = NULL;
596 u8 *pFirmwareBuf;
597 u32 FirmwareLen;
598
599 RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__));
600 pFirmware = (struct rt_firmware *)rtw_zmalloc(sizeof(struct rt_firmware));
601 if (!pFirmware) {
602 rtStatus = _FAIL;
603 goto Exit;
604 }
605
606 FwImage = (u8 *)Rtl8188E_FwImageArray;
607 FwImageLen = Rtl8188E_FWImgArrayLength;
608
609 pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
610
611 switch (pFirmware->eFWSource) {
612 case FW_SOURCE_IMG_FILE:
613 break;
614 case FW_SOURCE_HEADER_FILE:
615 if (FwImageLen > FW_8188E_SIZE) {
616 rtStatus = _FAIL;
617 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Firmware size exceed 0x%X. Check it.\n", FW_8188E_SIZE));
618 goto Exit;
619 }
620
621 pFirmware->szFwBuffer = FwImage;
622 pFirmware->ulFwLength = FwImageLen;
623 break;
624 }
625 pFirmwareBuf = pFirmware->szFwBuffer;
626 FirmwareLen = pFirmware->ulFwLength;
627 DBG_88E_LEVEL(_drv_info_, "+%s: !bUsedWoWLANFw, FmrmwareLen:%d+\n", __func__, FirmwareLen);
628
629 /* To Check Fw header. Added by tynli. 2009.12.04. */
630 pFwHdr = (struct rt_firmware_hdr *)pFirmware->szFwBuffer;
631
632 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
633 pHalData->FirmwareSubVersion = pFwHdr->Subversion;
634 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
635
636 DBG_88E("%s: fw_ver =%d fw_subver =%d sig = 0x%x\n",
637 __func__, pHalData->FirmwareVersion, pHalData->FirmwareSubVersion, pHalData->FirmwareSignature);
638
639 if (IS_FW_HEADER_EXIST(pFwHdr)) {
640 /* Shift 32 bytes for FW header */
641 pFirmwareBuf = pFirmwareBuf + 32;
642 FirmwareLen = FirmwareLen - 32;
643 }
644
645 /* Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, */
646 /* or it will cause download Fw fail. 2010.02.01. by tynli. */
647 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) { /* 8051 RAM code */
648 rtw_write8(padapter, REG_MCUFWDL, 0x00);
649 _8051Reset88E(padapter);
650 }
651
652 _FWDownloadEnable(padapter, true);
653 fwdl_start_time = rtw_get_current_time();
654 while (1) {
655 /* reset the FWDL chksum */
656 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL) | FWDL_ChkSum_rpt);
657
658 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
659
660 if (rtStatus == _SUCCESS ||
661 (rtw_get_passing_time_ms(fwdl_start_time) > 500 && writeFW_retry++ >= 3))
662 break;
663
664 DBG_88E("%s writeFW_retry:%u, time after fwdl_start_time:%ums\n",
665 __func__, writeFW_retry, rtw_get_passing_time_ms(fwdl_start_time)
666 );
667 }
668 _FWDownloadEnable(padapter, false);
669 if (_SUCCESS != rtStatus) {
670 DBG_88E("DL Firmware failed!\n");
671 goto Exit;
672 }
673
674 rtStatus = _FWFreeToGo(padapter);
675 if (_SUCCESS != rtStatus) {
676 DBG_88E("DL Firmware failed!\n");
677 goto Exit;
678 }
679 RT_TRACE(_module_hal_init_c_, _drv_info_, ("Firmware is ready to run!\n"));
680
681Exit:
682
683 kfree(pFirmware);
684 return rtStatus;
685}
686
687void rtl8188e_InitializeFirmwareVars(struct adapter *padapter)
688{
689 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
690
691 /* Init Fw LPS related. */
692 padapter->pwrctrlpriv.bFwCurrentInPSMode = false;
693
694 /* Init H2C counter. by tynli. 2009.12.09. */
695 pHalData->LastHMEBoxNum = 0;
696}
697
698static void rtl8188e_free_hal_data(struct adapter *padapter)
699{
700_func_enter_;
701 kfree(padapter->HalData);
702 padapter->HalData = NULL;
703_func_exit_;
704}
705
706/* */
707/* Efuse related code */
708/* */
709enum{
710 VOLTAGE_V25 = 0x03,
711 LDOE25_SHIFT = 28 ,
712 };
713
714static bool
715hal_EfusePgPacketWrite2ByteHeader(
716 struct adapter *pAdapter,
717 u8 efuseType,
718 u16 *pAddr,
719 struct pgpkt *pTargetPkt,
720 bool bPseudoTest);
721static bool
722hal_EfusePgPacketWrite1ByteHeader(
723 struct adapter *pAdapter,
724 u8 efuseType,
725 u16 *pAddr,
726 struct pgpkt *pTargetPkt,
727 bool bPseudoTest);
728static bool
729hal_EfusePgPacketWriteData(
730 struct adapter *pAdapter,
731 u8 efuseType,
732 u16 *pAddr,
733 struct pgpkt *pTargetPkt,
734 bool bPseudoTest);
735
736static void
737hal_EfusePowerSwitch_RTL8188E(
738 struct adapter *pAdapter,
739 u8 bWrite,
740 u8 PwrState)
741{
742 u8 tempval;
743 u16 tmpV16;
744
745 if (PwrState) {
746 rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
747
748 /* 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid */
749 tmpV16 = rtw_read16(pAdapter, REG_SYS_ISO_CTRL);
750 if (!(tmpV16 & PWC_EV12V)) {
751 tmpV16 |= PWC_EV12V;
752 rtw_write16(pAdapter, REG_SYS_ISO_CTRL, tmpV16);
753 }
754 /* Reset: 0x0000h[28], default valid */
755 tmpV16 = rtw_read16(pAdapter, REG_SYS_FUNC_EN);
756 if (!(tmpV16 & FEN_ELDR)) {
757 tmpV16 |= FEN_ELDR;
758 rtw_write16(pAdapter, REG_SYS_FUNC_EN, tmpV16);
759 }
760
761 /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
762 tmpV16 = rtw_read16(pAdapter, REG_SYS_CLKR);
763 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
764 tmpV16 |= (LOADER_CLK_EN | ANA8M);
765 rtw_write16(pAdapter, REG_SYS_CLKR, tmpV16);
766 }
767
768 if (bWrite) {
769 /* Enable LDO 2.5V before read/write action */
770 tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
771 tempval &= 0x0F;
772 tempval |= (VOLTAGE_V25 << 4);
773 rtw_write8(pAdapter, EFUSE_TEST+3, (tempval | 0x80));
774 }
775 } else {
776 rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
777
778 if (bWrite) {
779 /* Disable LDO 2.5V after read/write action */
780 tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
781 rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F));
782 }
783 }
784}
785
786static void
787rtl8188e_EfusePowerSwitch(
788 struct adapter *pAdapter,
789 u8 bWrite,
790 u8 PwrState)
791{
792 hal_EfusePowerSwitch_RTL8188E(pAdapter, bWrite, PwrState);
793}
794
795
796static void Hal_EfuseReadEFuse88E(struct adapter *Adapter,
797 u16 _offset,
798 u16 _size_byte,
799 u8 *pbuf,
800 bool bPseudoTest
801 )
802{
803 u8 *efuseTbl = NULL;
804 u8 rtemp8[1];
805 u16 eFuse_Addr = 0;
806 u8 offset, wren;
807 u16 i, j;
808 u16 **eFuseWord = NULL;
809 u16 efuse_utilized = 0;
810 u8 u1temp = 0;
811
812 /* */
813 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
814 /* */
815 if ((_offset + _size_byte) > EFUSE_MAP_LEN_88E) {/* total E-Fuse table is 512bytes */
816 DBG_88E("Hal_EfuseReadEFuse88E(): Invalid offset(%#x) with read bytes(%#x)!!\n", _offset, _size_byte);
817 goto exit;
818 }
819
820 efuseTbl = (u8 *)rtw_zmalloc(EFUSE_MAP_LEN_88E);
821 if (efuseTbl == NULL) {
822 DBG_88E("%s: alloc efuseTbl fail!\n", __func__);
823 goto exit;
824 }
825
826 eFuseWord = (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
827 if (eFuseWord == NULL) {
828 DBG_88E("%s: alloc eFuseWord fail!\n", __func__);
829 goto exit;
830 }
831
832 /* 0. Refresh efuse init map as all oxFF. */
833 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
834 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
835 eFuseWord[i][j] = 0xFFFF;
836
837 /* */
838 /* 1. Read the first byte to check if efuse is empty!!! */
839 /* */
840 /* */
841 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
842 if (*rtemp8 != 0xFF) {
843 efuse_utilized++;
844 eFuse_Addr++;
845 } else {
846 DBG_88E("EFUSE is empty efuse_Addr-%d efuse_data =%x\n", eFuse_Addr, *rtemp8);
847 goto exit;
848 }
849
850 /* */
851 /* 2. Read real efuse content. Filter PG header and every section data. */
852 /* */
853 while ((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
854 /* Check PG header for section num. */
855 if ((*rtemp8 & 0x1F) == 0x0F) { /* extended header */
856 u1temp = ((*rtemp8 & 0xE0) >> 5);
857
858 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
859
860 if ((*rtemp8 & 0x0F) == 0x0F) {
861 eFuse_Addr++;
862 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
863
864 if (*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
865 eFuse_Addr++;
866 continue;
867 } else {
868 offset = ((*rtemp8 & 0xF0) >> 1) | u1temp;
869 wren = (*rtemp8 & 0x0F);
870 eFuse_Addr++;
871 }
872 } else {
873 offset = ((*rtemp8 >> 4) & 0x0f);
874 wren = (*rtemp8 & 0x0f);
875 }
876
877 if (offset < EFUSE_MAX_SECTION_88E) {
878 /* Get word enable value from PG header */
879
880 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
881 /* Check word enable condition in the section */
882 if (!(wren & 0x01)) {
883 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
884 eFuse_Addr++;
885 efuse_utilized++;
886 eFuseWord[offset][i] = (*rtemp8 & 0xff);
887 if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
888 break;
889 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
890 eFuse_Addr++;
891 efuse_utilized++;
892 eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00);
893 if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
894 break;
895 }
896 wren >>= 1;
897 }
898 }
899
900 /* Read next PG header */
901 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
902
903 if (*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
904 efuse_utilized++;
905 eFuse_Addr++;
906 }
907 }
908
909 /* 3. Collect 16 sections and 4 word unit into Efuse map. */
910 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) {
911 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
912 efuseTbl[(i*8)+(j*2)] = (eFuseWord[i][j] & 0xff);
913 efuseTbl[(i*8)+((j*2)+1)] = ((eFuseWord[i][j] >> 8) & 0xff);
914 }
915 }
916
917 /* 4. Copy from Efuse map to output pointer memory!!! */
918 for (i = 0; i < _size_byte; i++)
919 pbuf[i] = efuseTbl[_offset+i];
920
921 /* 5. Calculate Efuse utilization. */
922 rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&eFuse_Addr);
923
924exit:
925 kfree(efuseTbl);
926
927 if (eFuseWord)
928 rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
929}
930
931static void ReadEFuseByIC(struct adapter *Adapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest)
932{
933 if (!bPseudoTest) {
934 int ret = _FAIL;
935 if (rtw_IOL_applied(Adapter)) {
936 rtw_hal_power_on(Adapter);
937
938 iol_mode_enable(Adapter, 1);
939 ret = iol_read_efuse(Adapter, 0, _offset, _size_byte, pbuf);
940 iol_mode_enable(Adapter, 0);
941
942 if (_SUCCESS == ret)
943 goto exit;
944 }
945 }
946 Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
947
948exit:
949 return;
950}
951
952static void ReadEFuse_Pseudo(struct adapter *Adapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest)
953{
954 Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
955}
956
957static void rtl8188e_ReadEFuse(struct adapter *Adapter, u8 efuseType,
958 u16 _offset, u16 _size_byte, u8 *pbuf,
959 bool bPseudoTest)
960{
961 if (bPseudoTest)
962 ReadEFuse_Pseudo (Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
963 else
964 ReadEFuseByIC(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
965}
966
967/* Do not support BT */
968static void Hal_EFUSEGetEfuseDefinition88E(struct adapter *pAdapter, u8 efuseType, u8 type, void *pOut)
969{
970 switch (type) {
971 case TYPE_EFUSE_MAX_SECTION:
972 {
973 u8 *pMax_section;
974 pMax_section = (u8 *)pOut;
975 *pMax_section = EFUSE_MAX_SECTION_88E;
976 }
977 break;
978 case TYPE_EFUSE_REAL_CONTENT_LEN:
979 {
980 u16 *pu2Tmp;
981 pu2Tmp = (u16 *)pOut;
982 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
983 }
984 break;
985 case TYPE_EFUSE_CONTENT_LEN_BANK:
986 {
987 u16 *pu2Tmp;
988 pu2Tmp = (u16 *)pOut;
989 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
990 }
991 break;
992 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
993 {
994 u16 *pu2Tmp;
995 pu2Tmp = (u16 *)pOut;
996 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
997 }
998 break;
999 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
1000 {
1001 u16 *pu2Tmp;
1002 pu2Tmp = (u16 *)pOut;
1003 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
1004 }
1005 break;
1006 case TYPE_EFUSE_MAP_LEN:
1007 {
1008 u16 *pu2Tmp;
1009 pu2Tmp = (u16 *)pOut;
1010 *pu2Tmp = (u16)EFUSE_MAP_LEN_88E;
1011 }
1012 break;
1013 case TYPE_EFUSE_PROTECT_BYTES_BANK:
1014 {
1015 u8 *pu1Tmp;
1016 pu1Tmp = (u8 *)pOut;
1017 *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E);
1018 }
1019 break;
1020 default:
1021 {
1022 u8 *pu1Tmp;
1023 pu1Tmp = (u8 *)pOut;
1024 *pu1Tmp = 0;
1025 }
1026 break;
1027 }
1028}
1029
1030static void Hal_EFUSEGetEfuseDefinition_Pseudo88E(struct adapter *pAdapter, u8 efuseType, u8 type, void *pOut)
1031{
1032 switch (type) {
1033 case TYPE_EFUSE_MAX_SECTION:
1034 {
1035 u8 *pMax_section;
1036 pMax_section = (u8 *)pOut;
1037 *pMax_section = EFUSE_MAX_SECTION_88E;
1038 }
1039 break;
1040 case TYPE_EFUSE_REAL_CONTENT_LEN:
1041 {
1042 u16 *pu2Tmp;
1043 pu2Tmp = (u16 *)pOut;
1044 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
1045 }
1046 break;
1047 case TYPE_EFUSE_CONTENT_LEN_BANK:
1048 {
1049 u16 *pu2Tmp;
1050 pu2Tmp = (u16 *)pOut;
1051 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
1052 }
1053 break;
1054 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
1055 {
1056 u16 *pu2Tmp;
1057 pu2Tmp = (u16 *)pOut;
1058 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
1059 }
1060 break;
1061 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
1062 {
1063 u16 *pu2Tmp;
1064 pu2Tmp = (u16 *)pOut;
1065 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
1066 }
1067 break;
1068 case TYPE_EFUSE_MAP_LEN:
1069 {
1070 u16 *pu2Tmp;
1071 pu2Tmp = (u16 *)pOut;
1072 *pu2Tmp = (u16)EFUSE_MAP_LEN_88E;
1073 }
1074 break;
1075 case TYPE_EFUSE_PROTECT_BYTES_BANK:
1076 {
1077 u8 *pu1Tmp;
1078 pu1Tmp = (u8 *)pOut;
1079 *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E);
1080 }
1081 break;
1082 default:
1083 {
1084 u8 *pu1Tmp;
1085 pu1Tmp = (u8 *)pOut;
1086 *pu1Tmp = 0;
1087 }
1088 break;
1089 }
1090}
1091
1092static void rtl8188e_EFUSE_GetEfuseDefinition(struct adapter *pAdapter, u8 efuseType, u8 type, void *pOut, bool bPseudoTest)
1093{
1094 if (bPseudoTest)
1095 Hal_EFUSEGetEfuseDefinition_Pseudo88E(pAdapter, efuseType, type, pOut);
1096 else
1097 Hal_EFUSEGetEfuseDefinition88E(pAdapter, efuseType, type, pOut);
1098}
1099
1100static u8 Hal_EfuseWordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_en, u8 *data, bool bPseudoTest)
1101{
1102 u16 tmpaddr = 0;
1103 u16 start_addr = efuse_addr;
1104 u8 badworden = 0x0F;
1105 u8 tmpdata[8];
1106
1107 _rtw_memset((void *)tmpdata, 0xff, PGPKT_DATA_SIZE);
1108
1109 if (!(word_en&BIT0)) {
1110 tmpaddr = start_addr;
1111 efuse_OneByteWrite(pAdapter, start_addr++, data[0], bPseudoTest);
1112 efuse_OneByteWrite(pAdapter, start_addr++, data[1], bPseudoTest);
1113
1114 efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[0], bPseudoTest);
1115 efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[1], bPseudoTest);
1116 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
1117 badworden &= (~BIT0);
1118 }
1119 if (!(word_en&BIT1)) {
1120 tmpaddr = start_addr;
1121 efuse_OneByteWrite(pAdapter, start_addr++, data[2], bPseudoTest);
1122 efuse_OneByteWrite(pAdapter, start_addr++, data[3], bPseudoTest);
1123
1124 efuse_OneByteRead(pAdapter, tmpaddr , &tmpdata[2], bPseudoTest);
1125 efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[3], bPseudoTest);
1126 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
1127 badworden &= (~BIT1);
1128 }
1129 if (!(word_en&BIT2)) {
1130 tmpaddr = start_addr;
1131 efuse_OneByteWrite(pAdapter, start_addr++, data[4], bPseudoTest);
1132 efuse_OneByteWrite(pAdapter, start_addr++, data[5], bPseudoTest);
1133
1134 efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[4], bPseudoTest);
1135 efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[5], bPseudoTest);
1136 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
1137 badworden &= (~BIT2);
1138 }
1139 if (!(word_en&BIT3)) {
1140 tmpaddr = start_addr;
1141 efuse_OneByteWrite(pAdapter, start_addr++, data[6], bPseudoTest);
1142 efuse_OneByteWrite(pAdapter, start_addr++, data[7], bPseudoTest);
1143
1144 efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[6], bPseudoTest);
1145 efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[7], bPseudoTest);
1146 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
1147 badworden &= (~BIT3);
1148 }
1149 return badworden;
1150}
1151
1152static u8 Hal_EfuseWordEnableDataWrite_Pseudo(struct adapter *pAdapter, u16 efuse_addr, u8 word_en, u8 *data, bool bPseudoTest)
1153{
1154 u8 ret;
1155
1156 ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
1157 return ret;
1158}
1159
1160static u8 rtl8188e_Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_en, u8 *data, bool bPseudoTest)
1161{
1162 u8 ret = 0;
1163
1164 if (bPseudoTest)
1165 ret = Hal_EfuseWordEnableDataWrite_Pseudo (pAdapter, efuse_addr, word_en, data, bPseudoTest);
1166 else
1167 ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
1168 return ret;
1169}
1170
1171static u16 hal_EfuseGetCurrentSize_8188e(struct adapter *pAdapter, bool bPseudoTest)
1172{
1173 int bContinual = true;
1174 u16 efuse_addr = 0;
1175 u8 hoffset = 0, hworden = 0;
1176 u8 efuse_data, word_cnts = 0;
1177
1178 if (bPseudoTest)
1179 efuse_addr = (u16)(fakeEfuseUsedBytes);
1180 else
1181 rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1182
1183 while (bContinual &&
1184 efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data, bPseudoTest) &&
1185 AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1186 if (efuse_data != 0xFF) {
1187 if ((efuse_data&0x1F) == 0x0F) { /* extended header */
1188 hoffset = efuse_data;
1189 efuse_addr++;
1190 efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data, bPseudoTest);
1191 if ((efuse_data & 0x0F) == 0x0F) {
1192 efuse_addr++;
1193 continue;
1194 } else {
1195 hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1196 hworden = efuse_data & 0x0F;
1197 }
1198 } else {
1199 hoffset = (efuse_data>>4) & 0x0F;
1200 hworden = efuse_data & 0x0F;
1201 }
1202 word_cnts = Efuse_CalculateWordCnts(hworden);
1203 /* read next header */
1204 efuse_addr = efuse_addr + (word_cnts*2)+1;
1205 } else {
1206 bContinual = false;
1207 }
1208 }
1209
1210 if (bPseudoTest)
1211 fakeEfuseUsedBytes = efuse_addr;
1212 else
1213 rtw_hal_set_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1214
1215 return efuse_addr;
1216}
1217
1218static u16 Hal_EfuseGetCurrentSize_Pseudo(struct adapter *pAdapter, bool bPseudoTest)
1219{
1220 u16 ret = 0;
1221
1222 ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest);
1223 return ret;
1224}
1225
1226static u16 rtl8188e_EfuseGetCurrentSize(struct adapter *pAdapter, u8 efuseType, bool bPseudoTest)
1227{
1228 u16 ret = 0;
1229
1230 if (bPseudoTest)
1231 ret = Hal_EfuseGetCurrentSize_Pseudo(pAdapter, bPseudoTest);
1232 else
1233 ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest);
1234 return ret;
1235}
1236
1237static int hal_EfusePgPacketRead_8188e(struct adapter *pAdapter, u8 offset, u8 *data, bool bPseudoTest)
1238{
1239 u8 ReadState = PG_STATE_HEADER;
1240 int bContinual = true;
1241 int bDataEmpty = true;
1242 u8 efuse_data, word_cnts = 0;
1243 u16 efuse_addr = 0;
1244 u8 hoffset = 0, hworden = 0;
1245 u8 tmpidx = 0;
1246 u8 tmpdata[8];
1247 u8 max_section = 0;
1248 u8 tmp_header = 0;
1249
1250 EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, (void *)&max_section, bPseudoTest);
1251
1252 if (data == NULL)
1253 return false;
1254 if (offset > max_section)
1255 return false;
1256
1257 _rtw_memset((void *)data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
1258 _rtw_memset((void *)tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
1259
1260 /* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */
1261 /* Skip dummy parts to prevent unexpected data read from Efuse. */
1262 /* By pass right now. 2009.02.19. */
1263 while (bContinual && AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1264 /* Header Read ------------- */
1265 if (ReadState & PG_STATE_HEADER) {
1266 if (efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
1267 if (EXT_HEADER(efuse_data)) {
1268 tmp_header = efuse_data;
1269 efuse_addr++;
1270 efuse_OneByteRead(pAdapter, efuse_addr, &efuse_data, bPseudoTest);
1271 if (!ALL_WORDS_DISABLED(efuse_data)) {
1272 hoffset = ((tmp_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1273 hworden = efuse_data & 0x0F;
1274 } else {
1275 DBG_88E("Error, All words disabled\n");
1276 efuse_addr++;
1277 continue;
1278 }
1279 } else {
1280 hoffset = (efuse_data>>4) & 0x0F;
1281 hworden = efuse_data & 0x0F;
1282 }
1283 word_cnts = Efuse_CalculateWordCnts(hworden);
1284 bDataEmpty = true;
1285
1286 if (hoffset == offset) {
1287 for (tmpidx = 0; tmpidx < word_cnts*2; tmpidx++) {
1288 if (efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx, &efuse_data, bPseudoTest)) {
1289 tmpdata[tmpidx] = efuse_data;
1290 if (efuse_data != 0xff)
1291 bDataEmpty = false;
1292 }
1293 }
1294 if (bDataEmpty == false) {
1295 ReadState = PG_STATE_DATA;
1296 } else {/* read next header */
1297 efuse_addr = efuse_addr + (word_cnts*2)+1;
1298 ReadState = PG_STATE_HEADER;
1299 }
1300 } else {/* read next header */
1301 efuse_addr = efuse_addr + (word_cnts*2)+1;
1302 ReadState = PG_STATE_HEADER;
1303 }
1304 } else {
1305 bContinual = false;
1306 }
1307 } else if (ReadState & PG_STATE_DATA) {
1308 /* Data section Read ------------- */
1309 efuse_WordEnableDataRead(hworden, tmpdata, data);
1310 efuse_addr = efuse_addr + (word_cnts*2)+1;
1311 ReadState = PG_STATE_HEADER;
1312 }
1313
1314 }
1315
1316 if ((data[0] == 0xff) && (data[1] == 0xff) && (data[2] == 0xff) && (data[3] == 0xff) &&
1317 (data[4] == 0xff) && (data[5] == 0xff) && (data[6] == 0xff) && (data[7] == 0xff))
1318 return false;
1319 else
1320 return true;
1321}
1322
1323static int Hal_EfusePgPacketRead(struct adapter *pAdapter, u8 offset, u8 *data, bool bPseudoTest)
1324{
1325 int ret;
1326
1327 ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest);
1328 return ret;
1329}
1330
1331static int Hal_EfusePgPacketRead_Pseudo(struct adapter *pAdapter, u8 offset, u8 *data, bool bPseudoTest)
1332{
1333 int ret;
1334
1335 ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest);
1336 return ret;
1337}
1338
1339static int rtl8188e_Efuse_PgPacketRead(struct adapter *pAdapter, u8 offset, u8 *data, bool bPseudoTest)
1340{
1341 int ret;
1342
1343 if (bPseudoTest)
1344 ret = Hal_EfusePgPacketRead_Pseudo (pAdapter, offset, data, bPseudoTest);
1345 else
1346 ret = Hal_EfusePgPacketRead(pAdapter, offset, data, bPseudoTest);
1347 return ret;
1348}
1349
1350static bool hal_EfuseFixHeaderProcess(struct adapter *pAdapter, u8 efuseType, struct pgpkt *pFixPkt, u16 *pAddr, bool bPseudoTest)
1351{
1352 u8 originaldata[8], badworden = 0;
1353 u16 efuse_addr = *pAddr;
1354 u32 PgWriteSuccess = 0;
1355
1356 _rtw_memset((void *)originaldata, 0xff, 8);
1357
1358 if (Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) {
1359 /* check if data exist */
1360 badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest);
1361
1362 if (badworden != 0xf) { /* write fail */
1363 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
1364
1365 if (!PgWriteSuccess)
1366 return false;
1367 else
1368 efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
1369 } else {
1370 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) + 1;
1371 }
1372 } else {
1373 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) + 1;
1374 }
1375 *pAddr = efuse_addr;
1376 return true;
1377}
1378
1379static bool hal_EfusePgPacketWrite2ByteHeader(struct adapter *pAdapter, u8 efuseType, u16 *pAddr, struct pgpkt *pTargetPkt, bool bPseudoTest)
1380{
1381 bool bRet = false;
1382 u16 efuse_addr = *pAddr, efuse_max_available_len = 0;
1383 u8 pg_header = 0, tmp_header = 0, pg_header_temp = 0;
1384 u8 repeatcnt = 0;
1385
1386 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (void *)&efuse_max_available_len, bPseudoTest);
1387
1388 while (efuse_addr < efuse_max_available_len) {
1389 pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
1390 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1391 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1392
1393 while (tmp_header == 0xFF) {
1394 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
1395 return false;
1396
1397 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1398 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1399 }
1400
1401 /* to write ext_header */
1402 if (tmp_header == pg_header) {
1403 efuse_addr++;
1404 pg_header_temp = pg_header;
1405 pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
1406
1407 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1408 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1409
1410 while (tmp_header == 0xFF) {
1411 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
1412 return false;
1413
1414 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1415 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1416 }
1417
1418 if ((tmp_header & 0x0F) == 0x0F) { /* word_en PG fail */
1419 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
1420 return false;
1421 } else {
1422 efuse_addr++;
1423 continue;
1424 }
1425 } else if (pg_header != tmp_header) { /* offset PG fail */
1426 struct pgpkt fixPkt;
1427 fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1);
1428 fixPkt.word_en = tmp_header & 0x0F;
1429 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
1430 if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
1431 return false;
1432 } else {
1433 bRet = true;
1434 break;
1435 }
1436 } else if ((tmp_header & 0x1F) == 0x0F) { /* wrong extended header */
1437 efuse_addr += 2;
1438 continue;
1439 }
1440 }
1441
1442 *pAddr = efuse_addr;
1443 return bRet;
1444}
1445
1446static bool hal_EfusePgPacketWrite1ByteHeader(struct adapter *pAdapter, u8 efuseType, u16 *pAddr, struct pgpkt *pTargetPkt, bool bPseudoTest)
1447{
1448 bool bRet = false;
1449 u8 pg_header = 0, tmp_header = 0;
1450 u16 efuse_addr = *pAddr;
1451 u8 repeatcnt = 0;
1452
1453 pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
1454
1455 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1456 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1457
1458 while (tmp_header == 0xFF) {
1459 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
1460 return false;
1461 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
1462 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
1463 }
1464
1465 if (pg_header == tmp_header) {
1466 bRet = true;
1467 } else {
1468 struct pgpkt fixPkt;
1469 fixPkt.offset = (tmp_header>>4) & 0x0F;
1470 fixPkt.word_en = tmp_header & 0x0F;
1471 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
1472 if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
1473 return false;
1474 }
1475
1476 *pAddr = efuse_addr;
1477 return bRet;
1478}
1479
1480static bool hal_EfusePgPacketWriteData(struct adapter *pAdapter, u8 efuseType, u16 *pAddr, struct pgpkt *pTargetPkt, bool bPseudoTest)
1481{
615a4d12
LF		 1482 u16 efuse_addr = *pAddr;
1483 u8 badworden = 0;
1484 u32 PgWriteSuccess = 0;
1485
1486 badworden = 0x0f;
1487 badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
1488 if (badworden == 0x0F) {
1489 /* write ok */
1490 return true;
1491 } else {
1492 /* reorganize other pg packet */
1493 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
1494 if (!PgWriteSuccess)
1495 return false;
1496 else
1497 return true;
1498 }
615a4d12
LF		 1499}
1500
1501static bool
1502hal_EfusePgPacketWriteHeader(
1503 struct adapter *pAdapter,
1504 u8 efuseType,
1505 u16 *pAddr,
1506 struct pgpkt *pTargetPkt,
1507 bool bPseudoTest)
1508{
1509 bool bRet = false;
1510
1511 if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
1512 bRet = hal_EfusePgPacketWrite2ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
1513 else
1514 bRet = hal_EfusePgPacketWrite1ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
1515
1516 return bRet;
1517}
1518
1519static bool wordEnMatched(struct pgpkt *pTargetPkt, struct pgpkt *pCurPkt,
1520 u8 *pWden)
1521{
1522 u8 match_word_en = 0x0F; /* default all words are disabled */
1523
1524 /* check if the same words are enabled both target and current PG packet */
1525 if (((pTargetPkt->word_en & BIT0) == 0) &&
1526 ((pCurPkt->word_en & BIT0) == 0))
1527 match_word_en &= ~BIT0; /* enable word 0 */
1528 if (((pTargetPkt->word_en & BIT1) == 0) &&
1529 ((pCurPkt->word_en & BIT1) == 0))
1530 match_word_en &= ~BIT1; /* enable word 1 */
1531 if (((pTargetPkt->word_en & BIT2) == 0) &&
1532 ((pCurPkt->word_en & BIT2) == 0))
1533 match_word_en &= ~BIT2; /* enable word 2 */
1534 if (((pTargetPkt->word_en & BIT3) == 0) &&
1535 ((pCurPkt->word_en & BIT3) == 0))
1536 match_word_en &= ~BIT3; /* enable word 3 */
1537
1538 *pWden = match_word_en;
1539
1540 if (match_word_en != 0xf)
1541 return true;
1542 else
1543 return false;
1544}
1545
1546static bool hal_EfuseCheckIfDatafollowed(struct adapter *pAdapter, u8 word_cnts, u16 startAddr, bool bPseudoTest)
1547{
1548 bool bRet = false;
1549 u8 i, efuse_data;
1550
1551 for (i = 0; i < (word_cnts*2); i++) {
1552 if (efuse_OneByteRead(pAdapter, (startAddr+i), &efuse_data, bPseudoTest) && (efuse_data != 0xFF))
1553 bRet = true;
1554 }
1555 return bRet;
1556}
1557
1558static bool hal_EfusePartialWriteCheck(struct adapter *pAdapter, u8 efuseType, u16 *pAddr, struct pgpkt *pTargetPkt, bool bPseudoTest)
1559{
1560 bool bRet = false;
1561 u8 i, efuse_data = 0, cur_header = 0;
1562 u8 matched_wden = 0, badworden = 0;
1563 u16 startAddr = 0, efuse_max_available_len = 0, efuse_max = 0;
1564 struct pgpkt curPkt;
1565
1566 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (void *)&efuse_max_available_len, bPseudoTest);
1567 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&efuse_max, bPseudoTest);
1568
1569 if (efuseType == EFUSE_WIFI) {
1570 if (bPseudoTest) {
1571 startAddr = (u16)(fakeEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
1572 } else {
1573 rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
1574 startAddr %= EFUSE_REAL_CONTENT_LEN;
1575 }
1576 } else {
1577 if (bPseudoTest)
1578 startAddr = (u16)(fakeBTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
1579 else
1580 startAddr = (u16)(BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
1581 }
1582
1583 while (1) {
1584 if (startAddr >= efuse_max_available_len) {
1585 bRet = false;
1586 break;
1587 }
1588
1589 if (efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
1590 if (EXT_HEADER(efuse_data)) {
1591 cur_header = efuse_data;
1592 startAddr++;
1593 efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest);
1594 if (ALL_WORDS_DISABLED(efuse_data)) {
1595 bRet = false;
1596 break;
1597 } else {
1598 curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1599 curPkt.word_en = efuse_data & 0x0F;
1600 }
1601 } else {
1602 cur_header = efuse_data;
1603 curPkt.offset = (cur_header>>4) & 0x0F;
1604 curPkt.word_en = cur_header & 0x0F;
1605 }
1606
1607 curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
1608 /* if same header is found but no data followed */
1609 /* write some part of data followed by the header. */
1610 if ((curPkt.offset == pTargetPkt->offset) &&
1611 (!hal_EfuseCheckIfDatafollowed(pAdapter, curPkt.word_cnts, startAddr+1, bPseudoTest)) &&
1612 wordEnMatched(pTargetPkt, &curPkt, &matched_wden)) {
1613 /* Here to write partial data */
1614 badworden = Efuse_WordEnableDataWrite(pAdapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest);
1615 if (badworden != 0x0F) {
1616 u32 PgWriteSuccess = 0;
1617 /* if write fail on some words, write these bad words again */
1618
1619 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
1620
1621 if (!PgWriteSuccess) {
1622 bRet = false; /* write fail, return */
1623 break;
1624 }
1625 }
1626 /* partial write ok, update the target packet for later use */
1627 for (i = 0; i < 4; i++) {
1628 if ((matched_wden & (0x1<<i)) == 0) /* this word has been written */
1629 pTargetPkt->word_en |= (0x1<<i); /* disable the word */
1630 }
1631 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
1632 }
1633 /* read from next header */
1634 startAddr = startAddr + (curPkt.word_cnts*2) + 1;
1635 } else {
1636 /* not used header, 0xff */
1637 *pAddr = startAddr;
1638 bRet = true;
1639 break;
1640 }
1641 }
1642 return bRet;
1643}
1644
1645static bool
1646hal_EfusePgCheckAvailableAddr(
1647 struct adapter *pAdapter,
1648 u8 efuseType,
1649 bool bPseudoTest
1650 )
1651{
1652 u16 efuse_max_available_len = 0;
1653
1654 /* Change to check TYPE_EFUSE_MAP_LEN , beacuse 8188E raw 256, logic map over 256. */
1655 EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&efuse_max_available_len, false);
1656
1657 if (Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= efuse_max_available_len)
1658 return false;
1659 return true;
1660}
1661
1662static void hal_EfuseConstructPGPkt(u8 offset, u8 word_en, u8 *pData, struct pgpkt *pTargetPkt)
1663{
1664 _rtw_memset((void *)pTargetPkt->data, 0xFF, sizeof(u8)*8);
1665 pTargetPkt->offset = offset;
1666 pTargetPkt->word_en = word_en;
1667 efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
1668 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
1669}
1670
1671static bool hal_EfusePgPacketWrite_8188e(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *pData, bool bPseudoTest)
1672{
1673 struct pgpkt targetPkt;
1674 u16 startAddr = 0;
1675 u8 efuseType = EFUSE_WIFI;
1676
1677 if (!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
1678 return false;
1679
1680 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
1681
1682 if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1683 return false;
1684
1685 if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1686 return false;
1687
1688 if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1689 return false;
1690
1691 return true;
1692}
1693
1694static int Hal_EfusePgPacketWrite_Pseudo(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest)
1695{
1696 int ret;
1697
1698 ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest);
1699 return ret;
1700}
1701
1702static int Hal_EfusePgPacketWrite(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest)
1703{
1704 int ret = 0;
1705 ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest);
1706
1707 return ret;
1708}
1709
1710static int rtl8188e_Efuse_PgPacketWrite(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest)
1711{
1712 int ret;
1713
1714 if (bPseudoTest)
1715 ret = Hal_EfusePgPacketWrite_Pseudo (pAdapter, offset, word_en, data, bPseudoTest);
1716 else
1717 ret = Hal_EfusePgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
1718 return ret;
1719}
1720
1721static struct HAL_VERSION ReadChipVersion8188E(struct adapter *padapter)
1722{
1723 u32 value32;
1724 struct HAL_VERSION ChipVersion;
1725 struct hal_data_8188e *pHalData;
1726
1727 pHalData = GET_HAL_DATA(padapter);
1728
1729 value32 = rtw_read32(padapter, REG_SYS_CFG);
1730 ChipVersion.ICType = CHIP_8188E;
1731 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
1732
1733 ChipVersion.RFType = RF_TYPE_1T1R;
1734 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
1735 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
1736
1737 /* For regulator mode. by tynli. 2011.01.14 */
1738 pHalData->RegulatorMode = ((value32 & TRP_BT_EN) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
1739
1740 ChipVersion.ROMVer = 0; /* ROM code version. */
1741 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
1742
1743 dump_chip_info(ChipVersion);
1744
1745 pHalData->VersionID = ChipVersion;
1746
1747 if (IS_1T2R(ChipVersion)) {
1748 pHalData->rf_type = RF_1T2R;
1749 pHalData->NumTotalRFPath = 2;
1750 } else if (IS_2T2R(ChipVersion)) {
1751 pHalData->rf_type = RF_2T2R;
1752 pHalData->NumTotalRFPath = 2;
1753 } else{
1754 pHalData->rf_type = RF_1T1R;
1755 pHalData->NumTotalRFPath = 1;
1756 }
1757
1758 MSG_88E("RF_Type is %x!!\n", pHalData->rf_type);
1759
1760 return ChipVersion;
1761}
1762
1763static void rtl8188e_read_chip_version(struct adapter *padapter)
1764{
1765 ReadChipVersion8188E(padapter);
1766}
1767
1768static void rtl8188e_GetHalODMVar(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
1769{
1770}
1771
1772static void rtl8188e_SetHalODMVar(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
1773{
1774 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
1775 struct odm_dm_struct *podmpriv = &pHalData->odmpriv;
1776 switch (eVariable) {
1777 case HAL_ODM_STA_INFO:
1778 {
1779 struct sta_info *psta = (struct sta_info *)pValue1;
1780 if (bSet) {
1781 DBG_88E("### Set STA_(%d) info\n", psta->mac_id);
1782 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
1783 ODM_RAInfo_Init(podmpriv, psta->mac_id);
1784 } else {
1785 DBG_88E("### Clean STA_(%d) info\n", psta->mac_id);
1786 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
1787 }
1788 }
1789 break;
1790 case HAL_ODM_P2P_STATE:
1791 ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
1792 break;
1793 case HAL_ODM_WIFI_DISPLAY_STATE:
1794 ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
1795 break;
1796 default:
1797 break;
1798 }
1799}
1800
1801void rtl8188e_clone_haldata(struct adapter *dst_adapter, struct adapter *src_adapter)
1802{
1803 memcpy(dst_adapter->HalData, src_adapter->HalData, dst_adapter->hal_data_sz);
1804}
1805
1806void rtl8188e_start_thread(struct adapter *padapter)
1807{
1808}
1809
1810void rtl8188e_stop_thread(struct adapter *padapter)
1811{
1812}
1813
1814static void hal_notch_filter_8188e(struct adapter *adapter, bool enable)
1815{
1816 if (enable) {
1817 DBG_88E("Enable notch filter\n");
1818 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
1819 } else {
1820 DBG_88E("Disable notch filter\n");
1821 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
1822 }
1823}
1824void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc)
1825{
1826 pHalFunc->free_hal_data = &rtl8188e_free_hal_data;
1827
1828 pHalFunc->dm_init = &rtl8188e_init_dm_priv;
1829 pHalFunc->dm_deinit = &rtl8188e_deinit_dm_priv;
1830
1831 pHalFunc->read_chip_version = &rtl8188e_read_chip_version;
1832
1833 pHalFunc->set_bwmode_handler = &PHY_SetBWMode8188E;
1834 pHalFunc->set_channel_handler = &PHY_SwChnl8188E;
1835
1836 pHalFunc->hal_dm_watchdog = &rtl8188e_HalDmWatchDog;
1837
1838 pHalFunc->Add_RateATid = &rtl8188e_Add_RateATid;
1839 pHalFunc->run_thread = &rtl8188e_start_thread;
1840 pHalFunc->cancel_thread = &rtl8188e_stop_thread;
1841
1842 pHalFunc->AntDivBeforeLinkHandler = &AntDivBeforeLink8188E;
1843 pHalFunc->AntDivCompareHandler = &AntDivCompare8188E;
1844 pHalFunc->read_bbreg = &rtl8188e_PHY_QueryBBReg;
1845 pHalFunc->write_bbreg = &rtl8188e_PHY_SetBBReg;
1846 pHalFunc->read_rfreg = &rtl8188e_PHY_QueryRFReg;
1847 pHalFunc->write_rfreg = &rtl8188e_PHY_SetRFReg;
1848
1849 /* Efuse related function */
1850 pHalFunc->EfusePowerSwitch = &rtl8188e_EfusePowerSwitch;
1851 pHalFunc->ReadEFuse = &rtl8188e_ReadEFuse;
1852 pHalFunc->EFUSEGetEfuseDefinition = &rtl8188e_EFUSE_GetEfuseDefinition;
1853 pHalFunc->EfuseGetCurrentSize = &rtl8188e_EfuseGetCurrentSize;
1854 pHalFunc->Efuse_PgPacketRead = &rtl8188e_Efuse_PgPacketRead;
1855 pHalFunc->Efuse_PgPacketWrite = &rtl8188e_Efuse_PgPacketWrite;
1856 pHalFunc->Efuse_WordEnableDataWrite = &rtl8188e_Efuse_WordEnableDataWrite;
1857
1858 pHalFunc->sreset_init_value = &sreset_init_value;
1859 pHalFunc->sreset_reset_value = &sreset_reset_value;
1860 pHalFunc->silentreset = &rtl8188e_silentreset_for_specific_platform;
1861 pHalFunc->sreset_xmit_status_check = &rtl8188e_sreset_xmit_status_check;
1862 pHalFunc->sreset_linked_status_check = &rtl8188e_sreset_linked_status_check;
1863 pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status;
1864
1865 pHalFunc->GetHalODMVarHandler = &rtl8188e_GetHalODMVar;
1866 pHalFunc->SetHalODMVarHandler = &rtl8188e_SetHalODMVar;
1867
1868 pHalFunc->IOL_exec_cmds_sync = &rtl8188e_IOL_exec_cmds_sync;
1869
1870 pHalFunc->hal_notch_filter = &hal_notch_filter_8188e;
1871}
1872
1873u8 GetEEPROMSize8188E(struct adapter *padapter)
1874{
1875 u8 size = 0;
1876 u32 cr;
1877
1878 cr = rtw_read16(padapter, REG_9346CR);
1879 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
1880 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
1881
1882 MSG_88E("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
1883
1884 return size;
1885}
1886
1887/* */
1888/* */
1889/* LLT R/W/Init function */
1890/* */
1891/* */
1892static s32 _LLTWrite(struct adapter *padapter, u32 address, u32 data)
1893{
1894 s32 status = _SUCCESS;
1895 s32 count = 0;
1896 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
1897 u16 LLTReg = REG_LLT_INIT;
1898
1899 rtw_write32(padapter, LLTReg, value);
1900
1901 /* polling */
1902 do {
1903 value = rtw_read32(padapter, LLTReg);
1904 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
1905 break;
1906
1907 if (count > POLLING_LLT_THRESHOLD) {
1908 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling write LLT done at address %d!\n", address));
1909 status = _FAIL;
1910 break;
1911 }
1912 } while (count++);
1913
1914 return status;
1915}
1916
1917s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
1918{
1919 s32 status = _FAIL;
1920 u32 i;
1921 u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;/* 176, 22k */
1922
1923 if (rtw_IOL_applied(padapter)) {
1924 status = iol_InitLLTTable(padapter, txpktbuf_bndy);
1925 } else {
1926 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
1927 status = _LLTWrite(padapter, i, i + 1);
1928 if (_SUCCESS != status)
1929 return status;
1930 }
1931
1932 /* end of list */
1933 status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
1934 if (_SUCCESS != status)
1935 return status;
1936
1937 /* Make the other pages as ring buffer */
1938 /* This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. */
1939 /* Otherwise used as local loopback buffer. */
1940 for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
1941 status = _LLTWrite(padapter, i, (i + 1));
1942 if (_SUCCESS != status)
1943 return status;
1944 }
1945
1946 /* Let last entry point to the start entry of ring buffer */
1947 status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
1948 if (_SUCCESS != status) {
1949 return status;
1950 }
1951 }
1952
1953 return status;
1954}
1955
1956void
1957Hal_InitPGData88E(struct adapter *padapter)
1958{
1959 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1960
1961 if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */
1962 if (!is_boot_from_eeprom(padapter)) {
1963 /* Read EFUSE real map to shadow. */
1964 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
1965 }
1966 } else {/* autoload fail */
1967 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n"));
1968 /* update to default value 0xFF */
1969 if (!is_boot_from_eeprom(padapter))
1970 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
1971 }
1972}
1973
1974void
1975Hal_EfuseParseIDCode88E(
1976 struct adapter *padapter,
1977 u8 *hwinfo
1978 )
1979{
1980 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1981 u16 EEPROMId;
1982
1983 /* Checl 0x8129 again for making sure autoload status!! */
1984 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
1985 if (EEPROMId != RTL_EEPROM_ID) {
1986 DBG_88E("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
1987 pEEPROM->bautoload_fail_flag = true;
1988 } else {
1989 pEEPROM->bautoload_fail_flag = false;
1990 }
1991
1992 DBG_88E("EEPROM ID = 0x%04x\n", EEPROMId);
1993}
1994
1995static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, u8 *PROMContent, bool AutoLoadFail)
1996{
1997 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_88E, group, TxCount = 0;
1998
1999 _rtw_memset(pwrInfo24G, 0, sizeof(struct txpowerinfo24g));
2000
2001 if (AutoLoadFail) {
2002 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
2003 /* 2.4G default value */
2004 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
2005 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2006 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2007 }
2008 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2009 if (TxCount == 0) {
2010 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
2011 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
2012 } else {
2013 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2014 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2015 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2016 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2017 }
2018 }
2019 }
2020 return;
2021 }
2022
2023 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
2024 /* 2.4G default value */
2025 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
2026 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
2027 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
2028 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2029 }
2030 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) {
2031 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
2032 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
2033 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2034 }
2035 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2036 if (TxCount == 0) {
2037 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
2038 if (PROMContent[eeAddr] == 0xFF) {
2039 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
2040 } else {
2041 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2042 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2043 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
2044 }
2045
2046 if (PROMContent[eeAddr] == 0xFF) {
2047 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
2048 } else {
2049 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2050 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2051 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
2052 }
2053 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
2054 eeAddr++;
2055 } else {
2056 if (PROMContent[eeAddr] == 0xFF) {
2057 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2058 } else {
2059 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2060 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2061 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
2062 }
2063
2064 if (PROMContent[eeAddr] == 0xFF) {
2065 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2066 } else {
2067 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2068 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2069 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
2070 }
2071 eeAddr++;
2072
2073 if (PROMContent[eeAddr] == 0xFF) {
2074 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2075 } else {
2076 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2077 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2078 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
2079 }
2080
2081 if (PROMContent[eeAddr] == 0xFF) {
2082 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2083 } else {
2084 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2085 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
2086 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
2087 }
2088 eeAddr++;
2089 }
2090 }
2091 }
2092}
2093
2094static u8 Hal_GetChnlGroup88E(u8 chnl, u8 *pGroup)
2095{
2096 u8 bIn24G = true;
2097
2098 if (chnl <= 14) {
2099 bIn24G = true;
2100
2101 if (chnl < 3) /* Chanel 1-2 */
2102 *pGroup = 0;
2103 else if (chnl < 6) /* Channel 3-5 */
2104 *pGroup = 1;
2105 else if (chnl < 9) /* Channel 6-8 */
2106 *pGroup = 2;
2107 else if (chnl < 12) /* Channel 9-11 */
2108 *pGroup = 3;
2109 else if (chnl < 14) /* Channel 12-13 */
2110 *pGroup = 4;
2111 else if (chnl == 14) /* Channel 14 */
2112 *pGroup = 5;
2113 } else {
2114 bIn24G = false;
2115
2116 if (chnl <= 40)
2117 *pGroup = 0;
2118 else if (chnl <= 48)
2119 *pGroup = 1;
2120 else if (chnl <= 56)
2121 *pGroup = 2;
2122 else if (chnl <= 64)
2123 *pGroup = 3;
2124 else if (chnl <= 104)
2125 *pGroup = 4;
2126 else if (chnl <= 112)
2127 *pGroup = 5;
2128 else if (chnl <= 120)
2129 *pGroup = 5;
2130 else if (chnl <= 128)
2131 *pGroup = 6;
2132 else if (chnl <= 136)
2133 *pGroup = 7;
2134 else if (chnl <= 144)
2135 *pGroup = 8;
2136 else if (chnl <= 153)
2137 *pGroup = 9;
2138 else if (chnl <= 161)
2139 *pGroup = 10;
2140 else if (chnl <= 177)
2141 *pGroup = 11;
2142 }
2143 return bIn24G;
2144}
2145
2146void Hal_ReadPowerSavingMode88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
2147{
2148 if (AutoLoadFail) {
2149 padapter->pwrctrlpriv.bHWPowerdown = false;
2150 padapter->pwrctrlpriv.bSupportRemoteWakeup = false;
2151 } else {
2152 /* hw power down mode selection , 0:rf-off / 1:power down */
2153
2154 if (padapter->registrypriv.hwpdn_mode == 2)
2155 padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT4);
2156 else
2157 padapter->pwrctrlpriv.bHWPowerdown = padapter->registrypriv.hwpdn_mode;
2158
2159 /* decide hw if support remote wakeup function */
2160 /* if hw supported, 8051 (SIE) will generate WeakUP signal(D+/D- toggle) when autoresume */
2161 padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1) ? true : false;
2162
2163 DBG_88E("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) , bSupportRemoteWakeup(%x)\n", __func__,
2164 padapter->pwrctrlpriv.bHWPwrPindetect, padapter->pwrctrlpriv.bHWPowerdown , padapter->pwrctrlpriv.bSupportRemoteWakeup);
2165
2166 DBG_88E("### PS params => power_mgnt(%x), usbss_enable(%x) ###\n", padapter->registrypriv.power_mgnt, padapter->registrypriv.usbss_enable);
2167 }
2168}
2169
2170void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail)
2171{
2172 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
2173 struct txpowerinfo24g pwrInfo24G;
2174 u8 rfPath, ch, group;
2175 u8 bIn24G, TxCount;
2176
2177 Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail);
2178
2179 if (!AutoLoadFail)
2180 pHalData->bTXPowerDataReadFromEEPORM = true;
2181
2182 for (rfPath = 0; rfPath < pHalData->NumTotalRFPath; rfPath++) {
1ad866e7 2183 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
615a4d12
LF		 2184 bIn24G = Hal_GetChnlGroup88E(ch, &group);
2185 if (bIn24G) {
2186 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];
2187 if (ch == 14)
2188 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][4];
2189 else
2190 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
2191 }
2192 if (bIn24G) {
2193 DBG_88E("======= Path %d, Channel %d =======\n", rfPath, ch);
2194 DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch , pHalData->Index24G_CCK_Base[rfPath][ch]);
2195 DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch , pHalData->Index24G_BW40_Base[rfPath][ch]);
2196 }
2197 }
2198 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2199 pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount];
2200 pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount];
2201 pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount];
2202 pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
2203 DBG_88E("======= TxCount %d =======\n", TxCount);
2204 DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount]);
2205 DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount]);
2206 DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount]);
2207 DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount]);
2208 }
2209 }
2210
2211 /* 2010/10/19 MH Add Regulator recognize for CU. */
2212 if (!AutoLoadFail) {
2213 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7); /* bit0~2 */
2214 if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2215 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */
2216 } else {
2217 pHalData->EEPROMRegulatory = 0;
2218 }
2219 DBG_88E("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
2220}
2221
2222void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
2223{
2224 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
2225
2226 if (!AutoLoadFail) {
2227 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E];
2228 if (pHalData->CrystalCap == 0xFF)
2229 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
2230 } else {
2231 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
2232 }
2233 DBG_88E("CrystalCap: 0x%2x\n", pHalData->CrystalCap);
2234}
2235
2236void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
2237{
2238 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
2239
2240 if (!AutoLoadFail)
2241 pHalData->BoardType = ((hwinfo[EEPROM_RF_BOARD_OPTION_88E]&0xE0)>>5);
2242 else
2243 pHalData->BoardType = 0;
2244 DBG_88E("Board Type: 0x%2x\n", pHalData->BoardType);
2245}
2246
2247void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
2248{
2249 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
2250
2251 if (!AutoLoadFail) {
2252 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_88E];
2253 if (pHalData->EEPROMVersion == 0xFF)
2254 pHalData->EEPROMVersion = EEPROM_Default_Version;
2255 } else {
2256 pHalData->EEPROMVersion = 1;
2257 }
2258 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
2259 ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
2260 pHalData->EEPROMVersion));
2261}
2262
2263void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
2264{
2265 padapter->mlmepriv.ChannelPlan =
2266 hal_com_get_channel_plan(padapter,
2267 hwinfo ? hwinfo[EEPROM_ChannelPlan_88E] : 0xFF,
2268 padapter->registrypriv.channel_plan,
2269 RT_CHANNEL_DOMAIN_WORLD_WIDE_13, AutoLoadFail);
2270
2271 DBG_88E("mlmepriv.ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan);
2272}
2273
2274void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
2275{
2276 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
2277
2278 if (!AutoLoadFail) {
2279 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CUSTOMERID_88E];
2280 } else {
2281 pHalData->EEPROMCustomerID = 0;
2282 pHalData->EEPROMSubCustomerID = 0;
2283 }
2284 DBG_88E("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID);
2285}
2286
2287void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent, bool AutoLoadFail)
2288{
2289 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
2290 struct registry_priv *registry_par = &pAdapter->registrypriv;
2291
2292 if (!AutoLoadFail) {
2293 /* Antenna Diversity setting. */
2294 if (registry_par->antdiv_cfg == 2) { /* 2:By EFUSE */
2295 pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x18)>>3;
2296 if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2297 pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION&0x18)>>3;;
2298 } else {
2299 pHalData->AntDivCfg = registry_par->antdiv_cfg; /* 0:OFF , 1:ON, 2:By EFUSE */
2300 }
2301
2302 if (registry_par->antdiv_type == 0) {
2303 /* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
2304 pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
2305 if (pHalData->TRxAntDivType == 0xFF)
2306 pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; /* For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
2307 } else {
2308 pHalData->TRxAntDivType = registry_par->antdiv_type;
2309 }
2310
2311 if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV)
2312 pHalData->AntDivCfg = 1; /* 0xC1[3] is ignored. */
2313 } else {
2314 pHalData->AntDivCfg = 0;
2315 pHalData->TRxAntDivType = pHalData->TRxAntDivType; /* The value in the driver setting of device manager. */
2316 }
2317 DBG_88E("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n", pHalData->AntDivCfg, pHalData->TRxAntDivType);
2318}
2319
2320void Hal_ReadThermalMeter_88E(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
2321{
2322 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
2323
2324 /* ThermalMeter from EEPROM */
2325 if (!AutoloadFail)
2326 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E];
2327 else
2328 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
2329
2330 if (pHalData->EEPROMThermalMeter == 0xff || AutoloadFail) {
2331 pHalData->bAPKThermalMeterIgnore = true;
2332 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
2333 }
2334 DBG_88E("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter);
2335}
2336
2337void Hal_InitChannelPlan(struct adapter *padapter)
2338{
2339}
2340
2341bool HalDetectPwrDownMode88E(struct adapter *Adapter)
2342{
2343 u8 tmpvalue = 0;
2344 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
2345 struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
2346
2347 EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_FEATURE_OPTION_88E, (u32 *)&tmpvalue);
2348
2349 /* 2010/08/25 MH INF priority > PDN Efuse value. */
2350 if (tmpvalue & BIT(4) && pwrctrlpriv->reg_pdnmode)
2351 pHalData->pwrdown = true;
2352 else
2353 pHalData->pwrdown = false;
2354
2355 DBG_88E("HalDetectPwrDownMode(): PDN =%d\n", pHalData->pwrdown);
2356
2357 return pHalData->pwrdown;
2358} /* HalDetectPwrDownMode */
2359
2360/* This function is used only for 92C to set REG_BCN_CTRL(0x550) register. */
2361/* We just reserve the value of the register in variable pHalData->RegBcnCtrlVal and then operate */
2362/* the value of the register via atomic operation. */
2363/* This prevents from race condition when setting this register. */
2364/* The value of pHalData->RegBcnCtrlVal is initialized in HwConfigureRTL8192CE() function. */
2365
2366void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits)
2367{
2368 struct hal_data_8188e *pHalData;
2369
2370 pHalData = GET_HAL_DATA(padapter);
2371
2372 pHalData->RegBcnCtrlVal |= SetBits;
2373 pHalData->RegBcnCtrlVal &= ~ClearBits;
2374
2375 rtw_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal);
2376}
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