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Commit | Line | Data |
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ecdfa446 GKH |
1 | #include "r8192E.h" |
2 | #include "r8192E_hw.h" | |
3 | #include "r819xE_phyreg.h" | |
4 | #include "r8190_rtl8256.h" | |
5 | #include "r819xE_phy.h" | |
6 | #include "r8192E_dm.h" | |
7 | #ifdef ENABLE_DOT11D | |
65a43784 | 8 | #include "ieee80211/dot11d.h" |
ecdfa446 | 9 | #endif |
ab2161a0 | 10 | static const u32 RF_CHANNEL_TABLE_ZEBRA[] = { |
ecdfa446 GKH |
11 | 0, |
12 | 0x085c, //2412 1 | |
13 | 0x08dc, //2417 2 | |
14 | 0x095c, //2422 3 | |
15 | 0x09dc, //2427 4 | |
16 | 0x0a5c, //2432 5 | |
17 | 0x0adc, //2437 6 | |
18 | 0x0b5c, //2442 7 | |
19 | 0x0bdc, //2447 8 | |
20 | 0x0c5c, //2452 9 | |
21 | 0x0cdc, //2457 10 | |
22 | 0x0d5c, //2462 11 | |
23 | 0x0ddc, //2467 12 | |
24 | 0x0e5c, //2472 13 | |
25 | 0x0f72, //2484 | |
26 | }; | |
4803ef77 | 27 | |
5e1ad18a | 28 | static u32 Rtl8192PciEMACPHY_Array[] = { |
ecdfa446 GKH |
29 | 0x03c,0xffff0000,0x00000f0f, |
30 | 0x340,0xffffffff,0x161a1a1a, | |
31 | 0x344,0xffffffff,0x12121416, | |
32 | 0x348,0x0000ffff,0x00001818, | |
33 | 0x12c,0xffffffff,0x04000802, | |
34 | 0x318,0x00000fff,0x00000100, | |
35 | }; | |
5e1ad18a | 36 | static u32 Rtl8192PciEMACPHY_Array_PG[] = { |
ecdfa446 GKH |
37 | 0x03c,0xffff0000,0x00000f0f, |
38 | 0xe00,0xffffffff,0x06090909, | |
39 | 0xe04,0xffffffff,0x00030306, | |
40 | 0xe08,0x0000ff00,0x00000000, | |
41 | 0xe10,0xffffffff,0x0a0c0d0f, | |
42 | 0xe14,0xffffffff,0x06070809, | |
43 | 0xe18,0xffffffff,0x0a0c0d0f, | |
44 | 0xe1c,0xffffffff,0x06070809, | |
45 | 0x12c,0xffffffff,0x04000802, | |
46 | 0x318,0x00000fff,0x00000800, | |
47 | }; | |
5e1ad18a | 48 | static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = { |
ecdfa446 GKH |
49 | 0xc78,0x7d000001, |
50 | 0xc78,0x7d010001, | |
51 | 0xc78,0x7d020001, | |
52 | 0xc78,0x7d030001, | |
53 | 0xc78,0x7d040001, | |
54 | 0xc78,0x7d050001, | |
55 | 0xc78,0x7c060001, | |
56 | 0xc78,0x7b070001, | |
57 | 0xc78,0x7a080001, | |
58 | 0xc78,0x79090001, | |
59 | 0xc78,0x780a0001, | |
60 | 0xc78,0x770b0001, | |
61 | 0xc78,0x760c0001, | |
62 | 0xc78,0x750d0001, | |
63 | 0xc78,0x740e0001, | |
64 | 0xc78,0x730f0001, | |
65 | 0xc78,0x72100001, | |
66 | 0xc78,0x71110001, | |
67 | 0xc78,0x70120001, | |
68 | 0xc78,0x6f130001, | |
69 | 0xc78,0x6e140001, | |
70 | 0xc78,0x6d150001, | |
71 | 0xc78,0x6c160001, | |
72 | 0xc78,0x6b170001, | |
73 | 0xc78,0x6a180001, | |
74 | 0xc78,0x69190001, | |
75 | 0xc78,0x681a0001, | |
76 | 0xc78,0x671b0001, | |
77 | 0xc78,0x661c0001, | |
78 | 0xc78,0x651d0001, | |
79 | 0xc78,0x641e0001, | |
80 | 0xc78,0x491f0001, | |
81 | 0xc78,0x48200001, | |
82 | 0xc78,0x47210001, | |
83 | 0xc78,0x46220001, | |
84 | 0xc78,0x45230001, | |
85 | 0xc78,0x44240001, | |
86 | 0xc78,0x43250001, | |
87 | 0xc78,0x28260001, | |
88 | 0xc78,0x27270001, | |
89 | 0xc78,0x26280001, | |
90 | 0xc78,0x25290001, | |
91 | 0xc78,0x242a0001, | |
92 | 0xc78,0x232b0001, | |
93 | 0xc78,0x222c0001, | |
94 | 0xc78,0x212d0001, | |
95 | 0xc78,0x202e0001, | |
96 | 0xc78,0x0a2f0001, | |
97 | 0xc78,0x08300001, | |
98 | 0xc78,0x06310001, | |
99 | 0xc78,0x05320001, | |
100 | 0xc78,0x04330001, | |
101 | 0xc78,0x03340001, | |
102 | 0xc78,0x02350001, | |
103 | 0xc78,0x01360001, | |
104 | 0xc78,0x00370001, | |
105 | 0xc78,0x00380001, | |
106 | 0xc78,0x00390001, | |
107 | 0xc78,0x003a0001, | |
108 | 0xc78,0x003b0001, | |
109 | 0xc78,0x003c0001, | |
110 | 0xc78,0x003d0001, | |
111 | 0xc78,0x003e0001, | |
112 | 0xc78,0x003f0001, | |
113 | 0xc78,0x7d400001, | |
114 | 0xc78,0x7d410001, | |
115 | 0xc78,0x7d420001, | |
116 | 0xc78,0x7d430001, | |
117 | 0xc78,0x7d440001, | |
118 | 0xc78,0x7d450001, | |
119 | 0xc78,0x7c460001, | |
120 | 0xc78,0x7b470001, | |
121 | 0xc78,0x7a480001, | |
122 | 0xc78,0x79490001, | |
123 | 0xc78,0x784a0001, | |
124 | 0xc78,0x774b0001, | |
125 | 0xc78,0x764c0001, | |
126 | 0xc78,0x754d0001, | |
127 | 0xc78,0x744e0001, | |
128 | 0xc78,0x734f0001, | |
129 | 0xc78,0x72500001, | |
130 | 0xc78,0x71510001, | |
131 | 0xc78,0x70520001, | |
132 | 0xc78,0x6f530001, | |
133 | 0xc78,0x6e540001, | |
134 | 0xc78,0x6d550001, | |
135 | 0xc78,0x6c560001, | |
136 | 0xc78,0x6b570001, | |
137 | 0xc78,0x6a580001, | |
138 | 0xc78,0x69590001, | |
139 | 0xc78,0x685a0001, | |
140 | 0xc78,0x675b0001, | |
141 | 0xc78,0x665c0001, | |
142 | 0xc78,0x655d0001, | |
143 | 0xc78,0x645e0001, | |
144 | 0xc78,0x495f0001, | |
145 | 0xc78,0x48600001, | |
146 | 0xc78,0x47610001, | |
147 | 0xc78,0x46620001, | |
148 | 0xc78,0x45630001, | |
149 | 0xc78,0x44640001, | |
150 | 0xc78,0x43650001, | |
151 | 0xc78,0x28660001, | |
152 | 0xc78,0x27670001, | |
153 | 0xc78,0x26680001, | |
154 | 0xc78,0x25690001, | |
155 | 0xc78,0x246a0001, | |
156 | 0xc78,0x236b0001, | |
157 | 0xc78,0x226c0001, | |
158 | 0xc78,0x216d0001, | |
159 | 0xc78,0x206e0001, | |
160 | 0xc78,0x0a6f0001, | |
161 | 0xc78,0x08700001, | |
162 | 0xc78,0x06710001, | |
163 | 0xc78,0x05720001, | |
164 | 0xc78,0x04730001, | |
165 | 0xc78,0x03740001, | |
166 | 0xc78,0x02750001, | |
167 | 0xc78,0x01760001, | |
168 | 0xc78,0x00770001, | |
169 | 0xc78,0x00780001, | |
170 | 0xc78,0x00790001, | |
171 | 0xc78,0x007a0001, | |
172 | 0xc78,0x007b0001, | |
173 | 0xc78,0x007c0001, | |
174 | 0xc78,0x007d0001, | |
175 | 0xc78,0x007e0001, | |
176 | 0xc78,0x007f0001, | |
177 | 0xc78,0x2e00001e, | |
178 | 0xc78,0x2e01001e, | |
179 | 0xc78,0x2e02001e, | |
180 | 0xc78,0x2e03001e, | |
181 | 0xc78,0x2e04001e, | |
182 | 0xc78,0x2e05001e, | |
183 | 0xc78,0x3006001e, | |
184 | 0xc78,0x3407001e, | |
185 | 0xc78,0x3908001e, | |
186 | 0xc78,0x3c09001e, | |
187 | 0xc78,0x3f0a001e, | |
188 | 0xc78,0x420b001e, | |
189 | 0xc78,0x440c001e, | |
190 | 0xc78,0x450d001e, | |
191 | 0xc78,0x460e001e, | |
192 | 0xc78,0x460f001e, | |
193 | 0xc78,0x4710001e, | |
194 | 0xc78,0x4811001e, | |
195 | 0xc78,0x4912001e, | |
196 | 0xc78,0x4a13001e, | |
197 | 0xc78,0x4b14001e, | |
198 | 0xc78,0x4b15001e, | |
199 | 0xc78,0x4c16001e, | |
200 | 0xc78,0x4d17001e, | |
201 | 0xc78,0x4e18001e, | |
202 | 0xc78,0x4f19001e, | |
203 | 0xc78,0x4f1a001e, | |
204 | 0xc78,0x501b001e, | |
205 | 0xc78,0x511c001e, | |
206 | 0xc78,0x521d001e, | |
207 | 0xc78,0x521e001e, | |
208 | 0xc78,0x531f001e, | |
209 | 0xc78,0x5320001e, | |
210 | 0xc78,0x5421001e, | |
211 | 0xc78,0x5522001e, | |
212 | 0xc78,0x5523001e, | |
213 | 0xc78,0x5624001e, | |
214 | 0xc78,0x5725001e, | |
215 | 0xc78,0x5726001e, | |
216 | 0xc78,0x5827001e, | |
217 | 0xc78,0x5828001e, | |
218 | 0xc78,0x5929001e, | |
219 | 0xc78,0x592a001e, | |
220 | 0xc78,0x5a2b001e, | |
221 | 0xc78,0x5b2c001e, | |
222 | 0xc78,0x5c2d001e, | |
223 | 0xc78,0x5c2e001e, | |
224 | 0xc78,0x5d2f001e, | |
225 | 0xc78,0x5e30001e, | |
226 | 0xc78,0x5f31001e, | |
227 | 0xc78,0x6032001e, | |
228 | 0xc78,0x6033001e, | |
229 | 0xc78,0x6134001e, | |
230 | 0xc78,0x6235001e, | |
231 | 0xc78,0x6336001e, | |
232 | 0xc78,0x6437001e, | |
233 | 0xc78,0x6438001e, | |
234 | 0xc78,0x6539001e, | |
235 | 0xc78,0x663a001e, | |
236 | 0xc78,0x673b001e, | |
237 | 0xc78,0x673c001e, | |
238 | 0xc78,0x683d001e, | |
239 | 0xc78,0x693e001e, | |
240 | 0xc78,0x6a3f001e, | |
241 | }; | |
5e1ad18a | 242 | static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = { |
ecdfa446 | 243 | 0x0, }; |
5e1ad18a | 244 | static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = { |
ecdfa446 GKH |
245 | 0x800,0x00000000, |
246 | 0x804,0x00000001, | |
247 | 0x808,0x0000fc00, | |
248 | 0x80c,0x0000001c, | |
249 | 0x810,0x801010aa, | |
250 | 0x814,0x008514d0, | |
251 | 0x818,0x00000040, | |
252 | 0x81c,0x00000000, | |
253 | 0x820,0x00000004, | |
254 | 0x824,0x00690000, | |
255 | 0x828,0x00000004, | |
256 | 0x82c,0x00e90000, | |
257 | 0x830,0x00000004, | |
258 | 0x834,0x00690000, | |
259 | 0x838,0x00000004, | |
260 | 0x83c,0x00e90000, | |
261 | 0x840,0x00000000, | |
262 | 0x844,0x00000000, | |
263 | 0x848,0x00000000, | |
264 | 0x84c,0x00000000, | |
265 | 0x850,0x00000000, | |
266 | 0x854,0x00000000, | |
267 | 0x858,0x65a965a9, | |
268 | 0x85c,0x65a965a9, | |
269 | 0x860,0x001f0010, | |
270 | 0x864,0x007f0010, | |
271 | 0x868,0x001f0010, | |
272 | 0x86c,0x007f0010, | |
273 | 0x870,0x0f100f70, | |
274 | 0x874,0x0f100f70, | |
275 | 0x878,0x00000000, | |
276 | 0x87c,0x00000000, | |
277 | 0x880,0x6870e36c, | |
278 | 0x884,0xe3573600, | |
279 | 0x888,0x4260c340, | |
280 | 0x88c,0x0000ff00, | |
281 | 0x890,0x00000000, | |
282 | 0x894,0xfffffffe, | |
283 | 0x898,0x4c42382f, | |
284 | 0x89c,0x00656056, | |
285 | 0x8b0,0x00000000, | |
286 | 0x8e0,0x00000000, | |
287 | 0x8e4,0x00000000, | |
288 | 0x900,0x00000000, | |
289 | 0x904,0x00000023, | |
290 | 0x908,0x00000000, | |
291 | 0x90c,0x31121311, | |
292 | 0xa00,0x00d0c7d8, | |
293 | 0xa04,0x811f0008, | |
294 | 0xa08,0x80cd8300, | |
295 | 0xa0c,0x2e62740f, | |
296 | 0xa10,0x95009b78, | |
297 | 0xa14,0x11145008, | |
298 | 0xa18,0x00881117, | |
299 | 0xa1c,0x89140fa0, | |
300 | 0xa20,0x1a1b0000, | |
301 | 0xa24,0x090e1317, | |
302 | 0xa28,0x00000204, | |
303 | 0xa2c,0x00000000, | |
304 | 0xc00,0x00000040, | |
305 | 0xc04,0x00005433, | |
306 | 0xc08,0x000000e4, | |
307 | 0xc0c,0x6c6c6c6c, | |
308 | 0xc10,0x08800000, | |
309 | 0xc14,0x40000100, | |
310 | 0xc18,0x08000000, | |
311 | 0xc1c,0x40000100, | |
312 | 0xc20,0x08000000, | |
313 | 0xc24,0x40000100, | |
314 | 0xc28,0x08000000, | |
315 | 0xc2c,0x40000100, | |
316 | 0xc30,0x6de9ac44, | |
317 | 0xc34,0x465c52cd, | |
318 | 0xc38,0x497f5994, | |
319 | 0xc3c,0x0a969764, | |
320 | 0xc40,0x1f7c403f, | |
321 | 0xc44,0x000100b7, | |
322 | 0xc48,0xec020000, | |
323 | 0xc4c,0x00000300, | |
324 | 0xc50,0x69543420, | |
325 | 0xc54,0x433c0094, | |
326 | 0xc58,0x69543420, | |
327 | 0xc5c,0x433c0094, | |
328 | 0xc60,0x69543420, | |
329 | 0xc64,0x433c0094, | |
330 | 0xc68,0x69543420, | |
331 | 0xc6c,0x433c0094, | |
332 | 0xc70,0x2c7f000d, | |
333 | 0xc74,0x0186175b, | |
334 | 0xc78,0x0000001f, | |
335 | 0xc7c,0x00b91612, | |
336 | 0xc80,0x40000100, | |
337 | 0xc84,0x20000000, | |
338 | 0xc88,0x40000100, | |
339 | 0xc8c,0x20200000, | |
340 | 0xc90,0x40000100, | |
341 | 0xc94,0x00000000, | |
342 | 0xc98,0x40000100, | |
343 | 0xc9c,0x00000000, | |
344 | 0xca0,0x00492492, | |
345 | 0xca4,0x00000000, | |
346 | 0xca8,0x00000000, | |
347 | 0xcac,0x00000000, | |
348 | 0xcb0,0x00000000, | |
349 | 0xcb4,0x00000000, | |
350 | 0xcb8,0x00000000, | |
351 | 0xcbc,0x00492492, | |
352 | 0xcc0,0x00000000, | |
353 | 0xcc4,0x00000000, | |
354 | 0xcc8,0x00000000, | |
355 | 0xccc,0x00000000, | |
356 | 0xcd0,0x00000000, | |
357 | 0xcd4,0x00000000, | |
358 | 0xcd8,0x64b22427, | |
359 | 0xcdc,0x00766932, | |
360 | 0xce0,0x00222222, | |
361 | 0xd00,0x00000750, | |
362 | 0xd04,0x00000403, | |
363 | 0xd08,0x0000907f, | |
364 | 0xd0c,0x00000001, | |
365 | 0xd10,0xa0633333, | |
366 | 0xd14,0x33333c63, | |
367 | 0xd18,0x6a8f5b6b, | |
368 | 0xd1c,0x00000000, | |
369 | 0xd20,0x00000000, | |
370 | 0xd24,0x00000000, | |
371 | 0xd28,0x00000000, | |
372 | 0xd2c,0xcc979975, | |
373 | 0xd30,0x00000000, | |
374 | 0xd34,0x00000000, | |
375 | 0xd38,0x00000000, | |
376 | 0xd3c,0x00027293, | |
377 | 0xd40,0x00000000, | |
378 | 0xd44,0x00000000, | |
379 | 0xd48,0x00000000, | |
380 | 0xd4c,0x00000000, | |
381 | 0xd50,0x6437140a, | |
382 | 0xd54,0x024dbd02, | |
383 | 0xd58,0x00000000, | |
384 | 0xd5c,0x04032064, | |
385 | 0xe00,0x161a1a1a, | |
386 | 0xe04,0x12121416, | |
387 | 0xe08,0x00001800, | |
388 | 0xe0c,0x00000000, | |
389 | 0xe10,0x161a1a1a, | |
390 | 0xe14,0x12121416, | |
391 | 0xe18,0x161a1a1a, | |
392 | 0xe1c,0x12121416, | |
393 | }; | |
5e1ad18a | 394 | static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = { |
ecdfa446 GKH |
395 | 0x019,0x00000003, |
396 | 0x000,0x000000bf, | |
397 | 0x001,0x00000ee0, | |
398 | 0x002,0x0000004c, | |
399 | 0x003,0x000007f1, | |
400 | 0x004,0x00000975, | |
401 | 0x005,0x00000c58, | |
402 | 0x006,0x00000ae6, | |
403 | 0x007,0x000000ca, | |
404 | 0x008,0x00000e1c, | |
405 | 0x009,0x000007f0, | |
406 | 0x00a,0x000009d0, | |
407 | 0x00b,0x000001ba, | |
408 | 0x00c,0x00000240, | |
409 | 0x00e,0x00000020, | |
410 | 0x00f,0x00000990, | |
411 | 0x012,0x00000806, | |
412 | 0x014,0x000005ab, | |
413 | 0x015,0x00000f80, | |
414 | 0x016,0x00000020, | |
415 | 0x017,0x00000597, | |
416 | 0x018,0x0000050a, | |
417 | 0x01a,0x00000f80, | |
418 | 0x01b,0x00000f5e, | |
419 | 0x01c,0x00000008, | |
420 | 0x01d,0x00000607, | |
421 | 0x01e,0x000006cc, | |
422 | 0x01f,0x00000000, | |
423 | 0x020,0x000001a5, | |
424 | 0x01f,0x00000001, | |
425 | 0x020,0x00000165, | |
426 | 0x01f,0x00000002, | |
427 | 0x020,0x000000c6, | |
428 | 0x01f,0x00000003, | |
429 | 0x020,0x00000086, | |
430 | 0x01f,0x00000004, | |
431 | 0x020,0x00000046, | |
432 | 0x01f,0x00000005, | |
433 | 0x020,0x000001e6, | |
434 | 0x01f,0x00000006, | |
435 | 0x020,0x000001a6, | |
436 | 0x01f,0x00000007, | |
437 | 0x020,0x00000166, | |
438 | 0x01f,0x00000008, | |
439 | 0x020,0x000000c7, | |
440 | 0x01f,0x00000009, | |
441 | 0x020,0x00000087, | |
442 | 0x01f,0x0000000a, | |
443 | 0x020,0x000000f7, | |
444 | 0x01f,0x0000000b, | |
445 | 0x020,0x000000d7, | |
446 | 0x01f,0x0000000c, | |
447 | 0x020,0x000000b7, | |
448 | 0x01f,0x0000000d, | |
449 | 0x020,0x00000097, | |
450 | 0x01f,0x0000000e, | |
451 | 0x020,0x00000077, | |
452 | 0x01f,0x0000000f, | |
453 | 0x020,0x00000057, | |
454 | 0x01f,0x00000010, | |
455 | 0x020,0x00000037, | |
456 | 0x01f,0x00000011, | |
457 | 0x020,0x000000fb, | |
458 | 0x01f,0x00000012, | |
459 | 0x020,0x000000db, | |
460 | 0x01f,0x00000013, | |
461 | 0x020,0x000000bb, | |
462 | 0x01f,0x00000014, | |
463 | 0x020,0x000000ff, | |
464 | 0x01f,0x00000015, | |
465 | 0x020,0x000000e3, | |
466 | 0x01f,0x00000016, | |
467 | 0x020,0x000000c3, | |
468 | 0x01f,0x00000017, | |
469 | 0x020,0x000000a3, | |
470 | 0x01f,0x00000018, | |
471 | 0x020,0x00000083, | |
472 | 0x01f,0x00000019, | |
473 | 0x020,0x00000063, | |
474 | 0x01f,0x0000001a, | |
475 | 0x020,0x00000043, | |
476 | 0x01f,0x0000001b, | |
477 | 0x020,0x00000023, | |
478 | 0x01f,0x0000001c, | |
479 | 0x020,0x00000003, | |
480 | 0x01f,0x0000001d, | |
481 | 0x020,0x000001e3, | |
482 | 0x01f,0x0000001e, | |
483 | 0x020,0x000001c3, | |
484 | 0x01f,0x0000001f, | |
485 | 0x020,0x000001a3, | |
486 | 0x01f,0x00000020, | |
487 | 0x020,0x00000183, | |
488 | 0x01f,0x00000021, | |
489 | 0x020,0x00000163, | |
490 | 0x01f,0x00000022, | |
491 | 0x020,0x00000143, | |
492 | 0x01f,0x00000023, | |
493 | 0x020,0x00000123, | |
494 | 0x01f,0x00000024, | |
495 | 0x020,0x00000103, | |
496 | 0x023,0x00000203, | |
497 | 0x024,0x00000100, | |
498 | 0x00b,0x000001ba, | |
499 | 0x02c,0x000003d7, | |
500 | 0x02d,0x00000ff0, | |
501 | 0x000,0x00000037, | |
502 | 0x004,0x00000160, | |
503 | 0x007,0x00000080, | |
504 | 0x002,0x0000088d, | |
505 | 0x0fe,0x00000000, | |
506 | 0x0fe,0x00000000, | |
507 | 0x016,0x00000200, | |
508 | 0x016,0x00000380, | |
509 | 0x016,0x00000020, | |
510 | 0x016,0x000001a0, | |
511 | 0x000,0x000000bf, | |
512 | 0x00d,0x0000001f, | |
513 | 0x00d,0x00000c9f, | |
514 | 0x002,0x0000004d, | |
515 | 0x000,0x00000cbf, | |
516 | 0x004,0x00000975, | |
517 | 0x007,0x00000700, | |
518 | }; | |
5e1ad18a | 519 | static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = { |
ecdfa446 GKH |
520 | 0x019,0x00000003, |
521 | 0x000,0x000000bf, | |
522 | 0x001,0x000006e0, | |
523 | 0x002,0x0000004c, | |
524 | 0x003,0x000007f1, | |
525 | 0x004,0x00000975, | |
526 | 0x005,0x00000c58, | |
527 | 0x006,0x00000ae6, | |
528 | 0x007,0x000000ca, | |
529 | 0x008,0x00000e1c, | |
530 | 0x000,0x000000b7, | |
531 | 0x00a,0x00000850, | |
532 | 0x000,0x000000bf, | |
533 | 0x00b,0x000001ba, | |
534 | 0x00c,0x00000240, | |
535 | 0x00e,0x00000020, | |
536 | 0x015,0x00000f80, | |
537 | 0x016,0x00000020, | |
538 | 0x017,0x00000597, | |
539 | 0x018,0x0000050a, | |
540 | 0x01a,0x00000e00, | |
541 | 0x01b,0x00000f5e, | |
542 | 0x01d,0x00000607, | |
543 | 0x01e,0x000006cc, | |
544 | 0x00b,0x000001ba, | |
545 | 0x023,0x00000203, | |
546 | 0x024,0x00000100, | |
547 | 0x000,0x00000037, | |
548 | 0x004,0x00000160, | |
549 | 0x016,0x00000200, | |
550 | 0x016,0x00000380, | |
551 | 0x016,0x00000020, | |
552 | 0x016,0x000001a0, | |
553 | 0x00d,0x00000ccc, | |
554 | 0x000,0x000000bf, | |
555 | 0x002,0x0000004d, | |
556 | 0x000,0x00000cbf, | |
557 | 0x004,0x00000975, | |
558 | 0x007,0x00000700, | |
559 | }; | |
5e1ad18a | 560 | static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = { |
ecdfa446 | 561 | 0x0, }; |
5e1ad18a | 562 | static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = { |
ecdfa446 | 563 | 0x0, }; |
ecdfa446 GKH |
564 | |
565 | /*************************Define local function prototype**********************/ | |
566 | ||
d9ffa6c2 MM |
567 | static u32 phy_FwRFSerialRead(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset); |
568 | static void phy_FwRFSerialWrite(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); | |
569 | ||
ecdfa446 GKH |
570 | /*************************Define local function prototype**********************/ |
571 | /****************************************************************************** | |
572 | *function: This function read BB parameters from Header file we gen, | |
573 | * and do register read/write | |
574 | * input: u32 dwBitMask //taget bit pos in the addr to be modified | |
575 | * output: none | |
576 | * return: u32 return the shift bit bit position of the mask | |
577 | * ****************************************************************************/ | |
5e1ad18a | 578 | static u32 rtl8192_CalculateBitShift(u32 dwBitMask) |
ecdfa446 GKH |
579 | { |
580 | u32 i; | |
581 | for (i=0; i<=31; i++) | |
582 | { | |
583 | if (((dwBitMask>>i)&0x1) == 1) | |
584 | break; | |
585 | } | |
586 | return i; | |
587 | } | |
588 | /****************************************************************************** | |
589 | *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false. | |
590 | * input: none | |
591 | * output: none | |
592 | * return: 0(illegal, false), 1(legal,true) | |
593 | * ***************************************************************************/ | |
d9ffa6c2 | 594 | u8 rtl8192_phy_CheckIsLegalRFPath(struct r8192_priv *priv, u32 eRFPath) |
ecdfa446 GKH |
595 | { |
596 | u8 ret = 1; | |
4803ef77 | 597 | |
ecdfa446 GKH |
598 | if (priv->rf_type == RF_2T4R) |
599 | ret = 0; | |
600 | else if (priv->rf_type == RF_1T2R) | |
601 | { | |
602 | if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) | |
603 | ret = 1; | |
604 | else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) | |
605 | ret = 0; | |
606 | } | |
4803ef77 | 607 | |
ecdfa446 GKH |
608 | return ret; |
609 | } | |
610 | /****************************************************************************** | |
611 | *function: This function set specific bits to BB register | |
612 | * input: net_device dev | |
613 | * u32 dwRegAddr //target addr to be modified | |
614 | * u32 dwBitMask //taget bit pos in the addr to be modified | |
615 | * u32 dwData //value to be write | |
616 | * output: none | |
617 | * return: none | |
618 | * notice: | |
619 | * ****************************************************************************/ | |
d9ffa6c2 | 620 | void rtl8192_setBBreg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask, u32 dwData) |
ecdfa446 | 621 | { |
ecdfa446 GKH |
622 | u32 OriginalValue, BitShift, NewValue; |
623 | ||
624 | if(dwBitMask!= bMaskDWord) | |
625 | {//if not "double word" write | |
3f9ab1ee | 626 | OriginalValue = read_nic_dword(priv, dwRegAddr); |
ecdfa446 GKH |
627 | BitShift = rtl8192_CalculateBitShift(dwBitMask); |
628 | NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); | |
3f9ab1ee | 629 | write_nic_dword(priv, dwRegAddr, NewValue); |
ecdfa446 | 630 | }else |
3f9ab1ee | 631 | write_nic_dword(priv, dwRegAddr, dwData); |
ecdfa446 GKH |
632 | } |
633 | /****************************************************************************** | |
634 | *function: This function reads specific bits from BB register | |
635 | * input: net_device dev | |
636 | * u32 dwRegAddr //target addr to be readback | |
637 | * u32 dwBitMask //taget bit pos in the addr to be readback | |
638 | * output: none | |
639 | * return: u32 Data //the readback register value | |
640 | * notice: | |
641 | * ****************************************************************************/ | |
d9ffa6c2 | 642 | u32 rtl8192_QueryBBReg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask) |
ecdfa446 | 643 | { |
49e57f2f | 644 | u32 OriginalValue, BitShift; |
ecdfa446 | 645 | |
3f9ab1ee | 646 | OriginalValue = read_nic_dword(priv, dwRegAddr); |
ecdfa446 | 647 | BitShift = rtl8192_CalculateBitShift(dwBitMask); |
49e57f2f | 648 | return (OriginalValue & dwBitMask) >> BitShift; |
ecdfa446 GKH |
649 | } |
650 | /****************************************************************************** | |
651 | *function: This function read register from RF chip | |
652 | * input: net_device dev | |
653 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D | |
654 | * u32 Offset //target address to be read | |
655 | * output: none | |
656 | * return: u32 readback value | |
657 | * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information. | |
658 | * ****************************************************************************/ | |
d9ffa6c2 MM |
659 | static u32 rtl8192_phy_RFSerialRead(struct r8192_priv *priv, |
660 | RF90_RADIO_PATH_E eRFPath, u32 Offset) | |
ecdfa446 | 661 | { |
ecdfa446 GKH |
662 | u32 ret = 0; |
663 | u32 NewOffset = 0; | |
664 | BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath]; | |
665 | //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); | |
666 | //make sure RF register offset is correct | |
667 | Offset &= 0x3f; | |
668 | ||
669 | //switch page for 8256 RF IC | |
6f304eb2 | 670 | //analog to digital off, for protection |
d9ffa6c2 | 671 | rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] |
6f304eb2 | 672 | if (Offset >= 31) |
ecdfa446 | 673 | { |
6f304eb2 MM |
674 | priv->RfReg0Value[eRFPath] |= 0x140; |
675 | //Switch to Reg_Mode2 for Reg 31-45 | |
d9ffa6c2 | 676 | rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); |
6f304eb2 MM |
677 | //modify offset |
678 | NewOffset = Offset -30; | |
679 | } | |
680 | else if (Offset >= 16) | |
681 | { | |
682 | priv->RfReg0Value[eRFPath] |= 0x100; | |
683 | priv->RfReg0Value[eRFPath] &= (~0x40); | |
684 | //Switch to Reg_Mode 1 for Reg16-30 | |
d9ffa6c2 | 685 | rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); |
ecdfa446 | 686 | |
6f304eb2 | 687 | NewOffset = Offset - 15; |
ecdfa446 GKH |
688 | } |
689 | else | |
ecdfa446 | 690 | NewOffset = Offset; |
6f304eb2 | 691 | |
ecdfa446 | 692 | //put desired read addr to LSSI control Register |
d9ffa6c2 | 693 | rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); |
ecdfa446 GKH |
694 | //Issue a posedge trigger |
695 | // | |
d9ffa6c2 MM |
696 | rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); |
697 | rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); | |
ecdfa446 GKH |
698 | |
699 | ||
700 | // TODO: we should not delay such a long time. Ask help from SD3 | |
701 | msleep(1); | |
702 | ||
d9ffa6c2 | 703 | ret = rtl8192_QueryBBReg(priv, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); |
ecdfa446 GKH |
704 | |
705 | ||
706 | // Switch back to Reg_Mode0; | |
6f304eb2 | 707 | priv->RfReg0Value[eRFPath] &= 0xebf; |
ecdfa446 | 708 | |
6f304eb2 | 709 | rtl8192_setBBreg( |
d9ffa6c2 | 710 | priv, |
6f304eb2 MM |
711 | pPhyReg->rf3wireOffset, |
712 | bMaskDWord, | |
713 | (priv->RfReg0Value[eRFPath] << 16)); | |
ecdfa446 | 714 | |
6f304eb2 | 715 | //analog to digital on |
d9ffa6c2 | 716 | rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] |
ecdfa446 GKH |
717 | |
718 | return ret; | |
ecdfa446 GKH |
719 | } |
720 | ||
721 | /****************************************************************************** | |
722 | *function: This function write data to RF register | |
723 | * input: net_device dev | |
724 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D | |
725 | * u32 Offset //target address to be written | |
726 | * u32 Data //The new register data to be written | |
727 | * output: none | |
728 | * return: none | |
729 | * notice: For RF8256 only. | |
730 | =========================================================== | |
731 | *Reg Mode RegCTL[1] RegCTL[0] Note | |
732 | * (Reg00[12]) (Reg00[10]) | |
733 | *=========================================================== | |
734 | *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) | |
735 | *------------------------------------------------------------------ | |
736 | *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) | |
737 | *------------------------------------------------------------------ | |
738 | * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) | |
739 | *------------------------------------------------------------------ | |
740 | * ****************************************************************************/ | |
d9ffa6c2 MM |
741 | static void rtl8192_phy_RFSerialWrite(struct r8192_priv *priv, |
742 | RF90_RADIO_PATH_E eRFPath, u32 Offset, | |
743 | u32 Data) | |
ecdfa446 | 744 | { |
ecdfa446 GKH |
745 | u32 DataAndAddr = 0, NewOffset = 0; |
746 | BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; | |
747 | ||
748 | Offset &= 0x3f; | |
ecdfa446 | 749 | |
6f304eb2 | 750 | //analog to digital off, for protection |
d9ffa6c2 | 751 | rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] |
ecdfa446 | 752 | |
6f304eb2 MM |
753 | if (Offset >= 31) |
754 | { | |
755 | priv->RfReg0Value[eRFPath] |= 0x140; | |
d9ffa6c2 | 756 | rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); |
6f304eb2 | 757 | NewOffset = Offset - 30; |
ecdfa446 | 758 | } |
6f304eb2 | 759 | else if (Offset >= 16) |
ecdfa446 | 760 | { |
6f304eb2 MM |
761 | priv->RfReg0Value[eRFPath] |= 0x100; |
762 | priv->RfReg0Value[eRFPath] &= (~0x40); | |
d9ffa6c2 | 763 | rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); |
6f304eb2 | 764 | NewOffset = Offset - 15; |
ecdfa446 | 765 | } |
6f304eb2 MM |
766 | else |
767 | NewOffset = Offset; | |
ecdfa446 GKH |
768 | |
769 | // Put write addr in [5:0] and write data in [31:16] | |
770 | DataAndAddr = (Data<<16) | (NewOffset&0x3f); | |
771 | ||
772 | // Write Operation | |
d9ffa6c2 | 773 | rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); |
ecdfa446 GKH |
774 | |
775 | ||
776 | if(Offset==0x0) | |
777 | priv->RfReg0Value[eRFPath] = Data; | |
778 | ||
779 | // Switch back to Reg_Mode0; | |
6f304eb2 | 780 | if(Offset != 0) |
ecdfa446 | 781 | { |
6f304eb2 MM |
782 | priv->RfReg0Value[eRFPath] &= 0xebf; |
783 | rtl8192_setBBreg( | |
d9ffa6c2 | 784 | priv, |
6f304eb2 MM |
785 | pPhyReg->rf3wireOffset, |
786 | bMaskDWord, | |
787 | (priv->RfReg0Value[eRFPath] << 16)); | |
ecdfa446 | 788 | } |
6f304eb2 | 789 | //analog to digital on |
d9ffa6c2 | 790 | rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] |
ecdfa446 GKH |
791 | } |
792 | ||
793 | /****************************************************************************** | |
794 | *function: This function set specific bits to RF register | |
d9ffa6c2 | 795 | * input: RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D |
ecdfa446 GKH |
796 | * u32 RegAddr //target addr to be modified |
797 | * u32 BitMask //taget bit pos in the addr to be modified | |
798 | * u32 Data //value to be write | |
799 | * output: none | |
800 | * return: none | |
801 | * notice: | |
802 | * ****************************************************************************/ | |
d9ffa6c2 MM |
803 | void rtl8192_phy_SetRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, |
804 | u32 RegAddr, u32 BitMask, u32 Data) | |
ecdfa446 | 805 | { |
ecdfa446 GKH |
806 | u32 Original_Value, BitShift, New_Value; |
807 | // u8 time = 0; | |
808 | ||
d9ffa6c2 | 809 | if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath)) |
ecdfa446 | 810 | return; |
4559854d | 811 | if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter) |
ecdfa446 | 812 | return; |
ecdfa446 GKH |
813 | //down(&priv->rf_sem); |
814 | ||
815 | RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); | |
816 | if (priv->Rf_Mode == RF_OP_By_FW) | |
817 | { | |
818 | if (BitMask != bMask12Bits) // RF data is 12 bits only | |
819 | { | |
d9ffa6c2 | 820 | Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr); |
ecdfa446 GKH |
821 | BitShift = rtl8192_CalculateBitShift(BitMask); |
822 | New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); | |
823 | ||
d9ffa6c2 | 824 | phy_FwRFSerialWrite(priv, eRFPath, RegAddr, New_Value); |
ecdfa446 | 825 | }else |
d9ffa6c2 | 826 | phy_FwRFSerialWrite(priv, eRFPath, RegAddr, Data); |
ecdfa446 GKH |
827 | udelay(200); |
828 | ||
829 | } | |
830 | else | |
831 | { | |
832 | if (BitMask != bMask12Bits) // RF data is 12 bits only | |
833 | { | |
d9ffa6c2 | 834 | Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr); |
ecdfa446 GKH |
835 | BitShift = rtl8192_CalculateBitShift(BitMask); |
836 | New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); | |
837 | ||
d9ffa6c2 | 838 | rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, New_Value); |
ecdfa446 | 839 | }else |
d9ffa6c2 | 840 | rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, Data); |
ecdfa446 | 841 | } |
ecdfa446 | 842 | //up(&priv->rf_sem); |
ecdfa446 GKH |
843 | } |
844 | ||
845 | /****************************************************************************** | |
846 | *function: This function reads specific bits from RF register | |
847 | * input: net_device dev | |
848 | * u32 RegAddr //target addr to be readback | |
849 | * u32 BitMask //taget bit pos in the addr to be readback | |
850 | * output: none | |
851 | * return: u32 Data //the readback register value | |
852 | * notice: | |
853 | * ****************************************************************************/ | |
d9ffa6c2 MM |
854 | u32 rtl8192_phy_QueryRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, |
855 | u32 RegAddr, u32 BitMask) | |
ecdfa446 GKH |
856 | { |
857 | u32 Original_Value, Readback_Value, BitShift; | |
d9ffa6c2 MM |
858 | |
859 | if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath)) | |
ecdfa446 | 860 | return 0; |
4559854d | 861 | if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter) |
ecdfa446 | 862 | return 0; |
ecdfa446 GKH |
863 | down(&priv->rf_sem); |
864 | if (priv->Rf_Mode == RF_OP_By_FW) | |
865 | { | |
d9ffa6c2 | 866 | Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr); |
ecdfa446 GKH |
867 | udelay(200); |
868 | } | |
869 | else | |
870 | { | |
d9ffa6c2 | 871 | Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr); |
ecdfa446 GKH |
872 | |
873 | } | |
874 | BitShift = rtl8192_CalculateBitShift(BitMask); | |
875 | Readback_Value = (Original_Value & BitMask) >> BitShift; | |
876 | up(&priv->rf_sem); | |
877 | // udelay(200); | |
c6eae677 | 878 | return Readback_Value; |
ecdfa446 GKH |
879 | } |
880 | ||
881 | /****************************************************************************** | |
882 | *function: We support firmware to execute RF-R/W. | |
883 | * input: dev | |
884 | * output: none | |
885 | * return: none | |
886 | * notice: | |
887 | * ***************************************************************************/ | |
d9ffa6c2 MM |
888 | static u32 phy_FwRFSerialRead(struct r8192_priv *priv, |
889 | RF90_RADIO_PATH_E eRFPath, u32 Offset) | |
ecdfa446 | 890 | { |
ecdfa446 GKH |
891 | u32 Data = 0; |
892 | u8 time = 0; | |
893 | //DbgPrint("FW RF CTRL\n\r"); | |
894 | /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can | |
895 | not execute the scheme in the initial step. Otherwise, RF-R/W will waste | |
896 | much time. This is only for site survey. */ | |
897 | // 1. Read operation need not insert data. bit 0-11 | |
898 | //Data &= bMask12Bits; | |
899 | // 2. Write RF register address. Bit 12-19 | |
900 | Data |= ((Offset&0xFF)<<12); | |
901 | // 3. Write RF path. bit 20-21 | |
902 | Data |= ((eRFPath&0x3)<<20); | |
903 | // 4. Set RF read indicator. bit 22=0 | |
904 | //Data |= 0x00000; | |
905 | // 5. Trigger Fw to operate the command. bit 31 | |
906 | Data |= 0x80000000; | |
907 | // 6. We can not execute read operation if bit 31 is 1. | |
3f9ab1ee | 908 | while (read_nic_dword(priv, QPNR)&0x80000000) |
ecdfa446 GKH |
909 | { |
910 | // If FW can not finish RF-R/W for more than ?? times. We must reset FW. | |
911 | if (time++ < 100) | |
912 | { | |
913 | //DbgPrint("FW not finish RF-R Time=%d\n\r", time); | |
914 | udelay(10); | |
915 | } | |
916 | else | |
917 | break; | |
918 | } | |
919 | // 7. Execute read operation. | |
3f9ab1ee | 920 | write_nic_dword(priv, QPNR, Data); |
ecdfa446 | 921 | // 8. Check if firmawre send back RF content. |
3f9ab1ee | 922 | while (read_nic_dword(priv, QPNR)&0x80000000) |
ecdfa446 GKH |
923 | { |
924 | // If FW can not finish RF-R/W for more than ?? times. We must reset FW. | |
925 | if (time++ < 100) | |
926 | { | |
927 | //DbgPrint("FW not finish RF-W Time=%d\n\r", time); | |
928 | udelay(10); | |
929 | } | |
930 | else | |
c6eae677 | 931 | return 0; |
ecdfa446 | 932 | } |
3f9ab1ee | 933 | return read_nic_dword(priv, RF_DATA); |
d5abdf72 | 934 | } |
ecdfa446 GKH |
935 | |
936 | /****************************************************************************** | |
937 | *function: We support firmware to execute RF-R/W. | |
938 | * input: dev | |
939 | * output: none | |
940 | * return: none | |
941 | * notice: | |
942 | * ***************************************************************************/ | |
d9ffa6c2 MM |
943 | static void phy_FwRFSerialWrite(struct r8192_priv *priv, |
944 | RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) | |
ecdfa446 GKH |
945 | { |
946 | u8 time = 0; | |
947 | ||
948 | //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); | |
949 | /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can | |
950 | not execute the scheme in the initial step. Otherwise, RF-R/W will waste | |
951 | much time. This is only for site survey. */ | |
952 | ||
953 | // 1. Set driver write bit and 12 bit data. bit 0-11 | |
954 | //Data &= bMask12Bits; // Done by uper layer. | |
955 | // 2. Write RF register address. bit 12-19 | |
956 | Data |= ((Offset&0xFF)<<12); | |
957 | // 3. Write RF path. bit 20-21 | |
958 | Data |= ((eRFPath&0x3)<<20); | |
959 | // 4. Set RF write indicator. bit 22=1 | |
960 | Data |= 0x400000; | |
961 | // 5. Trigger Fw to operate the command. bit 31=1 | |
962 | Data |= 0x80000000; | |
963 | ||
964 | // 6. Write operation. We can not write if bit 31 is 1. | |
3f9ab1ee | 965 | while (read_nic_dword(priv, QPNR)&0x80000000) |
ecdfa446 GKH |
966 | { |
967 | // If FW can not finish RF-R/W for more than ?? times. We must reset FW. | |
968 | if (time++ < 100) | |
969 | { | |
970 | //DbgPrint("FW not finish RF-W Time=%d\n\r", time); | |
971 | udelay(10); | |
972 | } | |
973 | else | |
974 | break; | |
975 | } | |
976 | // 7. No matter check bit. We always force the write. Because FW will | |
977 | // not accept the command. | |
3f9ab1ee | 978 | write_nic_dword(priv, QPNR, Data); |
ecdfa446 GKH |
979 | /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware |
980 | to finish RF write operation. */ | |
981 | /* 2008/01/17 MH We support delay in firmware side now. */ | |
982 | //delay_us(20); | |
983 | ||
d5abdf72 | 984 | } |
ecdfa446 GKH |
985 | |
986 | ||
987 | /****************************************************************************** | |
988 | *function: This function read BB parameters from Header file we gen, | |
989 | * and do register read/write | |
990 | * input: dev | |
991 | * output: none | |
992 | * return: none | |
993 | * notice: BB parameters may change all the time, so please make | |
994 | * sure it has been synced with the newest. | |
995 | * ***************************************************************************/ | |
d9ffa6c2 | 996 | void rtl8192_phy_configmac(struct r8192_priv *priv) |
ecdfa446 GKH |
997 | { |
998 | u32 dwArrayLen = 0, i = 0; | |
999 | u32* pdwArray = NULL; | |
ecdfa446 GKH |
1000 | #ifdef TO_DO_LIST |
1001 | if(Adapter->bInHctTest) | |
1002 | { | |
1003 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n"); | |
1004 | dwArrayLen = MACPHY_ArrayLengthDTM; | |
1005 | pdwArray = Rtl819XMACPHY_ArrayDTM; | |
1006 | } | |
1007 | else if(priv->bTXPowerDataReadFromEEPORM) | |
1008 | #endif | |
1009 | if(priv->bTXPowerDataReadFromEEPORM) | |
1010 | { | |
1011 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); | |
1012 | dwArrayLen = MACPHY_Array_PGLength; | |
1013 | pdwArray = Rtl819XMACPHY_Array_PG; | |
1014 | ||
1015 | } | |
1016 | else | |
1017 | { | |
1018 | RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n"); | |
1019 | dwArrayLen = MACPHY_ArrayLength; | |
1020 | pdwArray = Rtl819XMACPHY_Array; | |
1021 | } | |
1022 | for(i = 0; i<dwArrayLen; i=i+3){ | |
1023 | RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", | |
1024 | pdwArray[i], pdwArray[i+1], pdwArray[i+2]); | |
1025 | if(pdwArray[i] == 0x318) | |
1026 | { | |
1027 | pdwArray[i+2] = 0x00000800; | |
1028 | //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", | |
1029 | // ptrArray[i], ptrArray[i+1], ptrArray[i+2]); | |
1030 | } | |
d9ffa6c2 | 1031 | rtl8192_setBBreg(priv, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); |
ecdfa446 | 1032 | } |
ecdfa446 GKH |
1033 | } |
1034 | ||
1035 | /****************************************************************************** | |
1036 | *function: This function do dirty work | |
1037 | * input: dev | |
1038 | * output: none | |
1039 | * return: none | |
1040 | * notice: BB parameters may change all the time, so please make | |
1041 | * sure it has been synced with the newest. | |
1042 | * ***************************************************************************/ | |
1043 | ||
d9ffa6c2 | 1044 | void rtl8192_phyConfigBB(struct r8192_priv *priv, u8 ConfigType) |
ecdfa446 GKH |
1045 | { |
1046 | int i; | |
1047 | //u8 ArrayLength; | |
1048 | u32* Rtl819XPHY_REGArray_Table = NULL; | |
1049 | u32* Rtl819XAGCTAB_Array_Table = NULL; | |
1050 | u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; | |
ecdfa446 GKH |
1051 | #ifdef TO_DO_LIST |
1052 | u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; | |
1053 | if(Adapter->bInHctTest) | |
1054 | { | |
1055 | AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; | |
1056 | Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; | |
1057 | ||
1058 | if(priv->RF_Type == RF_2T4R) | |
1059 | { | |
1060 | PHY_REGArrayLen = PHY_REGArrayLengthDTM; | |
1061 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; | |
1062 | } | |
1063 | else if (priv->RF_Type == RF_1T2R) | |
1064 | { | |
1065 | PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM; | |
1066 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM; | |
1067 | } | |
1068 | } | |
1069 | else | |
1070 | #endif | |
1071 | { | |
1072 | AGCTAB_ArrayLen = AGCTAB_ArrayLength; | |
1073 | Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; | |
1074 | if(priv->rf_type == RF_2T4R) | |
1075 | { | |
1076 | PHY_REGArrayLen = PHY_REGArrayLength; | |
1077 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; | |
1078 | } | |
1079 | else if (priv->rf_type == RF_1T2R) | |
1080 | { | |
1081 | PHY_REGArrayLen = PHY_REG_1T2RArrayLength; | |
1082 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | if (ConfigType == BaseBand_Config_PHY_REG) | |
1087 | { | |
1088 | for (i=0; i<PHY_REGArrayLen; i+=2) | |
1089 | { | |
d9ffa6c2 | 1090 | rtl8192_setBBreg(priv, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); |
703fdcc3 | 1091 | RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]); |
ecdfa446 GKH |
1092 | } |
1093 | } | |
1094 | else if (ConfigType == BaseBand_Config_AGC_TAB) | |
1095 | { | |
1096 | for (i=0; i<AGCTAB_ArrayLen; i+=2) | |
1097 | { | |
d9ffa6c2 | 1098 | rtl8192_setBBreg(priv, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]); |
703fdcc3 | 1099 | RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]); |
ecdfa446 GKH |
1100 | } |
1101 | } | |
ecdfa446 GKH |
1102 | } |
1103 | /****************************************************************************** | |
1104 | *function: This function initialize Register definition offset for Radio Path | |
1105 | * A/B/C/D | |
1106 | * input: net_device dev | |
1107 | * output: none | |
1108 | * return: none | |
1109 | * notice: Initialization value here is constant and it should never be changed | |
1110 | * ***************************************************************************/ | |
d9ffa6c2 | 1111 | static void rtl8192_InitBBRFRegDef(struct r8192_priv *priv) |
ecdfa446 | 1112 | { |
ecdfa446 GKH |
1113 | // RF Interface Sowrtware Control |
1114 | priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 | |
1115 | priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) | |
1116 | priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 | |
1117 | priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) | |
1118 | ||
1119 | // RF Interface Readback Value | |
1120 | priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 | |
1121 | priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) | |
1122 | priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 | |
1123 | priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) | |
1124 | ||
1125 | // RF Interface Output (and Enable) | |
1126 | priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 | |
1127 | priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 | |
1128 | priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868 | |
1129 | priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C | |
1130 | ||
1131 | // RF Interface (Output and) Enable | |
1132 | priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) | |
1133 | priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) | |
1134 | priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) | |
1135 | priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) | |
1136 | ||
1137 | //Addr of LSSI. Wirte RF register by driver | |
1138 | priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter | |
1139 | priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; | |
1140 | priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; | |
1141 | priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; | |
1142 | ||
1143 | // RF parameter | |
1144 | priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select | |
1145 | priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; | |
1146 | priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; | |
1147 | priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; | |
1148 | ||
1149 | // Tx AGC Gain Stage (same for all path. Should we remove this?) | |
1150 | priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage | |
1151 | priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage | |
1152 | priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage | |
1153 | priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage | |
1154 | ||
1155 | // Tranceiver A~D HSSI Parameter-1 | |
1156 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 | |
1157 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 | |
1158 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1 | |
1159 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 | |
1160 | ||
1161 | // Tranceiver A~D HSSI Parameter-2 | |
1162 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 | |
1163 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 | |
1164 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2 | |
1165 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 | |
1166 | ||
1167 | // RF switch Control | |
1168 | priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control | |
1169 | priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; | |
1170 | priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; | |
1171 | priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; | |
1172 | ||
1173 | // AGC control 1 | |
1174 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; | |
1175 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; | |
1176 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; | |
1177 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; | |
1178 | ||
1179 | // AGC control 2 | |
1180 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; | |
1181 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; | |
1182 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; | |
1183 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; | |
1184 | ||
1185 | // RX AFE control 1 | |
1186 | priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; | |
1187 | priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; | |
1188 | priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; | |
1189 | priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; | |
1190 | ||
1191 | // RX AFE control 1 | |
1192 | priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; | |
1193 | priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; | |
1194 | priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; | |
1195 | priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; | |
1196 | ||
1197 | // Tx AFE control 1 | |
1198 | priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; | |
1199 | priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; | |
1200 | priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; | |
1201 | priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; | |
1202 | ||
1203 | // Tx AFE control 2 | |
1204 | priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; | |
1205 | priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; | |
1206 | priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; | |
1207 | priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; | |
1208 | ||
1209 | // Tranceiver LSSI Readback | |
1210 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; | |
1211 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; | |
1212 | priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; | |
1213 | priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; | |
1214 | ||
1215 | } | |
1216 | /****************************************************************************** | |
1217 | *function: This function is to write register and then readback to make sure whether BB and RF is OK | |
1218 | * input: net_device dev | |
1219 | * HW90_BLOCK_E CheckBlock | |
1220 | * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF | |
1221 | * output: none | |
1222 | * return: return whether BB and RF is ok(0:OK; 1:Fail) | |
1223 | * notice: This function may be removed in the ASIC | |
1224 | * ***************************************************************************/ | |
d9ffa6c2 MM |
1225 | RT_STATUS rtl8192_phy_checkBBAndRF(struct r8192_priv *priv, |
1226 | HW90_BLOCK_E CheckBlock, | |
1227 | RF90_RADIO_PATH_E eRFPath) | |
ecdfa446 | 1228 | { |
ecdfa446 GKH |
1229 | // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; |
1230 | RT_STATUS ret = RT_STATUS_SUCCESS; | |
1231 | u32 i, CheckTimes = 4, dwRegRead = 0; | |
1232 | u32 WriteAddr[4]; | |
1233 | u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; | |
1234 | // Initialize register address offset to be checked | |
1235 | WriteAddr[HW90_BLOCK_MAC] = 0x100; | |
1236 | WriteAddr[HW90_BLOCK_PHY0] = 0x900; | |
1237 | WriteAddr[HW90_BLOCK_PHY1] = 0x800; | |
1238 | WriteAddr[HW90_BLOCK_RF] = 0x3; | |
1239 | RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock); | |
1240 | for(i=0 ; i < CheckTimes ; i++) | |
1241 | { | |
1242 | ||
1243 | // | |
1244 | // Write Data to register and readback | |
1245 | // | |
1246 | switch(CheckBlock) | |
1247 | { | |
1248 | case HW90_BLOCK_MAC: | |
703fdcc3 | 1249 | RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n"); |
ecdfa446 GKH |
1250 | break; |
1251 | ||
1252 | case HW90_BLOCK_PHY0: | |
1253 | case HW90_BLOCK_PHY1: | |
3f9ab1ee MM |
1254 | write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]); |
1255 | dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]); | |
ecdfa446 GKH |
1256 | break; |
1257 | ||
1258 | case HW90_BLOCK_RF: | |
1259 | WriteData[i] &= 0xfff; | |
d9ffa6c2 | 1260 | rtl8192_phy_SetRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); |
ecdfa446 GKH |
1261 | // TODO: we should not delay for such a long time. Ask SD3 |
1262 | mdelay(10); | |
d9ffa6c2 | 1263 | dwRegRead = rtl8192_phy_QueryRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); |
ecdfa446 GKH |
1264 | mdelay(10); |
1265 | break; | |
1266 | ||
1267 | default: | |
1268 | ret = RT_STATUS_FAILURE; | |
1269 | break; | |
1270 | } | |
1271 | ||
1272 | ||
1273 | // | |
1274 | // Check whether readback data is correct | |
1275 | // | |
1276 | if(dwRegRead != WriteData[i]) | |
1277 | { | |
703fdcc3 | 1278 | RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x\n", dwRegRead, WriteData[i]); |
ecdfa446 GKH |
1279 | ret = RT_STATUS_FAILURE; |
1280 | break; | |
1281 | } | |
1282 | } | |
1283 | ||
1284 | return ret; | |
1285 | } | |
1286 | ||
1287 | ||
1288 | /****************************************************************************** | |
1289 | *function: This function initialize BB&RF | |
1290 | * input: net_device dev | |
1291 | * output: none | |
1292 | * return: none | |
1293 | * notice: Initialization value may change all the time, so please make | |
1294 | * sure it has been synced with the newest. | |
1295 | * ***************************************************************************/ | |
d9ffa6c2 | 1296 | static RT_STATUS rtl8192_BB_Config_ParaFile(struct r8192_priv *priv) |
ecdfa446 | 1297 | { |
ecdfa446 | 1298 | RT_STATUS rtStatus = RT_STATUS_SUCCESS; |
d9ffa6c2 | 1299 | |
ecdfa446 GKH |
1300 | u8 bRegValue = 0, eCheckItem = 0; |
1301 | u32 dwRegValue = 0; | |
1302 | /************************************** | |
1303 | //<1>Initialize BaseBand | |
1304 | **************************************/ | |
1305 | ||
1306 | /*--set BB Global Reset--*/ | |
3f9ab1ee MM |
1307 | bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET); |
1308 | write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); | |
ecdfa446 GKH |
1309 | |
1310 | /*---set BB reset Active---*/ | |
3f9ab1ee MM |
1311 | dwRegValue = read_nic_dword(priv, CPU_GEN); |
1312 | write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); | |
ecdfa446 GKH |
1313 | |
1314 | /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ | |
1315 | // TODO: this function should be removed on ASIC , Emily 2007.2.2 | |
1316 | for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) | |
1317 | { | |
d9ffa6c2 | 1318 | rtStatus = rtl8192_phy_checkBBAndRF(priv, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path |
ecdfa446 GKH |
1319 | if(rtStatus != RT_STATUS_SUCCESS) |
1320 | { | |
1321 | RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); | |
1322 | return rtStatus; | |
1323 | } | |
1324 | } | |
1325 | /*---- Set CCK and OFDM Block "OFF"----*/ | |
d9ffa6c2 | 1326 | rtl8192_setBBreg(priv, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); |
ecdfa446 GKH |
1327 | /*----BB Register Initilazation----*/ |
1328 | //==m==>Set PHY REG From Header<==m== | |
d9ffa6c2 | 1329 | rtl8192_phyConfigBB(priv, BaseBand_Config_PHY_REG); |
ecdfa446 GKH |
1330 | |
1331 | /*----Set BB reset de-Active----*/ | |
3f9ab1ee MM |
1332 | dwRegValue = read_nic_dword(priv, CPU_GEN); |
1333 | write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); | |
ecdfa446 GKH |
1334 | |
1335 | /*----BB AGC table Initialization----*/ | |
1336 | //==m==>Set PHY REG From Header<==m== | |
d9ffa6c2 | 1337 | rtl8192_phyConfigBB(priv, BaseBand_Config_AGC_TAB); |
ecdfa446 GKH |
1338 | |
1339 | if (priv->card_8192_version > VERSION_8190_BD) | |
1340 | { | |
1341 | if(priv->rf_type == RF_2T4R) | |
1342 | { | |
1343 | // Antenna gain offset from B/C/D to A | |
1344 | dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 | | |
1345 | priv->AntennaTxPwDiff[1]<<4 | | |
1346 | priv->AntennaTxPwDiff[0]); | |
1347 | } | |
1348 | else | |
1349 | dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R. | |
d9ffa6c2 | 1350 | rtl8192_setBBreg(priv, rFPGA0_TxGainStage, |
ecdfa446 GKH |
1351 | (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); |
1352 | ||
1353 | ||
1354 | //XSTALLCap | |
ecdfa446 | 1355 | dwRegValue = priv->CrystalCap; |
d9ffa6c2 | 1356 | rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); |
ecdfa446 GKH |
1357 | } |
1358 | ||
1359 | // Check if the CCK HighPower is turned ON. | |
1360 | // This is used to calculate PWDB. | |
1361 | // priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); | |
1362 | return rtStatus; | |
1363 | } | |
1364 | /****************************************************************************** | |
1365 | *function: This function initialize BB&RF | |
1366 | * input: net_device dev | |
1367 | * output: none | |
1368 | * return: none | |
1369 | * notice: Initialization value may change all the time, so please make | |
1370 | * sure it has been synced with the newest. | |
1371 | * ***************************************************************************/ | |
d9ffa6c2 | 1372 | RT_STATUS rtl8192_BBConfig(struct r8192_priv *priv) |
ecdfa446 | 1373 | { |
d9ffa6c2 | 1374 | rtl8192_InitBBRFRegDef(priv); |
ecdfa446 GKH |
1375 | //config BB&RF. As hardCode based initialization has not been well |
1376 | //implemented, so use file first.FIXME:should implement it for hardcode? | |
d9ffa6c2 | 1377 | return rtl8192_BB_Config_ParaFile(priv); |
ecdfa446 GKH |
1378 | } |
1379 | ||
1380 | /****************************************************************************** | |
1381 | *function: This function obtains the initialization value of Tx power Level offset | |
1382 | * input: net_device dev | |
1383 | * output: none | |
1384 | * return: none | |
1385 | * ***************************************************************************/ | |
d9ffa6c2 | 1386 | void rtl8192_phy_getTxPower(struct r8192_priv *priv) |
ecdfa446 | 1387 | { |
ecdfa446 | 1388 | priv->MCSTxPowerLevelOriginalOffset[0] = |
3f9ab1ee | 1389 | read_nic_dword(priv, rTxAGC_Rate18_06); |
ecdfa446 | 1390 | priv->MCSTxPowerLevelOriginalOffset[1] = |
3f9ab1ee | 1391 | read_nic_dword(priv, rTxAGC_Rate54_24); |
ecdfa446 | 1392 | priv->MCSTxPowerLevelOriginalOffset[2] = |
3f9ab1ee | 1393 | read_nic_dword(priv, rTxAGC_Mcs03_Mcs00); |
ecdfa446 | 1394 | priv->MCSTxPowerLevelOriginalOffset[3] = |
3f9ab1ee | 1395 | read_nic_dword(priv, rTxAGC_Mcs07_Mcs04); |
ecdfa446 | 1396 | priv->MCSTxPowerLevelOriginalOffset[4] = |
3f9ab1ee | 1397 | read_nic_dword(priv, rTxAGC_Mcs11_Mcs08); |
ecdfa446 | 1398 | priv->MCSTxPowerLevelOriginalOffset[5] = |
3f9ab1ee | 1399 | read_nic_dword(priv, rTxAGC_Mcs15_Mcs12); |
ecdfa446 GKH |
1400 | |
1401 | // read rx initial gain | |
3f9ab1ee MM |
1402 | priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1); |
1403 | priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1); | |
1404 | priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1); | |
1405 | priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1); | |
703fdcc3 | 1406 | RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", |
ecdfa446 GKH |
1407 | priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], |
1408 | priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); | |
1409 | ||
1410 | // read framesync | |
3f9ab1ee MM |
1411 | priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3); |
1412 | priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2); | |
703fdcc3 | 1413 | RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", |
ecdfa446 GKH |
1414 | rOFDM0_RxDetector3, priv->framesync); |
1415 | // read SIFS (save the value read fome MACPHY_REG.txt) | |
3f9ab1ee | 1416 | priv->SifsTime = read_nic_word(priv, SIFS); |
ecdfa446 GKH |
1417 | } |
1418 | ||
1419 | /****************************************************************************** | |
1420 | *function: This function obtains the initialization value of Tx power Level offset | |
1421 | * input: net_device dev | |
1422 | * output: none | |
1423 | * return: none | |
1424 | * ***************************************************************************/ | |
d9ffa6c2 | 1425 | void rtl8192_phy_setTxPower(struct r8192_priv *priv, u8 channel) |
ecdfa446 | 1426 | { |
ecdfa446 GKH |
1427 | u8 powerlevel = 0,powerlevelOFDM24G = 0; |
1428 | char ant_pwr_diff; | |
1429 | u32 u4RegValue; | |
1430 | ||
1431 | if(priv->epromtype == EPROM_93c46) | |
1432 | { | |
1433 | powerlevel = priv->TxPowerLevelCCK[channel-1]; | |
1434 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | |
1435 | } | |
1436 | else if(priv->epromtype == EPROM_93c56) | |
1437 | { | |
1438 | if(priv->rf_type == RF_1T2R) | |
1439 | { | |
1440 | powerlevel = priv->TxPowerLevelCCK_C[channel-1]; | |
1441 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; | |
1442 | } | |
1443 | else if(priv->rf_type == RF_2T4R) | |
1444 | { | |
1445 | // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx | |
1446 | // Power must be calculated by the antenna diff. | |
1447 | // So we have to rewrite Antenna gain offset register here. | |
1448 | powerlevel = priv->TxPowerLevelCCK_A[channel-1]; | |
1449 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; | |
1450 | ||
1451 | ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] | |
1452 | -priv->TxPowerLevelOFDM24G_A[channel-1]; | |
1453 | ant_pwr_diff &= 0xf; | |
ecdfa446 GKH |
1454 | |
1455 | priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care | |
1456 | priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C | |
1457 | priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care | |
1458 | ||
1459 | // Antenna gain offset from B/C/D to A | |
1460 | u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 | | |
1461 | priv->AntennaTxPwDiff[1]<<4 | | |
1462 | priv->AntennaTxPwDiff[0]); | |
1463 | ||
d9ffa6c2 | 1464 | rtl8192_setBBreg(priv, rFPGA0_TxGainStage, |
ecdfa446 GKH |
1465 | (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); |
1466 | } | |
1467 | } | |
1468 | #ifdef TODO | |
1469 | // | |
1470 | // CCX 2 S31, AP control of client transmit power: | |
1471 | // 1. We shall not exceed Cell Power Limit as possible as we can. | |
1472 | // 2. Tolerance is +/- 5dB. | |
1473 | // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit. | |
1474 | // | |
1475 | // TODO: | |
1476 | // 1. 802.11h power contraint | |
1477 | // | |
1478 | // 071011, by rcnjko. | |
1479 | // | |
1480 | if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE && | |
1481 | pMgntInfo->bWithCcxCellPwr && | |
1482 | channel == pMgntInfo->dot11CurrentChannelNumber) | |
1483 | { | |
1484 | u8 CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr); | |
1485 | u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr); | |
1486 | u8 OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr); | |
1487 | ||
1488 | RT_TRACE(COMP_TXAGC, DBG_LOUD, | |
1489 | ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", | |
1490 | pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx)); | |
1491 | RT_TRACE(COMP_TXAGC, DBG_LOUD, | |
1492 | ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", | |
1493 | channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G)); | |
1494 | ||
1495 | // CCK | |
1496 | if(powerlevel > CckCellPwrIdx) | |
1497 | powerlevel = CckCellPwrIdx; | |
1498 | // Legacy OFDM, HT OFDM | |
1499 | if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx) | |
1500 | { | |
1501 | if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0) | |
1502 | { | |
1503 | powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff; | |
1504 | } | |
1505 | else | |
1506 | { | |
1507 | LegacyOfdmCellPwrIdx = 0; | |
1508 | } | |
1509 | } | |
1510 | ||
1511 | RT_TRACE(COMP_TXAGC, DBG_LOUD, | |
1512 | ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", | |
1513 | powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G)); | |
1514 | } | |
1515 | ||
1516 | pHalData->CurrentCckTxPwrIdx = powerlevel; | |
1517 | pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G; | |
1518 | #endif | |
d9ffa6c2 MM |
1519 | PHY_SetRF8256CCKTxPower(priv, powerlevel); //need further implement |
1520 | PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G); | |
ecdfa446 GKH |
1521 | } |
1522 | ||
1523 | /****************************************************************************** | |
1524 | *function: This function check Rf chip to do RF config | |
1525 | * input: net_device dev | |
1526 | * output: none | |
1527 | * return: only 8256 is supported | |
1528 | * ***************************************************************************/ | |
d9ffa6c2 | 1529 | RT_STATUS rtl8192_phy_RFConfig(struct r8192_priv *priv) |
ecdfa446 | 1530 | { |
d9ffa6c2 | 1531 | return PHY_RF8256_Config(priv); |
ecdfa446 GKH |
1532 | } |
1533 | ||
1534 | /****************************************************************************** | |
1535 | *function: This function update Initial gain | |
1536 | * input: net_device dev | |
1537 | * output: none | |
1538 | * return: As Windows has not implemented this, wait for complement | |
1539 | * ***************************************************************************/ | |
d9ffa6c2 | 1540 | void rtl8192_phy_updateInitGain(struct r8192_priv *priv) |
ecdfa446 | 1541 | { |
ecdfa446 GKH |
1542 | } |
1543 | ||
1544 | /****************************************************************************** | |
1545 | *function: This function read RF parameters from general head file, and do RF 3-wire | |
1546 | * input: net_device dev | |
1547 | * output: none | |
1548 | * return: return code show if RF configuration is successful(0:pass, 1:fail) | |
1549 | * Note: Delay may be required for RF configuration | |
1550 | * ***************************************************************************/ | |
d9ffa6c2 MM |
1551 | u8 rtl8192_phy_ConfigRFWithHeaderFile(struct r8192_priv *priv, |
1552 | RF90_RADIO_PATH_E eRFPath) | |
ecdfa446 GKH |
1553 | { |
1554 | ||
1555 | int i; | |
1556 | //u32* pRFArray; | |
1557 | u8 ret = 0; | |
1558 | ||
1559 | switch(eRFPath){ | |
1560 | case RF90_PATH_A: | |
1561 | for(i = 0;i<RadioA_ArrayLength; i=i+2){ | |
1562 | ||
1563 | if(Rtl819XRadioA_Array[i] == 0xfe){ | |
1564 | msleep(100); | |
1565 | continue; | |
1566 | } | |
d9ffa6c2 | 1567 | rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]); |
ecdfa446 GKH |
1568 | //msleep(1); |
1569 | ||
1570 | } | |
1571 | break; | |
1572 | case RF90_PATH_B: | |
1573 | for(i = 0;i<RadioB_ArrayLength; i=i+2){ | |
1574 | ||
1575 | if(Rtl819XRadioB_Array[i] == 0xfe){ | |
1576 | msleep(100); | |
1577 | continue; | |
1578 | } | |
d9ffa6c2 | 1579 | rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]); |
ecdfa446 GKH |
1580 | //msleep(1); |
1581 | ||
1582 | } | |
1583 | break; | |
1584 | case RF90_PATH_C: | |
1585 | for(i = 0;i<RadioC_ArrayLength; i=i+2){ | |
1586 | ||
1587 | if(Rtl819XRadioC_Array[i] == 0xfe){ | |
1588 | msleep(100); | |
1589 | continue; | |
1590 | } | |
d9ffa6c2 | 1591 | rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]); |
ecdfa446 GKH |
1592 | //msleep(1); |
1593 | ||
1594 | } | |
1595 | break; | |
1596 | case RF90_PATH_D: | |
1597 | for(i = 0;i<RadioD_ArrayLength; i=i+2){ | |
1598 | ||
1599 | if(Rtl819XRadioD_Array[i] == 0xfe){ | |
1600 | msleep(100); | |
1601 | continue; | |
1602 | } | |
d9ffa6c2 | 1603 | rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]); |
ecdfa446 GKH |
1604 | //msleep(1); |
1605 | ||
1606 | } | |
1607 | break; | |
1608 | default: | |
1609 | break; | |
1610 | } | |
1611 | ||
859171ca | 1612 | return ret; |
ecdfa446 GKH |
1613 | |
1614 | } | |
1615 | /****************************************************************************** | |
1616 | *function: This function set Tx Power of the channel | |
1617 | * input: struct net_device *dev | |
1618 | * u8 channel | |
1619 | * output: none | |
1620 | * return: none | |
1621 | * Note: | |
1622 | * ***************************************************************************/ | |
d9ffa6c2 | 1623 | static void rtl8192_SetTxPowerLevel(struct r8192_priv *priv, u8 channel) |
ecdfa446 | 1624 | { |
ecdfa446 GKH |
1625 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; |
1626 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | |
1627 | ||
d9ffa6c2 MM |
1628 | PHY_SetRF8256CCKTxPower(priv, powerlevel); |
1629 | PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G); | |
ecdfa446 | 1630 | } |
6f304eb2 | 1631 | |
ecdfa446 GKH |
1632 | /**************************************************************************************** |
1633 | *function: This function set command table variable(struct SwChnlCmd). | |
1634 | * input: SwChnlCmd* CmdTable //table to be set. | |
1635 | * u32 CmdTableIdx //variable index in table to be set | |
1636 | * u32 CmdTableSz //table size. | |
1637 | * SwChnlCmdID CmdID //command ID to set. | |
1638 | * u32 Para1 | |
1639 | * u32 Para2 | |
1640 | * u32 msDelay | |
1641 | * output: | |
1642 | * return: true if finished, false otherwise | |
1643 | * Note: | |
1644 | * ************************************************************************************/ | |
5e1ad18a | 1645 | static u8 rtl8192_phy_SetSwChnlCmdArray( |
ecdfa446 GKH |
1646 | SwChnlCmd* CmdTable, |
1647 | u32 CmdTableIdx, | |
1648 | u32 CmdTableSz, | |
1649 | SwChnlCmdID CmdID, | |
1650 | u32 Para1, | |
1651 | u32 Para2, | |
1652 | u32 msDelay | |
1653 | ) | |
1654 | { | |
1655 | SwChnlCmd* pCmd; | |
1656 | ||
1657 | if(CmdTable == NULL) | |
1658 | { | |
1659 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); | |
1660 | return false; | |
1661 | } | |
1662 | if(CmdTableIdx >= CmdTableSz) | |
1663 | { | |
1664 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", | |
1665 | CmdTableIdx, CmdTableSz); | |
1666 | return false; | |
1667 | } | |
1668 | ||
1669 | pCmd = CmdTable + CmdTableIdx; | |
1670 | pCmd->CmdID = CmdID; | |
1671 | pCmd->Para1 = Para1; | |
1672 | pCmd->Para2 = Para2; | |
1673 | pCmd->msDelay = msDelay; | |
1674 | ||
1675 | return true; | |
1676 | } | |
1677 | /****************************************************************************** | |
1678 | *function: This function set channel step by step | |
1679 | * input: struct net_device *dev | |
1680 | * u8 channel | |
1681 | * u8* stage //3 stages | |
1682 | * u8* step // | |
1683 | * u32* delay //whether need to delay | |
1684 | * output: store new stage, step and delay for next step(combine with function above) | |
1685 | * return: true if finished, false otherwise | |
1686 | * Note: Wait for simpler function to replace it //wb | |
1687 | * ***************************************************************************/ | |
d9ffa6c2 MM |
1688 | static u8 rtl8192_phy_SwChnlStepByStep(struct r8192_priv *priv, u8 channel, |
1689 | u8* stage, u8* step, u32* delay) | |
ecdfa446 | 1690 | { |
ecdfa446 GKH |
1691 | // PCHANNEL_ACCESS_SETTING pChnlAccessSetting; |
1692 | SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; | |
1693 | u32 PreCommonCmdCnt; | |
1694 | SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; | |
1695 | u32 PostCommonCmdCnt; | |
1696 | SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; | |
1697 | u32 RfDependCmdCnt; | |
1698 | SwChnlCmd *CurrentCmd = NULL; | |
1699 | //RF90_RADIO_PATH_E eRFPath; | |
1700 | u8 eRFPath; | |
1701 | // u32 RfRetVal; | |
1702 | // u8 RetryCnt; | |
1703 | ||
1704 | RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel); | |
1705 | // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel)); | |
1706 | ||
1707 | #ifdef ENABLE_DOT11D | |
1708 | if (!IsLegalChannel(priv->ieee80211, channel)) | |
1709 | { | |
1710 | RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); | |
1711 | return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop. | |
1712 | } | |
1713 | #endif | |
1714 | ||
1715 | //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) | |
1716 | //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++) | |
1717 | { | |
1718 | //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | |
1719 | // return false; | |
1720 | // <1> Fill up pre common command. | |
1721 | PreCommonCmdCnt = 0; | |
1722 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, | |
1723 | CmdID_SetTxPowerLevel, 0, 0, 0); | |
1724 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, | |
1725 | CmdID_End, 0, 0, 0); | |
1726 | ||
1727 | // <2> Fill up post common command. | |
1728 | PostCommonCmdCnt = 0; | |
1729 | ||
1730 | rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, | |
1731 | CmdID_End, 0, 0, 0); | |
1732 | ||
1733 | // <3> Fill up RF dependent command. | |
1734 | RfDependCmdCnt = 0; | |
ecdfa446 | 1735 | |
6f304eb2 MM |
1736 | // TEST!! This is not the table for 8256!! |
1737 | if (!(channel >= 1 && channel <= 14)) | |
1738 | { | |
1739 | RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); | |
ecdfa446 | 1740 | return false; |
ecdfa446 | 1741 | } |
6f304eb2 MM |
1742 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
1743 | CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); | |
1744 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, | |
1745 | CmdID_End, 0, 0, 0); | |
ecdfa446 GKH |
1746 | |
1747 | do{ | |
1748 | switch(*stage) | |
1749 | { | |
1750 | case 0: | |
1751 | CurrentCmd=&PreCommonCmd[*step]; | |
1752 | break; | |
1753 | case 1: | |
1754 | CurrentCmd=&RfDependCmd[*step]; | |
1755 | break; | |
1756 | case 2: | |
1757 | CurrentCmd=&PostCommonCmd[*step]; | |
1758 | break; | |
1759 | } | |
1760 | ||
1761 | if(CurrentCmd->CmdID==CmdID_End) | |
1762 | { | |
1763 | if((*stage)==2) | |
1764 | { | |
1765 | return true; | |
1766 | } | |
1767 | else | |
1768 | { | |
1769 | (*stage)++; | |
1770 | (*step)=0; | |
1771 | continue; | |
1772 | } | |
1773 | } | |
1774 | ||
1775 | switch(CurrentCmd->CmdID) | |
1776 | { | |
1777 | case CmdID_SetTxPowerLevel: | |
1778 | if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later! | |
d9ffa6c2 | 1779 | rtl8192_SetTxPowerLevel(priv, channel); |
ecdfa446 GKH |
1780 | break; |
1781 | case CmdID_WritePortUlong: | |
3f9ab1ee | 1782 | write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2); |
ecdfa446 GKH |
1783 | break; |
1784 | case CmdID_WritePortUshort: | |
3f9ab1ee | 1785 | write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2); |
ecdfa446 GKH |
1786 | break; |
1787 | case CmdID_WritePortUchar: | |
3f9ab1ee | 1788 | write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2); |
ecdfa446 GKH |
1789 | break; |
1790 | case CmdID_RF_WriteReg: | |
1791 | for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) | |
d9ffa6c2 | 1792 | rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); |
ecdfa446 GKH |
1793 | break; |
1794 | default: | |
1795 | break; | |
1796 | } | |
1797 | ||
1798 | break; | |
1799 | }while(true); | |
1800 | }/*for(Number of RF paths)*/ | |
1801 | ||
1802 | (*delay)=CurrentCmd->msDelay; | |
1803 | (*step)++; | |
1804 | return false; | |
1805 | } | |
1806 | ||
1807 | /****************************************************************************** | |
1808 | *function: This function does acturally set channel work | |
1809 | * input: struct net_device *dev | |
1810 | * u8 channel | |
1811 | * output: none | |
1812 | * return: noin | |
1813 | * Note: We should not call this function directly | |
1814 | * ***************************************************************************/ | |
d9ffa6c2 | 1815 | static void rtl8192_phy_FinishSwChnlNow(struct r8192_priv *priv, u8 channel) |
ecdfa446 | 1816 | { |
ecdfa446 GKH |
1817 | u32 delay = 0; |
1818 | ||
d9ffa6c2 | 1819 | while (!rtl8192_phy_SwChnlStepByStep(priv, channel, &priv->SwChnlStage, &priv->SwChnlStep, &delay)) |
ecdfa446 GKH |
1820 | { |
1821 | if(delay>0) | |
1822 | msleep(delay);//or mdelay? need further consideration | |
1823 | if(!priv->up) | |
1824 | break; | |
1825 | } | |
1826 | } | |
1827 | /****************************************************************************** | |
1828 | *function: Callback routine of the work item for switch channel. | |
1829 | * input: | |
1830 | * | |
1831 | * output: none | |
1832 | * return: noin | |
1833 | * ***************************************************************************/ | |
d9ffa6c2 | 1834 | void rtl8192_SwChnl_WorkItem(struct r8192_priv *priv) |
ecdfa446 | 1835 | { |
ecdfa446 GKH |
1836 | RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); |
1837 | ||
1838 | RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv); | |
1839 | ||
d9ffa6c2 | 1840 | rtl8192_phy_FinishSwChnlNow(priv, priv->chan); |
ecdfa446 GKH |
1841 | |
1842 | RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); | |
1843 | } | |
1844 | ||
1845 | /****************************************************************************** | |
1846 | *function: This function scheduled actural workitem to set channel | |
1847 | * input: net_device dev | |
1848 | * u8 channel //channel to set | |
1849 | * output: none | |
1850 | * return: return code show if workitem is scheduled(1:pass, 0:fail) | |
1851 | * Note: Delay may be required for RF configuration | |
1852 | * ***************************************************************************/ | |
09145962 | 1853 | u8 rtl8192_phy_SwChnl(struct ieee80211_device *ieee80211, u8 channel) |
ecdfa446 | 1854 | { |
09145962 MM |
1855 | struct r8192_priv *priv = ieee80211_priv(ieee80211->dev); |
1856 | ||
ecdfa446 GKH |
1857 | RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__); |
1858 | if(!priv->up) | |
1859 | return false; | |
1860 | if(priv->SwChnlInProgress) | |
1861 | return false; | |
1862 | ||
1863 | // if(pHalData->SetBWModeInProgress) | |
1864 | // return; | |
1865 | ||
1866 | //-------------------------------------------- | |
1867 | switch(priv->ieee80211->mode) | |
1868 | { | |
1869 | case WIRELESS_MODE_A: | |
1870 | case WIRELESS_MODE_N_5G: | |
1871 | if (channel<=14){ | |
703fdcc3 | 1872 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n"); |
ecdfa446 GKH |
1873 | return false; |
1874 | } | |
1875 | break; | |
1876 | case WIRELESS_MODE_B: | |
1877 | if (channel>14){ | |
703fdcc3 | 1878 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n"); |
ecdfa446 GKH |
1879 | return false; |
1880 | } | |
1881 | break; | |
1882 | case WIRELESS_MODE_G: | |
1883 | case WIRELESS_MODE_N_24G: | |
1884 | if (channel>14){ | |
703fdcc3 | 1885 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n"); |
ecdfa446 GKH |
1886 | return false; |
1887 | } | |
1888 | break; | |
1889 | } | |
1890 | //-------------------------------------------- | |
1891 | ||
1892 | priv->SwChnlInProgress = true; | |
1893 | if(channel == 0) | |
1894 | channel = 1; | |
1895 | ||
1896 | priv->chan=channel; | |
1897 | ||
1898 | priv->SwChnlStage=0; | |
1899 | priv->SwChnlStep=0; | |
d9ffa6c2 MM |
1900 | if (priv->up) |
1901 | rtl8192_SwChnl_WorkItem(priv); | |
1902 | ||
ecdfa446 GKH |
1903 | priv->SwChnlInProgress = false; |
1904 | return true; | |
1905 | } | |
1906 | ||
d9ffa6c2 | 1907 | static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct r8192_priv *priv) |
ecdfa446 | 1908 | { |
ecdfa446 GKH |
1909 | switch(priv->CurrentChannelBW) |
1910 | { | |
1911 | /* 20 MHz channel*/ | |
1912 | case HT_CHANNEL_WIDTH_20: | |
1913 | //added by vivi, cck,tx power track, 20080703 | |
1914 | priv->CCKPresentAttentuation = | |
1915 | priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference; | |
1916 | ||
1917 | if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) | |
1918 | priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; | |
1919 | if(priv->CCKPresentAttentuation < 0) | |
1920 | priv->CCKPresentAttentuation = 0; | |
1921 | ||
1922 | RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); | |
1923 | ||
1924 | if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14) | |
1925 | { | |
1926 | priv->bcck_in_ch14 = TRUE; | |
7088dfb6 | 1927 | dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); |
ecdfa446 GKH |
1928 | } |
1929 | else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) | |
1930 | { | |
1931 | priv->bcck_in_ch14 = FALSE; | |
7088dfb6 | 1932 | dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); |
ecdfa446 GKH |
1933 | } |
1934 | else | |
7088dfb6 | 1935 | dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); |
ecdfa446 GKH |
1936 | break; |
1937 | ||
1938 | /* 40 MHz channel*/ | |
1939 | case HT_CHANNEL_WIDTH_20_40: | |
1940 | //added by vivi, cck,tx power track, 20080703 | |
1941 | priv->CCKPresentAttentuation = | |
1942 | priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference; | |
1943 | ||
1944 | RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); | |
1945 | if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) | |
1946 | priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; | |
1947 | if(priv->CCKPresentAttentuation < 0) | |
1948 | priv->CCKPresentAttentuation = 0; | |
1949 | ||
1950 | if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) | |
1951 | { | |
1952 | priv->bcck_in_ch14 = TRUE; | |
7088dfb6 | 1953 | dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); |
ecdfa446 GKH |
1954 | } |
1955 | else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) | |
1956 | { | |
1957 | priv->bcck_in_ch14 = FALSE; | |
7088dfb6 | 1958 | dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); |
ecdfa446 GKH |
1959 | } |
1960 | else | |
7088dfb6 | 1961 | dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); |
ecdfa446 GKH |
1962 | break; |
1963 | } | |
1964 | } | |
1965 | ||
d9ffa6c2 | 1966 | static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct r8192_priv *priv) |
ecdfa446 | 1967 | { |
ecdfa446 GKH |
1968 | if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) |
1969 | priv->bcck_in_ch14 = TRUE; | |
1970 | else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) | |
1971 | priv->bcck_in_ch14 = FALSE; | |
1972 | ||
1973 | //write to default index and tx power track will be done in dm. | |
1974 | switch(priv->CurrentChannelBW) | |
1975 | { | |
1976 | /* 20 MHz channel*/ | |
1977 | case HT_CHANNEL_WIDTH_20: | |
1978 | if(priv->Record_CCK_20Mindex == 0) | |
1979 | priv->Record_CCK_20Mindex = 6; //set default value. | |
1980 | priv->CCK_index = priv->Record_CCK_20Mindex;//6; | |
1981 | RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index); | |
1982 | break; | |
1983 | ||
1984 | /* 40 MHz channel*/ | |
1985 | case HT_CHANNEL_WIDTH_20_40: | |
1986 | priv->CCK_index = priv->Record_CCK_40Mindex;//0; | |
1987 | RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index); | |
1988 | break; | |
1989 | } | |
7088dfb6 | 1990 | dm_cck_txpower_adjust(priv, priv->bcck_in_ch14); |
ecdfa446 | 1991 | } |
ecdfa446 | 1992 | |
d9ffa6c2 | 1993 | static void CCK_Tx_Power_Track_BW_Switch(struct r8192_priv *priv) |
ecdfa446 | 1994 | { |
ecdfa446 | 1995 | |
ecdfa446 GKH |
1996 | //if(pHalData->bDcut == TRUE) |
1997 | if(priv->IC_Cut >= IC_VersionCut_D) | |
d9ffa6c2 | 1998 | CCK_Tx_Power_Track_BW_Switch_TSSI(priv); |
ecdfa446 | 1999 | else |
d9ffa6c2 | 2000 | CCK_Tx_Power_Track_BW_Switch_ThermalMeter(priv); |
ecdfa446 GKH |
2001 | } |
2002 | ||
2003 | ||
2004 | // | |
2005 | /****************************************************************************** | |
2006 | *function: Callback routine of the work item for set bandwidth mode. | |
2007 | * input: struct net_device *dev | |
2008 | * HT_CHANNEL_WIDTH Bandwidth //20M or 40M | |
2009 | * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care | |
2010 | * output: none | |
2011 | * return: none | |
2012 | * Note: I doubt whether SetBWModeInProgress flag is necessary as we can | |
2013 | * test whether current work in the queue or not.//do I? | |
2014 | * ***************************************************************************/ | |
d9ffa6c2 | 2015 | void rtl8192_SetBWModeWorkItem(struct r8192_priv *priv) |
ecdfa446 | 2016 | { |
ecdfa446 GKH |
2017 | u8 regBwOpMode; |
2018 | ||
207b58fb | 2019 | RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", |
ecdfa446 GKH |
2020 | priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") |
2021 | ||
2022 | ||
ecdfa446 GKH |
2023 | if(!priv->up) |
2024 | { | |
2025 | priv->SetBWModeInProgress= false; | |
2026 | return; | |
2027 | } | |
2028 | //<1>Set MAC register | |
3f9ab1ee | 2029 | regBwOpMode = read_nic_byte(priv, BW_OPMODE); |
ecdfa446 GKH |
2030 | |
2031 | switch(priv->CurrentChannelBW) | |
2032 | { | |
2033 | case HT_CHANNEL_WIDTH_20: | |
2034 | regBwOpMode |= BW_OPMODE_20MHZ; | |
25985edc | 2035 | // 2007/02/07 Mark by Emily because we have not verify whether this register works |
3f9ab1ee | 2036 | write_nic_byte(priv, BW_OPMODE, regBwOpMode); |
ecdfa446 GKH |
2037 | break; |
2038 | ||
2039 | case HT_CHANNEL_WIDTH_20_40: | |
2040 | regBwOpMode &= ~BW_OPMODE_20MHZ; | |
25985edc | 2041 | // 2007/02/07 Mark by Emily because we have not verify whether this register works |
3f9ab1ee | 2042 | write_nic_byte(priv, BW_OPMODE, regBwOpMode); |
ecdfa446 GKH |
2043 | break; |
2044 | ||
2045 | default: | |
2046 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); | |
2047 | break; | |
2048 | } | |
2049 | ||
2050 | //<2>Set PHY related register | |
2051 | switch(priv->CurrentChannelBW) | |
2052 | { | |
2053 | case HT_CHANNEL_WIDTH_20: | |
2054 | // Add by Vivi 20071119 | |
d9ffa6c2 MM |
2055 | rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x0); |
2056 | rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x0); | |
ecdfa446 GKH |
2057 | // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); |
2058 | ||
2059 | // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 | |
2060 | // write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); | |
2061 | // write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); | |
2062 | // write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); | |
2063 | if(!priv->btxpower_tracking) | |
2064 | { | |
3f9ab1ee MM |
2065 | write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000); |
2066 | write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317); | |
2067 | write_nic_dword(priv, rCCK0_DebugPort, 0x00000204); | |
ecdfa446 GKH |
2068 | } |
2069 | else | |
d9ffa6c2 | 2070 | CCK_Tx_Power_Track_BW_Switch(priv); |
ecdfa446 | 2071 | |
d9ffa6c2 | 2072 | rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 1); |
ecdfa446 GKH |
2073 | break; |
2074 | case HT_CHANNEL_WIDTH_20_40: | |
2075 | // Add by Vivi 20071119 | |
d9ffa6c2 MM |
2076 | rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x1); |
2077 | rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x1); | |
ecdfa446 GKH |
2078 | //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); |
2079 | //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); | |
2080 | //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); | |
2081 | ||
2082 | // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 | |
2083 | //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); | |
2084 | //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); | |
2085 | //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); | |
2086 | if(!priv->btxpower_tracking) | |
2087 | { | |
3f9ab1ee MM |
2088 | write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000); |
2089 | write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e); | |
2090 | write_nic_dword(priv, rCCK0_DebugPort, 0x00000409); | |
ecdfa446 GKH |
2091 | } |
2092 | else | |
d9ffa6c2 | 2093 | CCK_Tx_Power_Track_BW_Switch(priv); |
ecdfa446 GKH |
2094 | |
2095 | // Set Control channel to upper or lower. These settings are required only for 40MHz | |
d9ffa6c2 MM |
2096 | rtl8192_setBBreg(priv, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); |
2097 | rtl8192_setBBreg(priv, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); | |
ecdfa446 GKH |
2098 | |
2099 | ||
d9ffa6c2 | 2100 | rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 0); |
ecdfa446 GKH |
2101 | break; |
2102 | default: | |
2103 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); | |
2104 | break; | |
2105 | ||
2106 | } | |
2107 | //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 | |
2108 | ||
ecdfa446 | 2109 | //<3>Set RF related register |
d9ffa6c2 | 2110 | PHY_SetRF8256Bandwidth(priv, priv->CurrentChannelBW); |
4803ef77 | 2111 | |
ecdfa446 GKH |
2112 | atomic_dec(&(priv->ieee80211->atm_swbw)); |
2113 | priv->SetBWModeInProgress= false; | |
2114 | ||
703fdcc3 | 2115 | RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()\n"); |
ecdfa446 GKH |
2116 | } |
2117 | ||
2118 | /****************************************************************************** | |
25985edc | 2119 | *function: This function schedules bandwidth switch work. |
ecdfa446 GKH |
2120 | * input: struct net_device *dev |
2121 | * HT_CHANNEL_WIDTH Bandwidth //20M or 40M | |
2122 | * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care | |
2123 | * output: none | |
2124 | * return: none | |
2125 | * Note: I doubt whether SetBWModeInProgress flag is necessary as we can | |
2126 | * test whether current work in the queue or not.//do I? | |
2127 | * ***************************************************************************/ | |
1e04ca7a | 2128 | void rtl8192_SetBWMode(struct ieee80211_device *ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) |
ecdfa446 | 2129 | { |
1e04ca7a | 2130 | struct r8192_priv *priv = ieee80211_priv(ieee->dev); |
ecdfa446 GKH |
2131 | |
2132 | ||
2133 | if(priv->SetBWModeInProgress) | |
2134 | return; | |
2135 | ||
2136 | atomic_inc(&(priv->ieee80211->atm_swbw)); | |
2137 | priv->SetBWModeInProgress= true; | |
2138 | ||
2139 | priv->CurrentChannelBW = Bandwidth; | |
2140 | ||
2141 | if(Offset==HT_EXTCHNL_OFFSET_LOWER) | |
2142 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; | |
2143 | else if(Offset==HT_EXTCHNL_OFFSET_UPPER) | |
2144 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; | |
2145 | else | |
2146 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; | |
2147 | ||
2148 | //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem)); | |
2149 | // schedule_work(&(priv->SetBWModeWorkItem)); | |
d9ffa6c2 | 2150 | rtl8192_SetBWModeWorkItem(priv); |
ecdfa446 GKH |
2151 | |
2152 | } | |
2153 | ||
2154 | ||
1e04ca7a | 2155 | void InitialGain819xPci(struct ieee80211_device *ieee, u8 Operation) |
ecdfa446 GKH |
2156 | { |
2157 | #define SCAN_RX_INITIAL_GAIN 0x17 | |
2158 | #define POWER_DETECTION_TH 0x08 | |
1e04ca7a | 2159 | struct r8192_priv *priv = ieee80211_priv(ieee->dev); |
ecdfa446 GKH |
2160 | u32 BitMask; |
2161 | u8 initial_gain; | |
2162 | ||
2163 | if(priv->up) | |
2164 | { | |
2165 | switch(Operation) | |
2166 | { | |
2167 | case IG_Backup: | |
2168 | RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); | |
2169 | initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];// | |
2170 | BitMask = bMaskByte0; | |
2171 | if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) | |
d9ffa6c2 MM |
2172 | rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // FW DIG OFF |
2173 | priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XAAGCCore1, BitMask); | |
2174 | priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XBAGCCore1, BitMask); | |
2175 | priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XCAGCCore1, BitMask); | |
2176 | priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XDAGCCore1, BitMask); | |
ecdfa446 | 2177 | BitMask = bMaskByte2; |
d9ffa6c2 | 2178 | priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(priv, rCCK0_CCA, BitMask); |
ecdfa446 GKH |
2179 | |
2180 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); | |
2181 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); | |
2182 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); | |
2183 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); | |
2184 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); | |
2185 | ||
2186 | RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); | |
3f9ab1ee MM |
2187 | write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain); |
2188 | write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain); | |
2189 | write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain); | |
2190 | write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain); | |
ecdfa446 | 2191 | RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); |
3f9ab1ee | 2192 | write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH); |
ecdfa446 GKH |
2193 | break; |
2194 | case IG_Restore: | |
2195 | RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); | |
2196 | BitMask = 0x7f; //Bit0~ Bit6 | |
2197 | if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) | |
d9ffa6c2 | 2198 | rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // FW DIG OFF |
ecdfa446 | 2199 | |
d9ffa6c2 MM |
2200 | rtl8192_setBBreg(priv, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); |
2201 | rtl8192_setBBreg(priv, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); | |
2202 | rtl8192_setBBreg(priv, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); | |
2203 | rtl8192_setBBreg(priv, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); | |
ecdfa446 | 2204 | BitMask = bMaskByte2; |
d9ffa6c2 | 2205 | rtl8192_setBBreg(priv, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); |
ecdfa446 GKH |
2206 | |
2207 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); | |
2208 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); | |
2209 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); | |
2210 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); | |
2211 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); | |
2212 | ||
d9ffa6c2 | 2213 | rtl8192_phy_setTxPower(priv, priv->ieee80211->current_network.channel); |
ecdfa446 GKH |
2214 | |
2215 | ||
2216 | if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) | |
d9ffa6c2 | 2217 | rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x1); // FW DIG ON |
ecdfa446 GKH |
2218 | break; |
2219 | default: | |
703fdcc3 | 2220 | RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); |
ecdfa446 GKH |
2221 | break; |
2222 | } | |
2223 | } | |
2224 | } | |
2225 |