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staging: rtl8192e: Remove pointless hw_sleep_wq
[mirror_ubuntu-jammy-kernel.git] / drivers / staging / rtl8192e / r819xE_phy.c
CommitLineData
ecdfa446
GKH		 1#include "r8192E.h"
2#include "r8192E_hw.h"
3#include "r819xE_phyreg.h"
4#include "r8190_rtl8256.h"
5#include "r819xE_phy.h"
6#include "r8192E_dm.h"
7#ifdef ENABLE_DOT11D
65a43784 8#include "ieee80211/dot11d.h"
ecdfa446 9#endif
ab2161a0 10static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
ecdfa446
GKH		 11 0,
12 0x085c, //2412 1
13 0x08dc, //2417 2
14 0x095c, //2422 3
15 0x09dc, //2427 4
16 0x0a5c, //2432 5
17 0x0adc, //2437 6
18 0x0b5c, //2442 7
19 0x0bdc, //2447 8
20 0x0c5c, //2452 9
21 0x0cdc, //2457 10
22 0x0d5c, //2462 11
23 0x0ddc, //2467 12
24 0x0e5c, //2472 13
25 0x0f72, //2484
26};
4803ef77 27
5e1ad18a 28static u32 Rtl8192PciEMACPHY_Array[] = {
ecdfa446
GKH		 290x03c,0xffff0000,0x00000f0f,
300x340,0xffffffff,0x161a1a1a,
310x344,0xffffffff,0x12121416,
320x348,0x0000ffff,0x00001818,
330x12c,0xffffffff,0x04000802,
340x318,0x00000fff,0x00000100,
35};
5e1ad18a 36static u32 Rtl8192PciEMACPHY_Array_PG[] = {
ecdfa446
GKH		 370x03c,0xffff0000,0x00000f0f,
380xe00,0xffffffff,0x06090909,
390xe04,0xffffffff,0x00030306,
400xe08,0x0000ff00,0x00000000,
410xe10,0xffffffff,0x0a0c0d0f,
420xe14,0xffffffff,0x06070809,
430xe18,0xffffffff,0x0a0c0d0f,
440xe1c,0xffffffff,0x06070809,
450x12c,0xffffffff,0x04000802,
460x318,0x00000fff,0x00000800,
47};
5e1ad18a 48static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = {
ecdfa446
GKH		 490xc78,0x7d000001,
500xc78,0x7d010001,
510xc78,0x7d020001,
520xc78,0x7d030001,
530xc78,0x7d040001,
540xc78,0x7d050001,
550xc78,0x7c060001,
560xc78,0x7b070001,
570xc78,0x7a080001,
580xc78,0x79090001,
590xc78,0x780a0001,
600xc78,0x770b0001,
610xc78,0x760c0001,
620xc78,0x750d0001,
630xc78,0x740e0001,
640xc78,0x730f0001,
650xc78,0x72100001,
660xc78,0x71110001,
670xc78,0x70120001,
680xc78,0x6f130001,
690xc78,0x6e140001,
700xc78,0x6d150001,
710xc78,0x6c160001,
720xc78,0x6b170001,
730xc78,0x6a180001,
740xc78,0x69190001,
750xc78,0x681a0001,
760xc78,0x671b0001,
770xc78,0x661c0001,
780xc78,0x651d0001,
790xc78,0x641e0001,
800xc78,0x491f0001,
810xc78,0x48200001,
820xc78,0x47210001,
830xc78,0x46220001,
840xc78,0x45230001,
850xc78,0x44240001,
860xc78,0x43250001,
870xc78,0x28260001,
880xc78,0x27270001,
890xc78,0x26280001,
900xc78,0x25290001,
910xc78,0x242a0001,
920xc78,0x232b0001,
930xc78,0x222c0001,
940xc78,0x212d0001,
950xc78,0x202e0001,
960xc78,0x0a2f0001,
970xc78,0x08300001,
980xc78,0x06310001,
990xc78,0x05320001,
1000xc78,0x04330001,
1010xc78,0x03340001,
1020xc78,0x02350001,
1030xc78,0x01360001,
1040xc78,0x00370001,
1050xc78,0x00380001,
1060xc78,0x00390001,
1070xc78,0x003a0001,
1080xc78,0x003b0001,
1090xc78,0x003c0001,
1100xc78,0x003d0001,
1110xc78,0x003e0001,
1120xc78,0x003f0001,
1130xc78,0x7d400001,
1140xc78,0x7d410001,
1150xc78,0x7d420001,
1160xc78,0x7d430001,
1170xc78,0x7d440001,
1180xc78,0x7d450001,
1190xc78,0x7c460001,
1200xc78,0x7b470001,
1210xc78,0x7a480001,
1220xc78,0x79490001,
1230xc78,0x784a0001,
1240xc78,0x774b0001,
1250xc78,0x764c0001,
1260xc78,0x754d0001,
1270xc78,0x744e0001,
1280xc78,0x734f0001,
1290xc78,0x72500001,
1300xc78,0x71510001,
1310xc78,0x70520001,
1320xc78,0x6f530001,
1330xc78,0x6e540001,
1340xc78,0x6d550001,
1350xc78,0x6c560001,
1360xc78,0x6b570001,
1370xc78,0x6a580001,
1380xc78,0x69590001,
1390xc78,0x685a0001,
1400xc78,0x675b0001,
1410xc78,0x665c0001,
1420xc78,0x655d0001,
1430xc78,0x645e0001,
1440xc78,0x495f0001,
1450xc78,0x48600001,
1460xc78,0x47610001,
1470xc78,0x46620001,
1480xc78,0x45630001,
1490xc78,0x44640001,
1500xc78,0x43650001,
1510xc78,0x28660001,
1520xc78,0x27670001,
1530xc78,0x26680001,
1540xc78,0x25690001,
1550xc78,0x246a0001,
1560xc78,0x236b0001,
1570xc78,0x226c0001,
1580xc78,0x216d0001,
1590xc78,0x206e0001,
1600xc78,0x0a6f0001,
1610xc78,0x08700001,
1620xc78,0x06710001,
1630xc78,0x05720001,
1640xc78,0x04730001,
1650xc78,0x03740001,
1660xc78,0x02750001,
1670xc78,0x01760001,
1680xc78,0x00770001,
1690xc78,0x00780001,
1700xc78,0x00790001,
1710xc78,0x007a0001,
1720xc78,0x007b0001,
1730xc78,0x007c0001,
1740xc78,0x007d0001,
1750xc78,0x007e0001,
1760xc78,0x007f0001,
1770xc78,0x2e00001e,
1780xc78,0x2e01001e,
1790xc78,0x2e02001e,
1800xc78,0x2e03001e,
1810xc78,0x2e04001e,
1820xc78,0x2e05001e,
1830xc78,0x3006001e,
1840xc78,0x3407001e,
1850xc78,0x3908001e,
1860xc78,0x3c09001e,
1870xc78,0x3f0a001e,
1880xc78,0x420b001e,
1890xc78,0x440c001e,
1900xc78,0x450d001e,
1910xc78,0x460e001e,
1920xc78,0x460f001e,
1930xc78,0x4710001e,
1940xc78,0x4811001e,
1950xc78,0x4912001e,
1960xc78,0x4a13001e,
1970xc78,0x4b14001e,
1980xc78,0x4b15001e,
1990xc78,0x4c16001e,
2000xc78,0x4d17001e,
2010xc78,0x4e18001e,
2020xc78,0x4f19001e,
2030xc78,0x4f1a001e,
2040xc78,0x501b001e,
2050xc78,0x511c001e,
2060xc78,0x521d001e,
2070xc78,0x521e001e,
2080xc78,0x531f001e,
2090xc78,0x5320001e,
2100xc78,0x5421001e,
2110xc78,0x5522001e,
2120xc78,0x5523001e,
2130xc78,0x5624001e,
2140xc78,0x5725001e,
2150xc78,0x5726001e,
2160xc78,0x5827001e,
2170xc78,0x5828001e,
2180xc78,0x5929001e,
2190xc78,0x592a001e,
2200xc78,0x5a2b001e,
2210xc78,0x5b2c001e,
2220xc78,0x5c2d001e,
2230xc78,0x5c2e001e,
2240xc78,0x5d2f001e,
2250xc78,0x5e30001e,
2260xc78,0x5f31001e,
2270xc78,0x6032001e,
2280xc78,0x6033001e,
2290xc78,0x6134001e,
2300xc78,0x6235001e,
2310xc78,0x6336001e,
2320xc78,0x6437001e,
2330xc78,0x6438001e,
2340xc78,0x6539001e,
2350xc78,0x663a001e,
2360xc78,0x673b001e,
2370xc78,0x673c001e,
2380xc78,0x683d001e,
2390xc78,0x693e001e,
2400xc78,0x6a3f001e,
241};
5e1ad18a 242static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = {
ecdfa446 2430x0, };
5e1ad18a 244static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
ecdfa446
GKH		 2450x800,0x00000000,
2460x804,0x00000001,
2470x808,0x0000fc00,
2480x80c,0x0000001c,
2490x810,0x801010aa,
2500x814,0x008514d0,
2510x818,0x00000040,
2520x81c,0x00000000,
2530x820,0x00000004,
2540x824,0x00690000,
2550x828,0x00000004,
2560x82c,0x00e90000,
2570x830,0x00000004,
2580x834,0x00690000,
2590x838,0x00000004,
2600x83c,0x00e90000,
2610x840,0x00000000,
2620x844,0x00000000,
2630x848,0x00000000,
2640x84c,0x00000000,
2650x850,0x00000000,
2660x854,0x00000000,
2670x858,0x65a965a9,
2680x85c,0x65a965a9,
2690x860,0x001f0010,
2700x864,0x007f0010,
2710x868,0x001f0010,
2720x86c,0x007f0010,
2730x870,0x0f100f70,
2740x874,0x0f100f70,
2750x878,0x00000000,
2760x87c,0x00000000,
2770x880,0x6870e36c,
2780x884,0xe3573600,
2790x888,0x4260c340,
2800x88c,0x0000ff00,
2810x890,0x00000000,
2820x894,0xfffffffe,
2830x898,0x4c42382f,
2840x89c,0x00656056,
2850x8b0,0x00000000,
2860x8e0,0x00000000,
2870x8e4,0x00000000,
2880x900,0x00000000,
2890x904,0x00000023,
2900x908,0x00000000,
2910x90c,0x31121311,
2920xa00,0x00d0c7d8,
2930xa04,0x811f0008,
2940xa08,0x80cd8300,
2950xa0c,0x2e62740f,
2960xa10,0x95009b78,
2970xa14,0x11145008,
2980xa18,0x00881117,
2990xa1c,0x89140fa0,
3000xa20,0x1a1b0000,
3010xa24,0x090e1317,
3020xa28,0x00000204,
3030xa2c,0x00000000,
3040xc00,0x00000040,
3050xc04,0x00005433,
3060xc08,0x000000e4,
3070xc0c,0x6c6c6c6c,
3080xc10,0x08800000,
3090xc14,0x40000100,
3100xc18,0x08000000,
3110xc1c,0x40000100,
3120xc20,0x08000000,
3130xc24,0x40000100,
3140xc28,0x08000000,
3150xc2c,0x40000100,
3160xc30,0x6de9ac44,
3170xc34,0x465c52cd,
3180xc38,0x497f5994,
3190xc3c,0x0a969764,
3200xc40,0x1f7c403f,
3210xc44,0x000100b7,
3220xc48,0xec020000,
3230xc4c,0x00000300,
3240xc50,0x69543420,
3250xc54,0x433c0094,
3260xc58,0x69543420,
3270xc5c,0x433c0094,
3280xc60,0x69543420,
3290xc64,0x433c0094,
3300xc68,0x69543420,
3310xc6c,0x433c0094,
3320xc70,0x2c7f000d,
3330xc74,0x0186175b,
3340xc78,0x0000001f,
3350xc7c,0x00b91612,
3360xc80,0x40000100,
3370xc84,0x20000000,
3380xc88,0x40000100,
3390xc8c,0x20200000,
3400xc90,0x40000100,
3410xc94,0x00000000,
3420xc98,0x40000100,
3430xc9c,0x00000000,
3440xca0,0x00492492,
3450xca4,0x00000000,
3460xca8,0x00000000,
3470xcac,0x00000000,
3480xcb0,0x00000000,
3490xcb4,0x00000000,
3500xcb8,0x00000000,
3510xcbc,0x00492492,
3520xcc0,0x00000000,
3530xcc4,0x00000000,
3540xcc8,0x00000000,
3550xccc,0x00000000,
3560xcd0,0x00000000,
3570xcd4,0x00000000,
3580xcd8,0x64b22427,
3590xcdc,0x00766932,
3600xce0,0x00222222,
3610xd00,0x00000750,
3620xd04,0x00000403,
3630xd08,0x0000907f,
3640xd0c,0x00000001,
3650xd10,0xa0633333,
3660xd14,0x33333c63,
3670xd18,0x6a8f5b6b,
3680xd1c,0x00000000,
3690xd20,0x00000000,
3700xd24,0x00000000,
3710xd28,0x00000000,
3720xd2c,0xcc979975,
3730xd30,0x00000000,
3740xd34,0x00000000,
3750xd38,0x00000000,
3760xd3c,0x00027293,
3770xd40,0x00000000,
3780xd44,0x00000000,
3790xd48,0x00000000,
3800xd4c,0x00000000,
3810xd50,0x6437140a,
3820xd54,0x024dbd02,
3830xd58,0x00000000,
3840xd5c,0x04032064,
3850xe00,0x161a1a1a,
3860xe04,0x12121416,
3870xe08,0x00001800,
3880xe0c,0x00000000,
3890xe10,0x161a1a1a,
3900xe14,0x12121416,
3910xe18,0x161a1a1a,
3920xe1c,0x12121416,
393};
5e1ad18a 394static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = {
ecdfa446
GKH		 3950x019,0x00000003,
3960x000,0x000000bf,
3970x001,0x00000ee0,
3980x002,0x0000004c,
3990x003,0x000007f1,
4000x004,0x00000975,
4010x005,0x00000c58,
4020x006,0x00000ae6,
4030x007,0x000000ca,
4040x008,0x00000e1c,
4050x009,0x000007f0,
4060x00a,0x000009d0,
4070x00b,0x000001ba,
4080x00c,0x00000240,
4090x00e,0x00000020,
4100x00f,0x00000990,
4110x012,0x00000806,
4120x014,0x000005ab,
4130x015,0x00000f80,
4140x016,0x00000020,
4150x017,0x00000597,
4160x018,0x0000050a,
4170x01a,0x00000f80,
4180x01b,0x00000f5e,
4190x01c,0x00000008,
4200x01d,0x00000607,
4210x01e,0x000006cc,
4220x01f,0x00000000,
4230x020,0x000001a5,
4240x01f,0x00000001,
4250x020,0x00000165,
4260x01f,0x00000002,
4270x020,0x000000c6,
4280x01f,0x00000003,
4290x020,0x00000086,
4300x01f,0x00000004,
4310x020,0x00000046,
4320x01f,0x00000005,
4330x020,0x000001e6,
4340x01f,0x00000006,
4350x020,0x000001a6,
4360x01f,0x00000007,
4370x020,0x00000166,
4380x01f,0x00000008,
4390x020,0x000000c7,
4400x01f,0x00000009,
4410x020,0x00000087,
4420x01f,0x0000000a,
4430x020,0x000000f7,
4440x01f,0x0000000b,
4450x020,0x000000d7,
4460x01f,0x0000000c,
4470x020,0x000000b7,
4480x01f,0x0000000d,
4490x020,0x00000097,
4500x01f,0x0000000e,
4510x020,0x00000077,
4520x01f,0x0000000f,
4530x020,0x00000057,
4540x01f,0x00000010,
4550x020,0x00000037,
4560x01f,0x00000011,
4570x020,0x000000fb,
4580x01f,0x00000012,
4590x020,0x000000db,
4600x01f,0x00000013,
4610x020,0x000000bb,
4620x01f,0x00000014,
4630x020,0x000000ff,
4640x01f,0x00000015,
4650x020,0x000000e3,
4660x01f,0x00000016,
4670x020,0x000000c3,
4680x01f,0x00000017,
4690x020,0x000000a3,
4700x01f,0x00000018,
4710x020,0x00000083,
4720x01f,0x00000019,
4730x020,0x00000063,
4740x01f,0x0000001a,
4750x020,0x00000043,
4760x01f,0x0000001b,
4770x020,0x00000023,
4780x01f,0x0000001c,
4790x020,0x00000003,
4800x01f,0x0000001d,
4810x020,0x000001e3,
4820x01f,0x0000001e,
4830x020,0x000001c3,
4840x01f,0x0000001f,
4850x020,0x000001a3,
4860x01f,0x00000020,
4870x020,0x00000183,
4880x01f,0x00000021,
4890x020,0x00000163,
4900x01f,0x00000022,
4910x020,0x00000143,
4920x01f,0x00000023,
4930x020,0x00000123,
4940x01f,0x00000024,
4950x020,0x00000103,
4960x023,0x00000203,
4970x024,0x00000100,
4980x00b,0x000001ba,
4990x02c,0x000003d7,
5000x02d,0x00000ff0,
5010x000,0x00000037,
5020x004,0x00000160,
5030x007,0x00000080,
5040x002,0x0000088d,
5050x0fe,0x00000000,
5060x0fe,0x00000000,
5070x016,0x00000200,
5080x016,0x00000380,
5090x016,0x00000020,
5100x016,0x000001a0,
5110x000,0x000000bf,
5120x00d,0x0000001f,
5130x00d,0x00000c9f,
5140x002,0x0000004d,
5150x000,0x00000cbf,
5160x004,0x00000975,
5170x007,0x00000700,
518};
5e1ad18a 519static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = {
ecdfa446
GKH		 5200x019,0x00000003,
5210x000,0x000000bf,
5220x001,0x000006e0,
5230x002,0x0000004c,
5240x003,0x000007f1,
5250x004,0x00000975,
5260x005,0x00000c58,
5270x006,0x00000ae6,
5280x007,0x000000ca,
5290x008,0x00000e1c,
5300x000,0x000000b7,
5310x00a,0x00000850,
5320x000,0x000000bf,
5330x00b,0x000001ba,
5340x00c,0x00000240,
5350x00e,0x00000020,
5360x015,0x00000f80,
5370x016,0x00000020,
5380x017,0x00000597,
5390x018,0x0000050a,
5400x01a,0x00000e00,
5410x01b,0x00000f5e,
5420x01d,0x00000607,
5430x01e,0x000006cc,
5440x00b,0x000001ba,
5450x023,0x00000203,
5460x024,0x00000100,
5470x000,0x00000037,
5480x004,0x00000160,
5490x016,0x00000200,
5500x016,0x00000380,
5510x016,0x00000020,
5520x016,0x000001a0,
5530x00d,0x00000ccc,
5540x000,0x000000bf,
5550x002,0x0000004d,
5560x000,0x00000cbf,
5570x004,0x00000975,
5580x007,0x00000700,
559};
5e1ad18a 560static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
ecdfa446 5610x0, };
5e1ad18a 562static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
ecdfa446 5630x0, };
ecdfa446
GKH		 564
565/*************************Define local function prototype**********************/
566
567static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
568static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data);
569/*************************Define local function prototype**********************/
570/******************************************************************************
571 *function: This function read BB parameters from Header file we gen,
572 * and do register read/write
573 * input: u32 dwBitMask //taget bit pos in the addr to be modified
574 * output: none
575 * return: u32 return the shift bit bit position of the mask
576 * ****************************************************************************/
5e1ad18a 577static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
ecdfa446
GKH		 578{
579 u32 i;
580 for (i=0; i<=31; i++)
581 {
582 if (((dwBitMask>>i)&0x1) == 1)
583 break;
584 }
585 return i;
586}
587/******************************************************************************
588 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
589 * input: none
590 * output: none
591 * return: 0(illegal, false), 1(legal,true)
592 * ***************************************************************************/
593u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
594{
595 u8 ret = 1;
596 struct r8192_priv *priv = ieee80211_priv(dev);
4803ef77 597
ecdfa446
GKH		 598 if (priv->rf_type == RF_2T4R)
599 ret = 0;
600 else if (priv->rf_type == RF_1T2R)
601 {
602 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
603 ret = 1;
604 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
605 ret = 0;
606 }
4803ef77 607
ecdfa446
GKH		 608 return ret;
609}
610/******************************************************************************
611 *function: This function set specific bits to BB register
612 * input: net_device dev
613 * u32 dwRegAddr //target addr to be modified
614 * u32 dwBitMask //taget bit pos in the addr to be modified
615 * u32 dwData //value to be write
616 * output: none
617 * return: none
618 * notice:
619 * ****************************************************************************/
620void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
621{
3f9ab1ee 622 struct r8192_priv *priv = ieee80211_priv(dev);
ecdfa446
GKH		 623 u32 OriginalValue, BitShift, NewValue;
624
625 if(dwBitMask!= bMaskDWord)
626 {//if not "double word" write
3f9ab1ee 627 OriginalValue = read_nic_dword(priv, dwRegAddr);
ecdfa446
GKH		 628 BitShift = rtl8192_CalculateBitShift(dwBitMask);
629 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
3f9ab1ee 630 write_nic_dword(priv, dwRegAddr, NewValue);
ecdfa446 631 }else
3f9ab1ee 632 write_nic_dword(priv, dwRegAddr, dwData);
ecdfa446
GKH		 633}
634/******************************************************************************
635 *function: This function reads specific bits from BB register
636 * input: net_device dev
637 * u32 dwRegAddr //target addr to be readback
638 * u32 dwBitMask //taget bit pos in the addr to be readback
639 * output: none
640 * return: u32 Data //the readback register value
641 * notice:
642 * ****************************************************************************/
643u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
644{
3f9ab1ee 645 struct r8192_priv *priv = ieee80211_priv(dev);
49e57f2f 646 u32 OriginalValue, BitShift;
ecdfa446 647
3f9ab1ee 648 OriginalValue = read_nic_dword(priv, dwRegAddr);
ecdfa446 649 BitShift = rtl8192_CalculateBitShift(dwBitMask);
49e57f2f 650 return (OriginalValue & dwBitMask) >> BitShift;
ecdfa446
GKH		 651}
652/******************************************************************************
653 *function: This function read register from RF chip
654 * input: net_device dev
655 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
656 * u32 Offset //target address to be read
657 * output: none
658 * return: u32 readback value
659 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
660 * ****************************************************************************/
5e1ad18a 661static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
ecdfa446
GKH		 662{
663 struct r8192_priv *priv = ieee80211_priv(dev);
664 u32 ret = 0;
665 u32 NewOffset = 0;
666 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
667 //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
668 //make sure RF register offset is correct
669 Offset &= 0x3f;
670
671 //switch page for 8256 RF IC
6f304eb2
MM		 672 //analog to digital off, for protection
673 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
674 if (Offset >= 31)
ecdfa446 675 {
6f304eb2
MM		 676 priv->RfReg0Value[eRFPath] |= 0x140;
677 //Switch to Reg_Mode2 for Reg 31-45
678 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
679 //modify offset
680 NewOffset = Offset -30;
681 }
682 else if (Offset >= 16)
683 {
684 priv->RfReg0Value[eRFPath] |= 0x100;
685 priv->RfReg0Value[eRFPath] &= (~0x40);
686 //Switch to Reg_Mode 1 for Reg16-30
687 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
ecdfa446 688
6f304eb2 689 NewOffset = Offset - 15;
ecdfa446
GKH		 690 }
691 else
ecdfa446 692 NewOffset = Offset;
6f304eb2 693
ecdfa446
GKH		 694 //put desired read addr to LSSI control Register
695 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
696 //Issue a posedge trigger
697 //
698 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
699 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
700
701
702 // TODO: we should not delay such a long time. Ask help from SD3
703 msleep(1);
704
705 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
706
707
708 // Switch back to Reg_Mode0;
6f304eb2 709 priv->RfReg0Value[eRFPath] &= 0xebf;
ecdfa446 710
6f304eb2
MM		 711 rtl8192_setBBreg(
712 dev,
713 pPhyReg->rf3wireOffset,
714 bMaskDWord,
715 (priv->RfReg0Value[eRFPath] << 16));
ecdfa446 716
6f304eb2
MM		 717 //analog to digital on
718 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
ecdfa446
GKH		 719
720 return ret;
ecdfa446
GKH		 721}
722
723/******************************************************************************
724 *function: This function write data to RF register
725 * input: net_device dev
726 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
727 * u32 Offset //target address to be written
728 * u32 Data //The new register data to be written
729 * output: none
730 * return: none
731 * notice: For RF8256 only.
732 ===========================================================
733 *Reg Mode RegCTL[1] RegCTL[0] Note
734 * (Reg00[12]) (Reg00[10])
735 *===========================================================
736 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
737 *------------------------------------------------------------------
738 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
739 *------------------------------------------------------------------
740 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
741 *------------------------------------------------------------------
742 * ****************************************************************************/
5e1ad18a 743static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
ecdfa446
GKH		 744{
745 struct r8192_priv *priv = ieee80211_priv(dev);
746 u32 DataAndAddr = 0, NewOffset = 0;
747 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
748
749 Offset &= 0x3f;
ecdfa446 750
6f304eb2
MM		 751 //analog to digital off, for protection
752 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
ecdfa446 753
6f304eb2
MM		 754 if (Offset >= 31)
755 {
756 priv->RfReg0Value[eRFPath] |= 0x140;
757 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
758 NewOffset = Offset - 30;
ecdfa446 759 }
6f304eb2 760 else if (Offset >= 16)
ecdfa446 761 {
6f304eb2
MM		 762 priv->RfReg0Value[eRFPath] |= 0x100;
763 priv->RfReg0Value[eRFPath] &= (~0x40);
764 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
765 NewOffset = Offset - 15;
ecdfa446 766 }
6f304eb2
MM		 767 else
768 NewOffset = Offset;
ecdfa446
GKH		 769
770 // Put write addr in [5:0] and write data in [31:16]
771 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
772
773 // Write Operation
774 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
775
776
777 if(Offset==0x0)
778 priv->RfReg0Value[eRFPath] = Data;
779
780 // Switch back to Reg_Mode0;
6f304eb2 781 if(Offset != 0)
ecdfa446 782 {
6f304eb2
MM		 783 priv->RfReg0Value[eRFPath] &= 0xebf;
784 rtl8192_setBBreg(
785 dev,
786 pPhyReg->rf3wireOffset,
787 bMaskDWord,
788 (priv->RfReg0Value[eRFPath] << 16));
ecdfa446 789 }
6f304eb2
MM		 790 //analog to digital on
791 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
ecdfa446
GKH		 792}
793
794/******************************************************************************
795 *function: This function set specific bits to RF register
796 * input: net_device dev
797 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
798 * u32 RegAddr //target addr to be modified
799 * u32 BitMask //taget bit pos in the addr to be modified
800 * u32 Data //value to be write
801 * output: none
802 * return: none
803 * notice:
804 * ****************************************************************************/
805void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
806{
807 struct r8192_priv *priv = ieee80211_priv(dev);
808 u32 Original_Value, BitShift, New_Value;
809// u8 time = 0;
810
811 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
812 return;
ecdfa446
GKH		 813 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
814 return;
ecdfa446
GKH		 815 //down(&priv->rf_sem);
816
817 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
818 if (priv->Rf_Mode == RF_OP_By_FW)
819 {
820 if (BitMask != bMask12Bits) // RF data is 12 bits only
821 {
822 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
823 BitShift = rtl8192_CalculateBitShift(BitMask);
824 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
825
826 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
827 }else
828 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
829 udelay(200);
830
831 }
832 else
833 {
834 if (BitMask != bMask12Bits) // RF data is 12 bits only
835 {
836 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
837 BitShift = rtl8192_CalculateBitShift(BitMask);
838 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
839
840 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
841 }else
842 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
843 }
ecdfa446 844 //up(&priv->rf_sem);
ecdfa446
GKH		 845}
846
847/******************************************************************************
848 *function: This function reads specific bits from RF register
849 * input: net_device dev
850 * u32 RegAddr //target addr to be readback
851 * u32 BitMask //taget bit pos in the addr to be readback
852 * output: none
853 * return: u32 Data //the readback register value
854 * notice:
855 * ****************************************************************************/
856u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
857{
858 u32 Original_Value, Readback_Value, BitShift;
859 struct r8192_priv *priv = ieee80211_priv(dev);
860 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
861 return 0;
ecdfa446
GKH		 862 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
863 return 0;
ecdfa446
GKH		 864 down(&priv->rf_sem);
865 if (priv->Rf_Mode == RF_OP_By_FW)
866 {
867 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
868 udelay(200);
869 }
870 else
871 {
872 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
873
874 }
875 BitShift = rtl8192_CalculateBitShift(BitMask);
876 Readback_Value = (Original_Value & BitMask) >> BitShift;
877 up(&priv->rf_sem);
878// udelay(200);
c6eae677 879 return Readback_Value;
ecdfa446
GKH		 880}
881
882/******************************************************************************
883 *function: We support firmware to execute RF-R/W.
884 * input: dev
885 * output: none
886 * return: none
887 * notice:
888 * ***************************************************************************/
889static u32 phy_FwRFSerialRead(
890 struct net_device* dev,
891 RF90_RADIO_PATH_E eRFPath,
892 u32 Offset )
893{
3f9ab1ee 894 struct r8192_priv *priv = ieee80211_priv(dev);
ecdfa446
GKH		 895 u32 Data = 0;
896 u8 time = 0;
897 //DbgPrint("FW RF CTRL\n\r");
898 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
899 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
900 much time. This is only for site survey. */
901 // 1. Read operation need not insert data. bit 0-11
902 //Data &= bMask12Bits;
903 // 2. Write RF register address. Bit 12-19
904 Data |= ((Offset&0xFF)<<12);
905 // 3. Write RF path. bit 20-21
906 Data |= ((eRFPath&0x3)<<20);
907 // 4. Set RF read indicator. bit 22=0
908 //Data |= 0x00000;
909 // 5. Trigger Fw to operate the command. bit 31
910 Data |= 0x80000000;
911 // 6. We can not execute read operation if bit 31 is 1.
3f9ab1ee 912 while (read_nic_dword(priv, QPNR)&0x80000000)
ecdfa446
GKH		 913 {
914 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
915 if (time++ < 100)
916 {
917 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
918 udelay(10);
919 }
920 else
921 break;
922 }
923 // 7. Execute read operation.
3f9ab1ee 924 write_nic_dword(priv, QPNR, Data);
ecdfa446 925 // 8. Check if firmawre send back RF content.
3f9ab1ee 926 while (read_nic_dword(priv, QPNR)&0x80000000)
ecdfa446
GKH		 927 {
928 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
929 if (time++ < 100)
930 {
931 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
932 udelay(10);
933 }
934 else
c6eae677 935 return 0;
ecdfa446 936 }
3f9ab1ee 937 return read_nic_dword(priv, RF_DATA);
d5abdf72 938}
ecdfa446
GKH		 939
940/******************************************************************************
941 *function: We support firmware to execute RF-R/W.
942 * input: dev
943 * output: none
944 * return: none
945 * notice:
946 * ***************************************************************************/
947static void
948phy_FwRFSerialWrite(
949 struct net_device* dev,
950 RF90_RADIO_PATH_E eRFPath,
951 u32 Offset,
952 u32 Data )
953{
3f9ab1ee 954 struct r8192_priv *priv = ieee80211_priv(dev);
ecdfa446
GKH		 955 u8 time = 0;
956
957 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
958 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
959 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
960 much time. This is only for site survey. */
961
962 // 1. Set driver write bit and 12 bit data. bit 0-11
963 //Data &= bMask12Bits; // Done by uper layer.
964 // 2. Write RF register address. bit 12-19
965 Data |= ((Offset&0xFF)<<12);
966 // 3. Write RF path. bit 20-21
967 Data |= ((eRFPath&0x3)<<20);
968 // 4. Set RF write indicator. bit 22=1
969 Data |= 0x400000;
970 // 5. Trigger Fw to operate the command. bit 31=1
971 Data |= 0x80000000;
972
973 // 6. Write operation. We can not write if bit 31 is 1.
3f9ab1ee 974 while (read_nic_dword(priv, QPNR)&0x80000000)
ecdfa446
GKH		 975 {
976 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
977 if (time++ < 100)
978 {
979 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
980 udelay(10);
981 }
982 else
983 break;
984 }
985 // 7. No matter check bit. We always force the write. Because FW will
986 // not accept the command.
3f9ab1ee 987 write_nic_dword(priv, QPNR, Data);
ecdfa446
GKH		 988 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
989 to finish RF write operation. */
990 /* 2008/01/17 MH We support delay in firmware side now. */
991 //delay_us(20);
992
d5abdf72 993}
ecdfa446
GKH		 994
995
996/******************************************************************************
997 *function: This function read BB parameters from Header file we gen,
998 * and do register read/write
999 * input: dev
1000 * output: none
1001 * return: none
1002 * notice: BB parameters may change all the time, so please make
1003 * sure it has been synced with the newest.
1004 * ***************************************************************************/
1005void rtl8192_phy_configmac(struct net_device* dev)
1006{
1007 u32 dwArrayLen = 0, i = 0;
1008 u32* pdwArray = NULL;
1009 struct r8192_priv *priv = ieee80211_priv(dev);
1010#ifdef TO_DO_LIST
1011if(Adapter->bInHctTest)
1012 {
1013 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
1014 dwArrayLen = MACPHY_ArrayLengthDTM;
1015 pdwArray = Rtl819XMACPHY_ArrayDTM;
1016 }
1017 else if(priv->bTXPowerDataReadFromEEPORM)
1018#endif
1019 if(priv->bTXPowerDataReadFromEEPORM)
1020 {
1021 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
1022 dwArrayLen = MACPHY_Array_PGLength;
1023 pdwArray = Rtl819XMACPHY_Array_PG;
1024
1025 }
1026 else
1027 {
1028 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
1029 dwArrayLen = MACPHY_ArrayLength;
1030 pdwArray = Rtl819XMACPHY_Array;
1031 }
1032 for(i = 0; i<dwArrayLen; i=i+3){
1033 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
1034 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1035 if(pdwArray[i] == 0x318)
1036 {
1037 pdwArray[i+2] = 0x00000800;
1038 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1039 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1040 }
1041 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1042 }
ecdfa446
GKH		 1043}
1044
1045/******************************************************************************
1046 *function: This function do dirty work
1047 * input: dev
1048 * output: none
1049 * return: none
1050 * notice: BB parameters may change all the time, so please make
1051 * sure it has been synced with the newest.
1052 * ***************************************************************************/
1053
1054void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1055{
1056 int i;
1057 //u8 ArrayLength;
1058 u32* Rtl819XPHY_REGArray_Table = NULL;
1059 u32* Rtl819XAGCTAB_Array_Table = NULL;
1060 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1061 struct r8192_priv *priv = ieee80211_priv(dev);
1062#ifdef TO_DO_LIST
1063 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1064 if(Adapter->bInHctTest)
1065 {
1066 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1067 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1068
1069 if(priv->RF_Type == RF_2T4R)
1070 {
1071 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1072 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1073 }
1074 else if (priv->RF_Type == RF_1T2R)
1075 {
1076 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1077 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1078 }
1079 }
1080 else
1081#endif
1082 {
1083 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1084 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1085 if(priv->rf_type == RF_2T4R)
1086 {
1087 PHY_REGArrayLen = PHY_REGArrayLength;
1088 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
1089 }
1090 else if (priv->rf_type == RF_1T2R)
1091 {
1092 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
1093 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
1094 }
1095 }
1096
1097 if (ConfigType == BaseBand_Config_PHY_REG)
1098 {
1099 for (i=0; i<PHY_REGArrayLen; i+=2)
1100 {
1101 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
703fdcc3 1102 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
ecdfa446
GKH		 1103 }
1104 }
1105 else if (ConfigType == BaseBand_Config_AGC_TAB)
1106 {
1107 for (i=0; i<AGCTAB_ArrayLen; i+=2)
1108 {
1109 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
703fdcc3 1110 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
ecdfa446
GKH		 1111 }
1112 }
ecdfa446
GKH		 1113}
1114/******************************************************************************
1115 *function: This function initialize Register definition offset for Radio Path
1116 * A/B/C/D
1117 * input: net_device dev
1118 * output: none
1119 * return: none
1120 * notice: Initialization value here is constant and it should never be changed
1121 * ***************************************************************************/
5e1ad18a 1122static void rtl8192_InitBBRFRegDef(struct net_device* dev)
ecdfa446
GKH		 1123{
1124 struct r8192_priv *priv = ieee80211_priv(dev);
1125// RF Interface Sowrtware Control
1126 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1127 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
1128 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
1129 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1130
1131 // RF Interface Readback Value
1132 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
1133 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
1134 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
1135 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1136
1137 // RF Interface Output (and Enable)
1138 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
1139 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
1140 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
1141 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1142
1143 // RF Interface (Output and) Enable
1144 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
1145 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
1146 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
1147 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1148
1149 //Addr of LSSI. Wirte RF register by driver
1150 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
1151 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1152 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1153 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1154
1155 // RF parameter
1156 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
1157 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1158 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1159 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1160
1161 // Tx AGC Gain Stage (same for all path. Should we remove this?)
1162 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1163 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1164 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1165 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1166
1167 // Tranceiver A~D HSSI Parameter-1
1168 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
1169 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
1170 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
1171 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
1172
1173 // Tranceiver A~D HSSI Parameter-2
1174 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
1175 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
1176 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
1177 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
1178
1179 // RF switch Control
1180 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
1181 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1182 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1183 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1184
1185 // AGC control 1
1186 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1187 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1188 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1189 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1190
1191 // AGC control 2
1192 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1193 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1194 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1195 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1196
1197 // RX AFE control 1
1198 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1199 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1200 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1201 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1202
1203 // RX AFE control 1
1204 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1205 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1206 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1207 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1208
1209 // Tx AFE control 1
1210 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1211 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1212 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1213 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1214
1215 // Tx AFE control 2
1216 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1217 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1218 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1219 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1220
1221 // Tranceiver LSSI Readback
1222 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1223 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1224 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1225 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1226
1227}
1228/******************************************************************************
1229 *function: This function is to write register and then readback to make sure whether BB and RF is OK
1230 * input: net_device dev
1231 * HW90_BLOCK_E CheckBlock
1232 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
1233 * output: none
1234 * return: return whether BB and RF is ok(0:OK; 1:Fail)
1235 * notice: This function may be removed in the ASIC
1236 * ***************************************************************************/
1237RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
1238{
3f9ab1ee 1239 struct r8192_priv *priv = ieee80211_priv(dev);
ecdfa446
GKH		 1240// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1241 RT_STATUS ret = RT_STATUS_SUCCESS;
1242 u32 i, CheckTimes = 4, dwRegRead = 0;
1243 u32 WriteAddr[4];
1244 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1245 // Initialize register address offset to be checked
1246 WriteAddr[HW90_BLOCK_MAC] = 0x100;
1247 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1248 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1249 WriteAddr[HW90_BLOCK_RF] = 0x3;
1250 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
1251 for(i=0 ; i < CheckTimes ; i++)
1252 {
1253
1254 //
1255 // Write Data to register and readback
1256 //
1257 switch(CheckBlock)
1258 {
1259 case HW90_BLOCK_MAC:
703fdcc3 1260 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
ecdfa446
GKH		 1261 break;
1262
1263 case HW90_BLOCK_PHY0:
1264 case HW90_BLOCK_PHY1:
3f9ab1ee
MM		 1265 write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]);
1266 dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]);
ecdfa446
GKH		 1267 break;
1268
1269 case HW90_BLOCK_RF:
1270 WriteData[i] &= 0xfff;
1271 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
1272 // TODO: we should not delay for such a long time. Ask SD3
1273 mdelay(10);
1274 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1275 mdelay(10);
1276 break;
1277
1278 default:
1279 ret = RT_STATUS_FAILURE;
1280 break;
1281 }
1282
1283
1284 //
1285 // Check whether readback data is correct
1286 //
1287 if(dwRegRead != WriteData[i])
1288 {
703fdcc3 1289 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x\n", dwRegRead, WriteData[i]);
ecdfa446
GKH		 1290 ret = RT_STATUS_FAILURE;
1291 break;
1292 }
1293 }
1294
1295 return ret;
1296}
1297
1298
1299/******************************************************************************
1300 *function: This function initialize BB&RF
1301 * input: net_device dev
1302 * output: none
1303 * return: none
1304 * notice: Initialization value may change all the time, so please make
1305 * sure it has been synced with the newest.
1306 * ***************************************************************************/
5e1ad18a 1307static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
ecdfa446
GKH		 1308{
1309 struct r8192_priv *priv = ieee80211_priv(dev);
1310 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1311 u8 bRegValue = 0, eCheckItem = 0;
1312 u32 dwRegValue = 0;
1313 /**************************************
1314 //<1>Initialize BaseBand
1315 **************************************/
1316
1317 /*--set BB Global Reset--*/
3f9ab1ee
MM		 1318 bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET);
1319 write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
ecdfa446
GKH		 1320
1321 /*---set BB reset Active---*/
3f9ab1ee
MM		 1322 dwRegValue = read_nic_dword(priv, CPU_GEN);
1323 write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
ecdfa446
GKH		 1324
1325 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
1326 // TODO: this function should be removed on ASIC , Emily 2007.2.2
1327 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
1328 {
1329 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
1330 if(rtStatus != RT_STATUS_SUCCESS)
1331 {
1332 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
1333 return rtStatus;
1334 }
1335 }
1336 /*---- Set CCK and OFDM Block "OFF"----*/
1337 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
1338 /*----BB Register Initilazation----*/
1339 //==m==>Set PHY REG From Header<==m==
1340 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
1341
1342 /*----Set BB reset de-Active----*/
3f9ab1ee
MM		 1343 dwRegValue = read_nic_dword(priv, CPU_GEN);
1344 write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
ecdfa446
GKH		 1345
1346 /*----BB AGC table Initialization----*/
1347 //==m==>Set PHY REG From Header<==m==
1348 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
1349
1350 if (priv->card_8192_version > VERSION_8190_BD)
1351 {
1352 if(priv->rf_type == RF_2T4R)
1353 {
1354 // Antenna gain offset from B/C/D to A
1355 dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 |
1356 priv->AntennaTxPwDiff[1]<<4 |
1357 priv->AntennaTxPwDiff[0]);
1358 }
1359 else
1360 dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R.
1361 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
1362 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
1363
1364
1365 //XSTALLCap
ecdfa446
GKH		 1366 dwRegValue = priv->CrystalCap;
1367 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
ecdfa446
GKH		 1368 }
1369
1370 // Check if the CCK HighPower is turned ON.
1371 // This is used to calculate PWDB.
1372// priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
1373 return rtStatus;
1374}
1375/******************************************************************************
1376 *function: This function initialize BB&RF
1377 * input: net_device dev
1378 * output: none
1379 * return: none
1380 * notice: Initialization value may change all the time, so please make
1381 * sure it has been synced with the newest.
1382 * ***************************************************************************/
1383RT_STATUS rtl8192_BBConfig(struct net_device* dev)
1384{
ecdfa446
GKH		 1385 rtl8192_InitBBRFRegDef(dev);
1386 //config BB&RF. As hardCode based initialization has not been well
1387 //implemented, so use file first.FIXME:should implement it for hardcode?
49e57f2f 1388 return rtl8192_BB_Config_ParaFile(dev);
ecdfa446
GKH		 1389}
1390
1391/******************************************************************************
1392 *function: This function obtains the initialization value of Tx power Level offset
1393 * input: net_device dev
1394 * output: none
1395 * return: none
1396 * ***************************************************************************/
1397void rtl8192_phy_getTxPower(struct net_device* dev)
1398{
1399 struct r8192_priv *priv = ieee80211_priv(dev);
4803ef77 1400
ecdfa446 1401 priv->MCSTxPowerLevelOriginalOffset[0] =
3f9ab1ee 1402 read_nic_dword(priv, rTxAGC_Rate18_06);
ecdfa446 1403 priv->MCSTxPowerLevelOriginalOffset[1] =
3f9ab1ee 1404 read_nic_dword(priv, rTxAGC_Rate54_24);
ecdfa446 1405 priv->MCSTxPowerLevelOriginalOffset[2] =
3f9ab1ee 1406 read_nic_dword(priv, rTxAGC_Mcs03_Mcs00);
ecdfa446 1407 priv->MCSTxPowerLevelOriginalOffset[3] =
3f9ab1ee 1408 read_nic_dword(priv, rTxAGC_Mcs07_Mcs04);
ecdfa446 1409 priv->MCSTxPowerLevelOriginalOffset[4] =
3f9ab1ee 1410 read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
ecdfa446 1411 priv->MCSTxPowerLevelOriginalOffset[5] =
3f9ab1ee 1412 read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
ecdfa446
GKH		 1413
1414 // read rx initial gain
3f9ab1ee
MM		 1415 priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
1416 priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1);
1417 priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1);
1418 priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1);
703fdcc3 1419 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
ecdfa446
GKH		 1420 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1421 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1422
1423 // read framesync
3f9ab1ee
MM		 1424 priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3);
1425 priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2);
703fdcc3 1426 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
ecdfa446
GKH		 1427 rOFDM0_RxDetector3, priv->framesync);
1428 // read SIFS (save the value read fome MACPHY_REG.txt)
3f9ab1ee 1429 priv->SifsTime = read_nic_word(priv, SIFS);
ecdfa446
GKH		 1430}
1431
1432/******************************************************************************
1433 *function: This function obtains the initialization value of Tx power Level offset
1434 * input: net_device dev
1435 * output: none
1436 * return: none
1437 * ***************************************************************************/
1438void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
1439{
1440 struct r8192_priv *priv = ieee80211_priv(dev);
1441 u8 powerlevel = 0,powerlevelOFDM24G = 0;
1442 char ant_pwr_diff;
1443 u32 u4RegValue;
1444
1445 if(priv->epromtype == EPROM_93c46)
1446 {
1447 powerlevel = priv->TxPowerLevelCCK[channel-1];
1448 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1449 }
1450 else if(priv->epromtype == EPROM_93c56)
1451 {
1452 if(priv->rf_type == RF_1T2R)
1453 {
1454 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
1455 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
1456 }
1457 else if(priv->rf_type == RF_2T4R)
1458 {
1459 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx
1460 // Power must be calculated by the antenna diff.
1461 // So we have to rewrite Antenna gain offset register here.
1462 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
1463 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
1464
1465 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
1466 -priv->TxPowerLevelOFDM24G_A[channel-1];
1467 ant_pwr_diff &= 0xf;
1468 //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff));
1469 priv->RF_C_TxPwDiff = ant_pwr_diff;
1470
1471 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
1472 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C
1473 priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care
1474
1475 // Antenna gain offset from B/C/D to A
1476 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
1477 priv->AntennaTxPwDiff[1]<<4 |
1478 priv->AntennaTxPwDiff[0]);
1479
1480 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
1481 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1482 }
1483 }
1484#ifdef TODO
1485 //
1486 // CCX 2 S31, AP control of client transmit power:
1487 // 1. We shall not exceed Cell Power Limit as possible as we can.
1488 // 2. Tolerance is +/- 5dB.
1489 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
1490 //
1491 // TODO:
1492 // 1. 802.11h power contraint
1493 //
1494 // 071011, by rcnjko.
1495 //
1496 if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
1497 pMgntInfo->bWithCcxCellPwr &&
1498 channel == pMgntInfo->dot11CurrentChannelNumber)
1499 {
1500 u8 CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
1501 u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
1502 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
1503
1504 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1505 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1506 pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
1507 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1508 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1509 channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1510
1511 // CCK
1512 if(powerlevel > CckCellPwrIdx)
1513 powerlevel = CckCellPwrIdx;
1514 // Legacy OFDM, HT OFDM
1515 if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
1516 {
1517 if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
1518 {
1519 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
1520 }
1521 else
1522 {
1523 LegacyOfdmCellPwrIdx = 0;
1524 }
1525 }
1526
1527 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1528 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
1529 powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1530 }
1531
1532 pHalData->CurrentCckTxPwrIdx = powerlevel;
1533 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
1534#endif
6f304eb2
MM		 1535 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
1536 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
ecdfa446
GKH		 1537}
1538
1539/******************************************************************************
1540 *function: This function check Rf chip to do RF config
1541 * input: net_device dev
1542 * output: none
1543 * return: only 8256 is supported
1544 * ***************************************************************************/
1545RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev)
1546{
6f304eb2 1547 return PHY_RF8256_Config(dev);
ecdfa446
GKH		 1548}
1549
1550/******************************************************************************
1551 *function: This function update Initial gain
1552 * input: net_device dev
1553 * output: none
1554 * return: As Windows has not implemented this, wait for complement
1555 * ***************************************************************************/
1556void rtl8192_phy_updateInitGain(struct net_device* dev)
1557{
ecdfa446
GKH		 1558}
1559
1560/******************************************************************************
1561 *function: This function read RF parameters from general head file, and do RF 3-wire
1562 * input: net_device dev
1563 * output: none
1564 * return: return code show if RF configuration is successful(0:pass, 1:fail)
1565 * Note: Delay may be required for RF configuration
1566 * ***************************************************************************/
1567u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1568{
1569
1570 int i;
1571 //u32* pRFArray;
1572 u8 ret = 0;
1573
1574 switch(eRFPath){
1575 case RF90_PATH_A:
1576 for(i = 0;i<RadioA_ArrayLength; i=i+2){
1577
1578 if(Rtl819XRadioA_Array[i] == 0xfe){
1579 msleep(100);
1580 continue;
1581 }
1582 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
1583 //msleep(1);
1584
1585 }
1586 break;
1587 case RF90_PATH_B:
1588 for(i = 0;i<RadioB_ArrayLength; i=i+2){
1589
1590 if(Rtl819XRadioB_Array[i] == 0xfe){
1591 msleep(100);
1592 continue;
1593 }
1594 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
1595 //msleep(1);
1596
1597 }
1598 break;
1599 case RF90_PATH_C:
1600 for(i = 0;i<RadioC_ArrayLength; i=i+2){
1601
1602 if(Rtl819XRadioC_Array[i] == 0xfe){
1603 msleep(100);
1604 continue;
1605 }
1606 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
1607 //msleep(1);
1608
1609 }
1610 break;
1611 case RF90_PATH_D:
1612 for(i = 0;i<RadioD_ArrayLength; i=i+2){
1613
1614 if(Rtl819XRadioD_Array[i] == 0xfe){
1615 msleep(100);
1616 continue;
1617 }
1618 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
1619 //msleep(1);
1620
1621 }
1622 break;
1623 default:
1624 break;
1625 }
1626
859171ca 1627 return ret;
ecdfa446
GKH		 1628
1629}
1630/******************************************************************************
1631 *function: This function set Tx Power of the channel
1632 * input: struct net_device *dev
1633 * u8 channel
1634 * output: none
1635 * return: none
1636 * Note:
1637 * ***************************************************************************/
5e1ad18a 1638static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
ecdfa446
GKH		 1639{
1640 struct r8192_priv *priv = ieee80211_priv(dev);
1641 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1642 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1643
6f304eb2
MM		 1644 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1645 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
ecdfa446 1646}
6f304eb2 1647
ecdfa446
GKH		 1648/****************************************************************************************
1649 *function: This function set command table variable(struct SwChnlCmd).
1650 * input: SwChnlCmd* CmdTable //table to be set.
1651 * u32 CmdTableIdx //variable index in table to be set
1652 * u32 CmdTableSz //table size.
1653 * SwChnlCmdID CmdID //command ID to set.
1654 * u32 Para1
1655 * u32 Para2
1656 * u32 msDelay
1657 * output:
1658 * return: true if finished, false otherwise
1659 * Note:
1660 * ************************************************************************************/
5e1ad18a 1661static u8 rtl8192_phy_SetSwChnlCmdArray(
ecdfa446
GKH		 1662 SwChnlCmd* CmdTable,
1663 u32 CmdTableIdx,
1664 u32 CmdTableSz,
1665 SwChnlCmdID CmdID,
1666 u32 Para1,
1667 u32 Para2,
1668 u32 msDelay
1669 )
1670{
1671 SwChnlCmd* pCmd;
1672
1673 if(CmdTable == NULL)
1674 {
1675 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
1676 return false;
1677 }
1678 if(CmdTableIdx >= CmdTableSz)
1679 {
1680 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1681 CmdTableIdx, CmdTableSz);
1682 return false;
1683 }
1684
1685 pCmd = CmdTable + CmdTableIdx;
1686 pCmd->CmdID = CmdID;
1687 pCmd->Para1 = Para1;
1688 pCmd->Para2 = Para2;
1689 pCmd->msDelay = msDelay;
1690
1691 return true;
1692}
1693/******************************************************************************
1694 *function: This function set channel step by step
1695 * input: struct net_device *dev
1696 * u8 channel
1697 * u8* stage //3 stages
1698 * u8* step //
1699 * u32* delay //whether need to delay
1700 * output: store new stage, step and delay for next step(combine with function above)
1701 * return: true if finished, false otherwise
1702 * Note: Wait for simpler function to replace it //wb
1703 * ***************************************************************************/
5e1ad18a 1704static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
ecdfa446
GKH		 1705{
1706 struct r8192_priv *priv = ieee80211_priv(dev);
1707// PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
1708 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1709 u32 PreCommonCmdCnt;
1710 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1711 u32 PostCommonCmdCnt;
1712 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1713 u32 RfDependCmdCnt;
1714 SwChnlCmd *CurrentCmd = NULL;
1715 //RF90_RADIO_PATH_E eRFPath;
1716 u8 eRFPath;
1717// u32 RfRetVal;
1718// u8 RetryCnt;
1719
1720 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
1721// RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
1722
1723#ifdef ENABLE_DOT11D
1724 if (!IsLegalChannel(priv->ieee80211, channel))
1725 {
1726 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
1727 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
1728 }
1729#endif
1730
1731 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1732 //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
1733 {
1734 //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1735 // return false;
1736 // <1> Fill up pre common command.
1737 PreCommonCmdCnt = 0;
1738 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1739 CmdID_SetTxPowerLevel, 0, 0, 0);
1740 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1741 CmdID_End, 0, 0, 0);
1742
1743 // <2> Fill up post common command.
1744 PostCommonCmdCnt = 0;
1745
1746 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
1747 CmdID_End, 0, 0, 0);
1748
1749 // <3> Fill up RF dependent command.
1750 RfDependCmdCnt = 0;
ecdfa446 1751
6f304eb2
MM		 1752 // TEST!! This is not the table for 8256!!
1753 if (!(channel >= 1 && channel <= 14))
1754 {
1755 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
ecdfa446 1756 return false;
ecdfa446 1757 }
6f304eb2
MM		 1758 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1759 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
1760 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1761 CmdID_End, 0, 0, 0);
ecdfa446
GKH		 1762
1763 do{
1764 switch(*stage)
1765 {
1766 case 0:
1767 CurrentCmd=&PreCommonCmd[*step];
1768 break;
1769 case 1:
1770 CurrentCmd=&RfDependCmd[*step];
1771 break;
1772 case 2:
1773 CurrentCmd=&PostCommonCmd[*step];
1774 break;
1775 }
1776
1777 if(CurrentCmd->CmdID==CmdID_End)
1778 {
1779 if((*stage)==2)
1780 {
1781 return true;
1782 }
1783 else
1784 {
1785 (*stage)++;
1786 (*step)=0;
1787 continue;
1788 }
1789 }
1790
1791 switch(CurrentCmd->CmdID)
1792 {
1793 case CmdID_SetTxPowerLevel:
1794 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
1795 rtl8192_SetTxPowerLevel(dev,channel);
1796 break;
1797 case CmdID_WritePortUlong:
3f9ab1ee 1798 write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2);
ecdfa446
GKH		 1799 break;
1800 case CmdID_WritePortUshort:
3f9ab1ee 1801 write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
ecdfa446
GKH		 1802 break;
1803 case CmdID_WritePortUchar:
3f9ab1ee 1804 write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
ecdfa446
GKH		 1805 break;
1806 case CmdID_RF_WriteReg:
1807 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
1808 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
1809 break;
1810 default:
1811 break;
1812 }
1813
1814 break;
1815 }while(true);
1816 }/*for(Number of RF paths)*/
1817
1818 (*delay)=CurrentCmd->msDelay;
1819 (*step)++;
1820 return false;
1821}
1822
1823/******************************************************************************
1824 *function: This function does acturally set channel work
1825 * input: struct net_device *dev
1826 * u8 channel
1827 * output: none
1828 * return: noin
1829 * Note: We should not call this function directly
1830 * ***************************************************************************/
5e1ad18a 1831static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
ecdfa446
GKH		 1832{
1833 struct r8192_priv *priv = ieee80211_priv(dev);
1834 u32 delay = 0;
1835
1836 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
1837 {
1838 if(delay>0)
1839 msleep(delay);//or mdelay? need further consideration
1840 if(!priv->up)
1841 break;
1842 }
1843}
1844/******************************************************************************
1845 *function: Callback routine of the work item for switch channel.
1846 * input:
1847 *
1848 * output: none
1849 * return: noin
1850 * ***************************************************************************/
1851void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1852{
1853
1854 struct r8192_priv *priv = ieee80211_priv(dev);
1855
1856 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1857
1858 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
1859
1860 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1861
1862 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1863}
1864
1865/******************************************************************************
1866 *function: This function scheduled actural workitem to set channel
1867 * input: net_device dev
1868 * u8 channel //channel to set
1869 * output: none
1870 * return: return code show if workitem is scheduled(1:pass, 0:fail)
1871 * Note: Delay may be required for RF configuration
1872 * ***************************************************************************/
1873u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
1874{
1875 struct r8192_priv *priv = ieee80211_priv(dev);
1876 RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__);
1877 if(!priv->up)
1878 return false;
1879 if(priv->SwChnlInProgress)
1880 return false;
1881
1882// if(pHalData->SetBWModeInProgress)
1883// return;
1884
1885 //--------------------------------------------
1886 switch(priv->ieee80211->mode)
1887 {
1888 case WIRELESS_MODE_A:
1889 case WIRELESS_MODE_N_5G:
1890 if (channel<=14){
703fdcc3 1891 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
ecdfa446
GKH		 1892 return false;
1893 }
1894 break;
1895 case WIRELESS_MODE_B:
1896 if (channel>14){
703fdcc3 1897 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
ecdfa446
GKH		 1898 return false;
1899 }
1900 break;
1901 case WIRELESS_MODE_G:
1902 case WIRELESS_MODE_N_24G:
1903 if (channel>14){
703fdcc3 1904 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
ecdfa446
GKH		 1905 return false;
1906 }
1907 break;
1908 }
1909 //--------------------------------------------
1910
1911 priv->SwChnlInProgress = true;
1912 if(channel == 0)
1913 channel = 1;
1914
1915 priv->chan=channel;
1916
1917 priv->SwChnlStage=0;
1918 priv->SwChnlStep=0;
1919// schedule_work(&(priv->SwChnlWorkItem));
1920// rtl8192_SwChnl_WorkItem(dev);
1921 if(priv->up) {
1922// queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
1923 rtl8192_SwChnl_WorkItem(dev);
1924 }
1925 priv->SwChnlInProgress = false;
1926 return true;
1927}
1928
1929static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
1930{
1931 struct r8192_priv *priv = ieee80211_priv(dev);
1932
1933 switch(priv->CurrentChannelBW)
1934 {
1935 /* 20 MHz channel*/
1936 case HT_CHANNEL_WIDTH_20:
1937 //added by vivi, cck,tx power track, 20080703
1938 priv->CCKPresentAttentuation =
1939 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
1940
1941 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1942 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1943 if(priv->CCKPresentAttentuation < 0)
1944 priv->CCKPresentAttentuation = 0;
1945
1946 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1947
1948 if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14)
1949 {
1950 priv->bcck_in_ch14 = TRUE;
1951 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1952 }
1953 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1954 {
1955 priv->bcck_in_ch14 = FALSE;
1956 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1957 }
1958 else
1959 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1960 break;
1961
1962 /* 40 MHz channel*/
1963 case HT_CHANNEL_WIDTH_20_40:
1964 //added by vivi, cck,tx power track, 20080703
1965 priv->CCKPresentAttentuation =
1966 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
1967
1968 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1969 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1970 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1971 if(priv->CCKPresentAttentuation < 0)
1972 priv->CCKPresentAttentuation = 0;
1973
1974 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1975 {
1976 priv->bcck_in_ch14 = TRUE;
1977 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1978 }
1979 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1980 {
1981 priv->bcck_in_ch14 = FALSE;
1982 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1983 }
1984 else
1985 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1986 break;
1987 }
1988}
1989
ecdfa446
GKH		 1990static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
1991{
1992 struct r8192_priv *priv = ieee80211_priv(dev);
1993
1994 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1995 priv->bcck_in_ch14 = TRUE;
1996 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1997 priv->bcck_in_ch14 = FALSE;
1998
1999 //write to default index and tx power track will be done in dm.
2000 switch(priv->CurrentChannelBW)
2001 {
2002 /* 20 MHz channel*/
2003 case HT_CHANNEL_WIDTH_20:
2004 if(priv->Record_CCK_20Mindex == 0)
2005 priv->Record_CCK_20Mindex = 6; //set default value.
2006 priv->CCK_index = priv->Record_CCK_20Mindex;//6;
2007 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
2008 break;
2009
2010 /* 40 MHz channel*/
2011 case HT_CHANNEL_WIDTH_20_40:
2012 priv->CCK_index = priv->Record_CCK_40Mindex;//0;
2013 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
2014 break;
2015 }
2016 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
2017}
ecdfa446
GKH		 2018
2019static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
2020{
ecdfa446 2021 struct r8192_priv *priv = ieee80211_priv(dev);
ecdfa446 2022
ecdfa446
GKH		 2023 //if(pHalData->bDcut == TRUE)
2024 if(priv->IC_Cut >= IC_VersionCut_D)
2025 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
2026 else
2027 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
ecdfa446
GKH		 2028}
2029
2030
2031//
2032/******************************************************************************
2033 *function: Callback routine of the work item for set bandwidth mode.
2034 * input: struct net_device *dev
2035 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
2036 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
2037 * output: none
2038 * return: none
2039 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
2040 * test whether current work in the queue or not.//do I?
2041 * ***************************************************************************/
2042void rtl8192_SetBWModeWorkItem(struct net_device *dev)
2043{
2044
2045 struct r8192_priv *priv = ieee80211_priv(dev);
2046 u8 regBwOpMode;
2047
207b58fb 2048 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n",
ecdfa446
GKH		 2049 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
2050
2051
ecdfa446
GKH		 2052 if(!priv->up)
2053 {
2054 priv->SetBWModeInProgress= false;
2055 return;
2056 }
2057 //<1>Set MAC register
3f9ab1ee 2058 regBwOpMode = read_nic_byte(priv, BW_OPMODE);
ecdfa446
GKH		 2059
2060 switch(priv->CurrentChannelBW)
2061 {
2062 case HT_CHANNEL_WIDTH_20:
2063 regBwOpMode |= BW_OPMODE_20MHZ;
2064 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3f9ab1ee 2065 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
ecdfa446
GKH		 2066 break;
2067
2068 case HT_CHANNEL_WIDTH_20_40:
2069 regBwOpMode &= ~BW_OPMODE_20MHZ;
2070 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3f9ab1ee 2071 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
ecdfa446
GKH		 2072 break;
2073
2074 default:
2075 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
2076 break;
2077 }
2078
2079 //<2>Set PHY related register
2080 switch(priv->CurrentChannelBW)
2081 {
2082 case HT_CHANNEL_WIDTH_20:
2083 // Add by Vivi 20071119
2084 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
2085 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
2086// rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
2087
2088 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
2089// write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
2090// write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
2091// write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
2092 if(!priv->btxpower_tracking)
2093 {
3f9ab1ee
MM		 2094 write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000);
2095 write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317);
2096 write_nic_dword(priv, rCCK0_DebugPort, 0x00000204);
ecdfa446
GKH		 2097 }
2098 else
2099 CCK_Tx_Power_Track_BW_Switch(dev);
2100
ecdfa446 2101 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
ecdfa446
GKH		 2102 break;
2103 case HT_CHANNEL_WIDTH_20_40:
2104 // Add by Vivi 20071119
2105 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
2106 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
2107 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2108 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
2109 //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2110
2111 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2112 //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
2113 //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
2114 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
2115 if(!priv->btxpower_tracking)
2116 {
3f9ab1ee
MM		 2117 write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000);
2118 write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e);
2119 write_nic_dword(priv, rCCK0_DebugPort, 0x00000409);
ecdfa446
GKH		 2120 }
2121 else
2122 CCK_Tx_Power_Track_BW_Switch(dev);
2123
2124 // Set Control channel to upper or lower. These settings are required only for 40MHz
2125 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2126 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2127
2128
ecdfa446 2129 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
ecdfa446
GKH		 2130 break;
2131 default:
2132 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
2133 break;
2134
2135 }
2136 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2137
ecdfa446 2138 //<3>Set RF related register
6f304eb2 2139 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4803ef77 2140
ecdfa446
GKH		 2141 atomic_dec(&(priv->ieee80211->atm_swbw));
2142 priv->SetBWModeInProgress= false;
2143
703fdcc3 2144 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()\n");
ecdfa446
GKH		 2145}
2146
2147/******************************************************************************
2148 *function: This function schedules bandwith switch work.
2149 * input: struct net_device *dev
2150 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
2151 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
2152 * output: none
2153 * return: none
2154 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
2155 * test whether current work in the queue or not.//do I?
2156 * ***************************************************************************/
2157void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2158{
2159 struct r8192_priv *priv = ieee80211_priv(dev);
2160
2161
2162 if(priv->SetBWModeInProgress)
2163 return;
2164
2165 atomic_inc(&(priv->ieee80211->atm_swbw));
2166 priv->SetBWModeInProgress= true;
2167
2168 priv->CurrentChannelBW = Bandwidth;
2169
2170 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2171 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2172 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2173 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2174 else
2175 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2176
2177 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
2178 // schedule_work(&(priv->SetBWModeWorkItem));
2179 rtl8192_SetBWModeWorkItem(dev);
2180
2181}
2182
2183
5e1ad18a 2184void InitialGain819xPci(struct net_device *dev, u8 Operation)
ecdfa446
GKH		 2185{
2186#define SCAN_RX_INITIAL_GAIN 0x17
2187#define POWER_DETECTION_TH 0x08
2188 struct r8192_priv *priv = ieee80211_priv(dev);
2189 u32 BitMask;
2190 u8 initial_gain;
2191
2192 if(priv->up)
2193 {
2194 switch(Operation)
2195 {
2196 case IG_Backup:
2197 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
2198 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
2199 BitMask = bMaskByte0;
2200 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2201 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
2202 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
2203 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
2204 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
2205 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
2206 BitMask = bMaskByte2;
2207 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
2208
2209 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2210 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2211 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2212 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2213 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
2214
2215 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3f9ab1ee
MM		 2216 write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
2217 write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
2218 write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
2219 write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
ecdfa446 2220 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3f9ab1ee 2221 write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH);
ecdfa446
GKH		 2222 break;
2223 case IG_Restore:
2224 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
2225 BitMask = 0x7f; //Bit0~ Bit6
2226 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2227 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
2228
2229 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
2230 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
2231 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
2232 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
2233 BitMask = bMaskByte2;
2234 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
2235
2236 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2237 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2238 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2239 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2240 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
2241
2242 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
2243
2244
2245 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2246 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
2247 break;
2248 default:
703fdcc3 2249 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
ecdfa446
GKH		 2250 break;
2251 }
2252 }
2253}
2254
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