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Merge remote-tracking branch 'regulator/fix/max77802' into regulator-linus
[mirror_ubuntu-artful-kernel.git] / drivers / staging / rtl8192e / rtl8192e / r8192E_dev.c
CommitLineData
94a79942
LF		 1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * Based on the r8180 driver, which is:
559a4c31 5 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
94a79942
LF		 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
94a79942
LF		 15 * The full GNU General Public License is included in this distribution in the
16 * file called LICENSE.
17 *
18 * Contact Information:
19 * wlanfae <wlanfae@realtek.com>
a959dec1 20 *****************************************************************************/
94a79942
LF		 21#include "rtl_core.h"
22#include "r8192E_phy.h"
23#include "r8192E_phyreg.h"
24#include "r8190P_rtl8256.h"
25#include "r8192E_cmdpkt.h"
26#include "rtl_dm.h"
27#include "rtl_wx.h"
28
35e33b04
MK		 29static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
30 EDCAPARA_VO};
94a79942 31
89d4a8be 32void rtl92e_start_beacon(struct net_device *dev)
94a79942
LF		 33{
34 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
35 struct rtllib_network *net = &priv->rtllib->current_network;
36 u16 BcnTimeCfg = 0;
52629477
LF		 37 u16 BcnCW = 6;
38 u16 BcnIFS = 0xf;
94a79942 39
b7b50d65 40 rtl92e_irq_disable(dev);
94a79942 41
6dee0c88 42 rtl92e_writew(dev, ATIMWND, 2);
94a79942 43
6dee0c88
MK		 44 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
45 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
46 rtl92e_writew(dev, BCN_DMATIME, 256);
94a79942 47
d8ae1967 48 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
94a79942
LF		 49
50 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
51 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
6dee0c88 52 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
b74299cd 53 rtl92e_irq_enable(dev);
94a79942
LF		 54}
55
6ded6893 56static void _rtl92e_update_msr(struct net_device *dev)
94a79942
LF		 57{
58 struct r8192_priv *priv = rtllib_priv(dev);
59 u8 msr;
4fd7cedc 60 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
3a6b70c3 61
b59a4ca3 62 msr = rtl92e_readb(dev, MSR);
52629477 63 msr &= ~MSR_LINK_MASK;
94a79942
LF		 64
65 switch (priv->rtllib->iw_mode) {
66 case IW_MODE_INFRA:
67 if (priv->rtllib->state == RTLLIB_LINKED)
68 msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
69 else
70 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
71 LedAction = LED_CTL_LINK;
72 break;
73 case IW_MODE_ADHOC:
74 if (priv->rtllib->state == RTLLIB_LINKED)
75 msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
76 else
77 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
78 break;
79 case IW_MODE_MASTER:
80 if (priv->rtllib->state == RTLLIB_LINKED)
81 msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
82 else
83 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
84 break;
85 default:
86 break;
87 }
88
d8ae1967 89 rtl92e_writeb(dev, MSR, msr);
94a79942
LF		 90 if (priv->rtllib->LedControlHandler)
91 priv->rtllib->LedControlHandler(dev, LedAction);
92}
93
61fea239 94void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
94a79942 95{
52629477 96 struct r8192_priv *priv = rtllib_priv(dev);
94a79942 97
52629477
LF		 98 switch (variable) {
99 case HW_VAR_BSSID:
867510bd
MP		 100 /* BSSIDR 2 byte alignment */
101 rtl92e_writew(dev, BSSIDR, *(u16 *)val);
102 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2));
94a79942
LF		 103 break;
104
52629477
LF		 105 case HW_VAR_MEDIA_STATUS:
106 {
107 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
b59a4ca3 108 u8 btMsr = rtl92e_readb(dev, MSR);
94a79942 109
52629477 110 btMsr &= 0xfc;
94a79942 111
52629477
LF		 112 switch (OpMode) {
113 case RT_OP_MODE_INFRASTRUCTURE:
114 btMsr |= MSR_INFRA;
52629477 115 break;
94a79942 116
52629477
LF		 117 case RT_OP_MODE_IBSS:
118 btMsr |= MSR_ADHOC;
119 break;
94a79942 120
52629477
LF		 121 case RT_OP_MODE_AP:
122 btMsr |= MSR_AP;
52629477 123 break;
94a79942 124
52629477
LF		 125 default:
126 btMsr |= MSR_NOLINK;
127 break;
128 }
94a79942 129
d8ae1967 130 rtl92e_writeb(dev, MSR, btMsr);
94a79942 131
52629477
LF		 132 }
133 break;
94a79942 134
52629477
LF		 135 case HW_VAR_CECHK_BSSID:
136 {
137 u32 RegRCR, Type;
94a79942 138
4db665e5 139 Type = val[0];
99aa47e0 140 RegRCR = rtl92e_readl(dev, RCR);
52629477 141 priv->ReceiveConfig = RegRCR;
94a79942 142
52629477
LF		 143 if (Type == true)
144 RegRCR |= (RCR_CBSSID);
145 else if (Type == false)
146 RegRCR &= (~RCR_CBSSID);
94a79942 147
8ea54100 148 rtl92e_writel(dev, RCR, RegRCR);
52629477 149 priv->ReceiveConfig = RegRCR;
94a79942 150
52629477
LF		 151 }
152 break;
94a79942 153
52629477 154 case HW_VAR_SLOT_TIME:
94a79942 155
52629477 156 priv->slot_time = val[0];
d8ae1967 157 rtl92e_writeb(dev, SLOT_TIME, val[0]);
94a79942 158
94a79942
LF		 159 break;
160
52629477
LF		 161 case HW_VAR_ACK_PREAMBLE:
162 {
163 u32 regTmp;
3a6b70c3 164
4db665e5 165 priv->short_preamble = (bool)*val;
52629477
LF		 166 regTmp = priv->basic_rate;
167 if (priv->short_preamble)
168 regTmp |= BRSR_AckShortPmb;
8ea54100 169 rtl92e_writel(dev, RRSR, regTmp);
94a79942 170 break;
52629477 171 }
94a79942 172
52629477 173 case HW_VAR_CPU_RST:
8ea54100 174 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
94a79942
LF		 175 break;
176
52629477
LF		 177 case HW_VAR_AC_PARAM:
178 {
4db665e5 179 u8 pAcParam = *val;
52629477
LF		 180 u32 eACI = pAcParam;
181 u8 u1bAIFS;
182 u32 u4bAcParam;
183 u8 mode = priv->rtllib->mode;
35e33b04 184 struct rtllib_qos_parameters *qop =
52629477
LF		 185 &priv->rtllib->current_network.qos_data.parameters;
186
35e33b04 187 u1bAIFS = qop->aifs[pAcParam] *
52629477
LF		 188 ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
189
7842c2d5 190 rtl92e_dm_init_edca_turbo(dev);
52629477 191
35e33b04
MK		 192 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
193 AC_PARAM_TXOP_LIMIT_OFFSET) |
194 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
195 AC_PARAM_ECW_MAX_OFFSET) |
196 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
197 AC_PARAM_ECW_MIN_OFFSET) |
198 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
52629477
LF		 199
200 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
201 __func__, eACI, u4bAcParam);
202 switch (eACI) {
203 case AC1_BK:
8ea54100 204 rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
52629477 205 break;
94a79942 206
52629477 207 case AC0_BE:
8ea54100 208 rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
52629477 209 break;
94a79942 210
52629477 211 case AC2_VI:
8ea54100 212 rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
52629477 213 break;
94a79942 214
52629477 215 case AC3_VO:
8ea54100 216 rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
52629477 217 break;
94a79942 218
52629477 219 default:
d69d2054
MK		 220 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
221 eACI);
52629477
LF		 222 break;
223 }
224 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
4db665e5 225 &pAcParam);
52629477
LF		 226 break;
227 }
94a79942 228
52629477
LF		 229 case HW_VAR_ACM_CTRL:
230 {
231 struct rtllib_qos_parameters *qos_parameters =
232 &priv->rtllib->current_network.qos_data.parameters;
4db665e5 233 u8 pAcParam = *val;
52629477
LF		 234 u32 eACI = pAcParam;
235 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
236 (qos_parameters->aifs[0]);
237 u8 acm = pAciAifsn->f.acm;
b59a4ca3 238 u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl);
52629477
LF		 239
240 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
241 __func__, eACI);
242 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
243
244 if (acm) {
245 switch (eACI) {
94a79942 246 case AC0_BE:
52629477 247 AcmCtrl |= AcmHw_BeqEn;
94a79942
LF		 248 break;
249
250 case AC2_VI:
52629477 251 AcmCtrl |= AcmHw_ViqEn;
94a79942
LF		 252 break;
253
254 case AC3_VO:
52629477 255 AcmCtrl |= AcmHw_VoqEn;
94a79942
LF		 256 break;
257
258 default:
0822339b
MK		 259 RT_TRACE(COMP_QOS,
260 "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
261 eACI);
94a79942
LF		 262 break;
263 }
52629477
LF		 264 } else {
265 switch (eACI) {
266 case AC0_BE:
267 AcmCtrl &= (~AcmHw_BeqEn);
268 break;
94a79942 269
52629477
LF		 270 case AC2_VI:
271 AcmCtrl &= (~AcmHw_ViqEn);
272 break;
94a79942 273
52629477
LF		 274 case AC3_VO:
275 AcmCtrl &= (~AcmHw_BeqEn);
276 break;
94a79942 277
52629477
LF		 278 default:
279 break;
94a79942 280 }
94a79942 281 }
52629477 282
0822339b
MK		 283 RT_TRACE(COMP_QOS,
284 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
285 AcmCtrl);
d8ae1967 286 rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl);
94a79942 287 break;
52629477 288 }
94a79942 289
52629477 290 case HW_VAR_SIFS:
d8ae1967
MK		 291 rtl92e_writeb(dev, SIFS, val[0]);
292 rtl92e_writeb(dev, SIFS+1, val[0]);
94a79942
LF		 293 break;
294
52629477
LF		 295 case HW_VAR_RF_TIMING:
296 {
4db665e5 297 u8 Rf_Timing = *val;
3a6b70c3 298
d8ae1967 299 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
94a79942 300 break;
52629477 301 }
94a79942 302
52629477 303 default:
94a79942
LF		 304 break;
305 }
306
307}
308
676b8bae 309static void _rtl92e_read_eeprom_info(struct net_device *dev)
94a79942
LF		 310{
311 struct r8192_priv *priv = rtllib_priv(dev);
06c11107 312 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
52629477
LF		 313 u8 tempval;
314 u8 ICVer8192, ICVer8256;
315 u16 i, usValue, IC_Version;
316 u16 EEPROMId;
3a6b70c3 317
676b8bae 318 RT_TRACE(COMP_INIT, "====> _rtl92e_read_eeprom_info\n");
94a79942 319
68cb7b7a 320 EEPROMId = rtl92e_eeprom_read(dev, 0);
52629477 321 if (EEPROMId != RTL8190_EEPROM_ID) {
3b4140af
MK		 322 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
323 EEPROMId);
52629477
LF		 324 priv->AutoloadFailFlag = true;
325 } else {
326 priv->AutoloadFailFlag = false;
94a79942
LF		 327 }
328
52629477 329 if (!priv->AutoloadFailFlag) {
68cb7b7a
MK		 330 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
331 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
94a79942 332
68cb7b7a
MK		 333 usValue = rtl92e_eeprom_read(dev,
334 (u16)(EEPROM_Customer_ID>>1)) >> 8;
52629477 335 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
68cb7b7a
MK		 336 usValue = rtl92e_eeprom_read(dev,
337 EEPROM_ICVersion_ChannelPlan>>1);
94a79942 338 priv->eeprom_ChannelPlan = usValue&0xff;
0c401c1d 339 IC_Version = (usValue & 0xff00)>>8;
94a79942 340
94a79942 341 ICVer8192 = (IC_Version&0xf);
0c401c1d 342 ICVer8256 = (IC_Version & 0xf0)>>4;
94a79942
LF		 343 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
344 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
52629477 345 if (ICVer8192 == 0x2) {
94a79942 346 if (ICVer8256 == 0x5)
52629477 347 priv->card_8192_version = VERSION_8190_BE;
94a79942 348 }
52629477
LF		 349 switch (priv->card_8192_version) {
350 case VERSION_8190_BD:
351 case VERSION_8190_BE:
352 break;
353 default:
354 priv->card_8192_version = VERSION_8190_BD;
355 break;
94a79942 356 }
52629477
LF		 357 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
358 priv->card_8192_version);
359 } else {
94a79942
LF		 360 priv->card_8192_version = VERSION_8190_BD;
361 priv->eeprom_vid = 0;
362 priv->eeprom_did = 0;
363 priv->eeprom_CustomerID = 0;
364 priv->eeprom_ChannelPlan = 0;
365 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
366 }
367
368 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
369 RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
52629477
LF		 370 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
371 priv->eeprom_CustomerID);
372
373 if (!priv->AutoloadFailFlag) {
374 for (i = 0; i < 6; i += 2) {
68cb7b7a 375 usValue = rtl92e_eeprom_read(dev,
4db665e5 376 (EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1);
52629477 377 *(u16 *)(&dev->dev_addr[i]) = usValue;
94a79942
LF		 378 }
379 } else {
b57ceb19 380 ether_addr_copy(dev->dev_addr, bMac_Tmp_Addr);
94a79942
LF		 381 }
382
52629477
LF		 383 RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
384 dev->dev_addr);
94a79942 385
52629477 386 if (priv->card_8192_version > VERSION_8190_BD)
94a79942 387 priv->bTXPowerDataReadFromEEPORM = true;
52629477 388 else
94a79942 389 priv->bTXPowerDataReadFromEEPORM = false;
94a79942
LF		 390
391 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
392
52629477
LF		 393 if (priv->card_8192_version > VERSION_8190_BD) {
394 if (!priv->AutoloadFailFlag) {
68cb7b7a
MK		 395 tempval = (rtl92e_eeprom_read(dev,
396 (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
94a79942
LF		 397 priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
398
399 if (tempval&0x80)
400 priv->rf_type = RF_1T2R;
401 else
402 priv->rf_type = RF_2T4R;
52629477 403 } else {
94a79942
LF		 404 priv->EEPROMLegacyHTTxPowerDiff = 0x04;
405 }
406 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
407 priv->EEPROMLegacyHTTxPowerDiff);
408
409 if (!priv->AutoloadFailFlag)
68cb7b7a 410 priv->EEPROMThermalMeter = (u8)(((rtl92e_eeprom_read(dev,
52629477
LF		 411 (EEPROM_ThermalMeter>>1))) &
412 0xff00)>>8);
94a79942 413 else
94a79942 414 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
52629477
LF		 415 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
416 priv->EEPROMThermalMeter);
417 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
418
419 if (priv->epromtype == EEPROM_93C46) {
420 if (!priv->AutoloadFailFlag) {
68cb7b7a 421 usValue = rtl92e_eeprom_read(dev,
0c401c1d 422 EEPROM_TxPwDiff_CrystalCap >> 1);
94a79942 423 priv->EEPROMAntPwDiff = (usValue&0x0fff);
52629477
LF		 424 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
425 >> 12);
426 } else {
427 priv->EEPROMAntPwDiff =
428 EEPROM_Default_AntTxPowerDiff;
429 priv->EEPROMCrystalCap =
430 EEPROM_Default_TxPwDiff_CrystalCap;
94a79942 431 }
52629477
LF		 432 RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
433 priv->EEPROMAntPwDiff);
434 RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
435 priv->EEPROMCrystalCap);
436
437 for (i = 0; i < 14; i += 2) {
438 if (!priv->AutoloadFailFlag)
68cb7b7a 439 usValue = rtl92e_eeprom_read(dev,
4db665e5 440 (EEPROM_TxPwIndex_CCK + i) >> 1);
52629477
LF		 441 else
442 usValue = EEPROM_Default_TxPower;
443 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
444 usValue;
0822339b
MK		 445 RT_TRACE(COMP_INIT,
446 "CCK Tx Power Level, Index %d = 0x%02x\n",
447 i, priv->EEPROMTxPowerLevelCCK[i]);
448 RT_TRACE(COMP_INIT,
449 "CCK Tx Power Level, Index %d = 0x%02x\n",
450 i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
94a79942 451 }
52629477
LF		 452 for (i = 0; i < 14; i += 2) {
453 if (!priv->AutoloadFailFlag)
68cb7b7a 454 usValue = rtl92e_eeprom_read(dev,
4db665e5 455 (EEPROM_TxPwIndex_OFDM_24G + i) >> 1);
52629477
LF		 456 else
457 usValue = EEPROM_Default_TxPower;
458 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
459 = usValue;
0822339b
MK		 460 RT_TRACE(COMP_INIT,
461 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
462 i, priv->EEPROMTxPowerLevelOFDM24G[i]);
463 RT_TRACE(COMP_INIT,
464 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
465 i + 1,
52629477 466 priv->EEPROMTxPowerLevelOFDM24G[i+1]);
94a79942 467 }
94a79942 468 }
52629477
LF		 469 if (priv->epromtype == EEPROM_93C46) {
470 for (i = 0; i < 14; i++) {
471 priv->TxPowerLevelCCK[i] =
472 priv->EEPROMTxPowerLevelCCK[i];
473 priv->TxPowerLevelOFDM24G[i] =
474 priv->EEPROMTxPowerLevelOFDM24G[i];
94a79942 475 }
52629477
LF		 476 priv->LegacyHTTxPowerDiff =
477 priv->EEPROMLegacyHTTxPowerDiff;
478 priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
479 0xf);
0c401c1d
AM		 480 priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
481 0xf0) >> 4;
482 priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
483 0xf00) >> 8;
94a79942 484 priv->CrystalCap = priv->EEPROMCrystalCap;
52629477
LF		 485 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
486 0xf);
0c401c1d
AM		 487 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
488 0xf0) >> 4;
52629477
LF		 489 } else if (priv->epromtype == EEPROM_93C56) {
490
491 for (i = 0; i < 3; i++) {
492 priv->TxPowerLevelCCK_A[i] =
493 priv->EEPROMRfACCKChnl1TxPwLevel[0];
494 priv->TxPowerLevelOFDM24G_A[i] =
495 priv->EEPROMRfAOfdmChnlTxPwLevel[0];
496 priv->TxPowerLevelCCK_C[i] =
497 priv->EEPROMRfCCCKChnl1TxPwLevel[0];
498 priv->TxPowerLevelOFDM24G_C[i] =
499 priv->EEPROMRfCOfdmChnlTxPwLevel[0];
94a79942 500 }
52629477
LF		 501 for (i = 3; i < 9; i++) {
502 priv->TxPowerLevelCCK_A[i] =
503 priv->EEPROMRfACCKChnl1TxPwLevel[1];
504 priv->TxPowerLevelOFDM24G_A[i] =
505 priv->EEPROMRfAOfdmChnlTxPwLevel[1];
506 priv->TxPowerLevelCCK_C[i] =
507 priv->EEPROMRfCCCKChnl1TxPwLevel[1];
508 priv->TxPowerLevelOFDM24G_C[i] =
509 priv->EEPROMRfCOfdmChnlTxPwLevel[1];
94a79942 510 }
52629477
LF		 511 for (i = 9; i < 14; i++) {
512 priv->TxPowerLevelCCK_A[i] =
513 priv->EEPROMRfACCKChnl1TxPwLevel[2];
514 priv->TxPowerLevelOFDM24G_A[i] =
515 priv->EEPROMRfAOfdmChnlTxPwLevel[2];
516 priv->TxPowerLevelCCK_C[i] =
517 priv->EEPROMRfCCCKChnl1TxPwLevel[2];
518 priv->TxPowerLevelOFDM24G_C[i] =
519 priv->EEPROMRfCOfdmChnlTxPwLevel[2];
94a79942 520 }
52629477 521 for (i = 0; i < 14; i++)
0822339b
MK		 522 RT_TRACE(COMP_INIT,
523 "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
524 i, priv->TxPowerLevelCCK_A[i]);
52629477 525 for (i = 0; i < 14; i++)
0822339b
MK		 526 RT_TRACE(COMP_INIT,
527 "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
528 i, priv->TxPowerLevelOFDM24G_A[i]);
52629477 529 for (i = 0; i < 14; i++)
0822339b
MK		 530 RT_TRACE(COMP_INIT,
531 "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
532 i, priv->TxPowerLevelCCK_C[i]);
52629477 533 for (i = 0; i < 14; i++)
0822339b
MK		 534 RT_TRACE(COMP_INIT,
535 "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
536 i, priv->TxPowerLevelOFDM24G_C[i]);
52629477
LF		 537 priv->LegacyHTTxPowerDiff =
538 priv->EEPROMLegacyHTTxPowerDiff;
94a79942
LF		 539 priv->AntennaTxPwDiff[0] = 0;
540 priv->AntennaTxPwDiff[1] = 0;
541 priv->AntennaTxPwDiff[2] = 0;
542 priv->CrystalCap = priv->EEPROMCrystalCap;
52629477
LF		 543 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
544 0xf);
0c401c1d
AM		 545 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
546 0xf0) >> 4;
94a79942
LF		 547 }
548 }
549
52629477
LF		 550 if (priv->rf_type == RF_1T2R) {
551 /* no matter what checkpatch says, the braces are needed */
94a79942 552 RT_TRACE(COMP_INIT, "\n1T2R config\n");
52629477 553 } else if (priv->rf_type == RF_2T4R) {
94a79942
LF		 554 RT_TRACE(COMP_INIT, "\n2T4R config\n");
555 }
556
2e3ba83a 557 rtl92e_init_adaptive_rate(dev);
94a79942 558
52629477 559 priv->rf_chip = RF_8256;
94a79942
LF		 560
561 if (priv->RegChannelPlan == 0xf)
94a79942 562 priv->ChannelPlan = priv->eeprom_ChannelPlan;
94a79942 563 else
94a79942 564 priv->ChannelPlan = priv->RegChannelPlan;
94a79942 565
52629477 566 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
94a79942 567 priv->CustomerID = RT_CID_DLINK;
94a79942 568
52629477
LF		 569 switch (priv->eeprom_CustomerID) {
570 case EEPROM_CID_DEFAULT:
571 priv->CustomerID = RT_CID_DEFAULT;
572 break;
573 case EEPROM_CID_CAMEO:
574 priv->CustomerID = RT_CID_819x_CAMEO;
575 break;
576 case EEPROM_CID_RUNTOP:
577 priv->CustomerID = RT_CID_819x_RUNTOP;
578 break;
579 case EEPROM_CID_NetCore:
580 priv->CustomerID = RT_CID_819x_Netcore;
581 break;
582 case EEPROM_CID_TOSHIBA:
583 priv->CustomerID = RT_CID_TOSHIBA;
584 if (priv->eeprom_ChannelPlan&0x80)
585 priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
586 else
587 priv->ChannelPlan = 0x0;
588 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
589 priv->ChannelPlan);
590 break;
591 case EEPROM_CID_Nettronix:
592 priv->ScanDelay = 100;
593 priv->CustomerID = RT_CID_Nettronix;
594 break;
595 case EEPROM_CID_Pronet:
596 priv->CustomerID = RT_CID_PRONET;
597 break;
598 case EEPROM_CID_DLINK:
599 priv->CustomerID = RT_CID_DLINK;
600 break;
94a79942 601
52629477
LF		 602 case EEPROM_CID_WHQL:
603 break;
604 default:
605 break;
94a79942
LF		 606 }
607
608 if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
609 priv->ChannelPlan = 0;
94a79942 610 priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
94a79942 611
52629477 612 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
94a79942
LF		 613 priv->rtllib->bSupportRemoteWakeUp = true;
614 else
615 priv->rtllib->bSupportRemoteWakeUp = false;
616
617 RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
52629477 618 RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
94a79942 619 RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
94a79942
LF		 620}
621
b095be37 622void rtl92e_get_eeprom_size(struct net_device *dev)
94a79942 623{
52629477 624 u16 curCR;
94a79942 625 struct r8192_priv *priv = rtllib_priv(dev);
52629477 626
94a79942 627 RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
90be652c 628 curCR = rtl92e_readw(dev, EPROM_CMD);
52629477
LF		 629 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
630 curCR);
631 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
632 EEPROM_93C46;
633 RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
634 priv->epromtype);
676b8bae 635 _rtl92e_read_eeprom_info(dev);
94a79942
LF		 636}
637
f588a225 638static void _rtl92e_hwconfig(struct net_device *dev)
94a79942
LF		 639{
640 u32 regRATR = 0, regRRSR = 0;
641 u8 regBwOpMode = 0, regTmp = 0;
642 struct r8192_priv *priv = rtllib_priv(dev);
643
52629477 644 switch (priv->rtllib->mode) {
94a79942
LF		 645 case WIRELESS_MODE_B:
646 regBwOpMode = BW_OPMODE_20MHZ;
647 regRATR = RATE_ALL_CCK;
648 regRRSR = RATE_ALL_CCK;
649 break;
650 case WIRELESS_MODE_A:
52629477 651 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
94a79942
LF		 652 regRATR = RATE_ALL_OFDM_AG;
653 regRRSR = RATE_ALL_OFDM_AG;
654 break;
655 case WIRELESS_MODE_G:
656 regBwOpMode = BW_OPMODE_20MHZ;
657 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
658 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
659 break;
660 case WIRELESS_MODE_AUTO:
661 case WIRELESS_MODE_N_24G:
662 regBwOpMode = BW_OPMODE_20MHZ;
52629477
LF		 663 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
664 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
94a79942
LF		 665 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
666 break;
667 case WIRELESS_MODE_N_5G:
668 regBwOpMode = BW_OPMODE_5G;
52629477
LF		 669 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
670 RATE_ALL_OFDM_2SS;
94a79942
LF		 671 regRRSR = RATE_ALL_OFDM_AG;
672 break;
673 default:
674 regBwOpMode = BW_OPMODE_20MHZ;
675 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
676 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
677 break;
678 }
679
d8ae1967 680 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
94a79942 681 {
7949be66 682 u32 ratr_value;
3a6b70c3 683
94a79942
LF		 684 ratr_value = regRATR;
685 if (priv->rf_type == RF_1T2R)
94a79942 686 ratr_value &= ~(RATE_ALL_OFDM_2SS);
8ea54100 687 rtl92e_writel(dev, RATR0, ratr_value);
d8ae1967 688 rtl92e_writeb(dev, UFWP, 1);
94a79942 689 }
b59a4ca3 690 regTmp = rtl92e_readb(dev, 0x313);
94a79942 691 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
8ea54100 692 rtl92e_writel(dev, RRSR, regRRSR);
94a79942 693
6dee0c88
MK		 694 rtl92e_writew(dev, RETRY_LIMIT,
695 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
696 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
94a79942
LF		 697}
698
46026629 699bool rtl92e_start_adapter(struct net_device *dev)
94a79942
LF		 700{
701 struct r8192_priv *priv = rtllib_priv(dev);
702 u32 ulRegRead;
703 bool rtStatus = true;
704 u8 tmpvalue;
52629477 705 u8 ICVersion, SwitchingRegulatorOutput;
94a79942 706 bool bfirmwareok = true;
94a79942
LF		 707 u32 tmpRegA, tmpRegC, TempCCk;
708 int i = 0;
709 u32 retry_times = 0;
710
711 RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
712 priv->being_init_adapter = true;
713
94a79942 714start:
36154dc3 715 rtl92e_reset_desc_ring(dev);
94a79942 716 priv->Rf_Mode = RF_OP_By_SW_3wire;
52629477 717 if (priv->ResetProgress == RESET_TYPE_NORESET) {
d8ae1967 718 rtl92e_writeb(dev, ANAPAR, 0x37);
52629477
LF		 719 mdelay(500);
720 }
6167a6c8 721 priv->pFirmware->status = FW_STATUS_0_INIT;
94a79942 722
4bb01423 723 if (priv->RegRfOff)
94a79942
LF		 724 priv->rtllib->eRFPowerState = eRfOff;
725
99aa47e0 726 ulRegRead = rtl92e_readl(dev, CPU_GEN);
6167a6c8 727 if (priv->pFirmware->status == FW_STATUS_0_INIT)
94a79942 728 ulRegRead |= CPU_GEN_SYSTEM_RESET;
6167a6c8 729 else if (priv->pFirmware->status == FW_STATUS_5_READY)
94a79942
LF		 730 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
731 else
3b4140af 732 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
6167a6c8 733 __func__, priv->pFirmware->status);
94a79942 734
8ea54100 735 rtl92e_writel(dev, CPU_GEN, ulRegRead);
94a79942 736
b59a4ca3 737 ICVersion = rtl92e_readb(dev, IC_VERRSION);
52629477 738 if (ICVersion >= 0x4) {
b59a4ca3 739 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
52629477 740 if (SwitchingRegulatorOutput != 0xb8) {
d8ae1967 741 rtl92e_writeb(dev, SWREGULATOR, 0xa8);
94a79942 742 mdelay(1);
d8ae1967 743 rtl92e_writeb(dev, SWREGULATOR, 0xb8);
94a79942
LF		 744 }
745 }
94a79942 746 RT_TRACE(COMP_INIT, "BB Config Start!\n");
2949353d 747 rtStatus = rtl92e_config_bb(dev);
4bb01423 748 if (!rtStatus) {
3b4140af 749 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
94a79942
LF		 750 return rtStatus;
751 }
52629477 752 RT_TRACE(COMP_INIT, "BB Config Finished!\n");
94a79942
LF		 753
754 priv->LoopbackMode = RTL819X_NO_LOOPBACK;
52629477 755 if (priv->ResetProgress == RESET_TYPE_NORESET) {
99aa47e0 756 ulRegRead = rtl92e_readl(dev, CPU_GEN);
52629477
LF		 757 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
758 ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
759 CPU_GEN_NO_LOOPBACK_SET);
760 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
761 ulRegRead |= CPU_CCK_LOOPBACK;
762 else
3b4140af
MK		 763 netdev_err(dev, "%s: Invalid loopback mode setting.\n",
764 __func__);
94a79942 765
8ea54100 766 rtl92e_writel(dev, CPU_GEN, ulRegRead);
94a79942 767
52629477 768 udelay(500);
94a79942 769 }
f588a225 770 _rtl92e_hwconfig(dev);
d8ae1967 771 rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
94a79942 772
d8ae1967
MK		 773 rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
774 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
8ea54100 775 rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
6dee0c88 776 rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
8ea54100
MK		 777 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
778
779 rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
780 RSVD_FW_QUEUE_PAGE_BK_SHIFT |
781 NUM_OF_PAGE_IN_FW_QUEUE_BE <<
782 RSVD_FW_QUEUE_PAGE_BE_SHIFT |
783 NUM_OF_PAGE_IN_FW_QUEUE_VI <<
784 RSVD_FW_QUEUE_PAGE_VI_SHIFT |
785 NUM_OF_PAGE_IN_FW_QUEUE_VO <<
786 RSVD_FW_QUEUE_PAGE_VO_SHIFT);
787 rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
788 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
789 rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
790 NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
791 RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
792 NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
793 RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
94a79942 794
94199b35 795 rtl92e_tx_enable(dev);
630268b7 796 rtl92e_rx_enable(dev);
99aa47e0 797 ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR)) |
52629477 798 RATE_ALL_OFDM_AG | RATE_ALL_CCK;
8ea54100
MK		 799 rtl92e_writel(dev, RRSR, ulRegRead);
800 rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
94a79942 801
d8ae1967 802 rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
94a79942
LF		 803
804 if (priv->ResetProgress == RESET_TYPE_NORESET)
35bf848f 805 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
358e4ee1 806 rtl92e_cam_reset(dev);
94a79942
LF		 807 {
808 u8 SECR_value = 0x0;
3a6b70c3 809
94a79942
LF		 810 SECR_value |= SCR_TxEncEnable;
811 SECR_value |= SCR_RxDecEnable;
812 SECR_value |= SCR_NoSKMC;
d8ae1967 813 rtl92e_writeb(dev, SECR, SECR_value);
94a79942 814 }
6dee0c88
MK		 815 rtl92e_writew(dev, ATIMWND, 2);
816 rtl92e_writew(dev, BCN_INTERVAL, 100);
94a79942
LF		 817 {
818 int i;
3a6b70c3 819
52629477 820 for (i = 0; i < QOS_QUEUE_NUM; i++)
8ea54100 821 rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
94a79942 822 }
d8ae1967 823 rtl92e_writeb(dev, 0xbe, 0xc0);
94a79942 824
0efe7104 825 rtl92e_config_mac(dev);
94a79942
LF		 826
827 if (priv->card_8192_version > (u8) VERSION_8190_BD) {
78cc16fa 828 rtl92e_get_tx_power(dev);
5aa1b9ca 829 rtl92e_set_tx_power(dev, priv->chan);
94a79942
LF		 830 }
831
b59a4ca3 832 tmpvalue = rtl92e_readb(dev, IC_VERRSION);
52629477 833 priv->IC_Cut = tmpvalue;
94a79942 834 RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
52629477
LF		 835 if (priv->IC_Cut >= IC_VersionCut_D) {
836 if (priv->IC_Cut == IC_VersionCut_D) {
837 /* no matter what checkpatch says, braces are needed */
94a79942 838 RT_TRACE(COMP_INIT, "D-cut\n");
52629477 839 } else if (priv->IC_Cut == IC_VersionCut_E) {
94a79942
LF		 840 RT_TRACE(COMP_INIT, "E-cut\n");
841 }
842 } else {
843 RT_TRACE(COMP_INIT, "Before C-cut\n");
844 }
845
846 RT_TRACE(COMP_INIT, "Load Firmware!\n");
b8216b69 847 bfirmwareok = rtl92e_init_fw(dev);
94a79942
LF		 848 if (!bfirmwareok) {
849 if (retry_times < 10) {
850 retry_times++;
851 goto start;
852 } else {
853 rtStatus = false;
854 goto end;
855 }
856 }
857 RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
858 if (priv->ResetProgress == RESET_TYPE_NORESET) {
859 RT_TRACE(COMP_INIT, "RF Config Started!\n");
31aebbe2 860 rtStatus = rtl92e_config_phy(dev);
4bb01423 861 if (!rtStatus) {
3b4140af 862 netdev_info(dev, "RF Config failed\n");
94a79942
LF		 863 return rtStatus;
864 }
865 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
866 }
94a79942 867
153f9ddb
MK		 868 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
869 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
94a79942 870
d8ae1967 871 rtl92e_writeb(dev, 0x87, 0x0);
94a79942 872
4bb01423 873 if (priv->RegRfOff) {
52629477
LF		 874 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
875 "%s(): Turn off RF for RegRfOff ----------\n",
876 __func__);
2937a5d2 877 rtl92e_set_rf_state(dev, eRfOff, RF_CHANGE_BY_SW);
94a79942 878 } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
0822339b
MK		 879 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
880 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
881 __func__, priv->rtllib->RfOffReason);
2937a5d2 882 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
94a79942 883 } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
0822339b
MK		 884 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
885 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
886 __func__, priv->rtllib->RfOffReason);
2937a5d2 887 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
94a79942 888 } else {
52629477
LF		 889 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
890 __func__);
94a79942
LF		 891 priv->rtllib->eRFPowerState = eRfOn;
892 priv->rtllib->RfOffReason = 0;
94a79942
LF		 893 }
894
895 if (priv->rtllib->FwRWRF)
896 priv->Rf_Mode = RF_OP_By_FW;
897 else
898 priv->Rf_Mode = RF_OP_By_SW_3wire;
899
52629477 900 if (priv->ResetProgress == RESET_TYPE_NORESET) {
5a9f18cf 901 rtl92e_dm_init_txpower_tracking(dev);
94a79942 902
52629477 903 if (priv->IC_Cut >= IC_VersionCut_D) {
3c351fec
MK		 904 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
905 bMaskDWord);
906 tmpRegC = rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance,
907 bMaskDWord);
52629477 908 for (i = 0; i < TxBBGainTableLength; i++) {
20b7ec09 909 if (tmpRegA == dm_tx_bb_gain[i]) {
52629477
LF		 910 priv->rfa_txpowertrackingindex = (u8)i;
911 priv->rfa_txpowertrackingindex_real =
912 (u8)i;
913 priv->rfa_txpowertracking_default =
914 priv->rfa_txpowertrackingindex;
94a79942
LF		 915 break;
916 }
917 }
918
3c351fec
MK		 919 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
920 bMaskByte2);
94a79942
LF		 921
922 for (i = 0; i < CCKTxBBGainTableLength; i++) {
20b7ec09 923 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
52629477 924 priv->CCKPresentAttentuation_20Mdefault = (u8)i;
94a79942
LF		 925 break;
926 }
927 }
928 priv->CCKPresentAttentuation_40Mdefault = 0;
929 priv->CCKPresentAttentuation_difference = 0;
52629477
LF		 930 priv->CCKPresentAttentuation =
931 priv->CCKPresentAttentuation_20Mdefault;
0822339b
MK		 932 RT_TRACE(COMP_POWER_TRACKING,
933 "priv->rfa_txpowertrackingindex_initial = %d\n",
52629477 934 priv->rfa_txpowertrackingindex);
0822339b
MK		 935 RT_TRACE(COMP_POWER_TRACKING,
936 "priv->rfa_txpowertrackingindex_real__initial = %d\n",
52629477 937 priv->rfa_txpowertrackingindex_real);
0822339b
MK		 938 RT_TRACE(COMP_POWER_TRACKING,
939 "priv->CCKPresentAttentuation_difference_initial = %d\n",
52629477 940 priv->CCKPresentAttentuation_difference);
0822339b
MK		 941 RT_TRACE(COMP_POWER_TRACKING,
942 "priv->CCKPresentAttentuation_initial = %d\n",
52629477 943 priv->CCKPresentAttentuation);
94a79942
LF		 944 priv->btxpower_tracking = false;
945 }
946 }
b74299cd 947 rtl92e_irq_enable(dev);
94a79942
LF		 948end:
949 priv->being_init_adapter = false;
950 return rtStatus;
951}
952
479e2b8c 953static void _rtl92e_net_update(struct net_device *dev)
94a79942
LF		 954{
955
956 struct r8192_priv *priv = rtllib_priv(dev);
957 struct rtllib_network *net;
958 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
959 u16 rate_config = 0;
960
961 net = &priv->rtllib->current_network;
122fe9f1 962 rtl92e_config_rate(dev, &rate_config);
94a79942
LF		 963 priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
964 priv->basic_rate = rate_config &= 0x15f;
867510bd
MP		 965 rtl92e_writew(dev, BSSIDR, *(u16 *)net->bssid);
966 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(net->bssid + 2));
94a79942
LF		 967
968 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
6dee0c88
MK		 969 rtl92e_writew(dev, ATIMWND, 2);
970 rtl92e_writew(dev, BCN_DMATIME, 256);
971 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
972 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
d8ae1967 973 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
94a79942
LF		 974
975 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
976 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
977
6dee0c88 978 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
94a79942
LF		 979 }
980}
981
b974b289 982void rtl92e_link_change(struct net_device *dev)
94a79942
LF		 983{
984 struct r8192_priv *priv = rtllib_priv(dev);
52629477 985 struct rtllib_device *ieee = priv->rtllib;
94a79942
LF		 986
987 if (!priv->up)
52629477 988 return;
94a79942
LF		 989
990 if (ieee->state == RTLLIB_LINKED) {
479e2b8c 991 _rtl92e_net_update(dev);
94a79942 992 priv->ops->update_ratr_table(dev);
4c29207a
MK		 993 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
994 (ieee->pairwise_key_type == KEY_TYPE_WEP104))
37420932 995 rtl92e_enable_hw_security_config(dev);
94a79942 996 } else {
d8ae1967 997 rtl92e_writeb(dev, 0x173, 0);
94a79942 998 }
6ded6893 999 _rtl92e_update_msr(dev);
94a79942
LF		 1000
1001 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
7949be66 1002 u32 reg;
3a6b70c3 1003
99aa47e0 1004 reg = rtl92e_readl(dev, RCR);
94a79942
LF		 1005 if (priv->rtllib->state == RTLLIB_LINKED) {
1006 if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
52629477
LF		 1007 ;
1008 else
94a79942
LF		 1009 priv->ReceiveConfig = reg |= RCR_CBSSID;
1010 } else
1011 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1012
8ea54100 1013 rtl92e_writel(dev, RCR, reg);
94a79942
LF		 1014 }
1015}
1016
33e1748d
MK		 1017void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
1018 bool WriteIntoReg)
94a79942 1019{
52629477 1020 struct r8192_priv *priv = rtllib_priv(dev);
94a79942 1021
52629477
LF		 1022 if (bAllowAllDA)
1023 priv->ReceiveConfig |= RCR_AAP;
1024 else
1025 priv->ReceiveConfig &= ~RCR_AAP;
94a79942 1026
52629477 1027 if (WriteIntoReg)
8ea54100 1028 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
94a79942
LF		 1029}
1030
615c8d8d 1031static u8 _rtl92e_rate_mgn_to_hw(u8 rate)
94a79942
LF		 1032{
1033 u8 ret = DESC90_RATE1M;
1034
1035 switch (rate) {
1036 case MGN_1M:
1037 ret = DESC90_RATE1M;
1038 break;
1039 case MGN_2M:
1040 ret = DESC90_RATE2M;
1041 break;
1042 case MGN_5_5M:
1043 ret = DESC90_RATE5_5M;
1044 break;
1045 case MGN_11M:
1046 ret = DESC90_RATE11M;
1047 break;
1048 case MGN_6M:
1049 ret = DESC90_RATE6M;
1050 break;
1051 case MGN_9M:
1052 ret = DESC90_RATE9M;
1053 break;
1054 case MGN_12M:
1055 ret = DESC90_RATE12M;
1056 break;
1057 case MGN_18M:
1058 ret = DESC90_RATE18M;
1059 break;
1060 case MGN_24M:
1061 ret = DESC90_RATE24M;
1062 break;
1063 case MGN_36M:
1064 ret = DESC90_RATE36M;
1065 break;
1066 case MGN_48M:
1067 ret = DESC90_RATE48M;
1068 break;
1069 case MGN_54M:
1070 ret = DESC90_RATE54M;
1071 break;
1072 case MGN_MCS0:
1073 ret = DESC90_RATEMCS0;
1074 break;
1075 case MGN_MCS1:
1076 ret = DESC90_RATEMCS1;
1077 break;
1078 case MGN_MCS2:
1079 ret = DESC90_RATEMCS2;
1080 break;
1081 case MGN_MCS3:
1082 ret = DESC90_RATEMCS3;
1083 break;
1084 case MGN_MCS4:
1085 ret = DESC90_RATEMCS4;
1086 break;
1087 case MGN_MCS5:
1088 ret = DESC90_RATEMCS5;
1089 break;
1090 case MGN_MCS6:
1091 ret = DESC90_RATEMCS6;
1092 break;
1093 case MGN_MCS7:
1094 ret = DESC90_RATEMCS7;
1095 break;
1096 case MGN_MCS8:
1097 ret = DESC90_RATEMCS8;
1098 break;
1099 case MGN_MCS9:
1100 ret = DESC90_RATEMCS9;
1101 break;
1102 case MGN_MCS10:
1103 ret = DESC90_RATEMCS10;
1104 break;
1105 case MGN_MCS11:
1106 ret = DESC90_RATEMCS11;
1107 break;
1108 case MGN_MCS12:
1109 ret = DESC90_RATEMCS12;
1110 break;
1111 case MGN_MCS13:
1112 ret = DESC90_RATEMCS13;
1113 break;
1114 case MGN_MCS14:
1115 ret = DESC90_RATEMCS14;
1116 break;
1117 case MGN_MCS15:
1118 ret = DESC90_RATEMCS15;
1119 break;
1120 case (0x80|0x20):
1121 ret = DESC90_RATEMCS32;
1122 break;
1123 default:
1124 break;
1125 }
1126 return ret;
1127}
1128
e77891b3
MK		 1129static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID,
1130 u8 priority)
94a79942
LF		 1131{
1132 u8 QueueSelect = 0x0;
1133
1134 switch (QueueID) {
1135 case BE_QUEUE:
1136 QueueSelect = QSLT_BE;
1137 break;
1138
1139 case BK_QUEUE:
1140 QueueSelect = QSLT_BK;
1141 break;
1142
1143 case VO_QUEUE:
1144 QueueSelect = QSLT_VO;
1145 break;
1146
1147 case VI_QUEUE:
1148 QueueSelect = QSLT_VI;
1149 break;
1150 case MGNT_QUEUE:
1151 QueueSelect = QSLT_MGNT;
1152 break;
1153 case BEACON_QUEUE:
1154 QueueSelect = QSLT_BEACON;
1155 break;
1156 case TXCMD_QUEUE:
1157 QueueSelect = QSLT_CMD;
1158 break;
1159 case HIGH_QUEUE:
1160 QueueSelect = QSLT_HIGH;
1161 break;
1162 default:
3b4140af
MK		 1163 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
1164 __func__, QueueID);
94a79942
LF		 1165 break;
1166 }
1167 return QueueSelect;
1168}
1169
45de4283 1170static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
01b67faf
MK		 1171{
1172 u8 tmp_Short;
1173
1174 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
1175 ((tcb_desc->bUseShortPreamble) ? 1 : 0);
1176 if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
1177 tmp_Short = 0;
1178
1179 return tmp_Short;
1180}
1181
072b3948
MK		 1182void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
1183 struct cb_desc *cb_desc, struct sk_buff *skb)
94a79942 1184{
52629477 1185 struct r8192_priv *priv = rtllib_priv(dev);
baabd567 1186 dma_addr_t mapping;
7949be66 1187 struct tx_fwinfo_8190pci *pTxFwInfo;
3a6b70c3 1188
52629477
LF		 1189 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1190 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1191 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
615c8d8d 1192 pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->data_rate);
52629477 1193 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
45de4283
MK		 1194 pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT,
1195 pTxFwInfo->TxRate, cb_desc);
52629477
LF		 1196
1197 if (cb_desc->bAMPDUEnable) {
1198 pTxFwInfo->AllowAggregation = 1;
1199 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1200 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1201 } else {
1202 pTxFwInfo->AllowAggregation = 0;
1203 pTxFwInfo->RxMF = 0;
1204 pTxFwInfo->RxAMD = 0;
1205 }
1206
1207 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0;
1208 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1209 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1210 pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
615c8d8d 1211 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->rts_rate);
52629477
LF		 1212 pTxFwInfo->RtsBandwidth = 0;
1213 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1214 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1215 (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1216 (cb_desc->bRTSUseShortGI ? 1 : 0);
1217 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1218 if (cb_desc->bPacketBW) {
1219 pTxFwInfo->TxBandwidth = 1;
1220 pTxFwInfo->TxSubCarrier = 0;
1221 } else {
1222 pTxFwInfo->TxBandwidth = 0;
1223 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1224 }
1225 } else {
1226 pTxFwInfo->TxBandwidth = 0;
1227 pTxFwInfo->TxSubCarrier = 0;
1228 }
1229
1230 memset((u8 *)pdesc, 0, 12);
baabd567
MP		 1231
1232 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1233 PCI_DMA_TODEVICE);
1234 if (pci_dma_mapping_error(priv->pdev, mapping)) {
1235 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1236 return;
1237 }
1238
52629477
LF		 1239 pdesc->LINIP = 0;
1240 pdesc->CmdInit = 1;
1241 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1242 pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1243
1244 pdesc->SecCAMID = 0;
1245 pdesc->RATid = cb_desc->RATRIndex;
1246
1247
1248 pdesc->NoEnc = 1;
1249 pdesc->SecType = 0x0;
1250 if (cb_desc->bHwSec) {
1251 static u8 tmp;
3a6b70c3 1252
52629477
LF		 1253 if (!tmp) {
1254 RT_TRACE(COMP_DBG, "==>================hw sec\n");
1255 tmp = 1;
1256 }
1257 switch (priv->rtllib->pairwise_key_type) {
1258 case KEY_TYPE_WEP40:
1259 case KEY_TYPE_WEP104:
1260 pdesc->SecType = 0x1;
1261 pdesc->NoEnc = 0;
1262 break;
1263 case KEY_TYPE_TKIP:
1264 pdesc->SecType = 0x2;
1265 pdesc->NoEnc = 0;
1266 break;
1267 case KEY_TYPE_CCMP:
1268 pdesc->SecType = 0x3;
1269 pdesc->NoEnc = 0;
1270 break;
1271 case KEY_TYPE_NA:
1272 pdesc->SecType = 0x0;
1273 pdesc->NoEnc = 1;
1274 break;
1275 }
1276 }
1277
1278 pdesc->PktId = 0x0;
1279
e77891b3
MK		 1280 pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev,
1281 cb_desc->queue_index,
1282 cb_desc->priority);
52629477
LF		 1283 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1284
1285 pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1286 pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1287
1288 pdesc->FirstSeg = 1;
1289 pdesc->LastSeg = 1;
1290 pdesc->TxBufferSize = skb->len;
1291
285cce05 1292 pdesc->TxBuffAddr = mapping;
94a79942
LF		 1293}
1294
63b544a1
MK		 1295void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1296 struct cb_desc *cb_desc, struct sk_buff *skb)
94a79942 1297{
52629477
LF		 1298 struct r8192_priv *priv = rtllib_priv(dev);
1299 dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1300 PCI_DMA_TODEVICE);
1301
2dcb4a29 1302 if (pci_dma_mapping_error(priv->pdev, mapping))
3b4140af 1303 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
52629477
LF		 1304 memset(entry, 0, 12);
1305 entry->LINIP = cb_desc->bLastIniPkt;
1306 entry->FirstSeg = 1;
1307 entry->LastSeg = 1;
1308 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1309 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1310 } else {
3f8ddea0 1311 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
3a6b70c3 1312
52629477
LF		 1313 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1314 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1315 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1316 entry_tmp->Offset);
1317 entry_tmp->QueueSelect = QSLT_CMD;
1318 entry_tmp->TxFWInfoSize = 0x08;
1319 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1320 }
1321 entry->TxBufferSize = skb->len;
285cce05 1322 entry->TxBuffAddr = mapping;
52629477 1323 entry->OWN = 1;
94a79942
LF		 1324}
1325
01d5f566 1326static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate)
94a79942
LF		 1327{
1328 u8 ret_rate = 0x02;
1329
1330 if (!bIsHT) {
1331 switch (rate) {
52629477
LF		 1332 case DESC90_RATE1M:
1333 ret_rate = MGN_1M;
1334 break;
1335 case DESC90_RATE2M:
1336 ret_rate = MGN_2M;
1337 break;
1338 case DESC90_RATE5_5M:
1339 ret_rate = MGN_5_5M;
1340 break;
1341 case DESC90_RATE11M:
1342 ret_rate = MGN_11M;
1343 break;
1344 case DESC90_RATE6M:
1345 ret_rate = MGN_6M;
1346 break;
1347 case DESC90_RATE9M:
1348 ret_rate = MGN_9M;
1349 break;
1350 case DESC90_RATE12M:
1351 ret_rate = MGN_12M;
1352 break;
1353 case DESC90_RATE18M:
1354 ret_rate = MGN_18M;
1355 break;
1356 case DESC90_RATE24M:
1357 ret_rate = MGN_24M;
1358 break;
1359 case DESC90_RATE36M:
1360 ret_rate = MGN_36M;
1361 break;
1362 case DESC90_RATE48M:
1363 ret_rate = MGN_48M;
1364 break;
1365 case DESC90_RATE54M:
1366 ret_rate = MGN_54M;
1367 break;
94a79942 1368
52629477 1369 default:
0822339b 1370 RT_TRACE(COMP_RECV,
01d5f566 1371 "_rtl92e_rate_hw_to_mgn(): Non supportedRate [%x], bIsHT = %d!!!\n",
0822339b
MK		 1372 rate, bIsHT);
1373 break;
94a79942
LF		 1374 }
1375
1376 } else {
1377 switch (rate) {
52629477
LF		 1378 case DESC90_RATEMCS0:
1379 ret_rate = MGN_MCS0;
1380 break;
1381 case DESC90_RATEMCS1:
1382 ret_rate = MGN_MCS1;
1383 break;
1384 case DESC90_RATEMCS2:
1385 ret_rate = MGN_MCS2;
1386 break;
1387 case DESC90_RATEMCS3:
1388 ret_rate = MGN_MCS3;
1389 break;
1390 case DESC90_RATEMCS4:
1391 ret_rate = MGN_MCS4;
1392 break;
1393 case DESC90_RATEMCS5:
1394 ret_rate = MGN_MCS5;
1395 break;
1396 case DESC90_RATEMCS6:
1397 ret_rate = MGN_MCS6;
1398 break;
1399 case DESC90_RATEMCS7:
1400 ret_rate = MGN_MCS7;
1401 break;
1402 case DESC90_RATEMCS8:
1403 ret_rate = MGN_MCS8;
1404 break;
1405 case DESC90_RATEMCS9:
1406 ret_rate = MGN_MCS9;
1407 break;
1408 case DESC90_RATEMCS10:
1409 ret_rate = MGN_MCS10;
1410 break;
1411 case DESC90_RATEMCS11:
1412 ret_rate = MGN_MCS11;
1413 break;
1414 case DESC90_RATEMCS12:
1415 ret_rate = MGN_MCS12;
1416 break;
1417 case DESC90_RATEMCS13:
1418 ret_rate = MGN_MCS13;
1419 break;
1420 case DESC90_RATEMCS14:
1421 ret_rate = MGN_MCS14;
1422 break;
1423 case DESC90_RATEMCS15:
1424 ret_rate = MGN_MCS15;
1425 break;
1426 case DESC90_RATEMCS32:
1427 ret_rate = (0x80|0x20);
1428 break;
94a79942 1429
52629477 1430 default:
0822339b 1431 RT_TRACE(COMP_RECV,
01d5f566 1432 "_rtl92e_rate_hw_to_mgn(): Non supported Rate [%x], bIsHT = %d!!!\n",
0822339b 1433 rate, bIsHT);
52629477 1434 break;
94a79942
LF		 1435 }
1436 }
1437
1438 return ret_rate;
1439}
1440
af82349a 1441static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig)
94a79942
LF		 1442{
1443 long retsig;
1444
94a79942 1445 if (currsig >= 61 && currsig <= 100)
94a79942 1446 retsig = 90 + ((currsig - 60) / 4);
94a79942 1447 else if (currsig >= 41 && currsig <= 60)
94a79942 1448 retsig = 78 + ((currsig - 40) / 2);
94a79942 1449 else if (currsig >= 31 && currsig <= 40)
94a79942 1450 retsig = 66 + (currsig - 30);
94a79942 1451 else if (currsig >= 21 && currsig <= 30)
94a79942 1452 retsig = 54 + (currsig - 20);
94a79942 1453 else if (currsig >= 5 && currsig <= 20)
94a79942 1454 retsig = 42 + (((currsig - 5) * 2) / 3);
94a79942 1455 else if (currsig == 4)
94a79942 1456 retsig = 36;
94a79942 1457 else if (currsig == 3)
94a79942 1458 retsig = 27;
94a79942 1459 else if (currsig == 2)
94a79942 1460 retsig = 18;
94a79942 1461 else if (currsig == 1)
94a79942 1462 retsig = 9;
94a79942 1463 else
94a79942 1464 retsig = currsig;
94a79942
LF		 1465
1466 return retsig;
1467}
1468
1469
52629477
LF		 1470#define rx_hal_is_cck_rate(_pdrvinfo)\
1471 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
94a79942
LF		 1472 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1473 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1474 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
52629477
LF		 1475 !_pdrvinfo->RxHT)
1476
410bfd1d 1477static void _rtl92e_query_rxphystatus(
52629477
LF		 1478 struct r8192_priv *priv,
1479 struct rtllib_rx_stats *pstats,
4f534b36 1480 struct rx_desc *pdesc,
6f22c620 1481 struct rx_fwinfo *pdrvinfo,
52629477 1482 struct rtllib_rx_stats *precord_stats,
94a79942
LF		 1483 bool bpacket_match_bssid,
1484 bool bpacket_toself,
1485 bool bPacketBeacon,
1486 bool bToSelfBA
1487 )
1488{
52629477
LF		 1489 struct phy_sts_ofdm_819xpci *pofdm_buf;
1490 struct phy_sts_cck_819xpci *pcck_buf;
1491 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1492 u8 *prxpkt;
1493 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
5d5fd353
AB		 1494 s8 rx_pwr[4], rx_pwr_all = 0;
1495 s8 rx_snrX, rx_evmX;
52629477
LF		 1496 u8 evm, pwdb_all;
1497 u32 RSSI, total_rssi = 0;
1498 u8 is_cck_rate = 0;
1499 u8 rf_rx_num = 0;
1500 static u8 check_reg824;
1501 static u32 reg824_bit9;
94a79942
LF		 1502
1503 priv->stats.numqry_phystatus++;
1504
94a79942
LF		 1505 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1506 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
52629477
LF		 1507 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1508 bpacket_match_bssid;
94a79942
LF		 1509 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1510 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1511 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1512 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
52629477 1513 if (check_reg824 == 0) {
3c351fec
MK		 1514 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1515 rFPGA0_XA_HSSIParameter2,
1516 0x200);
94a79942
LF		 1517 check_reg824 = 1;
1518 }
1519
1520
52629477 1521 prxpkt = (u8 *)pdrvinfo;
94a79942 1522
6f22c620 1523 prxpkt += sizeof(struct rx_fwinfo);
94a79942 1524
ececd694 1525 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
2ae7ea8c 1526 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
94a79942
LF		 1527
1528 pstats->RxMIMOSignalQuality[0] = -1;
1529 pstats->RxMIMOSignalQuality[1] = -1;
1530 precord_stats->RxMIMOSignalQuality[0] = -1;
1531 precord_stats->RxMIMOSignalQuality[1] = -1;
1532
52629477 1533 if (is_cck_rate) {
94a79942 1534 u8 report;
b1d5ee70
LF		 1535
1536 priv->stats.numqry_phystatusCCK++;
52629477 1537 if (!reg824_bit9) {
94a79942 1538 report = pcck_buf->cck_agc_rpt & 0xc0;
0dbffe07 1539 report >>= 6;
52629477
LF		 1540 switch (report) {
1541 case 0x3:
1542 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1543 0x3e);
1544 break;
1545 case 0x2:
1546 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1547 0x3e);
1548 break;
1549 case 0x1:
1550 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1551 0x3e);
1552 break;
1553 case 0x0:
1554 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1555 break;
94a79942 1556 }
52629477 1557 } else {
94a79942 1558 report = pcck_buf->cck_agc_rpt & 0x60;
0dbffe07 1559 report >>= 5;
52629477
LF		 1560 switch (report) {
1561 case 0x3:
1562 rx_pwr_all = -35 -
1563 ((pcck_buf->cck_agc_rpt &
1564 0x1f) << 1);
1565 break;
1566 case 0x2:
1567 rx_pwr_all = -23 -
1568 ((pcck_buf->cck_agc_rpt &
1569 0x1f) << 1);
1570 break;
1571 case 0x1:
1572 rx_pwr_all = -11 -
1573 ((pcck_buf->cck_agc_rpt &
1574 0x1f) << 1);
1575 break;
1576 case 0x0:
1577 rx_pwr_all = -8 -
1578 ((pcck_buf->cck_agc_rpt &
1579 0x1f) << 1);
1580 break;
94a79942
LF		 1581 }
1582 }
1583
aa804031 1584 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
94a79942
LF		 1585 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1586 pstats->RecvSignalPower = rx_pwr_all;
1587
52629477 1588 if (bpacket_match_bssid) {
94a79942
LF		 1589 u8 sq;
1590
52629477 1591 if (pstats->RxPWDBAll > 40) {
94a79942 1592 sq = 100;
52629477 1593 } else {
94a79942
LF		 1594 sq = pcck_buf->sq_rpt;
1595
1596 if (pcck_buf->sq_rpt > 64)
1597 sq = 0;
1598 else if (pcck_buf->sq_rpt < 20)
1599 sq = 100;
1600 else
1601 sq = ((64-sq) * 100) / 44;
1602 }
52629477
LF		 1603 pstats->SignalQuality = sq;
1604 precord_stats->SignalQuality = sq;
1605 pstats->RxMIMOSignalQuality[0] = sq;
1606 precord_stats->RxMIMOSignalQuality[0] = sq;
1607 pstats->RxMIMOSignalQuality[1] = -1;
1608 precord_stats->RxMIMOSignalQuality[1] = -1;
94a79942 1609 }
52629477 1610 } else {
94a79942 1611 priv->stats.numqry_phystatusHT++;
52629477 1612 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
94a79942
LF		 1613 if (priv->brfpath_rxenable[i])
1614 rf_rx_num++;
1615
52629477
LF		 1616 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1617 2) - 110;
94a79942
LF		 1618
1619 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
5d5fd353 1620 rx_snrX = (s8)(tmp_rxsnr);
94a79942
LF		 1621 rx_snrX /= 2;
1622 priv->stats.rxSNRdB[i] = (long)rx_snrX;
1623
aa804031 1624 RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
94a79942
LF		 1625 if (priv->brfpath_rxenable[i])
1626 total_rssi += RSSI;
1627
52629477
LF		 1628 if (bpacket_match_bssid) {
1629 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1630 precord_stats->RxMIMOSignalStrength[i] =
1631 (u8) RSSI;
94a79942
LF		 1632 }
1633 }
1634
1635
52629477 1636 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
aa804031 1637 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
94a79942
LF		 1638
1639 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1640 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
1641 pstats->RecvSignalPower = rx_pwr_all;
52629477
LF		 1642 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1643 pdrvinfo->RxRate <= DESC90_RATEMCS15)
94a79942
LF		 1644 max_spatial_stream = 2;
1645 else
1646 max_spatial_stream = 1;
1647
52629477 1648 for (i = 0; i < max_spatial_stream; i++) {
94a79942 1649 tmp_rxevm = pofdm_buf->rxevm_X[i];
5d5fd353 1650 rx_evmX = (s8)(tmp_rxevm);
94a79942
LF		 1651
1652 rx_evmX /= 2;
1653
6b89d0e7 1654 evm = rtl92e_evm_db_to_percent(rx_evmX);
52629477
LF		 1655 if (bpacket_match_bssid) {
1656 if (i == 0) {
4db665e5
GS		 1657 pstats->SignalQuality = evm & 0xff;
1658 precord_stats->SignalQuality = evm & 0xff;
52629477 1659 }
4db665e5
GS		 1660 pstats->RxMIMOSignalQuality[i] = evm & 0xff;
1661 precord_stats->RxMIMOSignalQuality[i] = evm & 0xff;
94a79942
LF		 1662 }
1663 }
1664
1665
1666 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
52629477
LF		 1667 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1668 &rxsc_sgien_exflg;
94a79942
LF		 1669 if (pdrvinfo->BW)
1670 priv->stats.received_bwtype[1+prxsc->rxsc]++;
1671 else
1672 priv->stats.received_bwtype[0]++;
1673 }
1674
52629477
LF		 1675 if (is_cck_rate) {
1676 pstats->SignalStrength = precord_stats->SignalStrength =
af82349a 1677 (u8)(_rtl92e_signal_scale_mapping(priv,
52629477 1678 (long)pwdb_all));
94a79942 1679
52629477 1680 } else {
94a79942 1681 if (rf_rx_num != 0)
52629477 1682 pstats->SignalStrength = precord_stats->SignalStrength =
af82349a 1683 (u8)(_rtl92e_signal_scale_mapping(priv,
52629477 1684 (long)(total_rssi /= rf_rx_num)));
94a79942
LF		 1685 }
1686}
1687
1325ba08 1688static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
49aab5fd
LF		 1689 struct rtllib_rx_stats *prev_st,
1690 struct rtllib_rx_stats *curr_st)
94a79942
LF		 1691{
1692 bool bcheck = false;
1693 u8 rfpath;
52629477
LF		 1694 u32 ij, tmp_val;
1695 static u32 slide_rssi_index, slide_rssi_statistics;
1696 static u32 slide_evm_index, slide_evm_statistics;
1697 static u32 last_rssi, last_evm;
1698 static u32 slide_beacon_adc_pwdb_index;
1699 static u32 slide_beacon_adc_pwdb_statistics;
1700 static u32 last_beacon_adc_pwdb;
94a79942 1701 struct rtllib_hdr_3addr *hdr;
52629477
LF		 1702 u16 sc;
1703 unsigned int frag, seq;
1704
94a79942
LF		 1705 hdr = (struct rtllib_hdr_3addr *)buffer;
1706 sc = le16_to_cpu(hdr->seq_ctl);
1707 frag = WLAN_GET_SEQ_FRAG(sc);
1708 seq = WLAN_GET_SEQ_SEQ(sc);
52629477
LF		 1709 curr_st->Seq_Num = seq;
1710 if (!prev_st->bIsAMPDU)
94a79942
LF		 1711 bcheck = true;
1712
52629477 1713 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
94a79942
LF		 1714 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1715 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1716 priv->stats.slide_rssi_total -= last_rssi;
1717 }
52629477 1718 priv->stats.slide_rssi_total += prev_st->SignalStrength;
94a79942 1719
52629477
LF		 1720 priv->stats.slide_signal_strength[slide_rssi_index++] =
1721 prev_st->SignalStrength;
94a79942
LF		 1722 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1723 slide_rssi_index = 0;
1724
1725 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
f54f10bf
MK		 1726 priv->stats.signal_strength = rtl92e_translate_to_dbm(priv,
1727 (u8)tmp_val);
52629477
LF		 1728 curr_st->rssi = priv->stats.signal_strength;
1729 if (!prev_st->bPacketMatchBSSID) {
1730 if (!prev_st->bToSelfBA)
94a79942
LF		 1731 return;
1732 }
1733
1734 if (!bcheck)
1735 return;
1736
94a79942 1737 priv->stats.num_process_phyinfo++;
52629477
LF		 1738 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1739 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
5948d1fe 1740 if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
94a79942 1741 continue;
0822339b
MK		 1742 RT_TRACE(COMP_DBG,
1743 "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n",
52629477
LF		 1744 prev_st->RxMIMOSignalStrength[rfpath]);
1745 if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
94a79942 1746 priv->stats.rx_rssi_percentage[rfpath] =
52629477 1747 prev_st->RxMIMOSignalStrength[rfpath];
94a79942 1748 }
52629477
LF		 1749 if (prev_st->RxMIMOSignalStrength[rfpath] >
1750 priv->stats.rx_rssi_percentage[rfpath]) {
1751 priv->stats.rx_rssi_percentage[rfpath] =
1752 ((priv->stats.rx_rssi_percentage[rfpath]
1753 * (RX_SMOOTH - 1)) +
1754 (prev_st->RxMIMOSignalStrength
1755 [rfpath])) / (RX_SMOOTH);
94a79942 1756 priv->stats.rx_rssi_percentage[rfpath] =
52629477
LF		 1757 priv->stats.rx_rssi_percentage[rfpath]
1758 + 1;
1759 } else {
1760 priv->stats.rx_rssi_percentage[rfpath] =
1761 ((priv->stats.rx_rssi_percentage[rfpath] *
1762 (RX_SMOOTH-1)) +
1763 (prev_st->RxMIMOSignalStrength[rfpath])) /
1764 (RX_SMOOTH);
94a79942 1765 }
0822339b
MK		 1766 RT_TRACE(COMP_DBG,
1767 "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath] = %d\n",
52629477 1768 priv->stats.rx_rssi_percentage[rfpath]);
94a79942
LF		 1769 }
1770 }
1771
1772
52629477
LF		 1773 if (prev_st->bPacketBeacon) {
1774 if (slide_beacon_adc_pwdb_statistics++ >=
1775 PHY_Beacon_RSSI_SLID_WIN_MAX) {
1776 slide_beacon_adc_pwdb_statistics =
1777 PHY_Beacon_RSSI_SLID_WIN_MAX;
1778 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1779 [slide_beacon_adc_pwdb_index];
94a79942
LF		 1780 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1781 }
52629477
LF		 1782 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1783 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1784 prev_st->RxPWDBAll;
94a79942
LF		 1785 slide_beacon_adc_pwdb_index++;
1786 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1787 slide_beacon_adc_pwdb_index = 0;
52629477
LF		 1788 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1789 slide_beacon_adc_pwdb_statistics;
1790 if (prev_st->RxPWDBAll >= 3)
1791 prev_st->RxPWDBAll -= 3;
94a79942
LF		 1792 }
1793
1794 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
52629477
LF		 1795 prev_st->bIsCCK ? "CCK" : "OFDM",
1796 prev_st->RxPWDBAll);
94a79942 1797
52629477
LF		 1798 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1799 prev_st->bToSelfBA) {
94a79942 1800 if (priv->undecorated_smoothed_pwdb < 0)
52629477
LF		 1801 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1802 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
94a79942 1803 priv->undecorated_smoothed_pwdb =
52629477
LF		 1804 (((priv->undecorated_smoothed_pwdb) *
1805 (RX_SMOOTH-1)) +
1806 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1807 priv->undecorated_smoothed_pwdb =
1808 priv->undecorated_smoothed_pwdb + 1;
1809 } else {
94a79942 1810 priv->undecorated_smoothed_pwdb =
52629477
LF		 1811 (((priv->undecorated_smoothed_pwdb) *
1812 (RX_SMOOTH-1)) +
1813 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
94a79942 1814 }
97ef450b 1815 rtl92e_update_rx_statistics(priv, prev_st);
94a79942
LF		 1816 }
1817
52629477
LF		 1818 if (prev_st->SignalQuality != 0) {
1819 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1820 prev_st->bToSelfBA) {
1821 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
94a79942 1822 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
52629477
LF		 1823 last_evm =
1824 priv->stats.slide_evm[slide_evm_index];
94a79942
LF		 1825 priv->stats.slide_evm_total -= last_evm;
1826 }
1827
52629477 1828 priv->stats.slide_evm_total += prev_st->SignalQuality;
94a79942 1829
52629477
LF		 1830 priv->stats.slide_evm[slide_evm_index++] =
1831 prev_st->SignalQuality;
94a79942
LF		 1832 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1833 slide_evm_index = 0;
1834
52629477
LF		 1835 tmp_val = priv->stats.slide_evm_total /
1836 slide_evm_statistics;
94a79942
LF		 1837 priv->stats.signal_quality = tmp_val;
1838 priv->stats.last_signal_strength_inpercent = tmp_val;
1839 }
1840
52629477
LF		 1841 if (prev_st->bPacketToSelf ||
1842 prev_st->bPacketBeacon ||
1843 prev_st->bToSelfBA) {
1844 for (ij = 0; ij < 2; ij++) {
1845 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1846 if (priv->stats.rx_evm_percentage[ij] == 0)
1847 priv->stats.rx_evm_percentage[ij] =
1848 prev_st->RxMIMOSignalQuality[ij];
1849 priv->stats.rx_evm_percentage[ij] =
1850 ((priv->stats.rx_evm_percentage[ij] *
1851 (RX_SMOOTH - 1)) +
1852 (prev_st->RxMIMOSignalQuality[ij])) /
1853 (RX_SMOOTH);
94a79942
LF		 1854 }
1855 }
1856 }
1857 }
94a79942
LF		 1858}
1859
9d70ed83
MK		 1860static void _rtl92e_translate_rx_signal_stats(struct net_device *dev,
1861 struct sk_buff *skb,
1862 struct rtllib_rx_stats *pstats,
1863 struct rx_desc *pdesc,
1864 struct rx_fwinfo *pdrvinfo)
94a79942 1865{
52629477
LF		 1866 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1867 bool bpacket_match_bssid, bpacket_toself;
1868 bool bPacketBeacon = false;
1869 struct rtllib_hdr_3addr *hdr;
1870 bool bToSelfBA = false;
1871 static struct rtllib_rx_stats previous_stats;
1872 u16 fc, type;
1873 u8 *tmp_buf;
1874 u8 *praddr;
1875
1876 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1877
1878 hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1879 fc = le16_to_cpu(hdr->frame_ctl);
1880 type = WLAN_FC_GET_TYPE(fc);
1881 praddr = hdr->addr1;
1882
8329419a 1883 bpacket_match_bssid =
4c29207a 1884 ((type != RTLLIB_FTYPE_CTL) &&
8329419a
JP		 1885 ether_addr_equal(priv->rtllib->current_network.bssid,
1886 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1887 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1888 hdr->addr3) &&
1889 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1890 bpacket_toself = bpacket_match_bssid && /* check this */
1891 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
52629477
LF		 1892 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1893 bPacketBeacon = true;
1894 if (bpacket_match_bssid)
1895 priv->stats.numpacket_matchbssid++;
1896 if (bpacket_toself)
1897 priv->stats.numpacket_toself++;
1325ba08 1898 _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
410bfd1d 1899 _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
52629477
LF		 1900 &previous_stats, bpacket_match_bssid,
1901 bpacket_toself, bPacketBeacon, bToSelfBA);
e58701da 1902 rtl92e_copy_mpdu_stats(pstats, &previous_stats);
94a79942
LF		 1903}
1904
77055c56 1905static void _rtl92e_update_received_rate_histogram_stats(
49aab5fd 1906 struct net_device *dev,
52629477 1907 struct rtllib_rx_stats *pstats)
94a79942
LF		 1908{
1909 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
52629477 1910 u32 rcvType = 1;
94a79942
LF		 1911 u32 rateIndex;
1912 u32 preamble_guardinterval;
1913
1914 if (pstats->bCRC)
1915 rcvType = 2;
1916 else if (pstats->bICV)
1917 rcvType = 3;
1918
1919 if (pstats->bShortPreamble)
1920 preamble_guardinterval = 1;
1921 else
1922 preamble_guardinterval = 0;
1923
52629477
LF		 1924 switch (pstats->rate) {
1925 case MGN_1M:
1926 rateIndex = 0;
1927 break;
1928 case MGN_2M:
1929 rateIndex = 1;
1930 break;
1931 case MGN_5_5M:
1932 rateIndex = 2;
1933 break;
1934 case MGN_11M:
1935 rateIndex = 3;
1936 break;
1937 case MGN_6M:
1938 rateIndex = 4;
1939 break;
1940 case MGN_9M:
1941 rateIndex = 5;
1942 break;
1943 case MGN_12M:
1944 rateIndex = 6;
1945 break;
1946 case MGN_18M:
1947 rateIndex = 7;
1948 break;
1949 case MGN_24M:
1950 rateIndex = 8;
1951 break;
1952 case MGN_36M:
1953 rateIndex = 9;
1954 break;
1955 case MGN_48M:
1956 rateIndex = 10;
1957 break;
1958 case MGN_54M:
1959 rateIndex = 11;
1960 break;
1961 case MGN_MCS0:
1962 rateIndex = 12;
1963 break;
1964 case MGN_MCS1:
1965 rateIndex = 13;
1966 break;
1967 case MGN_MCS2:
1968 rateIndex = 14;
1969 break;
1970 case MGN_MCS3:
1971 rateIndex = 15;
1972 break;
1973 case MGN_MCS4:
1974 rateIndex = 16;
1975 break;
1976 case MGN_MCS5:
1977 rateIndex = 17;
1978 break;
1979 case MGN_MCS6:
1980 rateIndex = 18;
1981 break;
1982 case MGN_MCS7:
1983 rateIndex = 19;
1984 break;
1985 case MGN_MCS8:
1986 rateIndex = 20;
1987 break;
1988 case MGN_MCS9:
1989 rateIndex = 21;
1990 break;
1991 case MGN_MCS10:
1992 rateIndex = 22;
1993 break;
1994 case MGN_MCS11:
1995 rateIndex = 23;
1996 break;
1997 case MGN_MCS12:
1998 rateIndex = 24;
1999 break;
2000 case MGN_MCS13:
2001 rateIndex = 25;
2002 break;
2003 case MGN_MCS14:
2004 rateIndex = 26;
2005 break;
2006 case MGN_MCS15:
2007 rateIndex = 27;
2008 break;
2009 default:
2010 rateIndex = 28;
2011 break;
94a79942
LF		 2012 }
2013 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2014 priv->stats.received_rate_histogram[0][rateIndex]++;
2015 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2016}
2017
7897285c
MK		 2018bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
2019 struct rx_desc *pdesc, struct sk_buff *skb)
94a79942
LF		 2020{
2021 struct r8192_priv *priv = rtllib_priv(dev);
285b7c00 2022 struct rx_fwinfo *pDrvInfo = NULL;
94a79942
LF		 2023
2024 stats->bICV = pdesc->ICV;
2025 stats->bCRC = pdesc->CRC32;
2026 stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2027
2028 stats->Length = pdesc->Length;
2029 if (stats->Length < 24)
2030 stats->bHwError |= 1;
2031
2032 if (stats->bHwError) {
2033 stats->bShift = false;
2034
2035 if (pdesc->CRC32) {
52629477 2036 if (pdesc->Length < 500)
94a79942 2037 priv->stats.rxcrcerrmin++;
52629477 2038 else if (pdesc->Length > 1000)
94a79942
LF		 2039 priv->stats.rxcrcerrmax++;
2040 else
2041 priv->stats.rxcrcerrmid++;
2042 }
2043 return false;
285b7c00 2044 }
3a6b70c3 2045
285b7c00
MK		 2046 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2047 stats->RxBufShift = ((pdesc->Shift)&0x03);
2048 stats->Decrypted = !pdesc->SWDec;
94a79942 2049
285b7c00 2050 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
94a79942 2051
01d5f566
MK		 2052 stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT,
2053 (u8)pDrvInfo->RxRate);
285b7c00 2054 stats->bShortPreamble = pDrvInfo->SPLCP;
94a79942 2055
77055c56 2056 _rtl92e_update_received_rate_histogram_stats(dev, stats);
94a79942 2057
285b7c00
MK		 2058 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2059 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2060 (pDrvInfo->FirstAGGR == 1);
94a79942 2061
285b7c00 2062 stats->TimeStampLow = pDrvInfo->TSFL;
99aa47e0 2063 stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4);
94a79942 2064
7879efc5 2065 rtl92e_update_rx_pkt_timestamp(dev, stats);
94a79942 2066
285b7c00
MK		 2067 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2068 stats->bShift = 1;
94a79942 2069
285b7c00 2070 stats->RxIs40MHzPacket = pDrvInfo->BW;
94a79942 2071
9d70ed83 2072 _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo);
94a79942 2073
285b7c00
MK		 2074 if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2075 RT_TRACE(COMP_RXDESC,
2076 "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2077 pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2078 skb_trim(skb, skb->len - 4/*sCrcLng*/);
94a79942
LF		 2079
2080
285b7c00
MK		 2081 stats->packetlength = stats->Length-4;
2082 stats->fraglength = stats->packetlength;
2083 stats->fragoffset = 0;
2084 stats->ntotalfrag = 1;
2085 return true;
94a79942
LF		 2086}
2087
fe99c77b 2088void rtl92e_stop_adapter(struct net_device *dev, bool reset)
94a79942
LF		 2089{
2090 struct r8192_priv *priv = rtllib_priv(dev);
2091 int i;
2092 u8 OpMode;
2093 u8 u1bTmp;
2094 u32 ulRegRead;
94a79942
LF		 2095
2096 OpMode = RT_OP_MODE_NO_LINK;
2097 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2098
52629477 2099 if (!priv->rtllib->bSupportRemoteWakeUp) {
94a79942 2100 u1bTmp = 0x0;
d8ae1967 2101 rtl92e_writeb(dev, CMDR, u1bTmp);
94a79942 2102 }
94a79942
LF		 2103
2104 mdelay(20);
2105
52629477 2106 if (!reset) {
94a79942
LF		 2107 mdelay(150);
2108
f8f3b8a5 2109 priv->bHwRfOffAction = 2;
94a79942 2110
52629477 2111 if (!priv->rtllib->bSupportRemoteWakeUp) {
3803cb21 2112 rtl92e_set_rf_off(dev);
99aa47e0 2113 ulRegRead = rtl92e_readl(dev, CPU_GEN);
52629477 2114 ulRegRead |= CPU_GEN_SYSTEM_RESET;
8ea54100 2115 rtl92e_writel(dev, CPU_GEN, ulRegRead);
52629477 2116 } else {
8ea54100
MK		 2117 rtl92e_writel(dev, WFCRC0, 0xffffffff);
2118 rtl92e_writel(dev, WFCRC1, 0xffffffff);
2119 rtl92e_writel(dev, WFCRC2, 0xffffffff);
94a79942
LF		 2120
2121
d8ae1967
MK		 2122 rtl92e_writeb(dev, PMR, 0x5);
2123 rtl92e_writeb(dev, MacBlkCtrl, 0xa);
94a79942
LF		 2124 }
2125 }
2126
52629477
LF		 2127 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2128 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2129 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2130 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
94a79942
LF		 2131
2132 skb_queue_purge(&priv->skb_queue);
94a79942
LF		 2133}
2134
575d48c5 2135void rtl92e_update_ratr_table(struct net_device *dev)
94a79942 2136{
52629477
LF		 2137 struct r8192_priv *priv = rtllib_priv(dev);
2138 struct rtllib_device *ieee = priv->rtllib;
2139 u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
94a79942 2140 u32 ratr_value = 0;
71c8d893 2141 u16 rate_config = 0;
94a79942
LF		 2142 u8 rate_index = 0;
2143
122fe9f1 2144 rtl92e_config_rate(dev, &rate_config);
71c8d893 2145 ratr_value = rate_config | *pMcsRate << 12;
52629477
LF		 2146 switch (ieee->mode) {
2147 case IEEE_A:
2148 ratr_value &= 0x00000FF0;
2149 break;
2150 case IEEE_B:
2151 ratr_value &= 0x0000000F;
2152 break;
2153 case IEEE_G:
2154 case IEEE_G|IEEE_B:
2155 ratr_value &= 0x00000FF7;
2156 break;
2157 case IEEE_N_24G:
2158 case IEEE_N_5G:
2159 if (ieee->pHTInfo->PeerMimoPs == 0) {
2160 ratr_value &= 0x0007F007;
2161 } else {
2162 if (priv->rf_type == RF_1T2R)
2163 ratr_value &= 0x000FF007;
2164 else
2165 ratr_value &= 0x0F81F007;
2166 }
2167 break;
2168 default:
2169 break;
94a79942
LF		 2170 }
2171 ratr_value &= 0x0FFFFFFF;
52629477
LF		 2172 if (ieee->pHTInfo->bCurTxBW40MHz &&
2173 ieee->pHTInfo->bCurShortGI40MHz)
94a79942 2174 ratr_value |= 0x80000000;
52629477
LF		 2175 else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2176 ieee->pHTInfo->bCurShortGI20MHz)
94a79942 2177 ratr_value |= 0x80000000;
8ea54100 2178 rtl92e_writel(dev, RATR0+rate_index*4, ratr_value);
d8ae1967 2179 rtl92e_writeb(dev, UFWP, 1);
94a79942
LF		 2180}
2181
2182void
df85a131 2183rtl92e_init_variables(struct net_device *dev)
94a79942
LF		 2184{
2185 struct r8192_priv *priv = rtllib_priv(dev);
2186
94a79942 2187 strcpy(priv->nick, "rtl8192E");
94a79942 2188
94a79942
LF		 2189 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN |
2190 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
8852112e 2191 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
94a79942 2192
a07dc3d1 2193 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
94a79942
LF		 2194
2195 priv->ShortRetryLimit = 0x30;
2196 priv->LongRetryLimit = 0x30;
2197
94a79942
LF		 2198 priv->ReceiveConfig = RCR_ADD3 |
2199 RCR_AMF | RCR_ADF |
2200 RCR_AICV |
2201 RCR_AB | RCR_AM | RCR_APM |
2202 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2203 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2204
52629477
LF		 2205 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2206 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2207 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2208 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2209 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2210 IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
94a79942 2211
94a79942
LF		 2212 priv->PwrDomainProtect = false;
2213
014e4c27 2214 priv->bfirst_after_down = false;
94a79942
LF		 2215}
2216
6d99c68e 2217void rtl92e_enable_irq(struct net_device *dev)
94a79942
LF		 2218{
2219 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
3a6b70c3 2220
94a79942
LF		 2221 priv->irq_enabled = 1;
2222
8ea54100 2223 rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
94a79942 2224
94a79942
LF		 2225}
2226
baadea56 2227void rtl92e_disable_irq(struct net_device *dev)
94a79942
LF		 2228{
2229 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2230
8ea54100 2231 rtl92e_writel(dev, INTA_MASK, 0);
94a79942 2232
94a79942
LF		 2233 priv->irq_enabled = 0;
2234}
2235
dc578b41 2236void rtl92e_clear_irq(struct net_device *dev)
94a79942 2237{
7949be66 2238 u32 tmp;
3a6b70c3 2239
99aa47e0 2240 tmp = rtl92e_readl(dev, ISR);
8ea54100 2241 rtl92e_writel(dev, ISR, tmp);
94a79942
LF		 2242}
2243
2244
78c352b2 2245void rtl92e_enable_rx(struct net_device *dev)
94a79942 2246{
52629477 2247 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
3a6b70c3 2248
8ea54100 2249 rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
94a79942
LF		 2250}
2251
52629477
LF		 2252static const u32 TX_DESC_BASE[] = {
2253 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2254};
2255
6af7a8b6 2256void rtl92e_enable_tx(struct net_device *dev)
94a79942 2257{
52629477
LF		 2258 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2259 u32 i;
94a79942 2260
52629477 2261 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
8ea54100 2262 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
94a79942
LF		 2263}
2264
2265
a57165d1 2266void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb)
94a79942 2267{
99aa47e0 2268 *p_inta = rtl92e_readl(dev, ISR);
8ea54100 2269 rtl92e_writel(dev, ISR, *p_inta);
94a79942
LF		 2270}
2271
4d73bd26 2272bool rtl92e_is_rx_stuck(struct net_device *dev)
94a79942
LF		 2273{
2274 struct r8192_priv *priv = rtllib_priv(dev);
1c0a7c0e 2275 u16 RegRxCounter = rtl92e_readw(dev, 0x130);
94a79942 2276 bool bStuck = false;
52629477 2277 static u8 rx_chk_cnt;
94a79942
LF		 2278 u32 SlotIndex = 0, TotalRxStuckCount = 0;
2279 u8 i;
2280 u8 SilentResetRxSoltNum = 4;
2281
52629477
LF		 2282 RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2283 __func__, RegRxCounter, priv->RxCounter);
94a79942
LF		 2284
2285 rx_chk_cnt++;
52629477 2286 if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
94a79942 2287 rx_chk_cnt = 0;
52629477
LF		 2288 } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2289 && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2290 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2291 || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2292 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2293 if (rx_chk_cnt < 2)
94a79942 2294 return bStuck;
285b7c00 2295 rx_chk_cnt = 0;
94a79942
LF		 2296 } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2297 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2298 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2299 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2300 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
52629477 2301 if (rx_chk_cnt < 4)
94a79942 2302 return bStuck;
285b7c00 2303 rx_chk_cnt = 0;
94a79942 2304 } else {
52629477 2305 if (rx_chk_cnt < 8)
94a79942 2306 return bStuck;
285b7c00 2307 rx_chk_cnt = 0;
94a79942
LF		 2308 }
2309
2310
2311 SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2312
52629477 2313 if (priv->RxCounter == RegRxCounter) {
94a79942
LF		 2314 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2315
52629477 2316 for (i = 0; i < SilentResetRxSoltNum; i++)
94a79942
LF		 2317 TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2318
52629477
LF		 2319 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2320 bStuck = true;
2321 for (i = 0; i < SilentResetRxSoltNum; i++)
2322 TotalRxStuckCount +=
2323 priv->SilentResetRxStuckEvent[i];
94a79942
LF		 2324 }
2325
2326
2327 } else {
2328 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2329 }
2330
2331 priv->RxCounter = RegRxCounter;
2332
2333 return bStuck;
2334}
2335
c9cf5e78 2336bool rtl92e_is_tx_stuck(struct net_device *dev)
94a79942
LF		 2337{
2338 struct r8192_priv *priv = rtllib_priv(dev);
2339 bool bStuck = false;
1c0a7c0e 2340 u16 RegTxCounter = rtl92e_readw(dev, 0x128);
94a79942
LF		 2341
2342 RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
52629477 2343 __func__, RegTxCounter, priv->TxCounter);
94a79942
LF		 2344
2345 if (priv->TxCounter == RegTxCounter)
2346 bStuck = true;
2347
2348 priv->TxCounter = RegTxCounter;
2349
2350 return bStuck;
2351}
2352
56a5b5af 2353bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
94a79942 2354{
94a79942
LF		 2355 struct r8192_priv *priv = rtllib_priv(dev);
2356 struct rtllib_device *ieee = priv->rtllib;
3a6b70c3 2357
94a79942 2358 if (ieee->rtllib_ap_sec_type &&
52629477
LF		 2359 (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2360 SEC_ALG_TKIP))) {
94a79942
LF		 2361 return false;
2362 } else {
2363 return true;
2364 }
94a79942
LF		 2365}
2366
86534a29 2367bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
94a79942 2368{
52629477
LF		 2369 struct r8192_priv *priv = rtllib_priv(dev);
2370 struct rtllib_device *ieee = priv->rtllib;
94a79942 2371
99d4f5d2 2372 return ieee->bHalfWirelessN24GMode;
94a79942 2373}
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