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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
8fc8598e JC |
2 | #ifndef R819XUSB_CMDPKT_H |
3 | #define R819XUSB_CMDPKT_H | |
4 | /* Different command packet have dedicated message length and definition. */ | |
56340097 XR |
5 | #define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t) /* 20 */ |
6 | #define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t) /* 16 */ | |
7 | #define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t) /* 16 */ | |
8 | #define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t) | |
9 | #define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t) | |
b777736b | 10 | #define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t) |
8fc8598e JC |
11 | |
12 | /* 2008/05/08 amy For USB constant. */ | |
56b3152e AB |
13 | #define ISR_TxBcnOk BIT(27) /* Transmit Beacon OK */ |
14 | #define ISR_TxBcnErr BIT(26) /* Transmit Beacon Error */ | |
15 | #define ISR_BcnTimerIntr BIT(13) /* Beacon Timer Interrupt */ | |
8fc8598e | 16 | |
8fc8598e JC |
17 | |
18 | /* Define element ID of command packet. */ | |
19 | ||
20 | /*------------------------------Define structure----------------------------*/ | |
21 | /* Define different command packet structure. */ | |
22 | /* 1. RX side: TX feedback packet. */ | |
0db7a34e | 23 | typedef struct tag_cmd_pkt_tx_feedback { |
56340097 | 24 | /* DWORD 0 */ |
8fc8598e JC |
25 | u8 element_id; /* Command packet type. */ |
26 | u8 length; /* Command packet length. */ | |
56340097 | 27 | /* Change tx feedback info field. */ |
8fc8598e | 28 | /*------TX Feedback Info Field */ |
56340097 XR |
29 | u8 TID:4; |
30 | u8 fail_reason:3; | |
8fc8598e | 31 | u8 tok:1; /* Transmit ok. */ |
56340097 XR |
32 | u8 reserve1:4; |
33 | u8 pkt_type:2; | |
34 | u8 bandwidth:1; | |
35 | u8 qos_pkt:1; | |
8fc8598e | 36 | |
56340097 XR |
37 | /* DWORD 1 */ |
38 | u8 reserve2; | |
8fc8598e | 39 | /*------TX Feedback Info Field */ |
56340097 XR |
40 | u8 retry_cnt; |
41 | u16 pkt_id; | |
8fc8598e | 42 | |
56340097 XR |
43 | /* DWORD 3 */ |
44 | u16 seq_num; | |
8fc8598e JC |
45 | u8 s_rate; /* Start rate. */ |
46 | u8 f_rate; /* Final rate. */ | |
47 | ||
56340097 XR |
48 | /* DWORD 4 */ |
49 | u8 s_rts_rate; | |
50 | u8 f_rts_rate; | |
51 | u16 pkt_length; | |
8fc8598e | 52 | |
56340097 XR |
53 | /* DWORD 5 */ |
54 | u16 reserve3; | |
55 | u16 duration; | |
8f519cad | 56 | } cmpk_txfb_t; |
8fc8598e JC |
57 | |
58 | /* 2. RX side: Interrupt status packet. It includes Beacon State, | |
6a5e7311 DR |
59 | * Beacon Timer Interrupt and other useful informations in MAC ISR Reg. |
60 | */ | |
0db7a34e | 61 | typedef struct tag_cmd_pkt_interrupt_status { |
8fc8598e JC |
62 | u8 element_id; /* Command packet type. */ |
63 | u8 length; /* Command packet length. */ | |
64 | u16 reserve; | |
b777736b | 65 | u32 interrupt_status; /* Interrupt Status. */ |
8f519cad | 66 | } cmpk_intr_sta_t; |
8fc8598e JC |
67 | |
68 | ||
69 | /* 3. TX side: Set configuration packet. */ | |
0db7a34e | 70 | typedef struct tag_cmd_pkt_set_configuration { |
8fc8598e JC |
71 | u8 element_id; /* Command packet type. */ |
72 | u8 length; /* Command packet length. */ | |
56340097 XR |
73 | u16 reserve1; |
74 | /* Configuration info. */ | |
35997ff0 | 75 | u8 cfg_reserve1:3; |
56340097 XR |
76 | u8 cfg_size:2; |
77 | u8 cfg_type:2; | |
78 | u8 cfg_action:1; | |
79 | u8 cfg_reserve2; | |
80 | u8 cfg_page:4; | |
81 | u8 cfg_reserve3:4; | |
82 | u8 cfg_offset; | |
83 | u32 value; | |
84 | u32 mask; | |
8f519cad | 85 | } cmpk_set_cfg_t; |
8fc8598e JC |
86 | |
87 | /* 4. Both side : TX/RX query configuraton packet. The query structure is the | |
6a5e7311 DR |
88 | * same as set configuration. |
89 | */ | |
8fc8598e JC |
90 | #define cmpk_query_cfg_t cmpk_set_cfg_t |
91 | ||
92 | /* 5. Multi packet feedback status. */ | |
56340097 XR |
93 | typedef struct tag_tx_stats_feedback { |
94 | /* For endian transfer --> Driver will not the same as | |
6a5e7311 DR |
95 | * firmware structure. |
96 | */ | |
56340097 | 97 | /* DW 0 */ |
8fc8598e | 98 | u16 reserve1; |
56340097 XR |
99 | u8 length; /* Command packet length */ |
100 | u8 element_id; /* Command packet type */ | |
8fc8598e | 101 | |
56340097 XR |
102 | /* DW 1 */ |
103 | u16 txfail; /* Tx fail count */ | |
104 | u16 txok; /* Tx ok count */ | |
8fc8598e | 105 | |
56340097 XR |
106 | /* DW 2 */ |
107 | u16 txmcok; /* Tx multicast */ | |
108 | u16 txretry; /* Tx retry count */ | |
8fc8598e | 109 | |
56340097 | 110 | /* DW 3 */ |
feada066 | 111 | u16 txucok; /* Tx unicast */ |
56340097 | 112 | u16 txbcok; /* Tx broadcast */ |
8fc8598e | 113 | |
56340097 XR |
114 | /* DW 4 */ |
115 | u16 txbcfail; | |
116 | u16 txmcfail; | |
8fc8598e | 117 | |
56340097 XR |
118 | /* DW 5 */ |
119 | u16 reserve2; | |
120 | u16 txucfail; | |
8fc8598e | 121 | |
56340097 | 122 | /* DW 6-8 */ |
8fc8598e JC |
123 | u32 txmclength; |
124 | u32 txbclength; | |
125 | u32 txuclength; | |
126 | ||
56340097 | 127 | /* DW 9 */ |
8fc8598e JC |
128 | u16 reserve3_23; |
129 | u8 reserve3_1; | |
130 | u8 rate; | |
889cfe2f | 131 | } __packed cmpk_tx_status_t; |
8fc8598e JC |
132 | |
133 | /* 6. Debug feedback message. */ | |
56340097 | 134 | /* Define RX debug message */ |
0db7a34e | 135 | typedef struct tag_rx_debug_message_feedback { |
56340097 XR |
136 | /* For endian transfer --> for driver */ |
137 | /* DW 0 */ | |
8fc8598e | 138 | u16 reserve1; |
56340097 XR |
139 | u8 length; /* Command packet length */ |
140 | u8 element_id; /* Command packet type */ | |
8fc8598e | 141 | |
56340097 XR |
142 | /* DW 1-?? */ |
143 | /* Variable debug message. */ | |
8fc8598e | 144 | |
8f519cad | 145 | } cmpk_rx_dbginfo_t; |
8fc8598e | 146 | |
56340097 | 147 | /* Define transmit rate history. For big endian format. */ |
0db7a34e | 148 | typedef struct tag_tx_rate_history { |
56340097 XR |
149 | /* For endian transfer --> for driver */ |
150 | /* DW 0 */ | |
151 | u8 element_id; /* Command packet type */ | |
152 | u8 length; /* Command packet length */ | |
8fc8598e JC |
153 | u16 reserved1; |
154 | ||
56340097 | 155 | /* DW 1-2 CCK rate counter */ |
35997ff0 | 156 | u16 cck[4]; |
8fc8598e | 157 | |
56340097 | 158 | /* DW 3-6 */ |
35997ff0 | 159 | u16 ofdm[8]; |
8fc8598e | 160 | |
56340097 XR |
161 | /* DW 7-14 BW=0 SG=0 |
162 | * DW 15-22 BW=1 SG=0 | |
163 | * DW 23-30 BW=0 SG=1 | |
164 | * DW 31-38 BW=1 SG=1 | |
165 | */ | |
8fc8598e JC |
166 | u16 ht_mcs[4][16]; |
167 | ||
889cfe2f | 168 | } __packed cmpk_tx_rahis_t; |
8fc8598e | 169 | |
f96f8df2 | 170 | typedef enum tag_command_packet_directories { |
feada066 | 171 | RX_TX_FEEDBACK = 0, |
b7cc1d0c | 172 | RX_INTERRUPT_STATUS = 1, |
feada066 XR |
173 | TX_SET_CONFIG = 2, |
174 | BOTH_QUERY_CONFIG = 3, | |
175 | RX_TX_STATUS = 4, | |
b7cc1d0c XR |
176 | RX_DBGINFO_FEEDBACK = 5, |
177 | RX_TX_PER_PKT_FEEDBACK = 6, | |
178 | RX_TX_RATE_HISTORY = 7, | |
179 | RX_CMD_ELE_MAX | |
8f519cad | 180 | } cmpk_element_e; |
8fc8598e | 181 | |
f96f8df2 | 182 | typedef enum _rt_status { |
e406322b MCC |
183 | RT_STATUS_SUCCESS, |
184 | RT_STATUS_FAILURE, | |
185 | RT_STATUS_PENDING, | |
186 | RT_STATUS_RESOURCE | |
8f519cad | 187 | } rt_status, *prt_status; |
8fc8598e | 188 | |
beb12167 JP |
189 | u32 cmpk_message_handle_rx(struct net_device *dev, |
190 | struct ieee80211_rx_stats *pstats); | |
191 | rt_status SendTxCommandPacket(struct net_device *dev, | |
192 | void *pData, u32 DataLen); | |
8fc8598e JC |
193 | |
194 | ||
195 | #endif |