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1 | #ifndef __RTL8712_GP_BITDEF_H__ |
2 | #define __RTL8712_GP_BITDEF_H__ | |
3 | ||
4 | /*GPIO_CTRL*/ | |
5 | #define _GPIO_MOD_MSK 0xFF000000 | |
6 | #define _GPIO_MOD_SHT 24 | |
7 | #define _GPIO_IO_SEL_MSK 0x00FF0000 | |
8 | #define _GPIO_IO_SEL_SHT 16 | |
9 | #define _GPIO_OUT_MSK 0x0000FF00 | |
10 | #define _GPIO_OUT_SHT 8 | |
11 | #define _GPIO_IN_MSK 0x000000FF | |
12 | #define _GPIO_IN_SHT 0 | |
13 | ||
14 | /*SYS_PINMUX_CFG*/ | |
15 | #define _GPIOSEL_MSK 0x0003 | |
16 | #define _GPIOSEL_SHT 0 | |
17 | ||
18 | /*LED_CFG*/ | |
19 | #define _LED1SV BIT(7) | |
20 | #define _LED1CM_MSK 0x0070 | |
21 | #define _LED1CM_SHT 4 | |
22 | #define _LED0SV BIT(3) | |
23 | #define _LED0CM_MSK 0x0007 | |
24 | #define _LED0CM_SHT 0 | |
25 | ||
26 | /*PHY_REG*/ | |
27 | #define _HST_RDRDY_SHT 0 | |
28 | #define _HST_RDRDY_MSK 0xFF | |
29 | #define _HST_RDRDY BIT(_HST_RDRDY_SHT) | |
30 | #define _CPU_WTBUSY_SHT 1 | |
31 | #define _CPU_WTBUSY_MSK 0xFF | |
32 | #define _CPU_WTBUSY BIT(_CPU_WTBUSY_SHT) | |
33 | ||
34 | /* 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)*/ | |
35 | ||
36 | /* 8192S GPIO Config Setting (offset 0x2F1, 1 byte)*/ | |
37 | ||
38 | /*----------------------------------------------------------------------------*/ | |
39 | ||
40 | #define GPIOMUX_EN BIT(3) /* When this bit is set to "1", | |
41 | * GPIO PINs will switch to MAC | |
42 | * GPIO Function*/ | |
43 | #define GPIOSEL_GPIO 0 /* UART or JTAG or pure GPIO*/ | |
44 | #define GPIOSEL_PHYDBG 1 /* PHYDBG*/ | |
45 | #define GPIOSEL_BT 2 /* BT_coex*/ | |
46 | #define GPIOSEL_WLANDBG 3 /* WLANDBG*/ | |
47 | #define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1))) | |
48 | /* HW Readio OFF switch (GPIO BIT) */ | |
49 | #define HAL_8192S_HW_GPIO_OFF_BIT BIT(3) | |
50 | #define HAL_8192S_HW_GPIO_OFF_MASK 0xF7 | |
51 | #define HAL_8192S_HW_GPIO_WPS_BIT BIT(4) | |
52 | ||
53 | #endif /*__RTL8712_GP_BITDEF_H__*/ | |
54 |