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fa590c22 MC |
1 | /* Driver for Realtek PCI-Express card reader |
2 | * Header file | |
3 | * | |
4 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2, or (at your option) any | |
9 | * later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * Author: | |
20 | * Wei WANG (wei_wang@realsil.com.cn) | |
21 | * Micky Ching (micky_ching@realsil.com.cn) | |
22 | */ | |
23 | ||
24 | #ifndef __REALTEK_RTSX_CARD_H | |
25 | #define __REALTEK_RTSX_CARD_H | |
26 | ||
fa590c22 MC |
27 | #include "rtsx.h" |
28 | #include "rtsx_chip.h" | |
29 | #include "rtsx_transport.h" | |
30 | #include "sd.h" | |
31 | ||
32 | #define SSC_POWER_DOWN 0x01 | |
33 | #define SD_OC_POWER_DOWN 0x02 | |
34 | #define MS_OC_POWER_DOWN 0x04 | |
35 | #define ALL_POWER_DOWN 0x07 | |
36 | #define OC_POWER_DOWN 0x06 | |
37 | ||
38 | #define PMOS_STRG_MASK 0x10 | |
39 | #define PMOS_STRG_800mA 0x10 | |
40 | #define PMOS_STRG_400mA 0x00 | |
41 | ||
42 | #define POWER_OFF 0x03 | |
43 | #define PARTIAL_POWER_ON 0x01 | |
44 | #define POWER_ON 0x00 | |
45 | ||
46 | #define MS_POWER_OFF 0x0C | |
47 | #define MS_PARTIAL_POWER_ON 0x04 | |
48 | #define MS_POWER_ON 0x00 | |
49 | #define MS_POWER_MASK 0x0C | |
50 | ||
51 | #define SD_POWER_OFF 0x03 | |
52 | #define SD_PARTIAL_POWER_ON 0x01 | |
53 | #define SD_POWER_ON 0x00 | |
54 | #define SD_POWER_MASK 0x03 | |
55 | ||
56 | #define XD_OUTPUT_EN 0x02 | |
57 | #define SD_OUTPUT_EN 0x04 | |
58 | #define MS_OUTPUT_EN 0x08 | |
59 | #define SPI_OUTPUT_EN 0x10 | |
60 | ||
61 | #define CLK_LOW_FREQ 0x01 | |
62 | ||
63 | #define CLK_DIV_1 0x01 | |
64 | #define CLK_DIV_2 0x02 | |
65 | #define CLK_DIV_4 0x03 | |
66 | #define CLK_DIV_8 0x04 | |
67 | ||
68 | #define SSC_80 0 | |
69 | #define SSC_100 1 | |
70 | #define SSC_120 2 | |
71 | #define SSC_150 3 | |
72 | #define SSC_200 4 | |
73 | ||
74 | #define XD_CLK_EN 0x02 | |
75 | #define SD_CLK_EN 0x04 | |
76 | #define MS_CLK_EN 0x08 | |
77 | #define SPI_CLK_EN 0x10 | |
78 | ||
79 | #define XD_MOD_SEL 1 | |
80 | #define SD_MOD_SEL 2 | |
81 | #define MS_MOD_SEL 3 | |
82 | #define SPI_MOD_SEL 4 | |
83 | ||
84 | #define CHANGE_CLK 0x01 | |
85 | ||
86 | #define SD_CRC7_ERR 0x80 | |
87 | #define SD_CRC16_ERR 0x40 | |
88 | #define SD_CRC_WRITE_ERR 0x20 | |
89 | #define SD_CRC_WRITE_ERR_MASK 0x1C | |
90 | #define GET_CRC_TIME_OUT 0x02 | |
91 | #define SD_TUNING_COMPARE_ERR 0x01 | |
92 | ||
93 | #define SD_RSP_80CLK_TIMEOUT 0x01 | |
94 | ||
95 | #define SD_CLK_TOGGLE_EN 0x80 | |
96 | #define SD_CLK_FORCE_STOP 0x40 | |
97 | #define SD_DAT3_STATUS 0x10 | |
98 | #define SD_DAT2_STATUS 0x08 | |
99 | #define SD_DAT1_STATUS 0x04 | |
100 | #define SD_DAT0_STATUS 0x02 | |
101 | #define SD_CMD_STATUS 0x01 | |
102 | ||
103 | #define SD_IO_USING_1V8 0x80 | |
104 | #define SD_IO_USING_3V3 0x7F | |
105 | #define TYPE_A_DRIVING 0x00 | |
106 | #define TYPE_B_DRIVING 0x01 | |
107 | #define TYPE_C_DRIVING 0x02 | |
108 | #define TYPE_D_DRIVING 0x03 | |
109 | ||
110 | #define DDR_FIX_RX_DAT 0x00 | |
111 | #define DDR_VAR_RX_DAT 0x80 | |
112 | #define DDR_FIX_RX_DAT_EDGE 0x00 | |
113 | #define DDR_FIX_RX_DAT_14_DELAY 0x40 | |
114 | #define DDR_FIX_RX_CMD 0x00 | |
115 | #define DDR_VAR_RX_CMD 0x20 | |
116 | #define DDR_FIX_RX_CMD_POS_EDGE 0x00 | |
117 | #define DDR_FIX_RX_CMD_14_DELAY 0x10 | |
118 | #define SD20_RX_POS_EDGE 0x00 | |
119 | #define SD20_RX_14_DELAY 0x08 | |
120 | #define SD20_RX_SEL_MASK 0x08 | |
121 | ||
122 | #define DDR_FIX_TX_CMD_DAT 0x00 | |
123 | #define DDR_VAR_TX_CMD_DAT 0x80 | |
124 | #define DDR_FIX_TX_DAT_14_TSU 0x00 | |
125 | #define DDR_FIX_TX_DAT_12_TSU 0x40 | |
126 | #define DDR_FIX_TX_CMD_NEG_EDGE 0x00 | |
127 | #define DDR_FIX_TX_CMD_14_AHEAD 0x20 | |
128 | #define SD20_TX_NEG_EDGE 0x00 | |
129 | #define SD20_TX_14_AHEAD 0x10 | |
130 | #define SD20_TX_SEL_MASK 0x10 | |
131 | #define DDR_VAR_SDCLK_POL_SWAP 0x01 | |
132 | ||
133 | #define SD_TRANSFER_START 0x80 | |
134 | #define SD_TRANSFER_END 0x40 | |
135 | #define SD_STAT_IDLE 0x20 | |
136 | #define SD_TRANSFER_ERR 0x10 | |
137 | #define SD_TM_NORMAL_WRITE 0x00 | |
138 | #define SD_TM_AUTO_WRITE_3 0x01 | |
139 | #define SD_TM_AUTO_WRITE_4 0x02 | |
140 | #define SD_TM_AUTO_READ_3 0x05 | |
141 | #define SD_TM_AUTO_READ_4 0x06 | |
142 | #define SD_TM_CMD_RSP 0x08 | |
143 | #define SD_TM_AUTO_WRITE_1 0x09 | |
144 | #define SD_TM_AUTO_WRITE_2 0x0A | |
145 | #define SD_TM_NORMAL_READ 0x0C | |
146 | #define SD_TM_AUTO_READ_1 0x0D | |
147 | #define SD_TM_AUTO_READ_2 0x0E | |
148 | #define SD_TM_AUTO_TUNING 0x0F | |
149 | ||
150 | #define PHASE_CHANGE 0x80 | |
151 | #define PHASE_NOT_RESET 0x40 | |
152 | ||
153 | #define DCMPS_CHANGE 0x80 | |
154 | #define DCMPS_CHANGE_DONE 0x40 | |
155 | #define DCMPS_ERROR 0x20 | |
156 | #define DCMPS_CURRENT_PHASE 0x1F | |
157 | ||
158 | #define SD_CLK_DIVIDE_0 0x00 | |
159 | #define SD_CLK_DIVIDE_256 0xC0 | |
160 | #define SD_CLK_DIVIDE_128 0x80 | |
161 | #define SD_BUS_WIDTH_1 0x00 | |
162 | #define SD_BUS_WIDTH_4 0x01 | |
163 | #define SD_BUS_WIDTH_8 0x02 | |
164 | #define SD_ASYNC_FIFO_NOT_RST 0x10 | |
165 | #define SD_20_MODE 0x00 | |
166 | #define SD_DDR_MODE 0x04 | |
167 | #define SD_30_MODE 0x08 | |
168 | ||
169 | #define SD_CLK_DIVIDE_MASK 0xC0 | |
170 | ||
171 | #define SD_CMD_IDLE 0x80 | |
172 | ||
173 | #define SD_DATA_IDLE 0x80 | |
174 | ||
175 | #define DCM_RESET 0x08 | |
176 | #define DCM_LOCKED 0x04 | |
177 | #define DCM_208M 0x00 | |
178 | #define DCM_TX 0x01 | |
179 | #define DCM_RX 0x02 | |
180 | ||
181 | #define DRP_START 0x80 | |
182 | #define DRP_DONE 0x40 | |
183 | ||
184 | #define DRP_WRITE 0x80 | |
185 | #define DRP_READ 0x00 | |
186 | #define DCM_WRITE_ADDRESS_50 0x50 | |
187 | #define DCM_WRITE_ADDRESS_51 0x51 | |
188 | #define DCM_READ_ADDRESS_00 0x00 | |
189 | #define DCM_READ_ADDRESS_51 0x51 | |
190 | ||
191 | #define SD_CALCULATE_CRC7 0x00 | |
192 | #define SD_NO_CALCULATE_CRC7 0x80 | |
193 | #define SD_CHECK_CRC16 0x00 | |
194 | #define SD_NO_CHECK_CRC16 0x40 | |
195 | #define SD_NO_CHECK_WAIT_CRC_TO 0x20 | |
196 | #define SD_WAIT_BUSY_END 0x08 | |
197 | #define SD_NO_WAIT_BUSY_END 0x00 | |
198 | #define SD_CHECK_CRC7 0x00 | |
199 | #define SD_NO_CHECK_CRC7 0x04 | |
200 | #define SD_RSP_LEN_0 0x00 | |
201 | #define SD_RSP_LEN_6 0x01 | |
202 | #define SD_RSP_LEN_17 0x02 | |
203 | #define SD_RSP_TYPE_R0 0x04 | |
204 | #define SD_RSP_TYPE_R1 0x01 | |
205 | #define SD_RSP_TYPE_R1b 0x09 | |
206 | #define SD_RSP_TYPE_R2 0x02 | |
207 | #define SD_RSP_TYPE_R3 0x05 | |
208 | #define SD_RSP_TYPE_R4 0x05 | |
209 | #define SD_RSP_TYPE_R5 0x01 | |
210 | #define SD_RSP_TYPE_R6 0x01 | |
211 | #define SD_RSP_TYPE_R7 0x01 | |
212 | ||
213 | #define SD_RSP_80CLK_TIMEOUT_EN 0x01 | |
214 | ||
215 | #define SAMPLE_TIME_RISING 0x00 | |
216 | #define SAMPLE_TIME_FALLING 0x80 | |
217 | #define PUSH_TIME_DEFAULT 0x00 | |
218 | #define PUSH_TIME_ODD 0x40 | |
219 | #define NO_EXTEND_TOGGLE 0x00 | |
220 | #define EXTEND_TOGGLE_CHK 0x20 | |
221 | #define MS_BUS_WIDTH_1 0x00 | |
222 | #define MS_BUS_WIDTH_4 0x10 | |
223 | #define MS_BUS_WIDTH_8 0x18 | |
224 | #define MS_2K_SECTOR_MODE 0x04 | |
225 | #define MS_512_SECTOR_MODE 0x00 | |
226 | #define MS_TOGGLE_TIMEOUT_EN 0x00 | |
227 | #define MS_TOGGLE_TIMEOUT_DISEN 0x01 | |
228 | #define MS_NO_CHECK_INT 0x02 | |
229 | ||
230 | #define WAIT_INT 0x80 | |
231 | #define NO_WAIT_INT 0x00 | |
232 | #define NO_AUTO_READ_INT_REG 0x00 | |
233 | #define AUTO_READ_INT_REG 0x40 | |
234 | #define MS_CRC16_ERR 0x20 | |
235 | #define MS_RDY_TIMEOUT 0x10 | |
236 | #define MS_INT_CMDNK 0x08 | |
237 | #define MS_INT_BREQ 0x04 | |
238 | #define MS_INT_ERR 0x02 | |
239 | #define MS_INT_CED 0x01 | |
240 | ||
241 | #define MS_TRANSFER_START 0x80 | |
242 | #define MS_TRANSFER_END 0x40 | |
243 | #define MS_TRANSFER_ERR 0x20 | |
244 | #define MS_BS_STATE 0x10 | |
245 | #define MS_TM_READ_BYTES 0x00 | |
246 | #define MS_TM_NORMAL_READ 0x01 | |
247 | #define MS_TM_WRITE_BYTES 0x04 | |
248 | #define MS_TM_NORMAL_WRITE 0x05 | |
249 | #define MS_TM_AUTO_READ 0x08 | |
250 | #define MS_TM_AUTO_WRITE 0x0C | |
251 | ||
252 | #define CARD_SHARE_MASK 0x0F | |
253 | #define CARD_SHARE_MULTI_LUN 0x00 | |
254 | #define CARD_SHARE_NORMAL 0x00 | |
255 | #define CARD_SHARE_48_XD 0x02 | |
256 | #define CARD_SHARE_48_SD 0x04 | |
257 | #define CARD_SHARE_48_MS 0x08 | |
258 | #define CARD_SHARE_BAROSSA_XD 0x00 | |
259 | #define CARD_SHARE_BAROSSA_SD 0x01 | |
260 | #define CARD_SHARE_BAROSSA_MS 0x02 | |
261 | ||
262 | #define MS_DRIVE_8 0x00 | |
263 | #define MS_DRIVE_4 0x40 | |
264 | #define MS_DRIVE_12 0x80 | |
265 | #define SD_DRIVE_8 0x00 | |
266 | #define SD_DRIVE_4 0x10 | |
267 | #define SD_DRIVE_12 0x20 | |
268 | #define XD_DRIVE_8 0x00 | |
269 | #define XD_DRIVE_4 0x04 | |
270 | #define XD_DRIVE_12 0x08 | |
271 | ||
272 | #define SPI_STOP 0x01 | |
273 | #define XD_STOP 0x02 | |
274 | #define SD_STOP 0x04 | |
275 | #define MS_STOP 0x08 | |
276 | #define SPI_CLR_ERR 0x10 | |
277 | #define XD_CLR_ERR 0x20 | |
278 | #define SD_CLR_ERR 0x40 | |
279 | #define MS_CLR_ERR 0x80 | |
280 | ||
281 | #define CRC_FIX_CLK (0x00 << 0) | |
282 | #define CRC_VAR_CLK0 (0x01 << 0) | |
283 | #define CRC_VAR_CLK1 (0x02 << 0) | |
284 | #define SD30_FIX_CLK (0x00 << 2) | |
285 | #define SD30_VAR_CLK0 (0x01 << 2) | |
286 | #define SD30_VAR_CLK1 (0x02 << 2) | |
287 | #define SAMPLE_FIX_CLK (0x00 << 4) | |
288 | #define SAMPLE_VAR_CLK0 (0x01 << 4) | |
289 | #define SAMPLE_VAR_CLK1 (0x02 << 4) | |
290 | ||
291 | #define SDIO_VER_20 0x80 | |
292 | #define SDIO_VER_10 0x00 | |
293 | #define SDIO_VER_CHG 0x40 | |
294 | #define SDIO_BUS_AUTO_SWITCH 0x10 | |
295 | ||
296 | #define PINGPONG_BUFFER 0x01 | |
297 | #define RING_BUFFER 0x00 | |
298 | ||
299 | #define RB_FLUSH 0x80 | |
300 | ||
301 | #define DMA_DONE_INT_EN 0x80 | |
302 | #define SUSPEND_INT_EN 0x40 | |
303 | #define LINK_RDY_INT_EN 0x20 | |
304 | #define LINK_DOWN_INT_EN 0x10 | |
305 | ||
306 | #define DMA_DONE_INT 0x80 | |
307 | #define SUSPEND_INT 0x40 | |
308 | #define LINK_RDY_INT 0x20 | |
309 | #define LINK_DOWN_INT 0x10 | |
310 | ||
311 | #define MRD_ERR_INT_EN 0x40 | |
312 | #define MWR_ERR_INT_EN 0x20 | |
313 | #define SCSI_CMD_INT_EN 0x10 | |
314 | #define TLP_RCV_INT_EN 0x08 | |
315 | #define TLP_TRSMT_INT_EN 0x04 | |
316 | #define MRD_COMPLETE_INT_EN 0x02 | |
317 | #define MWR_COMPLETE_INT_EN 0x01 | |
318 | ||
319 | #define MRD_ERR_INT 0x40 | |
320 | #define MWR_ERR_INT 0x20 | |
321 | #define SCSI_CMD_INT 0x10 | |
322 | #define TLP_RX_INT 0x08 | |
323 | #define TLP_TX_INT 0x04 | |
324 | #define MRD_COMPLETE_INT 0x02 | |
325 | #define MWR_COMPLETE_INT 0x01 | |
326 | ||
327 | #define MSG_RX_INT_EN 0x08 | |
328 | #define MRD_RX_INT_EN 0x04 | |
329 | #define MWR_RX_INT_EN 0x02 | |
330 | #define CPLD_RX_INT_EN 0x01 | |
331 | ||
332 | #define MSG_RX_INT 0x08 | |
333 | #define MRD_RX_INT 0x04 | |
334 | #define MWR_RX_INT 0x02 | |
335 | #define CPLD_RX_INT 0x01 | |
336 | ||
337 | #define MSG_TX_INT_EN 0x08 | |
338 | #define MRD_TX_INT_EN 0x04 | |
339 | #define MWR_TX_INT_EN 0x02 | |
340 | #define CPLD_TX_INT_EN 0x01 | |
341 | ||
342 | #define MSG_TX_INT 0x08 | |
343 | #define MRD_TX_INT 0x04 | |
344 | #define MWR_TX_INT 0x02 | |
345 | #define CPLD_TX_INT 0x01 | |
346 | ||
347 | #define DMA_RST 0x80 | |
348 | #define DMA_BUSY 0x04 | |
349 | #define DMA_DIR_TO_CARD 0x00 | |
350 | #define DMA_DIR_FROM_CARD 0x02 | |
351 | #define DMA_EN 0x01 | |
352 | #define DMA_128 (0 << 4) | |
353 | #define DMA_256 (1 << 4) | |
354 | #define DMA_512 (2 << 4) | |
355 | #define DMA_1024 (3 << 4) | |
356 | #define DMA_PACK_SIZE_MASK 0x30 | |
357 | ||
358 | #define XD_PWR_OFF_DELAY0 0x00 | |
359 | #define XD_PWR_OFF_DELAY1 0x02 | |
360 | #define XD_PWR_OFF_DELAY2 0x04 | |
361 | #define XD_PWR_OFF_DELAY3 0x06 | |
362 | #define XD_AUTO_PWR_OFF_EN 0xF7 | |
363 | #define XD_NO_AUTO_PWR_OFF 0x08 | |
364 | ||
365 | #define XD_TIME_RWN_1 0x00 | |
366 | #define XD_TIME_RWN_STEP 0x20 | |
367 | #define XD_TIME_RW_1 0x00 | |
368 | #define XD_TIME_RW_STEP 0x04 | |
369 | #define XD_TIME_SETUP_1 0x00 | |
370 | #define XD_TIME_SETUP_STEP 0x01 | |
371 | ||
372 | #define XD_ECC2_UNCORRECTABLE 0x80 | |
373 | #define XD_ECC2_ERROR 0x40 | |
374 | #define XD_ECC1_UNCORRECTABLE 0x20 | |
375 | #define XD_ECC1_ERROR 0x10 | |
376 | #define XD_RDY 0x04 | |
377 | #define XD_CE_EN 0xFD | |
378 | #define XD_CE_DISEN 0x02 | |
379 | #define XD_WP_EN 0xFE | |
380 | #define XD_WP_DISEN 0x01 | |
381 | ||
382 | #define XD_TRANSFER_START 0x80 | |
383 | #define XD_TRANSFER_END 0x40 | |
384 | #define XD_PPB_EMPTY 0x20 | |
385 | #define XD_RESET 0x00 | |
386 | #define XD_ERASE 0x01 | |
387 | #define XD_READ_STATUS 0x02 | |
388 | #define XD_READ_ID 0x03 | |
389 | #define XD_READ_REDUNDANT 0x04 | |
390 | #define XD_READ_PAGES 0x05 | |
391 | #define XD_SET_CMD 0x06 | |
392 | #define XD_NORMAL_READ 0x07 | |
393 | #define XD_WRITE_PAGES 0x08 | |
394 | #define XD_NORMAL_WRITE 0x09 | |
395 | #define XD_WRITE_REDUNDANT 0x0A | |
396 | #define XD_SET_ADDR 0x0B | |
397 | ||
398 | #define XD_PPB_TO_SIE 0x80 | |
399 | #define XD_TO_PPB_ONLY 0x00 | |
400 | #define XD_BA_TRANSFORM 0x40 | |
401 | #define XD_BA_NO_TRANSFORM 0x00 | |
402 | #define XD_NO_CALC_ECC 0x20 | |
403 | #define XD_CALC_ECC 0x00 | |
404 | #define XD_IGNORE_ECC 0x10 | |
405 | #define XD_CHECK_ECC 0x00 | |
406 | #define XD_DIRECT_TO_RB 0x08 | |
407 | #define XD_ADDR_LENGTH_0 0x00 | |
408 | #define XD_ADDR_LENGTH_1 0x01 | |
409 | #define XD_ADDR_LENGTH_2 0x02 | |
410 | #define XD_ADDR_LENGTH_3 0x03 | |
411 | #define XD_ADDR_LENGTH_4 0x04 | |
412 | ||
413 | #define XD_GPG 0xFF | |
414 | #define XD_BPG 0x00 | |
415 | ||
416 | #define XD_GBLK 0xFF | |
417 | #define XD_LATER_BBLK 0xF0 | |
418 | ||
419 | #define XD_ECC2_ALL1 0x80 | |
420 | #define XD_ECC1_ALL1 0x40 | |
421 | #define XD_BA2_ALL0 0x20 | |
422 | #define XD_BA1_ALL0 0x10 | |
423 | #define XD_BA1_BA2_EQL 0x04 | |
424 | #define XD_BA2_VALID 0x02 | |
425 | #define XD_BA1_VALID 0x01 | |
426 | ||
427 | #define XD_PGSTS_ZEROBIT_OVER4 0x00 | |
428 | #define XD_PGSTS_NOT_FF 0x02 | |
429 | #define XD_AUTO_CHK_DATA_STATUS 0x01 | |
430 | ||
431 | #define RSTB_MODE_DETECT 0x80 | |
432 | #define MODE_OUT_VLD 0x40 | |
433 | #define MODE_OUT_0_NONE 0x00 | |
434 | #define MODE_OUT_10_NONE 0x04 | |
435 | #define MODE_OUT_10_47 0x05 | |
436 | #define MODE_OUT_10_180 0x06 | |
437 | #define MODE_OUT_10_680 0x07 | |
438 | #define MODE_OUT_16_NONE 0x08 | |
439 | #define MODE_OUT_16_47 0x09 | |
440 | #define MODE_OUT_16_180 0x0A | |
441 | #define MODE_OUT_16_680 0x0B | |
442 | #define MODE_OUT_NONE_NONE 0x0C | |
443 | #define MODE_OUT_NONE_47 0x0D | |
444 | #define MODE_OUT_NONE_180 0x0E | |
445 | #define MODE_OUT_NONE_680 0x0F | |
446 | ||
447 | #define CARD_OC_INT_EN 0x20 | |
448 | #define CARD_DETECT_EN 0x08 | |
449 | ||
450 | #define MS_DETECT_EN 0x80 | |
451 | #define MS_OCP_INT_EN 0x40 | |
452 | #define MS_OCP_INT_CLR 0x20 | |
453 | #define MS_OC_CLR 0x10 | |
454 | #define SD_DETECT_EN 0x08 | |
455 | #define SD_OCP_INT_EN 0x04 | |
456 | #define SD_OCP_INT_CLR 0x02 | |
457 | #define SD_OC_CLR 0x01 | |
458 | ||
459 | #define CARD_OCP_DETECT 0x80 | |
460 | #define CARD_OC_NOW 0x08 | |
461 | #define CARD_OC_EVER 0x04 | |
462 | ||
463 | #define MS_OCP_DETECT 0x80 | |
464 | #define MS_OC_NOW 0x40 | |
465 | #define MS_OC_EVER 0x20 | |
466 | #define SD_OCP_DETECT 0x08 | |
467 | #define SD_OC_NOW 0x04 | |
468 | #define SD_OC_EVER 0x02 | |
469 | ||
470 | #define CARD_OC_INT_CLR 0x08 | |
471 | #define CARD_OC_CLR 0x02 | |
472 | ||
473 | #define SD_OCP_GLITCH_MASK 0x07 | |
474 | #define SD_OCP_GLITCH_6_4 0x00 | |
475 | #define SD_OCP_GLITCH_64 0x01 | |
476 | #define SD_OCP_GLITCH_640 0x02 | |
477 | #define SD_OCP_GLITCH_1000 0x03 | |
478 | #define SD_OCP_GLITCH_2000 0x04 | |
479 | #define SD_OCP_GLITCH_4000 0x05 | |
480 | #define SD_OCP_GLITCH_8000 0x06 | |
481 | #define SD_OCP_GLITCH_10000 0x07 | |
482 | ||
483 | #define MS_OCP_GLITCH_MASK 0x70 | |
484 | #define MS_OCP_GLITCH_6_4 (0x00 << 4) | |
485 | #define MS_OCP_GLITCH_64 (0x01 << 4) | |
486 | #define MS_OCP_GLITCH_640 (0x02 << 4) | |
487 | #define MS_OCP_GLITCH_1000 (0x03 << 4) | |
488 | #define MS_OCP_GLITCH_2000 (0x04 << 4) | |
489 | #define MS_OCP_GLITCH_4000 (0x05 << 4) | |
490 | #define MS_OCP_GLITCH_8000 (0x06 << 4) | |
491 | #define MS_OCP_GLITCH_10000 (0x07 << 4) | |
492 | ||
493 | #define OCP_TIME_60 0x00 | |
494 | #define OCP_TIME_100 (0x01 << 3) | |
495 | #define OCP_TIME_200 (0x02 << 3) | |
496 | #define OCP_TIME_400 (0x03 << 3) | |
497 | #define OCP_TIME_600 (0x04 << 3) | |
498 | #define OCP_TIME_800 (0x05 << 3) | |
499 | #define OCP_TIME_1100 (0x06 << 3) | |
500 | #define OCP_TIME_MASK 0x38 | |
501 | ||
502 | #define MS_OCP_TIME_60 0x00 | |
503 | #define MS_OCP_TIME_100 (0x01 << 4) | |
504 | #define MS_OCP_TIME_200 (0x02 << 4) | |
505 | #define MS_OCP_TIME_400 (0x03 << 4) | |
506 | #define MS_OCP_TIME_600 (0x04 << 4) | |
507 | #define MS_OCP_TIME_800 (0x05 << 4) | |
508 | #define MS_OCP_TIME_1100 (0x06 << 4) | |
509 | #define MS_OCP_TIME_MASK 0x70 | |
510 | ||
511 | #define SD_OCP_TIME_60 0x00 | |
512 | #define SD_OCP_TIME_100 0x01 | |
513 | #define SD_OCP_TIME_200 0x02 | |
514 | #define SD_OCP_TIME_400 0x03 | |
515 | #define SD_OCP_TIME_600 0x04 | |
516 | #define SD_OCP_TIME_800 0x05 | |
517 | #define SD_OCP_TIME_1100 0x06 | |
518 | #define SD_OCP_TIME_MASK 0x07 | |
519 | ||
520 | #define OCP_THD_315_417 0x00 | |
521 | #define OCP_THD_283_783 (0x01 << 6) | |
522 | #define OCP_THD_244_946 (0x02 << 6) | |
523 | #define OCP_THD_191_1080 (0x03 << 6) | |
524 | #define OCP_THD_MASK 0xC0 | |
525 | ||
526 | #define MS_OCP_THD_450 0x00 | |
527 | #define MS_OCP_THD_550 (0x01 << 4) | |
528 | #define MS_OCP_THD_650 (0x02 << 4) | |
529 | #define MS_OCP_THD_750 (0x03 << 4) | |
530 | #define MS_OCP_THD_850 (0x04 << 4) | |
531 | #define MS_OCP_THD_950 (0x05 << 4) | |
532 | #define MS_OCP_THD_1050 (0x06 << 4) | |
533 | #define MS_OCP_THD_1150 (0x07 << 4) | |
534 | #define MS_OCP_THD_MASK 0x70 | |
535 | ||
536 | #define SD_OCP_THD_450 0x00 | |
537 | #define SD_OCP_THD_550 0x01 | |
538 | #define SD_OCP_THD_650 0x02 | |
539 | #define SD_OCP_THD_750 0x03 | |
540 | #define SD_OCP_THD_850 0x04 | |
541 | #define SD_OCP_THD_950 0x05 | |
542 | #define SD_OCP_THD_1050 0x06 | |
543 | #define SD_OCP_THD_1150 0x07 | |
544 | #define SD_OCP_THD_MASK 0x07 | |
545 | ||
546 | #define FPGA_MS_PULL_CTL_EN 0xEF | |
547 | #define FPGA_SD_PULL_CTL_EN 0xF7 | |
548 | #define FPGA_XD_PULL_CTL_EN1 0xFE | |
549 | #define FPGA_XD_PULL_CTL_EN2 0xFD | |
550 | #define FPGA_XD_PULL_CTL_EN3 0xFB | |
551 | ||
552 | #define FPGA_MS_PULL_CTL_BIT 0x10 | |
553 | #define FPGA_SD_PULL_CTL_BIT 0x08 | |
554 | ||
555 | #define BLINK_EN 0x08 | |
556 | #define LED_GPIO0 (0 << 4) | |
557 | #define LED_GPIO1 (1 << 4) | |
558 | #define LED_GPIO2 (2 << 4) | |
559 | ||
560 | #define SDIO_BUS_CTRL 0x01 | |
561 | #define SDIO_CD_CTRL 0x02 | |
562 | ||
563 | #define SSC_RSTB 0x80 | |
564 | #define SSC_8X_EN 0x40 | |
565 | #define SSC_FIX_FRAC 0x20 | |
566 | #define SSC_SEL_1M 0x00 | |
567 | #define SSC_SEL_2M 0x08 | |
568 | #define SSC_SEL_4M 0x10 | |
569 | #define SSC_SEL_8M 0x18 | |
570 | ||
571 | #define SSC_DEPTH_MASK 0x07 | |
572 | #define SSC_DEPTH_DISALBE 0x00 | |
573 | #define SSC_DEPTH_4M 0x01 | |
574 | #define SSC_DEPTH_2M 0x02 | |
575 | #define SSC_DEPTH_1M 0x03 | |
576 | #define SSC_DEPTH_512K 0x04 | |
577 | #define SSC_DEPTH_256K 0x05 | |
578 | #define SSC_DEPTH_128K 0x06 | |
579 | #define SSC_DEPTH_64K 0x07 | |
580 | ||
581 | #define XD_D3_NP 0x00 | |
582 | #define XD_D3_PD (0x01 << 6) | |
583 | #define XD_D3_PU (0x02 << 6) | |
584 | #define XD_D2_NP 0x00 | |
585 | #define XD_D2_PD (0x01 << 4) | |
586 | #define XD_D2_PU (0x02 << 4) | |
587 | #define XD_D1_NP 0x00 | |
588 | #define XD_D1_PD (0x01 << 2) | |
589 | #define XD_D1_PU (0x02 << 2) | |
590 | #define XD_D0_NP 0x00 | |
591 | #define XD_D0_PD 0x01 | |
592 | #define XD_D0_PU 0x02 | |
593 | ||
594 | #define SD_D7_NP 0x00 | |
595 | #define SD_D7_PD (0x01 << 4) | |
596 | #define SD_DAT7_PU (0x02 << 4) | |
597 | #define SD_CLK_NP 0x00 | |
598 | #define SD_CLK_PD (0x01 << 2) | |
599 | #define SD_CLK_PU (0x02 << 2) | |
600 | #define SD_D5_NP 0x00 | |
601 | #define SD_D5_PD 0x01 | |
602 | #define SD_D5_PU 0x02 | |
603 | ||
604 | #define MS_D1_NP 0x00 | |
605 | #define MS_D1_PD (0x01 << 6) | |
606 | #define MS_D1_PU (0x02 << 6) | |
607 | #define MS_D2_NP 0x00 | |
608 | #define MS_D2_PD (0x01 << 4) | |
609 | #define MS_D2_PU (0x02 << 4) | |
610 | #define MS_CLK_NP 0x00 | |
611 | #define MS_CLK_PD (0x01 << 2) | |
612 | #define MS_CLK_PU (0x02 << 2) | |
613 | #define MS_D6_NP 0x00 | |
614 | #define MS_D6_PD 0x01 | |
615 | #define MS_D6_PU 0x02 | |
616 | ||
617 | #define XD_D7_NP 0x00 | |
618 | #define XD_D7_PD (0x01 << 6) | |
619 | #define XD_D7_PU (0x02 << 6) | |
620 | #define XD_D6_NP 0x00 | |
621 | #define XD_D6_PD (0x01 << 4) | |
622 | #define XD_D6_PU (0x02 << 4) | |
623 | #define XD_D5_NP 0x00 | |
624 | #define XD_D5_PD (0x01 << 2) | |
625 | #define XD_D5_PU (0x02 << 2) | |
626 | #define XD_D4_NP 0x00 | |
627 | #define XD_D4_PD 0x01 | |
628 | #define XD_D4_PU 0x02 | |
629 | ||
630 | #define SD_D6_NP 0x00 | |
631 | #define SD_D6_PD (0x01 << 6) | |
632 | #define SD_D6_PU (0x02 << 6) | |
633 | #define SD_D0_NP 0x00 | |
634 | #define SD_D0_PD (0x01 << 4) | |
635 | #define SD_D0_PU (0x02 << 4) | |
636 | #define SD_D1_NP 0x00 | |
637 | #define SD_D1_PD 0x01 | |
638 | #define SD_D1_PU 0x02 | |
639 | ||
640 | #define MS_D3_NP 0x00 | |
641 | #define MS_D3_PD (0x01 << 6) | |
642 | #define MS_D3_PU (0x02 << 6) | |
643 | #define MS_D0_NP 0x00 | |
644 | #define MS_D0_PD (0x01 << 4) | |
645 | #define MS_D0_PU (0x02 << 4) | |
646 | #define MS_BS_NP 0x00 | |
647 | #define MS_BS_PD (0x01 << 2) | |
648 | #define MS_BS_PU (0x02 << 2) | |
649 | ||
650 | #define XD_WP_NP 0x00 | |
651 | #define XD_WP_PD (0x01 << 6) | |
652 | #define XD_WP_PU (0x02 << 6) | |
653 | #define XD_CE_NP 0x00 | |
654 | #define XD_CE_PD (0x01 << 3) | |
655 | #define XD_CE_PU (0x02 << 3) | |
656 | #define XD_CLE_NP 0x00 | |
657 | #define XD_CLE_PD (0x01 << 1) | |
658 | #define XD_CLE_PU (0x02 << 1) | |
659 | #define XD_CD_PD 0x00 | |
660 | #define XD_CD_PU 0x01 | |
661 | ||
662 | #define SD_D4_NP 0x00 | |
663 | #define SD_D4_PD (0x01 << 6) | |
664 | #define SD_D4_PU (0x02 << 6) | |
665 | ||
666 | #define MS_D7_NP 0x00 | |
667 | #define MS_D7_PD (0x01 << 6) | |
668 | #define MS_D7_PU (0x02 << 6) | |
669 | ||
670 | #define XD_RDY_NP 0x00 | |
671 | #define XD_RDY_PD (0x01 << 6) | |
672 | #define XD_RDY_PU (0x02 << 6) | |
673 | #define XD_WE_NP 0x00 | |
674 | #define XD_WE_PD (0x01 << 4) | |
675 | #define XD_WE_PU (0x02 << 4) | |
676 | #define XD_RE_NP 0x00 | |
677 | #define XD_RE_PD (0x01 << 2) | |
678 | #define XD_RE_PU (0x02 << 2) | |
679 | #define XD_ALE_NP 0x00 | |
680 | #define XD_ALE_PD 0x01 | |
681 | #define XD_ALE_PU 0x02 | |
682 | ||
683 | #define SD_D3_NP 0x00 | |
684 | #define SD_D3_PD (0x01 << 4) | |
685 | #define SD_D3_PU (0x02 << 4) | |
686 | #define SD_D2_NP 0x00 | |
687 | #define SD_D2_PD (0x01 << 2) | |
688 | #define SD_D2_PU (0x02 << 2) | |
689 | ||
690 | #define MS_INS_PD 0x00 | |
691 | #define MS_INS_PU (0x01 << 7) | |
692 | #define SD_WP_NP 0x00 | |
693 | #define SD_WP_PD (0x01 << 5) | |
694 | #define SD_WP_PU (0x02 << 5) | |
695 | #define SD_CD_PD 0x00 | |
696 | #define SD_CD_PU (0x01 << 4) | |
697 | #define SD_CMD_NP 0x00 | |
698 | #define SD_CMD_PD (0x01 << 2) | |
699 | #define SD_CMD_PU (0x02 << 2) | |
700 | ||
701 | #define MS_D5_NP 0x00 | |
702 | #define MS_D5_PD (0x01 << 2) | |
703 | #define MS_D5_PU (0x02 << 2) | |
704 | #define MS_D4_NP 0x00 | |
705 | #define MS_D4_PD 0x01 | |
706 | #define MS_D4_PU 0x02 | |
707 | ||
708 | #define FORCE_PM_CLOCK 0x10 | |
709 | #define EN_CLOCK_PM 0x01 | |
710 | ||
711 | #define HOST_ENTER_S3 0x02 | |
712 | #define HOST_ENTER_S1 0x01 | |
713 | ||
714 | #define AUX_PWR_DETECTED 0x01 | |
715 | ||
716 | #define PHY_DEBUG_MODE 0x01 | |
717 | ||
718 | #define SPI_COMMAND_BIT_8 0xE0 | |
719 | #define SPI_ADDRESS_BIT_24 0x17 | |
720 | #define SPI_ADDRESS_BIT_32 0x1F | |
721 | ||
722 | #define SPI_TRANSFER0_START 0x80 | |
723 | #define SPI_TRANSFER0_END 0x40 | |
724 | #define SPI_C_MODE0 0x00 | |
725 | #define SPI_CA_MODE0 0x01 | |
726 | #define SPI_CDO_MODE0 0x02 | |
727 | #define SPI_CDI_MODE0 0x03 | |
728 | #define SPI_CADO_MODE0 0x04 | |
729 | #define SPI_CADI_MODE0 0x05 | |
730 | #define SPI_POLLING_MODE0 0x06 | |
731 | ||
732 | #define SPI_TRANSFER1_START 0x80 | |
733 | #define SPI_TRANSFER1_END 0x40 | |
734 | #define SPI_DO_MODE1 0x00 | |
735 | #define SPI_DI_MODE1 0x01 | |
736 | ||
737 | #define CS_POLARITY_HIGH 0x40 | |
738 | #define CS_POLARITY_LOW 0x00 | |
739 | #define DTO_MSB_FIRST 0x00 | |
740 | #define DTO_LSB_FIRST 0x20 | |
741 | #define SPI_MASTER 0x00 | |
742 | #define SPI_SLAVE 0x10 | |
743 | #define SPI_MODE0 0x00 | |
744 | #define SPI_MODE1 0x04 | |
745 | #define SPI_MODE2 0x08 | |
746 | #define SPI_MODE3 0x0C | |
747 | #define SPI_MANUAL 0x00 | |
748 | #define SPI_HALF_AUTO 0x01 | |
749 | #define SPI_AUTO 0x02 | |
750 | #define SPI_EEPROM_AUTO 0x03 | |
751 | ||
752 | #define EDO_TIMING_MASK 0x03 | |
753 | #define SAMPLE_RISING 0x00 | |
754 | #define SAMPLE_DELAY_HALF 0x01 | |
755 | #define SAMPLE_DELAY_ONE 0x02 | |
756 | #define SAPMLE_DELAY_ONE_HALF 0x03 | |
757 | #define TCS_MASK 0x0C | |
758 | ||
759 | #define NOT_BYPASS_SD 0x02 | |
760 | #define DISABLE_SDIO_FUNC 0x04 | |
761 | #define SELECT_1LUN 0x08 | |
762 | ||
763 | #define PWR_GATE_EN 0x01 | |
764 | #define LDO3318_PWR_MASK 0x06 | |
765 | #define LDO_ON 0x00 | |
766 | #define LDO_SUSPEND 0x04 | |
767 | #define LDO_OFF 0x06 | |
768 | ||
769 | #define SD_CFG1 0xFDA0 | |
770 | #define SD_CFG2 0xFDA1 | |
771 | #define SD_CFG3 0xFDA2 | |
772 | #define SD_STAT1 0xFDA3 | |
773 | #define SD_STAT2 0xFDA4 | |
774 | #define SD_BUS_STAT 0xFDA5 | |
775 | #define SD_PAD_CTL 0xFDA6 | |
776 | #define SD_SAMPLE_POINT_CTL 0xFDA7 | |
777 | #define SD_PUSH_POINT_CTL 0xFDA8 | |
778 | #define SD_CMD0 0xFDA9 | |
779 | #define SD_CMD1 0xFDAA | |
780 | #define SD_CMD2 0xFDAB | |
781 | #define SD_CMD3 0xFDAC | |
782 | #define SD_CMD4 0xFDAD | |
783 | #define SD_CMD5 0xFDAE | |
784 | #define SD_BYTE_CNT_L 0xFDAF | |
785 | #define SD_BYTE_CNT_H 0xFDB0 | |
786 | #define SD_BLOCK_CNT_L 0xFDB1 | |
787 | #define SD_BLOCK_CNT_H 0xFDB2 | |
788 | #define SD_TRANSFER 0xFDB3 | |
789 | #define SD_CMD_STATE 0xFDB5 | |
790 | #define SD_DATA_STATE 0xFDB6 | |
791 | ||
792 | #define DCM_DRP_CTL 0xFC23 | |
793 | #define DCM_DRP_TRIG 0xFC24 | |
794 | #define DCM_DRP_CFG 0xFC25 | |
795 | #define DCM_DRP_WR_DATA_L 0xFC26 | |
796 | #define DCM_DRP_WR_DATA_H 0xFC27 | |
797 | #define DCM_DRP_RD_DATA_L 0xFC28 | |
798 | #define DCM_DRP_RD_DATA_H 0xFC29 | |
799 | #define SD_VPCLK0_CTL 0xFC2A | |
800 | #define SD_VPCLK1_CTL 0xFC2B | |
801 | #define SD_DCMPS0_CTL 0xFC2C | |
802 | #define SD_DCMPS1_CTL 0xFC2D | |
803 | #define SD_VPTX_CTL SD_VPCLK0_CTL | |
804 | #define SD_VPRX_CTL SD_VPCLK1_CTL | |
805 | #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL | |
806 | #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL | |
807 | ||
808 | #define CARD_CLK_SOURCE 0xFC2E | |
809 | ||
810 | #define CARD_PWR_CTL 0xFD50 | |
811 | #define CARD_CLK_SWITCH 0xFD51 | |
812 | #define CARD_SHARE_MODE 0xFD52 | |
813 | #define CARD_DRIVE_SEL 0xFD53 | |
814 | #define CARD_STOP 0xFD54 | |
815 | #define CARD_OE 0xFD55 | |
816 | #define CARD_AUTO_BLINK 0xFD56 | |
817 | #define CARD_GPIO_DIR 0xFD57 | |
818 | #define CARD_GPIO 0xFD58 | |
819 | ||
820 | #define CARD_DATA_SOURCE 0xFD5B | |
821 | #define CARD_SELECT 0xFD5C | |
822 | #define SD30_DRIVE_SEL 0xFD5E | |
823 | ||
824 | #define CARD_CLK_EN 0xFD69 | |
825 | ||
826 | #define SDIO_CTRL 0xFD6B | |
827 | ||
828 | #define FPDCTL 0xFC00 | |
829 | #define PDINFO 0xFC01 | |
830 | ||
831 | #define CLK_CTL 0xFC02 | |
832 | #define CLK_DIV 0xFC03 | |
833 | #define CLK_SEL 0xFC04 | |
834 | ||
835 | #define SSC_DIV_N_0 0xFC0F | |
836 | #define SSC_DIV_N_1 0xFC10 | |
837 | ||
838 | #define RCCTL 0xFC14 | |
839 | ||
840 | #define FPGA_PULL_CTL 0xFC1D | |
841 | ||
842 | #define CARD_PULL_CTL1 0xFD60 | |
843 | #define CARD_PULL_CTL2 0xFD61 | |
844 | #define CARD_PULL_CTL3 0xFD62 | |
845 | #define CARD_PULL_CTL4 0xFD63 | |
846 | #define CARD_PULL_CTL5 0xFD64 | |
847 | #define CARD_PULL_CTL6 0xFD65 | |
848 | ||
849 | #define IRQEN0 0xFE20 | |
850 | #define IRQSTAT0 0xFE21 | |
851 | #define IRQEN1 0xFE22 | |
852 | #define IRQSTAT1 0xFE23 | |
853 | #define TLPRIEN 0xFE24 | |
854 | #define TLPRISTAT 0xFE25 | |
855 | #define TLPTIEN 0xFE26 | |
856 | #define TLPTISTAT 0xFE27 | |
857 | #define DMATC0 0xFE28 | |
858 | #define DMATC1 0xFE29 | |
859 | #define DMATC2 0xFE2A | |
860 | #define DMATC3 0xFE2B | |
861 | #define DMACTL 0xFE2C | |
862 | #define BCTL 0xFE2D | |
863 | #define RBBC0 0xFE2E | |
864 | #define RBBC1 0xFE2F | |
865 | #define RBDAT 0xFE30 | |
866 | #define RBCTL 0xFE34 | |
867 | #define CFGADDR0 0xFE35 | |
868 | #define CFGADDR1 0xFE36 | |
869 | #define CFGDATA0 0xFE37 | |
870 | #define CFGDATA1 0xFE38 | |
871 | #define CFGDATA2 0xFE39 | |
872 | #define CFGDATA3 0xFE3A | |
873 | #define CFGRWCTL 0xFE3B | |
874 | #define PHYRWCTL 0xFE3C | |
875 | #define PHYDATA0 0xFE3D | |
876 | #define PHYDATA1 0xFE3E | |
877 | #define PHYADDR 0xFE3F | |
878 | #define MSGRXDATA0 0xFE40 | |
879 | #define MSGRXDATA1 0xFE41 | |
880 | #define MSGRXDATA2 0xFE42 | |
881 | #define MSGRXDATA3 0xFE43 | |
882 | #define MSGTXDATA0 0xFE44 | |
883 | #define MSGTXDATA1 0xFE45 | |
884 | #define MSGTXDATA2 0xFE46 | |
885 | #define MSGTXDATA3 0xFE47 | |
886 | #define MSGTXCTL 0xFE48 | |
887 | #define PETXCFG 0xFE49 | |
888 | ||
889 | #define CDRESUMECTL 0xFE52 | |
890 | #define WAKE_SEL_CTL 0xFE54 | |
891 | #define PME_FORCE_CTL 0xFE56 | |
892 | #define ASPM_FORCE_CTL 0xFE57 | |
893 | #define PM_CLK_FORCE_CTL 0xFE58 | |
894 | #define PERST_GLITCH_WIDTH 0xFE5C | |
895 | #define CHANGE_LINK_STATE 0xFE5B | |
896 | #define RESET_LOAD_REG 0xFE5E | |
897 | #define HOST_SLEEP_STATE 0xFE60 | |
898 | #define MAIN_PWR_OFF_CTL 0xFE70 /* RTS5208 */ | |
899 | ||
900 | #define NFTS_TX_CTRL 0xFE72 | |
901 | ||
902 | #define PWR_GATE_CTRL 0xFE75 | |
903 | #define PWD_SUSPEND_EN 0xFE76 | |
904 | ||
905 | #define EFUSE_CONTENT 0xFE5F | |
906 | ||
907 | #define XD_INIT 0xFD10 | |
908 | #define XD_DTCTL 0xFD11 | |
909 | #define XD_CTL 0xFD12 | |
910 | #define XD_TRANSFER 0xFD13 | |
911 | #define XD_CFG 0xFD14 | |
912 | #define XD_ADDRESS0 0xFD15 | |
913 | #define XD_ADDRESS1 0xFD16 | |
914 | #define XD_ADDRESS2 0xFD17 | |
915 | #define XD_ADDRESS3 0xFD18 | |
916 | #define XD_ADDRESS4 0xFD19 | |
917 | #define XD_DAT 0xFD1A | |
918 | #define XD_PAGE_CNT 0xFD1B | |
919 | #define XD_PAGE_STATUS 0xFD1C | |
920 | #define XD_BLOCK_STATUS 0xFD1D | |
921 | #define XD_BLOCK_ADDR1_L 0xFD1E | |
922 | #define XD_BLOCK_ADDR1_H 0xFD1F | |
923 | #define XD_BLOCK_ADDR2_L 0xFD20 | |
924 | #define XD_BLOCK_ADDR2_H 0xFD21 | |
925 | #define XD_BYTE_CNT_L 0xFD22 | |
926 | #define XD_BYTE_CNT_H 0xFD23 | |
927 | #define XD_PARITY 0xFD24 | |
928 | #define XD_ECC_BIT1 0xFD25 | |
929 | #define XD_ECC_BYTE1 0xFD26 | |
930 | #define XD_ECC_BIT2 0xFD27 | |
931 | #define XD_ECC_BYTE2 0xFD28 | |
932 | #define XD_RESERVED0 0xFD29 | |
933 | #define XD_RESERVED1 0xFD2A | |
934 | #define XD_RESERVED2 0xFD2B | |
935 | #define XD_RESERVED3 0xFD2C | |
936 | #define XD_CHK_DATA_STATUS 0xFD2D | |
937 | #define XD_CATCTL 0xFD2E | |
938 | ||
939 | #define MS_CFG 0xFD40 | |
940 | #define MS_TPC 0xFD41 | |
941 | #define MS_TRANS_CFG 0xFD42 | |
942 | #define MS_TRANSFER 0xFD43 | |
943 | #define MS_INT_REG 0xFD44 | |
944 | #define MS_BYTE_CNT 0xFD45 | |
945 | #define MS_SECTOR_CNT_L 0xFD46 | |
946 | #define MS_SECTOR_CNT_H 0xFD47 | |
947 | #define MS_DBUS_H 0xFD48 | |
948 | ||
949 | #define SSC_CTL1 0xFC11 | |
950 | #define SSC_CTL2 0xFC12 | |
951 | ||
952 | #define OCPCTL 0xFC15 | |
953 | #define OCPSTAT 0xFC16 | |
954 | #define OCPCLR 0xFC17 /* 5208 */ | |
955 | #define OCPPARA1 0xFC18 | |
956 | #define OCPPARA2 0xFC19 | |
957 | ||
958 | #define EFUSE_OP 0xFC20 | |
959 | #define EFUSE_CTRL 0xFC21 | |
960 | #define EFUSE_DATA 0xFC22 | |
961 | ||
962 | #define SPI_COMMAND 0xFD80 | |
963 | #define SPI_ADDR0 0xFD81 | |
964 | #define SPI_ADDR1 0xFD82 | |
965 | #define SPI_ADDR2 0xFD83 | |
966 | #define SPI_ADDR3 0xFD84 | |
967 | #define SPI_CA_NUMBER 0xFD85 | |
968 | #define SPI_LENGTH0 0xFD86 | |
969 | #define SPI_LENGTH1 0xFD87 | |
970 | #define SPI_DATA 0xFD88 | |
971 | #define SPI_DATA_NUMBER 0xFD89 | |
972 | #define SPI_TRANSFER0 0xFD90 | |
973 | #define SPI_TRANSFER1 0xFD91 | |
974 | #define SPI_CONTROL 0xFD92 | |
975 | #define SPI_SIG 0xFD93 | |
976 | #define SPI_TCTL 0xFD94 | |
977 | #define SPI_SLAVE_NUM 0xFD95 | |
978 | #define SPI_CLK_DIVIDER0 0xFD96 | |
979 | #define SPI_CLK_DIVIDER1 0xFD97 | |
980 | ||
981 | #define SRAM_BASE 0xE600 | |
982 | #define RBUF_BASE 0xF400 | |
983 | #define PPBUF_BASE1 0xF800 | |
984 | #define PPBUF_BASE2 0xFA00 | |
985 | #define IMAGE_FLAG_ADDR0 0xCE80 | |
986 | #define IMAGE_FLAG_ADDR1 0xCE81 | |
987 | ||
988 | #define READ_OP 1 | |
989 | #define WRITE_OP 2 | |
990 | ||
991 | #define LCTLR 0x80 | |
992 | ||
993 | #define POLLING_WAIT_CNT 1 | |
994 | #define IDLE_MAX_COUNT 10 | |
995 | #define SDIO_IDLE_COUNT 10 | |
996 | ||
997 | #define DEBOUNCE_CNT 5 | |
998 | ||
999 | void do_remaining_work(struct rtsx_chip *chip); | |
1000 | void try_to_switch_sdio_ctrl(struct rtsx_chip *chip); | |
1001 | void do_reset_sd_card(struct rtsx_chip *chip); | |
1002 | void do_reset_xd_card(struct rtsx_chip *chip); | |
1003 | void do_reset_ms_card(struct rtsx_chip *chip); | |
1004 | void rtsx_power_off_card(struct rtsx_chip *chip); | |
1005 | void rtsx_release_cards(struct rtsx_chip *chip); | |
1006 | void rtsx_reset_cards(struct rtsx_chip *chip); | |
1007 | void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip); | |
1008 | void rtsx_init_cards(struct rtsx_chip *chip); | |
1009 | int switch_ssc_clock(struct rtsx_chip *chip, int clk); | |
1010 | int switch_normal_clock(struct rtsx_chip *chip, int clk); | |
1011 | int enable_card_clock(struct rtsx_chip *chip, u8 card); | |
1012 | int disable_card_clock(struct rtsx_chip *chip, u8 card); | |
1013 | int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, | |
5d2de0d9 | 1014 | u32 sec_addr, u16 sec_cnt); |
fa590c22 | 1015 | void trans_dma_enable(enum dma_data_direction dir, |
5d2de0d9 | 1016 | struct rtsx_chip *chip, u32 byte_cnt, u8 pack_size); |
fa590c22 MC |
1017 | void toggle_gpio(struct rtsx_chip *chip, u8 gpio); |
1018 | void turn_on_led(struct rtsx_chip *chip, u8 gpio); | |
1019 | void turn_off_led(struct rtsx_chip *chip, u8 gpio); | |
1020 | ||
1021 | int card_share_mode(struct rtsx_chip *chip, int card); | |
1022 | int select_card(struct rtsx_chip *chip, int card); | |
1023 | int detect_card_cd(struct rtsx_chip *chip, int card); | |
1024 | int check_card_exist(struct rtsx_chip *chip, unsigned int lun); | |
1025 | int check_card_ready(struct rtsx_chip *chip, unsigned int lun); | |
1026 | int check_card_wp(struct rtsx_chip *chip, unsigned int lun); | |
fa590c22 MC |
1027 | void eject_card(struct rtsx_chip *chip, unsigned int lun); |
1028 | u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun); | |
1029 | ||
1030 | static inline u32 get_card_size(struct rtsx_chip *chip, unsigned int lun) | |
1031 | { | |
1032 | #ifdef SUPPORT_SD_LOCK | |
f5becff7 | 1033 | struct sd_info *sd_card = &chip->sd_card; |
fa590c22 MC |
1034 | |
1035 | if ((get_lun_card(chip, lun) == SD_CARD) && | |
5d2de0d9 | 1036 | (sd_card->sd_lock_status & SD_LOCKED)) |
fa590c22 | 1037 | return 0; |
45252847 RB |
1038 | |
1039 | return chip->capacity[lun]; | |
fa590c22 MC |
1040 | #else |
1041 | return chip->capacity[lun]; | |
1042 | #endif | |
1043 | } | |
1044 | ||
1045 | static inline int switch_clock(struct rtsx_chip *chip, int clk) | |
1046 | { | |
1047 | int retval = 0; | |
1048 | ||
1049 | if (chip->asic_code) | |
1050 | retval = switch_ssc_clock(chip, clk); | |
1051 | else | |
1052 | retval = switch_normal_clock(chip, clk); | |
1053 | ||
1054 | return retval; | |
1055 | } | |
1056 | ||
1057 | int card_power_on(struct rtsx_chip *chip, u8 card); | |
1058 | int card_power_off(struct rtsx_chip *chip, u8 card); | |
1059 | ||
1060 | static inline int card_power_off_all(struct rtsx_chip *chip) | |
1061 | { | |
8ee775f9 JP |
1062 | int retval; |
1063 | ||
1064 | retval = rtsx_write_register(chip, CARD_PWR_CTL, 0x0F, 0x0F); | |
1065 | if (retval) { | |
1066 | rtsx_trace(chip); | |
1067 | return retval; | |
1068 | } | |
fa590c22 MC |
1069 | |
1070 | return STATUS_SUCCESS; | |
1071 | } | |
1072 | ||
1073 | static inline void rtsx_clear_xd_error(struct rtsx_chip *chip) | |
1074 | { | |
1075 | rtsx_write_register(chip, CARD_STOP, XD_STOP | XD_CLR_ERR, | |
5d2de0d9 | 1076 | XD_STOP | XD_CLR_ERR); |
fa590c22 MC |
1077 | } |
1078 | ||
1079 | static inline void rtsx_clear_sd_error(struct rtsx_chip *chip) | |
1080 | { | |
1081 | rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, | |
5d2de0d9 | 1082 | SD_STOP | SD_CLR_ERR); |
fa590c22 MC |
1083 | } |
1084 | ||
1085 | static inline void rtsx_clear_ms_error(struct rtsx_chip *chip) | |
1086 | { | |
1087 | rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, | |
5d2de0d9 | 1088 | MS_STOP | MS_CLR_ERR); |
fa590c22 MC |
1089 | } |
1090 | ||
1091 | static inline void rtsx_clear_spi_error(struct rtsx_chip *chip) | |
1092 | { | |
1093 | rtsx_write_register(chip, CARD_STOP, SPI_STOP | SPI_CLR_ERR, | |
5d2de0d9 | 1094 | SPI_STOP | SPI_CLR_ERR); |
fa590c22 MC |
1095 | } |
1096 | ||
1097 | #ifdef SUPPORT_SDIO_ASPM | |
1098 | void dynamic_configure_sdio_aspm(struct rtsx_chip *chip); | |
1099 | #endif | |
1100 | ||
1101 | #endif /* __REALTEK_RTSX_CARD_H */ |